2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/flow_dissector.h>
34 #include <net/sch_generic.h>
35 #include <net/pkt_cls.h>
36 #include <net/tc_act/tc_gact.h>
37 #include <net/tc_act/tc_skbedit.h>
38 #include <linux/mlx5/fs.h>
39 #include <linux/mlx5/device.h>
40 #include <linux/rhashtable.h>
41 #include <net/switchdev.h>
42 #include <net/tc_act/tc_mirred.h>
43 #include <net/tc_act/tc_vlan.h>
44 #include <net/tc_act/tc_tunnel_key.h>
45 #include <net/tc_act/tc_pedit.h>
46 #include <net/tc_act/tc_csum.h>
47 #include <net/vxlan.h>
56 struct mlx5_nic_flow_attr {
61 struct mlx5_flow_table *hairpin_ft;
65 MLX5E_TC_FLOW_ESWITCH = BIT(0),
66 MLX5E_TC_FLOW_NIC = BIT(1),
67 MLX5E_TC_FLOW_OFFLOADED = BIT(2),
68 MLX5E_TC_FLOW_HAIRPIN = BIT(3),
69 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(4),
72 struct mlx5e_tc_flow {
73 struct rhash_head node;
76 struct mlx5_flow_handle *rule;
77 struct list_head encap; /* flows sharing the same encap ID */
78 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
79 struct list_head hairpin; /* flows sharing the same hairpin */
81 struct mlx5_esw_flow_attr esw_attr[0];
82 struct mlx5_nic_flow_attr nic_attr[0];
86 struct mlx5e_tc_flow_parse_attr {
87 struct ip_tunnel_info tun_info;
88 struct mlx5_flow_spec spec;
89 int num_mod_hdr_actions;
90 void *mod_hdr_actions;
95 MLX5_HEADER_TYPE_VXLAN = 0x0,
96 MLX5_HEADER_TYPE_NVGRE = 0x1,
99 #define MLX5E_TC_TABLE_NUM_GROUPS 4
100 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE (1 << 16)
102 struct mlx5e_hairpin {
103 struct mlx5_hairpin *pair;
105 struct mlx5_core_dev *func_mdev;
106 struct mlx5e_priv *func_priv;
111 struct mlx5e_rqt indir_rqt;
112 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
113 struct mlx5e_ttc_table ttc;
116 struct mlx5e_hairpin_entry {
117 /* a node of a hash table which keeps all the hairpin entries */
118 struct hlist_node hairpin_hlist;
120 /* flows sharing the same hairpin */
121 struct list_head flows;
125 struct mlx5e_hairpin *hp;
133 struct mlx5e_mod_hdr_entry {
134 /* a node of a hash table which keeps all the mod_hdr entries */
135 struct hlist_node mod_hdr_hlist;
137 /* flows sharing the same mod_hdr entry */
138 struct list_head flows;
140 struct mod_hdr_key key;
145 #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
147 static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
149 return jhash(key->actions,
150 key->num_actions * MLX5_MH_ACT_SZ, 0);
153 static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
154 struct mod_hdr_key *b)
156 if (a->num_actions != b->num_actions)
159 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
162 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
163 struct mlx5e_tc_flow *flow,
164 struct mlx5e_tc_flow_parse_attr *parse_attr)
166 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
167 int num_actions, actions_size, namespace, err;
168 struct mlx5e_mod_hdr_entry *mh;
169 struct mod_hdr_key key;
173 num_actions = parse_attr->num_mod_hdr_actions;
174 actions_size = MLX5_MH_ACT_SZ * num_actions;
176 key.actions = parse_attr->mod_hdr_actions;
177 key.num_actions = num_actions;
179 hash_key = hash_mod_hdr_info(&key);
181 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
182 namespace = MLX5_FLOW_NAMESPACE_FDB;
183 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
184 mod_hdr_hlist, hash_key) {
185 if (!cmp_mod_hdr_info(&mh->key, &key)) {
191 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
192 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
193 mod_hdr_hlist, hash_key) {
194 if (!cmp_mod_hdr_info(&mh->key, &key)) {
204 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
208 mh->key.actions = (void *)mh + sizeof(*mh);
209 memcpy(mh->key.actions, key.actions, actions_size);
210 mh->key.num_actions = num_actions;
211 INIT_LIST_HEAD(&mh->flows);
213 err = mlx5_modify_header_alloc(priv->mdev, namespace,
220 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
221 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
223 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
226 list_add(&flow->mod_hdr, &mh->flows);
227 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
228 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
230 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
239 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
240 struct mlx5e_tc_flow *flow)
242 struct list_head *next = flow->mod_hdr.next;
244 list_del(&flow->mod_hdr);
246 if (list_empty(next)) {
247 struct mlx5e_mod_hdr_entry *mh;
249 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
251 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
252 hash_del(&mh->mod_hdr_hlist);
258 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
260 struct net_device *netdev;
261 struct mlx5e_priv *priv;
263 netdev = __dev_get_by_index(net, ifindex);
264 priv = netdev_priv(netdev);
268 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
270 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
274 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
278 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
280 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
281 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
282 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
284 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
291 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
296 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
298 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
299 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
302 static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
304 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
305 struct mlx5e_priv *priv = hp->func_priv;
306 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
308 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
311 for (i = 0; i < sz; i++) {
313 if (priv->channels.params.rss_hfunc == ETH_RSS_HASH_XOR)
314 ix = mlx5e_bits_invert(i, ilog2(sz));
315 ix = indirection_rqt[ix];
316 rqn = hp->pair->rqn[ix];
317 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
321 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
323 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
324 struct mlx5e_priv *priv = hp->func_priv;
325 struct mlx5_core_dev *mdev = priv->mdev;
329 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
330 in = kvzalloc(inlen, GFP_KERNEL);
334 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
336 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
337 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
339 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
341 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
343 hp->indir_rqt.enabled = true;
349 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
351 struct mlx5e_priv *priv = hp->func_priv;
352 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
356 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
357 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
358 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
360 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
361 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
362 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
363 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
365 err = mlx5_core_create_tir(hp->func_mdev, in,
366 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
368 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
369 goto err_destroy_tirs;
375 for (i = 0; i < tt; i++)
376 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
380 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
384 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
385 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
388 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
389 struct ttc_params *ttc_params)
391 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
394 memset(ttc_params, 0, sizeof(*ttc_params));
396 ttc_params->any_tt_tirn = hp->tirn;
398 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
399 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
401 ft_attr->max_fte = MLX5E_NUM_TT;
402 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
403 ft_attr->prio = MLX5E_TC_PRIO;
406 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
408 struct mlx5e_priv *priv = hp->func_priv;
409 struct ttc_params ttc_params;
412 err = mlx5e_hairpin_create_indirect_rqt(hp);
416 err = mlx5e_hairpin_create_indirect_tirs(hp);
418 goto err_create_indirect_tirs;
420 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
421 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
423 goto err_create_ttc_table;
425 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
426 hp->num_channels, hp->ttc.ft.t->id);
430 err_create_ttc_table:
431 mlx5e_hairpin_destroy_indirect_tirs(hp);
432 err_create_indirect_tirs:
433 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
438 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
440 struct mlx5e_priv *priv = hp->func_priv;
442 mlx5e_destroy_ttc_table(priv, &hp->ttc);
443 mlx5e_hairpin_destroy_indirect_tirs(hp);
444 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
447 static struct mlx5e_hairpin *
448 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
451 struct mlx5_core_dev *func_mdev, *peer_mdev;
452 struct mlx5e_hairpin *hp;
453 struct mlx5_hairpin *pair;
456 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
458 return ERR_PTR(-ENOMEM);
460 func_mdev = priv->mdev;
461 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
463 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
466 goto create_pair_err;
469 hp->func_mdev = func_mdev;
470 hp->func_priv = priv;
471 hp->num_channels = params->num_channels;
473 err = mlx5e_hairpin_create_transport(hp);
475 goto create_transport_err;
477 if (hp->num_channels > 1) {
478 err = mlx5e_hairpin_rss_init(hp);
486 mlx5e_hairpin_destroy_transport(hp);
487 create_transport_err:
488 mlx5_core_hairpin_destroy(hp->pair);
494 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
496 if (hp->num_channels > 1)
497 mlx5e_hairpin_rss_cleanup(hp);
498 mlx5e_hairpin_destroy_transport(hp);
499 mlx5_core_hairpin_destroy(hp->pair);
503 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
505 return (peer_vhca_id << 16 | prio);
508 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
509 u16 peer_vhca_id, u8 prio)
511 struct mlx5e_hairpin_entry *hpe;
512 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
514 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
515 hairpin_hlist, hash_key) {
516 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
523 #define UNKNOWN_MATCH_PRIO 8
525 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
526 struct mlx5_flow_spec *spec, u8 *match_prio)
528 void *headers_c, *headers_v;
529 u8 prio_val, prio_mask = 0;
532 #ifdef CONFIG_MLX5_CORE_EN_DCB
533 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
534 netdev_warn(priv->netdev,
535 "only PCP trust state supported for hairpin\n");
539 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
540 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
542 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
544 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
545 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
548 if (!vlan_present || !prio_mask) {
549 prio_val = UNKNOWN_MATCH_PRIO;
550 } else if (prio_mask != 0x7) {
551 netdev_warn(priv->netdev,
552 "masked priority match not supported for hairpin\n");
556 *match_prio = prio_val;
560 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
561 struct mlx5e_tc_flow *flow,
562 struct mlx5e_tc_flow_parse_attr *parse_attr)
564 int peer_ifindex = parse_attr->mirred_ifindex;
565 struct mlx5_hairpin_params params;
566 struct mlx5_core_dev *peer_mdev;
567 struct mlx5e_hairpin_entry *hpe;
568 struct mlx5e_hairpin *hp;
575 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
576 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
577 netdev_warn(priv->netdev, "hairpin is not supported\n");
581 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
582 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio);
585 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
589 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
593 INIT_LIST_HEAD(&hpe->flows);
594 hpe->peer_vhca_id = peer_id;
595 hpe->prio = match_prio;
597 params.log_data_size = 15;
598 params.log_data_size = min_t(u8, params.log_data_size,
599 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
600 params.log_data_size = max_t(u8, params.log_data_size,
601 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
603 params.log_num_packets = params.log_data_size -
604 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
605 params.log_num_packets = min_t(u8, params.log_num_packets,
606 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
608 params.q_counter = priv->q_counter;
609 /* set hairpin pair per each 50Gbs share of the link */
610 mlx5e_get_max_linkspeed(priv->mdev, &link_speed);
611 link_speed = max_t(u32, link_speed, 50000);
612 link_speed64 = link_speed;
613 do_div(link_speed64, 50000);
614 params.num_channels = link_speed64;
616 hp = mlx5e_hairpin_create(priv, ¶ms, peer_ifindex);
619 goto create_hairpin_err;
622 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
623 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
624 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
627 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
628 hash_hairpin_info(peer_id, match_prio));
631 if (hpe->hp->num_channels > 1) {
632 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
633 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
635 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
637 list_add(&flow->hairpin, &hpe->flows);
646 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
647 struct mlx5e_tc_flow *flow)
649 struct list_head *next = flow->hairpin.next;
651 list_del(&flow->hairpin);
653 /* no more hairpin flows for us, release the hairpin pair */
654 if (list_empty(next)) {
655 struct mlx5e_hairpin_entry *hpe;
657 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
659 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
660 hpe->hp->pair->peer_mdev->priv.name);
662 mlx5e_hairpin_destroy(hpe->hp);
663 hash_del(&hpe->hairpin_hlist);
668 static struct mlx5_flow_handle *
669 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
670 struct mlx5e_tc_flow_parse_attr *parse_attr,
671 struct mlx5e_tc_flow *flow)
673 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
674 struct mlx5_core_dev *dev = priv->mdev;
675 struct mlx5_flow_destination dest[2] = {};
676 struct mlx5_flow_act flow_act = {
677 .action = attr->action,
678 .has_flow_tag = true,
679 .flow_tag = attr->flow_tag,
682 struct mlx5_fc *counter = NULL;
683 struct mlx5_flow_handle *rule;
684 bool table_created = false;
685 int err, dest_ix = 0;
687 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
688 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr);
691 goto err_add_hairpin_flow;
693 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
694 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
695 dest[dest_ix].ft = attr->hairpin_ft;
697 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
698 dest[dest_ix].tir_num = attr->hairpin_tirn;
701 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
702 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
703 dest[dest_ix].ft = priv->fs.vlan.ft.t;
707 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
708 counter = mlx5_fc_create(dev, true);
709 if (IS_ERR(counter)) {
710 rule = ERR_CAST(counter);
713 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
714 dest[dest_ix].counter = counter;
718 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
719 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
720 flow_act.modify_id = attr->mod_hdr_id;
721 kfree(parse_attr->mod_hdr_actions);
724 goto err_create_mod_hdr_id;
728 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
729 int tc_grp_size, tc_tbl_size;
730 u32 max_flow_counter;
732 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
733 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
735 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
737 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
738 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
741 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
744 MLX5E_TC_TABLE_NUM_GROUPS,
745 MLX5E_TC_FT_LEVEL, 0);
746 if (IS_ERR(priv->fs.tc.t)) {
747 netdev_err(priv->netdev,
748 "Failed to create tc offload table\n");
749 rule = ERR_CAST(priv->fs.tc.t);
753 table_created = true;
756 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
757 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
758 &flow_act, dest, dest_ix);
767 mlx5_destroy_flow_table(priv->fs.tc.t);
768 priv->fs.tc.t = NULL;
771 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
772 mlx5e_detach_mod_hdr(priv, flow);
773 err_create_mod_hdr_id:
774 mlx5_fc_destroy(dev, counter);
776 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
777 mlx5e_hairpin_flow_del(priv, flow);
778 err_add_hairpin_flow:
782 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
783 struct mlx5e_tc_flow *flow)
785 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
786 struct mlx5_fc *counter = NULL;
788 counter = mlx5_flow_rule_counter(flow->rule);
789 mlx5_del_flow_rules(flow->rule);
790 mlx5_fc_destroy(priv->mdev, counter);
792 if (!mlx5e_tc_num_filters(priv) && (priv->fs.tc.t)) {
793 mlx5_destroy_flow_table(priv->fs.tc.t);
794 priv->fs.tc.t = NULL;
797 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
798 mlx5e_detach_mod_hdr(priv, flow);
800 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
801 mlx5e_hairpin_flow_del(priv, flow);
804 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
805 struct mlx5e_tc_flow *flow);
807 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
808 struct ip_tunnel_info *tun_info,
809 struct net_device *mirred_dev,
810 struct net_device **encap_dev,
811 struct mlx5e_tc_flow *flow);
813 static struct mlx5_flow_handle *
814 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
815 struct mlx5e_tc_flow_parse_attr *parse_attr,
816 struct mlx5e_tc_flow *flow)
818 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
819 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
820 struct net_device *out_dev, *encap_dev = NULL;
821 struct mlx5_flow_handle *rule = NULL;
822 struct mlx5e_rep_priv *rpriv;
823 struct mlx5e_priv *out_priv;
826 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
827 out_dev = __dev_get_by_index(dev_net(priv->netdev),
828 attr->parse_attr->mirred_ifindex);
829 err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
830 out_dev, &encap_dev, flow);
834 goto err_attach_encap;
836 out_priv = netdev_priv(encap_dev);
837 rpriv = out_priv->ppriv;
838 attr->out_rep = rpriv->rep;
841 err = mlx5_eswitch_add_vlan_action(esw, attr);
847 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
848 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
849 kfree(parse_attr->mod_hdr_actions);
856 /* we get here if (1) there's no error (rule being null) or when
857 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
859 if (rule != ERR_PTR(-EAGAIN)) {
860 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
867 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
868 mlx5e_detach_mod_hdr(priv, flow);
870 mlx5_eswitch_del_vlan_action(esw, attr);
872 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
873 mlx5e_detach_encap(priv, flow);
878 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
879 struct mlx5e_tc_flow *flow)
881 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
882 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
884 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
885 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
886 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, attr);
889 mlx5_eswitch_del_vlan_action(esw, attr);
891 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
892 mlx5e_detach_encap(priv, flow);
893 kvfree(attr->parse_attr);
896 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
897 mlx5e_detach_mod_hdr(priv, flow);
900 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
901 struct mlx5e_encap_entry *e)
903 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
904 struct mlx5_esw_flow_attr *esw_attr;
905 struct mlx5e_tc_flow *flow;
908 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
909 e->encap_size, e->encap_header,
912 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
916 e->flags |= MLX5_ENCAP_ENTRY_VALID;
917 mlx5e_rep_queue_neigh_stats_work(priv);
919 list_for_each_entry(flow, &e->flows, encap) {
920 esw_attr = flow->esw_attr;
921 esw_attr->encap_id = e->encap_id;
922 flow->rule = mlx5_eswitch_add_offloaded_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
923 if (IS_ERR(flow->rule)) {
924 err = PTR_ERR(flow->rule);
925 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
929 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
933 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
934 struct mlx5e_encap_entry *e)
936 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
937 struct mlx5e_tc_flow *flow;
939 list_for_each_entry(flow, &e->flows, encap) {
940 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
941 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
942 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, flow->esw_attr);
946 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
947 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
948 mlx5_encap_dealloc(priv->mdev, e->encap_id);
952 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
954 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
955 u64 bytes, packets, lastuse = 0;
956 struct mlx5e_tc_flow *flow;
957 struct mlx5e_encap_entry *e;
958 struct mlx5_fc *counter;
959 struct neigh_table *tbl;
960 bool neigh_used = false;
963 if (m_neigh->family == AF_INET)
965 #if IS_ENABLED(CONFIG_IPV6)
966 else if (m_neigh->family == AF_INET6)
972 list_for_each_entry(e, &nhe->encap_list, encap_list) {
973 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
975 list_for_each_entry(flow, &e->flows, encap) {
976 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
977 counter = mlx5_flow_rule_counter(flow->rule);
978 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
979 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
988 nhe->reported_lastuse = jiffies;
990 /* find the relevant neigh according to the cached device and
993 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
995 WARN(1, "The neighbour already freed\n");
999 neigh_event_send(n, NULL);
1004 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1005 struct mlx5e_tc_flow *flow)
1007 struct list_head *next = flow->encap.next;
1009 list_del(&flow->encap);
1010 if (list_empty(next)) {
1011 struct mlx5e_encap_entry *e;
1013 e = list_entry(next, struct mlx5e_encap_entry, flows);
1014 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1016 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1017 mlx5_encap_dealloc(priv->mdev, e->encap_id);
1019 hash_del_rcu(&e->encap_hlist);
1020 kfree(e->encap_header);
1025 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
1026 struct mlx5e_tc_flow *flow)
1028 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1029 mlx5e_tc_del_fdb_flow(priv, flow);
1031 mlx5e_tc_del_nic_flow(priv, flow);
1034 static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
1035 struct tc_cls_flower_offload *f)
1037 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1039 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1041 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1043 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1046 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
1047 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1049 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
1050 struct flow_dissector_key_keyid *key =
1051 skb_flow_dissector_target(f->dissector,
1052 FLOW_DISSECTOR_KEY_ENC_KEYID,
1054 struct flow_dissector_key_keyid *mask =
1055 skb_flow_dissector_target(f->dissector,
1056 FLOW_DISSECTOR_KEY_ENC_KEYID,
1058 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
1059 be32_to_cpu(mask->keyid));
1060 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
1061 be32_to_cpu(key->keyid));
1065 static int parse_tunnel_attr(struct mlx5e_priv *priv,
1066 struct mlx5_flow_spec *spec,
1067 struct tc_cls_flower_offload *f)
1069 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1071 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1074 struct flow_dissector_key_control *enc_control =
1075 skb_flow_dissector_target(f->dissector,
1076 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1079 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
1080 struct flow_dissector_key_ports *key =
1081 skb_flow_dissector_target(f->dissector,
1082 FLOW_DISSECTOR_KEY_ENC_PORTS,
1084 struct flow_dissector_key_ports *mask =
1085 skb_flow_dissector_target(f->dissector,
1086 FLOW_DISSECTOR_KEY_ENC_PORTS,
1088 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1089 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1090 struct net_device *up_dev = uplink_rpriv->netdev;
1091 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
1093 /* Full udp dst port must be given */
1094 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
1095 goto vxlan_match_offload_err;
1097 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
1098 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
1099 parse_vxlan_attr(spec, f);
1101 netdev_warn(priv->netdev,
1102 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
1106 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1107 udp_dport, ntohs(mask->dst));
1108 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1109 udp_dport, ntohs(key->dst));
1111 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1112 udp_sport, ntohs(mask->src));
1113 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1114 udp_sport, ntohs(key->src));
1115 } else { /* udp dst port must be given */
1116 vxlan_match_offload_err:
1117 netdev_warn(priv->netdev,
1118 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
1122 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1123 struct flow_dissector_key_ipv4_addrs *key =
1124 skb_flow_dissector_target(f->dissector,
1125 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1127 struct flow_dissector_key_ipv4_addrs *mask =
1128 skb_flow_dissector_target(f->dissector,
1129 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1131 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1132 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1134 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1135 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1138 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1139 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1141 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1142 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1145 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1146 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
1147 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1148 struct flow_dissector_key_ipv6_addrs *key =
1149 skb_flow_dissector_target(f->dissector,
1150 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1152 struct flow_dissector_key_ipv6_addrs *mask =
1153 skb_flow_dissector_target(f->dissector,
1154 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1157 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1158 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1159 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1160 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1161 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1162 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1164 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1165 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1166 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1167 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1168 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1169 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1171 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1172 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
1175 /* Enforce DMAC when offloading incoming tunneled flows.
1176 * Flow counters require a match on the DMAC.
1178 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1179 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1180 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1181 dmac_47_16), priv->netdev->dev_addr);
1183 /* let software handle IP fragments */
1184 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1185 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1190 static int __parse_cls_flower(struct mlx5e_priv *priv,
1191 struct mlx5_flow_spec *spec,
1192 struct tc_cls_flower_offload *f,
1195 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1197 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1202 *min_inline = MLX5_INLINE_MODE_L2;
1204 if (f->dissector->used_keys &
1205 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1206 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1207 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
1208 BIT(FLOW_DISSECTOR_KEY_VLAN) |
1209 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1210 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
1211 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1212 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1213 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1214 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1215 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
1216 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
1217 BIT(FLOW_DISSECTOR_KEY_TCP) |
1218 BIT(FLOW_DISSECTOR_KEY_IP))) {
1219 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1220 f->dissector->used_keys);
1224 if ((dissector_uses_key(f->dissector,
1225 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1226 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1227 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1228 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1229 struct flow_dissector_key_control *key =
1230 skb_flow_dissector_target(f->dissector,
1231 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1233 switch (key->addr_type) {
1234 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
1235 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
1236 if (parse_tunnel_attr(priv, spec, f))
1243 /* In decap flow, header pointers should point to the inner
1244 * headers, outer header were already set by parse_tunnel_attr
1246 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1248 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1252 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1253 struct flow_dissector_key_control *key =
1254 skb_flow_dissector_target(f->dissector,
1255 FLOW_DISSECTOR_KEY_CONTROL,
1258 struct flow_dissector_key_control *mask =
1259 skb_flow_dissector_target(f->dissector,
1260 FLOW_DISSECTOR_KEY_CONTROL,
1262 addr_type = key->addr_type;
1264 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1265 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1266 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1267 key->flags & FLOW_DIS_IS_FRAGMENT);
1269 /* the HW doesn't need L3 inline to match on frag=no */
1270 if (key->flags & FLOW_DIS_IS_FRAGMENT)
1271 *min_inline = MLX5_INLINE_MODE_IP;
1275 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1276 struct flow_dissector_key_basic *key =
1277 skb_flow_dissector_target(f->dissector,
1278 FLOW_DISSECTOR_KEY_BASIC,
1280 struct flow_dissector_key_basic *mask =
1281 skb_flow_dissector_target(f->dissector,
1282 FLOW_DISSECTOR_KEY_BASIC,
1284 ip_proto = key->ip_proto;
1286 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1287 ntohs(mask->n_proto));
1288 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1289 ntohs(key->n_proto));
1291 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1293 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1297 *min_inline = MLX5_INLINE_MODE_IP;
1300 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1301 struct flow_dissector_key_eth_addrs *key =
1302 skb_flow_dissector_target(f->dissector,
1303 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1305 struct flow_dissector_key_eth_addrs *mask =
1306 skb_flow_dissector_target(f->dissector,
1307 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1310 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1313 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1317 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1320 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1325 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1326 struct flow_dissector_key_vlan *key =
1327 skb_flow_dissector_target(f->dissector,
1328 FLOW_DISSECTOR_KEY_VLAN,
1330 struct flow_dissector_key_vlan *mask =
1331 skb_flow_dissector_target(f->dissector,
1332 FLOW_DISSECTOR_KEY_VLAN,
1334 if (mask->vlan_id || mask->vlan_priority) {
1335 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1336 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
1338 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1339 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
1341 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1342 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
1346 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1347 struct flow_dissector_key_ipv4_addrs *key =
1348 skb_flow_dissector_target(f->dissector,
1349 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1351 struct flow_dissector_key_ipv4_addrs *mask =
1352 skb_flow_dissector_target(f->dissector,
1353 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1356 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1357 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1358 &mask->src, sizeof(mask->src));
1359 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1360 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1361 &key->src, sizeof(key->src));
1362 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1363 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1364 &mask->dst, sizeof(mask->dst));
1365 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1366 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1367 &key->dst, sizeof(key->dst));
1369 if (mask->src || mask->dst)
1370 *min_inline = MLX5_INLINE_MODE_IP;
1373 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1374 struct flow_dissector_key_ipv6_addrs *key =
1375 skb_flow_dissector_target(f->dissector,
1376 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1378 struct flow_dissector_key_ipv6_addrs *mask =
1379 skb_flow_dissector_target(f->dissector,
1380 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1383 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1384 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1385 &mask->src, sizeof(mask->src));
1386 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1387 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1388 &key->src, sizeof(key->src));
1390 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1391 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1392 &mask->dst, sizeof(mask->dst));
1393 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1394 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1395 &key->dst, sizeof(key->dst));
1397 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1398 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
1399 *min_inline = MLX5_INLINE_MODE_IP;
1402 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1403 struct flow_dissector_key_ip *key =
1404 skb_flow_dissector_target(f->dissector,
1405 FLOW_DISSECTOR_KEY_IP,
1407 struct flow_dissector_key_ip *mask =
1408 skb_flow_dissector_target(f->dissector,
1409 FLOW_DISSECTOR_KEY_IP,
1412 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1413 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1415 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1416 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1418 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1419 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1422 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
1423 ft_field_support.outer_ipv4_ttl))
1426 if (mask->tos || mask->ttl)
1427 *min_inline = MLX5_INLINE_MODE_IP;
1430 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1431 struct flow_dissector_key_ports *key =
1432 skb_flow_dissector_target(f->dissector,
1433 FLOW_DISSECTOR_KEY_PORTS,
1435 struct flow_dissector_key_ports *mask =
1436 skb_flow_dissector_target(f->dissector,
1437 FLOW_DISSECTOR_KEY_PORTS,
1441 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1442 tcp_sport, ntohs(mask->src));
1443 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1444 tcp_sport, ntohs(key->src));
1446 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1447 tcp_dport, ntohs(mask->dst));
1448 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1449 tcp_dport, ntohs(key->dst));
1453 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1454 udp_sport, ntohs(mask->src));
1455 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1456 udp_sport, ntohs(key->src));
1458 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1459 udp_dport, ntohs(mask->dst));
1460 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1461 udp_dport, ntohs(key->dst));
1464 netdev_err(priv->netdev,
1465 "Only UDP and TCP transport are supported\n");
1469 if (mask->src || mask->dst)
1470 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
1473 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1474 struct flow_dissector_key_tcp *key =
1475 skb_flow_dissector_target(f->dissector,
1476 FLOW_DISSECTOR_KEY_TCP,
1478 struct flow_dissector_key_tcp *mask =
1479 skb_flow_dissector_target(f->dissector,
1480 FLOW_DISSECTOR_KEY_TCP,
1483 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1484 ntohs(mask->flags));
1485 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1489 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
1495 static int parse_cls_flower(struct mlx5e_priv *priv,
1496 struct mlx5e_tc_flow *flow,
1497 struct mlx5_flow_spec *spec,
1498 struct tc_cls_flower_offload *f)
1500 struct mlx5_core_dev *dev = priv->mdev;
1501 struct mlx5_eswitch *esw = dev->priv.eswitch;
1502 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1503 struct mlx5_eswitch_rep *rep;
1507 err = __parse_cls_flower(priv, spec, f, &min_inline);
1509 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1511 if (rep->vport != FDB_UPLINK_VPORT &&
1512 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
1513 esw->offloads.inline_mode < min_inline)) {
1514 netdev_warn(priv->netdev,
1515 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
1516 min_inline, esw->offloads.inline_mode);
1524 struct pedit_headers {
1532 static int pedit_header_offsets[] = {
1533 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1534 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1535 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1536 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1537 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1540 #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1542 static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1543 struct pedit_headers *masks,
1544 struct pedit_headers *vals)
1546 u32 *curr_pmask, *curr_pval;
1548 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1551 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1552 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1554 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1557 *curr_pmask |= mask;
1558 *curr_pval |= (val & mask);
1566 struct mlx5_fields {
1572 #define OFFLOAD(fw_field, size, field, off) \
1573 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1575 static struct mlx5_fields fields[] = {
1576 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1577 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1578 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1579 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1580 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1581 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1583 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1584 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1585 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1587 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1588 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1589 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1590 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1591 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1592 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1593 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1594 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
1595 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
1597 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1598 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1599 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1601 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1602 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
1605 /* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1606 * max from the SW pedit action. On success, it says how many HW actions were
1609 static int offload_pedit_fields(struct pedit_headers *masks,
1610 struct pedit_headers *vals,
1611 struct mlx5e_tc_flow_parse_attr *parse_attr)
1613 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
1614 int i, action_size, nactions, max_actions, first, last, next_z;
1615 void *s_masks_p, *a_masks_p, *vals_p;
1616 struct mlx5_fields *f;
1617 u8 cmd, field_bsize;
1624 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1625 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1626 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1627 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1629 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1630 action = parse_attr->mod_hdr_actions;
1631 max_actions = parse_attr->num_mod_hdr_actions;
1634 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1636 /* avoid seeing bits set from previous iterations */
1640 s_masks_p = (void *)set_masks + f->offset;
1641 a_masks_p = (void *)add_masks + f->offset;
1643 memcpy(&s_mask, s_masks_p, f->size);
1644 memcpy(&a_mask, a_masks_p, f->size);
1646 if (!s_mask && !a_mask) /* nothing to offload here */
1649 if (s_mask && a_mask) {
1650 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1654 if (nactions == max_actions) {
1655 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1660 cmd = MLX5_ACTION_TYPE_SET;
1662 vals_p = (void *)set_vals + f->offset;
1663 /* clear to denote we consumed this field */
1664 memset(s_masks_p, 0, f->size);
1666 cmd = MLX5_ACTION_TYPE_ADD;
1668 vals_p = (void *)add_vals + f->offset;
1669 /* clear to denote we consumed this field */
1670 memset(a_masks_p, 0, f->size);
1673 field_bsize = f->size * BITS_PER_BYTE;
1675 if (field_bsize == 32) {
1676 mask_be32 = *(__be32 *)&mask;
1677 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1678 } else if (field_bsize == 16) {
1679 mask_be16 = *(__be16 *)&mask;
1680 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1683 first = find_first_bit(&mask, field_bsize);
1684 next_z = find_next_zero_bit(&mask, field_bsize, first);
1685 last = find_last_bit(&mask, field_bsize);
1686 if (first < next_z && next_z < last) {
1687 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
1692 MLX5_SET(set_action_in, action, action_type, cmd);
1693 MLX5_SET(set_action_in, action, field, f->field);
1695 if (cmd == MLX5_ACTION_TYPE_SET) {
1696 MLX5_SET(set_action_in, action, offset, first);
1697 /* length is num of bits to be written, zero means length of 32 */
1698 MLX5_SET(set_action_in, action, length, (last - first + 1));
1701 if (field_bsize == 32)
1702 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
1703 else if (field_bsize == 16)
1704 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
1705 else if (field_bsize == 8)
1706 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
1708 action += action_size;
1712 parse_attr->num_mod_hdr_actions = nactions;
1716 static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1717 const struct tc_action *a, int namespace,
1718 struct mlx5e_tc_flow_parse_attr *parse_attr)
1720 int nkeys, action_size, max_actions;
1722 nkeys = tcf_pedit_nkeys(a);
1723 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1725 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1726 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1727 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1728 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1730 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1731 max_actions = min(max_actions, nkeys * 16);
1733 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1734 if (!parse_attr->mod_hdr_actions)
1737 parse_attr->num_mod_hdr_actions = max_actions;
1741 static const struct pedit_headers zero_masks = {};
1743 static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1744 const struct tc_action *a, int namespace,
1745 struct mlx5e_tc_flow_parse_attr *parse_attr)
1747 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1748 int nkeys, i, err = -EOPNOTSUPP;
1749 u32 mask, val, offset;
1752 nkeys = tcf_pedit_nkeys(a);
1754 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1755 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1757 for (i = 0; i < nkeys; i++) {
1758 htype = tcf_pedit_htype(a, i);
1759 cmd = tcf_pedit_cmd(a, i);
1760 err = -EOPNOTSUPP; /* can't be all optimistic */
1762 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
1763 printk(KERN_WARNING "mlx5: legacy pedit isn't offloaded\n");
1767 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
1768 printk(KERN_WARNING "mlx5: pedit cmd %d isn't offloaded\n", cmd);
1772 mask = tcf_pedit_mask(a, i);
1773 val = tcf_pedit_val(a, i);
1774 offset = tcf_pedit_offset(a, i);
1776 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1781 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1785 err = offload_pedit_fields(masks, vals, parse_attr);
1787 goto out_dealloc_parsed_actions;
1789 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1790 cmd_masks = &masks[cmd];
1791 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
1792 printk(KERN_WARNING "mlx5: attempt to offload an unsupported field (cmd %d)\n",
1794 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1795 16, 1, cmd_masks, sizeof(zero_masks), true);
1797 goto out_dealloc_parsed_actions;
1803 out_dealloc_parsed_actions:
1804 kfree(parse_attr->mod_hdr_actions);
1809 static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
1811 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
1812 TCA_CSUM_UPDATE_FLAG_UDP;
1814 /* The HW recalcs checksums only if re-writing headers */
1815 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
1816 netdev_warn(priv->netdev,
1817 "TC csum action is only offloaded with pedit\n");
1821 if (update_flags & ~prot_flags) {
1822 netdev_warn(priv->netdev,
1823 "can't offload TC csum action for some header/s - flags %#x\n",
1831 static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
1832 struct tcf_exts *exts)
1834 const struct tc_action *a;
1835 bool modify_ip_header;
1842 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1843 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1845 /* for non-IP we only re-write MACs, so we're okay */
1846 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
1849 modify_ip_header = false;
1850 tcf_exts_to_list(exts, &actions);
1851 list_for_each_entry(a, &actions, list) {
1852 if (!is_tcf_pedit(a))
1855 nkeys = tcf_pedit_nkeys(a);
1856 for (i = 0; i < nkeys; i++) {
1857 htype = tcf_pedit_htype(a, i);
1858 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
1859 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
1860 modify_ip_header = true;
1866 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1867 if (modify_ip_header && ip_proto != IPPROTO_TCP && ip_proto != IPPROTO_UDP) {
1868 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
1876 static bool actions_match_supported(struct mlx5e_priv *priv,
1877 struct tcf_exts *exts,
1878 struct mlx5e_tc_flow_parse_attr *parse_attr,
1879 struct mlx5e_tc_flow *flow)
1883 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1884 actions = flow->esw_attr->action;
1886 actions = flow->nic_attr->action;
1888 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1889 return modify_header_match_supported(&parse_attr->spec, exts);
1894 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
1896 struct mlx5_core_dev *fmdev, *pmdev;
1897 u16 func_id, peer_id;
1900 pmdev = peer_priv->mdev;
1902 func_id = (u16)((fmdev->pdev->bus->number << 8) | PCI_SLOT(fmdev->pdev->devfn));
1903 peer_id = (u16)((pmdev->pdev->bus->number << 8) | PCI_SLOT(pmdev->pdev->devfn));
1905 return (func_id == peer_id);
1908 static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
1909 struct mlx5e_tc_flow_parse_attr *parse_attr,
1910 struct mlx5e_tc_flow *flow)
1912 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
1913 const struct tc_action *a;
1917 if (!tcf_exts_has_actions(exts))
1920 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
1923 tcf_exts_to_list(exts, &actions);
1924 list_for_each_entry(a, &actions, list) {
1925 if (is_tcf_gact_shot(a)) {
1926 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
1927 if (MLX5_CAP_FLOWTABLE(priv->mdev,
1928 flow_table_properties_nic_receive.flow_counter))
1929 attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
1933 if (is_tcf_pedit(a)) {
1934 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
1939 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
1940 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1944 if (is_tcf_csum(a)) {
1945 if (csum_offload_supported(priv, attr->action,
1946 tcf_csum_update_flags(a)))
1952 if (is_tcf_mirred_egress_redirect(a)) {
1953 struct net_device *peer_dev = tcf_mirred_dev(a);
1955 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
1956 same_hw_devs(priv, netdev_priv(peer_dev))) {
1957 parse_attr->mirred_ifindex = peer_dev->ifindex;
1958 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1959 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1960 MLX5_FLOW_CONTEXT_ACTION_COUNT;
1962 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
1969 if (is_tcf_skbedit_mark(a)) {
1970 u32 mark = tcf_skbedit_mark(a);
1972 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
1973 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
1978 attr->flow_tag = mark;
1979 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1986 if (!actions_match_supported(priv, exts, parse_attr, flow))
1992 static inline int cmp_encap_info(struct ip_tunnel_key *a,
1993 struct ip_tunnel_key *b)
1995 return memcmp(a, b, sizeof(*a));
1998 static inline int hash_encap_info(struct ip_tunnel_key *key)
2000 return jhash(key, sizeof(*key), 0);
2003 static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
2004 struct net_device *mirred_dev,
2005 struct net_device **out_dev,
2007 struct neighbour **out_n,
2010 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2011 struct mlx5e_rep_priv *uplink_rpriv;
2013 struct neighbour *n = NULL;
2015 #if IS_ENABLED(CONFIG_INET)
2018 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
2019 ret = PTR_ERR_OR_ZERO(rt);
2025 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2026 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2027 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
2028 *out_dev = uplink_rpriv->netdev;
2030 *out_dev = rt->dst.dev;
2032 *out_ttl = ip4_dst_hoplimit(&rt->dst);
2033 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
2042 static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
2043 struct net_device *mirred_dev,
2044 struct net_device **out_dev,
2046 struct neighbour **out_n,
2049 struct neighbour *n = NULL;
2050 struct dst_entry *dst;
2052 #if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
2053 struct mlx5e_rep_priv *uplink_rpriv;
2054 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2057 ret = ipv6_stub->ipv6_dst_lookup(dev_net(mirred_dev), NULL, &dst,
2062 *out_ttl = ip6_dst_hoplimit(dst);
2064 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2065 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2066 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
2067 *out_dev = uplink_rpriv->netdev;
2069 *out_dev = dst->dev;
2074 n = dst_neigh_lookup(dst, &fl6->daddr);
2083 static void gen_vxlan_header_ipv4(struct net_device *out_dev,
2084 char buf[], int encap_size,
2085 unsigned char h_dest[ETH_ALEN],
2089 __be16 udp_dst_port,
2092 struct ethhdr *eth = (struct ethhdr *)buf;
2093 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
2094 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
2095 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2097 memset(buf, 0, encap_size);
2099 ether_addr_copy(eth->h_dest, h_dest);
2100 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2101 eth->h_proto = htons(ETH_P_IP);
2107 ip->protocol = IPPROTO_UDP;
2111 udp->dest = udp_dst_port;
2112 vxh->vx_flags = VXLAN_HF_VNI;
2113 vxh->vx_vni = vxlan_vni_field(vx_vni);
2116 static void gen_vxlan_header_ipv6(struct net_device *out_dev,
2117 char buf[], int encap_size,
2118 unsigned char h_dest[ETH_ALEN],
2120 struct in6_addr *daddr,
2121 struct in6_addr *saddr,
2122 __be16 udp_dst_port,
2125 struct ethhdr *eth = (struct ethhdr *)buf;
2126 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
2127 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
2128 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2130 memset(buf, 0, encap_size);
2132 ether_addr_copy(eth->h_dest, h_dest);
2133 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2134 eth->h_proto = htons(ETH_P_IPV6);
2136 ip6_flow_hdr(ip6h, 0, 0);
2137 /* the HW fills up ipv6 payload len */
2138 ip6h->nexthdr = IPPROTO_UDP;
2139 ip6h->hop_limit = ttl;
2140 ip6h->daddr = *daddr;
2141 ip6h->saddr = *saddr;
2143 udp->dest = udp_dst_port;
2144 vxh->vx_flags = VXLAN_HF_VNI;
2145 vxh->vx_vni = vxlan_vni_field(vx_vni);
2148 static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
2149 struct net_device *mirred_dev,
2150 struct mlx5e_encap_entry *e)
2152 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
2153 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
2154 struct ip_tunnel_key *tun_key = &e->tun_info.key;
2155 struct net_device *out_dev;
2156 struct neighbour *n = NULL;
2157 struct flowi4 fl4 = {};
2162 if (max_encap_size < ipv4_encap_size) {
2163 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2164 ipv4_encap_size, max_encap_size);
2168 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
2172 switch (e->tunnel_type) {
2173 case MLX5_HEADER_TYPE_VXLAN:
2174 fl4.flowi4_proto = IPPROTO_UDP;
2175 fl4.fl4_dport = tun_key->tp_dst;
2181 fl4.flowi4_tos = tun_key->tos;
2182 fl4.daddr = tun_key->u.ipv4.dst;
2183 fl4.saddr = tun_key->u.ipv4.src;
2185 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
2190 /* used by mlx5e_detach_encap to lookup a neigh hash table
2191 * entry in the neigh hash table when a user deletes a rule
2193 e->m_neigh.dev = n->dev;
2194 e->m_neigh.family = n->ops->family;
2195 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2196 e->out_dev = out_dev;
2198 /* It's importent to add the neigh to the hash table before checking
2199 * the neigh validity state. So if we'll get a notification, in case the
2200 * neigh changes it's validity state, we would find the relevant neigh
2203 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2207 read_lock_bh(&n->lock);
2208 nud_state = n->nud_state;
2209 ether_addr_copy(e->h_dest, n->ha);
2210 read_unlock_bh(&n->lock);
2212 switch (e->tunnel_type) {
2213 case MLX5_HEADER_TYPE_VXLAN:
2214 gen_vxlan_header_ipv4(out_dev, encap_header,
2215 ipv4_encap_size, e->h_dest, ttl,
2217 fl4.saddr, tun_key->tp_dst,
2218 tunnel_id_to_key32(tun_key->tun_id));
2222 goto destroy_neigh_entry;
2224 e->encap_size = ipv4_encap_size;
2225 e->encap_header = encap_header;
2227 if (!(nud_state & NUD_VALID)) {
2228 neigh_event_send(n, NULL);
2233 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
2234 ipv4_encap_size, encap_header, &e->encap_id);
2236 goto destroy_neigh_entry;
2238 e->flags |= MLX5_ENCAP_ENTRY_VALID;
2239 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
2243 destroy_neigh_entry:
2244 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
2246 kfree(encap_header);
2253 static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
2254 struct net_device *mirred_dev,
2255 struct mlx5e_encap_entry *e)
2257 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
2258 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
2259 struct ip_tunnel_key *tun_key = &e->tun_info.key;
2260 struct net_device *out_dev;
2261 struct neighbour *n = NULL;
2262 struct flowi6 fl6 = {};
2267 if (max_encap_size < ipv6_encap_size) {
2268 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2269 ipv6_encap_size, max_encap_size);
2273 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
2277 switch (e->tunnel_type) {
2278 case MLX5_HEADER_TYPE_VXLAN:
2279 fl6.flowi6_proto = IPPROTO_UDP;
2280 fl6.fl6_dport = tun_key->tp_dst;
2287 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
2288 fl6.daddr = tun_key->u.ipv6.dst;
2289 fl6.saddr = tun_key->u.ipv6.src;
2291 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
2296 /* used by mlx5e_detach_encap to lookup a neigh hash table
2297 * entry in the neigh hash table when a user deletes a rule
2299 e->m_neigh.dev = n->dev;
2300 e->m_neigh.family = n->ops->family;
2301 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2302 e->out_dev = out_dev;
2304 /* It's importent to add the neigh to the hash table before checking
2305 * the neigh validity state. So if we'll get a notification, in case the
2306 * neigh changes it's validity state, we would find the relevant neigh
2309 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2313 read_lock_bh(&n->lock);
2314 nud_state = n->nud_state;
2315 ether_addr_copy(e->h_dest, n->ha);
2316 read_unlock_bh(&n->lock);
2318 switch (e->tunnel_type) {
2319 case MLX5_HEADER_TYPE_VXLAN:
2320 gen_vxlan_header_ipv6(out_dev, encap_header,
2321 ipv6_encap_size, e->h_dest, ttl,
2323 &fl6.saddr, tun_key->tp_dst,
2324 tunnel_id_to_key32(tun_key->tun_id));
2328 goto destroy_neigh_entry;
2331 e->encap_size = ipv6_encap_size;
2332 e->encap_header = encap_header;
2334 if (!(nud_state & NUD_VALID)) {
2335 neigh_event_send(n, NULL);
2340 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
2341 ipv6_encap_size, encap_header, &e->encap_id);
2343 goto destroy_neigh_entry;
2345 e->flags |= MLX5_ENCAP_ENTRY_VALID;
2346 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
2350 destroy_neigh_entry:
2351 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
2353 kfree(encap_header);
2360 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2361 struct ip_tunnel_info *tun_info,
2362 struct net_device *mirred_dev,
2363 struct net_device **encap_dev,
2364 struct mlx5e_tc_flow *flow)
2366 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2367 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw,
2369 struct net_device *up_dev = uplink_rpriv->netdev;
2370 unsigned short family = ip_tunnel_info_af(tun_info);
2371 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
2372 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2373 struct ip_tunnel_key *key = &tun_info->key;
2374 struct mlx5e_encap_entry *e;
2375 int tunnel_type, err = 0;
2379 /* udp dst port must be set */
2380 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2381 goto vxlan_encap_offload_err;
2383 /* setting udp src port isn't supported */
2384 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
2385 vxlan_encap_offload_err:
2386 netdev_warn(priv->netdev,
2387 "must set udp dst port and not set udp src port\n");
2391 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
2392 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
2393 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
2395 netdev_warn(priv->netdev,
2396 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
2400 hash_key = hash_encap_info(key);
2402 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2403 encap_hlist, hash_key) {
2404 if (!cmp_encap_info(&e->tun_info.key, key)) {
2410 /* must verify if encap is valid or not */
2414 e = kzalloc(sizeof(*e), GFP_KERNEL);
2418 e->tun_info = *tun_info;
2419 e->tunnel_type = tunnel_type;
2420 INIT_LIST_HEAD(&e->flows);
2422 if (family == AF_INET)
2423 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
2424 else if (family == AF_INET6)
2425 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
2427 if (err && err != -EAGAIN)
2430 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2433 list_add(&flow->encap, &e->flows);
2434 *encap_dev = e->out_dev;
2435 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2436 attr->encap_id = e->encap_id;
2447 static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
2448 struct mlx5e_tc_flow_parse_attr *parse_attr,
2449 struct mlx5e_tc_flow *flow)
2451 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2452 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2453 struct ip_tunnel_info *info = NULL;
2454 const struct tc_action *a;
2459 if (!tcf_exts_has_actions(exts))
2462 memset(attr, 0, sizeof(*attr));
2463 attr->in_rep = rpriv->rep;
2465 tcf_exts_to_list(exts, &actions);
2466 list_for_each_entry(a, &actions, list) {
2467 if (is_tcf_gact_shot(a)) {
2468 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2469 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2473 if (is_tcf_pedit(a)) {
2474 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
2479 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2483 if (is_tcf_csum(a)) {
2484 if (csum_offload_supported(priv, attr->action,
2485 tcf_csum_update_flags(a)))
2491 if (is_tcf_mirred_egress_redirect(a)) {
2492 struct net_device *out_dev;
2493 struct mlx5e_priv *out_priv;
2495 out_dev = tcf_mirred_dev(a);
2497 if (switchdev_port_same_parent_id(priv->netdev,
2499 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2500 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2501 out_priv = netdev_priv(out_dev);
2502 rpriv = out_priv->ppriv;
2503 attr->out_rep = rpriv->rep;
2505 parse_attr->mirred_ifindex = out_dev->ifindex;
2506 parse_attr->tun_info = *info;
2507 attr->parse_attr = parse_attr;
2508 attr->action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
2509 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2510 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2511 /* attr->out_rep is resolved when we handle encap */
2513 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2514 priv->netdev->name, out_dev->name);
2520 if (is_tcf_tunnel_set(a)) {
2521 info = tcf_tunnel_info(a);
2529 if (is_tcf_vlan(a)) {
2530 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
2531 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2532 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
2533 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
2534 attr->vlan_vid = tcf_vlan_push_vid(a);
2535 if (mlx5_eswitch_vlan_actions_supported(priv->mdev)) {
2536 attr->vlan_prio = tcf_vlan_push_prio(a);
2537 attr->vlan_proto = tcf_vlan_push_proto(a);
2538 if (!attr->vlan_proto)
2539 attr->vlan_proto = htons(ETH_P_8021Q);
2540 } else if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2541 tcf_vlan_push_prio(a)) {
2544 } else { /* action is TCA_VLAN_ACT_MODIFY */
2550 if (is_tcf_tunnel_release(a)) {
2551 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2558 if (!actions_match_supported(priv, exts, parse_attr, flow))
2564 int mlx5e_configure_flower(struct mlx5e_priv *priv,
2565 struct tc_cls_flower_offload *f)
2567 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2568 struct mlx5e_tc_flow_parse_attr *parse_attr;
2569 struct mlx5e_tc_table *tc = &priv->fs.tc;
2570 struct mlx5e_tc_flow *flow;
2571 int attr_size, err = 0;
2574 if (esw && esw->mode == SRIOV_OFFLOADS) {
2575 flow_flags = MLX5E_TC_FLOW_ESWITCH;
2576 attr_size = sizeof(struct mlx5_esw_flow_attr);
2578 flow_flags = MLX5E_TC_FLOW_NIC;
2579 attr_size = sizeof(struct mlx5_nic_flow_attr);
2582 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
2583 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
2584 if (!parse_attr || !flow) {
2589 flow->cookie = f->cookie;
2590 flow->flags = flow_flags;
2592 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
2596 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
2597 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
2600 flow->rule = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
2602 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
2605 flow->rule = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
2608 if (IS_ERR(flow->rule)) {
2609 err = PTR_ERR(flow->rule);
2615 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2617 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
2618 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
2621 err = rhashtable_insert_fast(&tc->ht, &flow->node,
2624 mlx5e_tc_del_flow(priv, flow);
2636 int mlx5e_delete_flower(struct mlx5e_priv *priv,
2637 struct tc_cls_flower_offload *f)
2639 struct mlx5e_tc_flow *flow;
2640 struct mlx5e_tc_table *tc = &priv->fs.tc;
2642 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2647 rhashtable_remove_fast(&tc->ht, &flow->node, tc->ht_params);
2649 mlx5e_tc_del_flow(priv, flow);
2656 int mlx5e_stats_flower(struct mlx5e_priv *priv,
2657 struct tc_cls_flower_offload *f)
2659 struct mlx5e_tc_table *tc = &priv->fs.tc;
2660 struct mlx5e_tc_flow *flow;
2661 struct mlx5_fc *counter;
2666 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2671 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
2674 counter = mlx5_flow_rule_counter(flow->rule);
2678 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
2680 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
2685 static const struct rhashtable_params mlx5e_tc_flow_ht_params = {
2686 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2687 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2688 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2689 .automatic_shrinking = true,
2692 int mlx5e_tc_init(struct mlx5e_priv *priv)
2694 struct mlx5e_tc_table *tc = &priv->fs.tc;
2696 hash_init(tc->mod_hdr_tbl);
2697 hash_init(tc->hairpin_tbl);
2699 tc->ht_params = mlx5e_tc_flow_ht_params;
2700 return rhashtable_init(&tc->ht, &tc->ht_params);
2703 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
2705 struct mlx5e_tc_flow *flow = ptr;
2706 struct mlx5e_priv *priv = arg;
2708 mlx5e_tc_del_flow(priv, flow);
2712 void mlx5e_tc_cleanup(struct mlx5e_priv *priv)
2714 struct mlx5e_tc_table *tc = &priv->fs.tc;
2716 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, priv);
2718 if (!IS_ERR_OR_NULL(tc->t)) {
2719 mlx5_destroy_flow_table(tc->t);