net/mlx5e: Apply the correct check for supporting TC esw rules split
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
1 /*
2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <net/flow_dissector.h>
34 #include <net/sch_generic.h>
35 #include <net/pkt_cls.h>
36 #include <net/tc_act/tc_gact.h>
37 #include <net/tc_act/tc_skbedit.h>
38 #include <linux/mlx5/fs.h>
39 #include <linux/mlx5/device.h>
40 #include <linux/rhashtable.h>
41 #include <net/switchdev.h>
42 #include <net/tc_act/tc_mirred.h>
43 #include <net/tc_act/tc_vlan.h>
44 #include <net/tc_act/tc_tunnel_key.h>
45 #include <net/tc_act/tc_pedit.h>
46 #include <net/tc_act/tc_csum.h>
47 #include <net/vxlan.h>
48 #include <net/arp.h>
49 #include "en.h"
50 #include "en_rep.h"
51 #include "en_tc.h"
52 #include "eswitch.h"
53 #include "lib/vxlan.h"
54 #include "fs_core.h"
55 #include "en/port.h"
56
57 struct mlx5_nic_flow_attr {
58         u32 action;
59         u32 flow_tag;
60         u32 mod_hdr_id;
61         u32 hairpin_tirn;
62         u8 match_level;
63         struct mlx5_flow_table  *hairpin_ft;
64         struct mlx5_fc          *counter;
65 };
66
67 #define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
68
69 enum {
70         MLX5E_TC_FLOW_INGRESS   = MLX5E_TC_INGRESS,
71         MLX5E_TC_FLOW_EGRESS    = MLX5E_TC_EGRESS,
72         MLX5E_TC_FLOW_ESWITCH   = BIT(MLX5E_TC_FLOW_BASE),
73         MLX5E_TC_FLOW_NIC       = BIT(MLX5E_TC_FLOW_BASE + 1),
74         MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE + 2),
75         MLX5E_TC_FLOW_HAIRPIN   = BIT(MLX5E_TC_FLOW_BASE + 3),
76         MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 4),
77         MLX5E_TC_FLOW_SLOW        = BIT(MLX5E_TC_FLOW_BASE + 5),
78 };
79
80 #define MLX5E_TC_MAX_SPLITS 1
81
82 struct mlx5e_tc_flow {
83         struct rhash_head       node;
84         struct mlx5e_priv       *priv;
85         u64                     cookie;
86         u16                     flags;
87         struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
88         struct list_head        encap;   /* flows sharing the same encap ID */
89         struct list_head        mod_hdr; /* flows sharing the same mod hdr ID */
90         struct list_head        hairpin; /* flows sharing the same hairpin */
91         union {
92                 struct mlx5_esw_flow_attr esw_attr[0];
93                 struct mlx5_nic_flow_attr nic_attr[0];
94         };
95 };
96
97 struct mlx5e_tc_flow_parse_attr {
98         struct ip_tunnel_info tun_info;
99         struct mlx5_flow_spec spec;
100         int num_mod_hdr_actions;
101         void *mod_hdr_actions;
102         int mirred_ifindex;
103 };
104
105 #define MLX5E_TC_TABLE_NUM_GROUPS 4
106 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
107
108 struct mlx5e_hairpin {
109         struct mlx5_hairpin *pair;
110
111         struct mlx5_core_dev *func_mdev;
112         struct mlx5e_priv *func_priv;
113         u32 tdn;
114         u32 tirn;
115
116         int num_channels;
117         struct mlx5e_rqt indir_rqt;
118         u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
119         struct mlx5e_ttc_table ttc;
120 };
121
122 struct mlx5e_hairpin_entry {
123         /* a node of a hash table which keeps all the  hairpin entries */
124         struct hlist_node hairpin_hlist;
125
126         /* flows sharing the same hairpin */
127         struct list_head flows;
128
129         u16 peer_vhca_id;
130         u8 prio;
131         struct mlx5e_hairpin *hp;
132 };
133
134 struct mod_hdr_key {
135         int num_actions;
136         void *actions;
137 };
138
139 struct mlx5e_mod_hdr_entry {
140         /* a node of a hash table which keeps all the mod_hdr entries */
141         struct hlist_node mod_hdr_hlist;
142
143         /* flows sharing the same mod_hdr entry */
144         struct list_head flows;
145
146         struct mod_hdr_key key;
147
148         u32 mod_hdr_id;
149 };
150
151 #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
152
153 static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
154 {
155         return jhash(key->actions,
156                      key->num_actions * MLX5_MH_ACT_SZ, 0);
157 }
158
159 static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
160                                    struct mod_hdr_key *b)
161 {
162         if (a->num_actions != b->num_actions)
163                 return 1;
164
165         return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
166 }
167
168 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
169                                 struct mlx5e_tc_flow *flow,
170                                 struct mlx5e_tc_flow_parse_attr *parse_attr)
171 {
172         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
173         int num_actions, actions_size, namespace, err;
174         struct mlx5e_mod_hdr_entry *mh;
175         struct mod_hdr_key key;
176         bool found = false;
177         u32 hash_key;
178
179         num_actions  = parse_attr->num_mod_hdr_actions;
180         actions_size = MLX5_MH_ACT_SZ * num_actions;
181
182         key.actions = parse_attr->mod_hdr_actions;
183         key.num_actions = num_actions;
184
185         hash_key = hash_mod_hdr_info(&key);
186
187         if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
188                 namespace = MLX5_FLOW_NAMESPACE_FDB;
189                 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
190                                        mod_hdr_hlist, hash_key) {
191                         if (!cmp_mod_hdr_info(&mh->key, &key)) {
192                                 found = true;
193                                 break;
194                         }
195                 }
196         } else {
197                 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
198                 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
199                                        mod_hdr_hlist, hash_key) {
200                         if (!cmp_mod_hdr_info(&mh->key, &key)) {
201                                 found = true;
202                                 break;
203                         }
204                 }
205         }
206
207         if (found)
208                 goto attach_flow;
209
210         mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
211         if (!mh)
212                 return -ENOMEM;
213
214         mh->key.actions = (void *)mh + sizeof(*mh);
215         memcpy(mh->key.actions, key.actions, actions_size);
216         mh->key.num_actions = num_actions;
217         INIT_LIST_HEAD(&mh->flows);
218
219         err = mlx5_modify_header_alloc(priv->mdev, namespace,
220                                        mh->key.num_actions,
221                                        mh->key.actions,
222                                        &mh->mod_hdr_id);
223         if (err)
224                 goto out_err;
225
226         if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
227                 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
228         else
229                 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
230
231 attach_flow:
232         list_add(&flow->mod_hdr, &mh->flows);
233         if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
234                 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
235         else
236                 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
237
238         return 0;
239
240 out_err:
241         kfree(mh);
242         return err;
243 }
244
245 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
246                                  struct mlx5e_tc_flow *flow)
247 {
248         struct list_head *next = flow->mod_hdr.next;
249
250         list_del(&flow->mod_hdr);
251
252         if (list_empty(next)) {
253                 struct mlx5e_mod_hdr_entry *mh;
254
255                 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
256
257                 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
258                 hash_del(&mh->mod_hdr_hlist);
259                 kfree(mh);
260         }
261 }
262
263 static
264 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
265 {
266         struct net_device *netdev;
267         struct mlx5e_priv *priv;
268
269         netdev = __dev_get_by_index(net, ifindex);
270         priv = netdev_priv(netdev);
271         return priv->mdev;
272 }
273
274 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
275 {
276         u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
277         void *tirc;
278         int err;
279
280         err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
281         if (err)
282                 goto alloc_tdn_err;
283
284         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
285
286         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
287         MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
288         MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
289
290         err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
291         if (err)
292                 goto create_tir_err;
293
294         return 0;
295
296 create_tir_err:
297         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
298 alloc_tdn_err:
299         return err;
300 }
301
302 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
303 {
304         mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
305         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
306 }
307
308 static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
309 {
310         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
311         struct mlx5e_priv *priv = hp->func_priv;
312         int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
313
314         mlx5e_build_default_indir_rqt(indirection_rqt, sz,
315                                       hp->num_channels);
316
317         for (i = 0; i < sz; i++) {
318                 ix = i;
319                 if (priv->channels.params.rss_hfunc == ETH_RSS_HASH_XOR)
320                         ix = mlx5e_bits_invert(i, ilog2(sz));
321                 ix = indirection_rqt[ix];
322                 rqn = hp->pair->rqn[ix];
323                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
324         }
325 }
326
327 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
328 {
329         int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
330         struct mlx5e_priv *priv = hp->func_priv;
331         struct mlx5_core_dev *mdev = priv->mdev;
332         void *rqtc;
333         u32 *in;
334
335         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
336         in = kvzalloc(inlen, GFP_KERNEL);
337         if (!in)
338                 return -ENOMEM;
339
340         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
341
342         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
343         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
344
345         mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
346
347         err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
348         if (!err)
349                 hp->indir_rqt.enabled = true;
350
351         kvfree(in);
352         return err;
353 }
354
355 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
356 {
357         struct mlx5e_priv *priv = hp->func_priv;
358         u32 in[MLX5_ST_SZ_DW(create_tir_in)];
359         int tt, i, err;
360         void *tirc;
361
362         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
363                 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
364                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
365
366                 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
367                 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
368                 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
369                 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
370
371                 err = mlx5_core_create_tir(hp->func_mdev, in,
372                                            MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
373                 if (err) {
374                         mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
375                         goto err_destroy_tirs;
376                 }
377         }
378         return 0;
379
380 err_destroy_tirs:
381         for (i = 0; i < tt; i++)
382                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
383         return err;
384 }
385
386 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
387 {
388         int tt;
389
390         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
391                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
392 }
393
394 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
395                                          struct ttc_params *ttc_params)
396 {
397         struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
398         int tt;
399
400         memset(ttc_params, 0, sizeof(*ttc_params));
401
402         ttc_params->any_tt_tirn = hp->tirn;
403
404         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
405                 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
406
407         ft_attr->max_fte = MLX5E_NUM_TT;
408         ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
409         ft_attr->prio = MLX5E_TC_PRIO;
410 }
411
412 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
413 {
414         struct mlx5e_priv *priv = hp->func_priv;
415         struct ttc_params ttc_params;
416         int err;
417
418         err = mlx5e_hairpin_create_indirect_rqt(hp);
419         if (err)
420                 return err;
421
422         err = mlx5e_hairpin_create_indirect_tirs(hp);
423         if (err)
424                 goto err_create_indirect_tirs;
425
426         mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
427         err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
428         if (err)
429                 goto err_create_ttc_table;
430
431         netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
432                    hp->num_channels, hp->ttc.ft.t->id);
433
434         return 0;
435
436 err_create_ttc_table:
437         mlx5e_hairpin_destroy_indirect_tirs(hp);
438 err_create_indirect_tirs:
439         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
440
441         return err;
442 }
443
444 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
445 {
446         struct mlx5e_priv *priv = hp->func_priv;
447
448         mlx5e_destroy_ttc_table(priv, &hp->ttc);
449         mlx5e_hairpin_destroy_indirect_tirs(hp);
450         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
451 }
452
453 static struct mlx5e_hairpin *
454 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
455                      int peer_ifindex)
456 {
457         struct mlx5_core_dev *func_mdev, *peer_mdev;
458         struct mlx5e_hairpin *hp;
459         struct mlx5_hairpin *pair;
460         int err;
461
462         hp = kzalloc(sizeof(*hp), GFP_KERNEL);
463         if (!hp)
464                 return ERR_PTR(-ENOMEM);
465
466         func_mdev = priv->mdev;
467         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
468
469         pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
470         if (IS_ERR(pair)) {
471                 err = PTR_ERR(pair);
472                 goto create_pair_err;
473         }
474         hp->pair = pair;
475         hp->func_mdev = func_mdev;
476         hp->func_priv = priv;
477         hp->num_channels = params->num_channels;
478
479         err = mlx5e_hairpin_create_transport(hp);
480         if (err)
481                 goto create_transport_err;
482
483         if (hp->num_channels > 1) {
484                 err = mlx5e_hairpin_rss_init(hp);
485                 if (err)
486                         goto rss_init_err;
487         }
488
489         return hp;
490
491 rss_init_err:
492         mlx5e_hairpin_destroy_transport(hp);
493 create_transport_err:
494         mlx5_core_hairpin_destroy(hp->pair);
495 create_pair_err:
496         kfree(hp);
497         return ERR_PTR(err);
498 }
499
500 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
501 {
502         if (hp->num_channels > 1)
503                 mlx5e_hairpin_rss_cleanup(hp);
504         mlx5e_hairpin_destroy_transport(hp);
505         mlx5_core_hairpin_destroy(hp->pair);
506         kvfree(hp);
507 }
508
509 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
510 {
511         return (peer_vhca_id << 16 | prio);
512 }
513
514 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
515                                                      u16 peer_vhca_id, u8 prio)
516 {
517         struct mlx5e_hairpin_entry *hpe;
518         u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
519
520         hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
521                                hairpin_hlist, hash_key) {
522                 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
523                         return hpe;
524         }
525
526         return NULL;
527 }
528
529 #define UNKNOWN_MATCH_PRIO 8
530
531 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
532                                   struct mlx5_flow_spec *spec, u8 *match_prio,
533                                   struct netlink_ext_ack *extack)
534 {
535         void *headers_c, *headers_v;
536         u8 prio_val, prio_mask = 0;
537         bool vlan_present;
538
539 #ifdef CONFIG_MLX5_CORE_EN_DCB
540         if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
541                 NL_SET_ERR_MSG_MOD(extack,
542                                    "only PCP trust state supported for hairpin");
543                 return -EOPNOTSUPP;
544         }
545 #endif
546         headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
547         headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
548
549         vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
550         if (vlan_present) {
551                 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
552                 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
553         }
554
555         if (!vlan_present || !prio_mask) {
556                 prio_val = UNKNOWN_MATCH_PRIO;
557         } else if (prio_mask != 0x7) {
558                 NL_SET_ERR_MSG_MOD(extack,
559                                    "masked priority match not supported for hairpin");
560                 return -EOPNOTSUPP;
561         }
562
563         *match_prio = prio_val;
564         return 0;
565 }
566
567 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
568                                   struct mlx5e_tc_flow *flow,
569                                   struct mlx5e_tc_flow_parse_attr *parse_attr,
570                                   struct netlink_ext_ack *extack)
571 {
572         int peer_ifindex = parse_attr->mirred_ifindex;
573         struct mlx5_hairpin_params params;
574         struct mlx5_core_dev *peer_mdev;
575         struct mlx5e_hairpin_entry *hpe;
576         struct mlx5e_hairpin *hp;
577         u64 link_speed64;
578         u32 link_speed;
579         u8 match_prio;
580         u16 peer_id;
581         int err;
582
583         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
584         if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
585                 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
586                 return -EOPNOTSUPP;
587         }
588
589         peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
590         err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
591                                      extack);
592         if (err)
593                 return err;
594         hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
595         if (hpe)
596                 goto attach_flow;
597
598         hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
599         if (!hpe)
600                 return -ENOMEM;
601
602         INIT_LIST_HEAD(&hpe->flows);
603         hpe->peer_vhca_id = peer_id;
604         hpe->prio = match_prio;
605
606         params.log_data_size = 15;
607         params.log_data_size = min_t(u8, params.log_data_size,
608                                      MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
609         params.log_data_size = max_t(u8, params.log_data_size,
610                                      MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
611
612         params.log_num_packets = params.log_data_size -
613                                  MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
614         params.log_num_packets = min_t(u8, params.log_num_packets,
615                                        MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
616
617         params.q_counter = priv->q_counter;
618         /* set hairpin pair per each 50Gbs share of the link */
619         mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
620         link_speed = max_t(u32, link_speed, 50000);
621         link_speed64 = link_speed;
622         do_div(link_speed64, 50000);
623         params.num_channels = link_speed64;
624
625         hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
626         if (IS_ERR(hp)) {
627                 err = PTR_ERR(hp);
628                 goto create_hairpin_err;
629         }
630
631         netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
632                    hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
633                    hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
634
635         hpe->hp = hp;
636         hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
637                  hash_hairpin_info(peer_id, match_prio));
638
639 attach_flow:
640         if (hpe->hp->num_channels > 1) {
641                 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
642                 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
643         } else {
644                 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
645         }
646         list_add(&flow->hairpin, &hpe->flows);
647
648         return 0;
649
650 create_hairpin_err:
651         kfree(hpe);
652         return err;
653 }
654
655 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
656                                    struct mlx5e_tc_flow *flow)
657 {
658         struct list_head *next = flow->hairpin.next;
659
660         list_del(&flow->hairpin);
661
662         /* no more hairpin flows for us, release the hairpin pair */
663         if (list_empty(next)) {
664                 struct mlx5e_hairpin_entry *hpe;
665
666                 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
667
668                 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
669                            hpe->hp->pair->peer_mdev->priv.name);
670
671                 mlx5e_hairpin_destroy(hpe->hp);
672                 hash_del(&hpe->hairpin_hlist);
673                 kfree(hpe);
674         }
675 }
676
677 static int
678 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
679                       struct mlx5e_tc_flow_parse_attr *parse_attr,
680                       struct mlx5e_tc_flow *flow,
681                       struct netlink_ext_ack *extack)
682 {
683         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
684         struct mlx5_core_dev *dev = priv->mdev;
685         struct mlx5_flow_destination dest[2] = {};
686         struct mlx5_flow_act flow_act = {
687                 .action = attr->action,
688                 .flow_tag = attr->flow_tag,
689                 .reformat_id = 0,
690                 .flags    = FLOW_ACT_HAS_TAG | FLOW_ACT_NO_APPEND,
691         };
692         struct mlx5_fc *counter = NULL;
693         bool table_created = false;
694         int err, dest_ix = 0;
695
696         if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
697                 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
698                 if (err) {
699                         goto err_add_hairpin_flow;
700                 }
701                 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
702                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
703                         dest[dest_ix].ft = attr->hairpin_ft;
704                 } else {
705                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
706                         dest[dest_ix].tir_num = attr->hairpin_tirn;
707                 }
708                 dest_ix++;
709         } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
710                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
711                 dest[dest_ix].ft = priv->fs.vlan.ft.t;
712                 dest_ix++;
713         }
714
715         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
716                 counter = mlx5_fc_create(dev, true);
717                 if (IS_ERR(counter)) {
718                         err = PTR_ERR(counter);
719                         goto err_fc_create;
720                 }
721                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
722                 dest[dest_ix].counter_id = mlx5_fc_id(counter);
723                 dest_ix++;
724                 attr->counter = counter;
725         }
726
727         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
728                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
729                 flow_act.modify_id = attr->mod_hdr_id;
730                 kfree(parse_attr->mod_hdr_actions);
731                 if (err)
732                         goto err_create_mod_hdr_id;
733         }
734
735         if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
736                 int tc_grp_size, tc_tbl_size;
737                 u32 max_flow_counter;
738
739                 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
740                                     MLX5_CAP_GEN(dev, max_flow_counter_15_0);
741
742                 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
743
744                 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
745                                     BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
746
747                 priv->fs.tc.t =
748                         mlx5_create_auto_grouped_flow_table(priv->fs.ns,
749                                                             MLX5E_TC_PRIO,
750                                                             tc_tbl_size,
751                                                             MLX5E_TC_TABLE_NUM_GROUPS,
752                                                             MLX5E_TC_FT_LEVEL, 0);
753                 if (IS_ERR(priv->fs.tc.t)) {
754                         NL_SET_ERR_MSG_MOD(extack,
755                                            "Failed to create tc offload table\n");
756                         netdev_err(priv->netdev,
757                                    "Failed to create tc offload table\n");
758                         err = PTR_ERR(priv->fs.tc.t);
759                         goto err_create_ft;
760                 }
761
762                 table_created = true;
763         }
764
765         if (attr->match_level != MLX5_MATCH_NONE)
766                 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
767
768         flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
769                                             &flow_act, dest, dest_ix);
770
771         if (IS_ERR(flow->rule[0])) {
772                 err = PTR_ERR(flow->rule[0]);
773                 goto err_add_rule;
774         }
775
776         return 0;
777
778 err_add_rule:
779         if (table_created) {
780                 mlx5_destroy_flow_table(priv->fs.tc.t);
781                 priv->fs.tc.t = NULL;
782         }
783 err_create_ft:
784         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
785                 mlx5e_detach_mod_hdr(priv, flow);
786 err_create_mod_hdr_id:
787         mlx5_fc_destroy(dev, counter);
788 err_fc_create:
789         if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
790                 mlx5e_hairpin_flow_del(priv, flow);
791 err_add_hairpin_flow:
792         return err;
793 }
794
795 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
796                                   struct mlx5e_tc_flow *flow)
797 {
798         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
799         struct mlx5_fc *counter = NULL;
800
801         counter = attr->counter;
802         mlx5_del_flow_rules(flow->rule[0]);
803         mlx5_fc_destroy(priv->mdev, counter);
804
805         if (!mlx5e_tc_num_filters(priv) && priv->fs.tc.t) {
806                 mlx5_destroy_flow_table(priv->fs.tc.t);
807                 priv->fs.tc.t = NULL;
808         }
809
810         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
811                 mlx5e_detach_mod_hdr(priv, flow);
812
813         if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
814                 mlx5e_hairpin_flow_del(priv, flow);
815 }
816
817 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
818                                struct mlx5e_tc_flow *flow);
819
820 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
821                               struct ip_tunnel_info *tun_info,
822                               struct net_device *mirred_dev,
823                               struct net_device **encap_dev,
824                               struct mlx5e_tc_flow *flow,
825                               struct netlink_ext_ack *extack);
826
827 static struct mlx5_flow_handle *
828 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
829                            struct mlx5e_tc_flow *flow,
830                            struct mlx5_flow_spec *spec,
831                            struct mlx5_esw_flow_attr *attr)
832 {
833         struct mlx5_flow_handle *rule;
834
835         rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
836         if (IS_ERR(rule))
837                 return rule;
838
839         if (attr->mirror_count) {
840                 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
841                 if (IS_ERR(flow->rule[1])) {
842                         mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
843                         return flow->rule[1];
844                 }
845         }
846
847         flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
848         return rule;
849 }
850
851 static void
852 mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
853                              struct mlx5e_tc_flow *flow,
854                            struct mlx5_esw_flow_attr *attr)
855 {
856         flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
857
858         if (attr->mirror_count)
859                 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
860
861         mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
862 }
863
864 static struct mlx5_flow_handle *
865 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
866                               struct mlx5e_tc_flow *flow,
867                               struct mlx5_flow_spec *spec,
868                               struct mlx5_esw_flow_attr *slow_attr)
869 {
870         struct mlx5_flow_handle *rule;
871
872         memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
873         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
874         slow_attr->mirror_count = 0,
875         slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN,
876
877         rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
878         if (!IS_ERR(rule))
879                 flow->flags |= MLX5E_TC_FLOW_SLOW;
880
881         return rule;
882 }
883
884 static void
885 mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
886                                   struct mlx5e_tc_flow *flow,
887                                   struct mlx5_esw_flow_attr *slow_attr)
888 {
889         memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
890         mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
891         flow->flags &= ~MLX5E_TC_FLOW_SLOW;
892 }
893
894 static int
895 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
896                       struct mlx5e_tc_flow_parse_attr *parse_attr,
897                       struct mlx5e_tc_flow *flow,
898                       struct netlink_ext_ack *extack)
899 {
900         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
901         u32 max_chain = mlx5_eswitch_get_chain_range(esw);
902         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
903         u16 max_prio = mlx5_eswitch_get_prio_range(esw);
904         struct net_device *out_dev, *encap_dev = NULL;
905         struct mlx5_fc *counter = NULL;
906         struct mlx5e_rep_priv *rpriv;
907         struct mlx5e_priv *out_priv;
908         int err = 0, encap_err = 0;
909
910         /* if prios are not supported, keep the old behaviour of using same prio
911          * for all offloaded rules.
912          */
913         if (!mlx5_eswitch_prios_supported(esw))
914                 attr->prio = 1;
915
916         if (attr->chain > max_chain) {
917                 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
918                 err = -EOPNOTSUPP;
919                 goto err_max_prio_chain;
920         }
921
922         if (attr->prio > max_prio) {
923                 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
924                 err = -EOPNOTSUPP;
925                 goto err_max_prio_chain;
926         }
927
928         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) {
929                 out_dev = __dev_get_by_index(dev_net(priv->netdev),
930                                              attr->parse_attr->mirred_ifindex);
931                 encap_err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
932                                                out_dev, &encap_dev, flow,
933                                                extack);
934                 if (encap_err && encap_err != -EAGAIN) {
935                         err = encap_err;
936                         goto err_attach_encap;
937                 }
938                 out_priv = netdev_priv(encap_dev);
939                 rpriv = out_priv->ppriv;
940                 attr->out_rep[attr->out_count] = rpriv->rep;
941                 attr->out_mdev[attr->out_count++] = out_priv->mdev;
942         }
943
944         err = mlx5_eswitch_add_vlan_action(esw, attr);
945         if (err)
946                 goto err_add_vlan;
947
948         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
949                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
950                 kfree(parse_attr->mod_hdr_actions);
951                 if (err)
952                         goto err_mod_hdr;
953         }
954
955         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
956                 counter = mlx5_fc_create(esw->dev, true);
957                 if (IS_ERR(counter)) {
958                         err = PTR_ERR(counter);
959                         goto err_create_counter;
960                 }
961
962                 attr->counter = counter;
963         }
964
965         /* we get here if (1) there's no error or when
966          * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
967          */
968         if (encap_err == -EAGAIN) {
969                 /* continue with goto slow path rule instead */
970                 struct mlx5_esw_flow_attr slow_attr;
971
972                 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
973         } else {
974                 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
975         }
976
977         if (IS_ERR(flow->rule[0])) {
978                 err = PTR_ERR(flow->rule[0]);
979                 goto err_add_rule;
980         }
981
982         return 0;
983
984 err_add_rule:
985         mlx5_fc_destroy(esw->dev, counter);
986 err_create_counter:
987         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
988                 mlx5e_detach_mod_hdr(priv, flow);
989 err_mod_hdr:
990         mlx5_eswitch_del_vlan_action(esw, attr);
991 err_add_vlan:
992         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
993                 mlx5e_detach_encap(priv, flow);
994 err_attach_encap:
995 err_max_prio_chain:
996         return err;
997 }
998
999 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1000                                   struct mlx5e_tc_flow *flow)
1001 {
1002         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1003         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1004         struct mlx5_esw_flow_attr slow_attr;
1005
1006         if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1007                 if (flow->flags & MLX5E_TC_FLOW_SLOW)
1008                         mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1009                 else
1010                         mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1011         }
1012
1013         mlx5_eswitch_del_vlan_action(esw, attr);
1014
1015         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) {
1016                 mlx5e_detach_encap(priv, flow);
1017                 kvfree(attr->parse_attr);
1018         }
1019
1020         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1021                 mlx5e_detach_mod_hdr(priv, flow);
1022
1023         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1024                 mlx5_fc_destroy(esw->dev, attr->counter);
1025 }
1026
1027 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1028                               struct mlx5e_encap_entry *e)
1029 {
1030         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1031         struct mlx5_esw_flow_attr slow_attr, *esw_attr;
1032         struct mlx5_flow_handle *rule;
1033         struct mlx5_flow_spec *spec;
1034         struct mlx5e_tc_flow *flow;
1035         int err;
1036
1037         err = mlx5_packet_reformat_alloc(priv->mdev, e->tunnel_type,
1038                                          e->encap_size, e->encap_header,
1039                                          MLX5_FLOW_NAMESPACE_FDB,
1040                                          &e->encap_id);
1041         if (err) {
1042                 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1043                                err);
1044                 return;
1045         }
1046         e->flags |= MLX5_ENCAP_ENTRY_VALID;
1047         mlx5e_rep_queue_neigh_stats_work(priv);
1048
1049         list_for_each_entry(flow, &e->flows, encap) {
1050                 esw_attr = flow->esw_attr;
1051                 esw_attr->encap_id = e->encap_id;
1052                 spec = &esw_attr->parse_attr->spec;
1053
1054                 /* update from slow path rule to encap rule */
1055                 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1056                 if (IS_ERR(rule)) {
1057                         err = PTR_ERR(rule);
1058                         mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1059                                        err);
1060                         continue;
1061                 }
1062
1063                 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1064                 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when slow path rule removed */
1065                 flow->rule[0] = rule;
1066         }
1067 }
1068
1069 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1070                               struct mlx5e_encap_entry *e)
1071 {
1072         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1073         struct mlx5_esw_flow_attr slow_attr;
1074         struct mlx5_flow_handle *rule;
1075         struct mlx5_flow_spec *spec;
1076         struct mlx5e_tc_flow *flow;
1077         int err;
1078
1079         list_for_each_entry(flow, &e->flows, encap) {
1080                 spec = &flow->esw_attr->parse_attr->spec;
1081
1082                 /* update from encap rule to slow path rule */
1083                 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
1084
1085                 if (IS_ERR(rule)) {
1086                         err = PTR_ERR(rule);
1087                         mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1088                                        err);
1089                         continue;
1090                 }
1091
1092                 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1093                 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when fast path rule removed */
1094                 flow->rule[0] = rule;
1095         }
1096
1097         if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
1098                 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1099                 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
1100         }
1101 }
1102
1103 static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1104 {
1105         if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1106                 return flow->esw_attr->counter;
1107         else
1108                 return flow->nic_attr->counter;
1109 }
1110
1111 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1112 {
1113         struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1114         u64 bytes, packets, lastuse = 0;
1115         struct mlx5e_tc_flow *flow;
1116         struct mlx5e_encap_entry *e;
1117         struct mlx5_fc *counter;
1118         struct neigh_table *tbl;
1119         bool neigh_used = false;
1120         struct neighbour *n;
1121
1122         if (m_neigh->family == AF_INET)
1123                 tbl = &arp_tbl;
1124 #if IS_ENABLED(CONFIG_IPV6)
1125         else if (m_neigh->family == AF_INET6)
1126                 tbl = &nd_tbl;
1127 #endif
1128         else
1129                 return;
1130
1131         list_for_each_entry(e, &nhe->encap_list, encap_list) {
1132                 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1133                         continue;
1134                 list_for_each_entry(flow, &e->flows, encap) {
1135                         if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1136                                 counter = mlx5e_tc_get_counter(flow);
1137                                 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1138                                 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1139                                         neigh_used = true;
1140                                         break;
1141                                 }
1142                         }
1143                 }
1144                 if (neigh_used)
1145                         break;
1146         }
1147
1148         if (neigh_used) {
1149                 nhe->reported_lastuse = jiffies;
1150
1151                 /* find the relevant neigh according to the cached device and
1152                  * dst ip pair
1153                  */
1154                 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
1155                 if (!n)
1156                         return;
1157
1158                 neigh_event_send(n, NULL);
1159                 neigh_release(n);
1160         }
1161 }
1162
1163 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1164                                struct mlx5e_tc_flow *flow)
1165 {
1166         struct list_head *next = flow->encap.next;
1167
1168         list_del(&flow->encap);
1169         if (list_empty(next)) {
1170                 struct mlx5e_encap_entry *e;
1171
1172                 e = list_entry(next, struct mlx5e_encap_entry, flows);
1173                 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1174
1175                 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1176                         mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
1177
1178                 hash_del_rcu(&e->encap_hlist);
1179                 kfree(e->encap_header);
1180                 kfree(e);
1181         }
1182 }
1183
1184 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
1185                               struct mlx5e_tc_flow *flow)
1186 {
1187         if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1188                 mlx5e_tc_del_fdb_flow(priv, flow);
1189         else
1190                 mlx5e_tc_del_nic_flow(priv, flow);
1191 }
1192
1193 static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
1194                              struct tc_cls_flower_offload *f)
1195 {
1196         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1197                                        outer_headers);
1198         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1199                                        outer_headers);
1200         void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1201                                     misc_parameters);
1202         void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1203                                     misc_parameters);
1204
1205         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
1206         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1207
1208         if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
1209                 struct flow_dissector_key_keyid *key =
1210                         skb_flow_dissector_target(f->dissector,
1211                                                   FLOW_DISSECTOR_KEY_ENC_KEYID,
1212                                                   f->key);
1213                 struct flow_dissector_key_keyid *mask =
1214                         skb_flow_dissector_target(f->dissector,
1215                                                   FLOW_DISSECTOR_KEY_ENC_KEYID,
1216                                                   f->mask);
1217                 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
1218                          be32_to_cpu(mask->keyid));
1219                 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
1220                          be32_to_cpu(key->keyid));
1221         }
1222 }
1223
1224 static int parse_tunnel_attr(struct mlx5e_priv *priv,
1225                              struct mlx5_flow_spec *spec,
1226                              struct tc_cls_flower_offload *f)
1227 {
1228         struct netlink_ext_ack *extack = f->common.extack;
1229         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1230                                        outer_headers);
1231         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1232                                        outer_headers);
1233
1234         struct flow_dissector_key_control *enc_control =
1235                 skb_flow_dissector_target(f->dissector,
1236                                           FLOW_DISSECTOR_KEY_ENC_CONTROL,
1237                                           f->key);
1238
1239         if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
1240                 struct flow_dissector_key_ports *key =
1241                         skb_flow_dissector_target(f->dissector,
1242                                                   FLOW_DISSECTOR_KEY_ENC_PORTS,
1243                                                   f->key);
1244                 struct flow_dissector_key_ports *mask =
1245                         skb_flow_dissector_target(f->dissector,
1246                                                   FLOW_DISSECTOR_KEY_ENC_PORTS,
1247                                                   f->mask);
1248
1249                 /* Full udp dst port must be given */
1250                 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
1251                         goto vxlan_match_offload_err;
1252
1253                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, be16_to_cpu(key->dst)) &&
1254                     MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
1255                         parse_vxlan_attr(spec, f);
1256                 else {
1257                         NL_SET_ERR_MSG_MOD(extack,
1258                                            "port isn't an offloaded vxlan udp dport");
1259                         netdev_warn(priv->netdev,
1260                                     "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
1261                         return -EOPNOTSUPP;
1262                 }
1263
1264                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1265                          udp_dport, ntohs(mask->dst));
1266                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1267                          udp_dport, ntohs(key->dst));
1268
1269                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1270                          udp_sport, ntohs(mask->src));
1271                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1272                          udp_sport, ntohs(key->src));
1273         } else { /* udp dst port must be given */
1274 vxlan_match_offload_err:
1275                 NL_SET_ERR_MSG_MOD(extack,
1276                                    "IP tunnel decap offload supported only for vxlan, must set UDP dport");
1277                 netdev_warn(priv->netdev,
1278                             "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
1279                 return -EOPNOTSUPP;
1280         }
1281
1282         if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1283                 struct flow_dissector_key_ipv4_addrs *key =
1284                         skb_flow_dissector_target(f->dissector,
1285                                                   FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1286                                                   f->key);
1287                 struct flow_dissector_key_ipv4_addrs *mask =
1288                         skb_flow_dissector_target(f->dissector,
1289                                                   FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1290                                                   f->mask);
1291                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1292                          src_ipv4_src_ipv6.ipv4_layout.ipv4,
1293                          ntohl(mask->src));
1294                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1295                          src_ipv4_src_ipv6.ipv4_layout.ipv4,
1296                          ntohl(key->src));
1297
1298                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1299                          dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1300                          ntohl(mask->dst));
1301                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1302                          dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1303                          ntohl(key->dst));
1304
1305                 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1306                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
1307         } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1308                 struct flow_dissector_key_ipv6_addrs *key =
1309                         skb_flow_dissector_target(f->dissector,
1310                                                   FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1311                                                   f->key);
1312                 struct flow_dissector_key_ipv6_addrs *mask =
1313                         skb_flow_dissector_target(f->dissector,
1314                                                   FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1315                                                   f->mask);
1316
1317                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1318                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1319                        &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1320                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1321                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1322                        &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1323
1324                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1325                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1326                        &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1327                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1328                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1329                        &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1330
1331                 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1332                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
1333         }
1334
1335         if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_IP)) {
1336                 struct flow_dissector_key_ip *key =
1337                         skb_flow_dissector_target(f->dissector,
1338                                                   FLOW_DISSECTOR_KEY_ENC_IP,
1339                                                   f->key);
1340                 struct flow_dissector_key_ip *mask =
1341                         skb_flow_dissector_target(f->dissector,
1342                                                   FLOW_DISSECTOR_KEY_ENC_IP,
1343                                                   f->mask);
1344
1345                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1346                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1347
1348                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1349                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos  >> 2);
1350
1351                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1352                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1353
1354                 if (mask->ttl &&
1355                     !MLX5_CAP_ESW_FLOWTABLE_FDB
1356                         (priv->mdev,
1357                          ft_field_support.outer_ipv4_ttl)) {
1358                         NL_SET_ERR_MSG_MOD(extack,
1359                                            "Matching on TTL is not supported");
1360                         return -EOPNOTSUPP;
1361                 }
1362
1363         }
1364
1365         /* Enforce DMAC when offloading incoming tunneled flows.
1366          * Flow counters require a match on the DMAC.
1367          */
1368         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1369         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1370         ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1371                                      dmac_47_16), priv->netdev->dev_addr);
1372
1373         /* let software handle IP fragments */
1374         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1375         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1376
1377         return 0;
1378 }
1379
1380 static int __parse_cls_flower(struct mlx5e_priv *priv,
1381                               struct mlx5_flow_spec *spec,
1382                               struct tc_cls_flower_offload *f,
1383                               u8 *match_level)
1384 {
1385         struct netlink_ext_ack *extack = f->common.extack;
1386         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1387                                        outer_headers);
1388         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1389                                        outer_headers);
1390         void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1391                                     misc_parameters);
1392         void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1393                                     misc_parameters);
1394         u16 addr_type = 0;
1395         u8 ip_proto = 0;
1396
1397         *match_level = MLX5_MATCH_NONE;
1398
1399         if (f->dissector->used_keys &
1400             ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1401               BIT(FLOW_DISSECTOR_KEY_BASIC) |
1402               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
1403               BIT(FLOW_DISSECTOR_KEY_VLAN) |
1404               BIT(FLOW_DISSECTOR_KEY_CVLAN) |
1405               BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1406               BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
1407               BIT(FLOW_DISSECTOR_KEY_PORTS) |
1408               BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1409               BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1410               BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1411               BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
1412               BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
1413               BIT(FLOW_DISSECTOR_KEY_TCP) |
1414               BIT(FLOW_DISSECTOR_KEY_IP)  |
1415               BIT(FLOW_DISSECTOR_KEY_ENC_IP))) {
1416                 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
1417                 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1418                             f->dissector->used_keys);
1419                 return -EOPNOTSUPP;
1420         }
1421
1422         if ((dissector_uses_key(f->dissector,
1423                                 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1424              dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1425              dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1426             dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1427                 struct flow_dissector_key_control *key =
1428                         skb_flow_dissector_target(f->dissector,
1429                                                   FLOW_DISSECTOR_KEY_ENC_CONTROL,
1430                                                   f->key);
1431                 switch (key->addr_type) {
1432                 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
1433                 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
1434                         if (parse_tunnel_attr(priv, spec, f))
1435                                 return -EOPNOTSUPP;
1436                         break;
1437                 default:
1438                         return -EOPNOTSUPP;
1439                 }
1440
1441                 /* In decap flow, header pointers should point to the inner
1442                  * headers, outer header were already set by parse_tunnel_attr
1443                  */
1444                 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1445                                          inner_headers);
1446                 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1447                                          inner_headers);
1448         }
1449
1450         if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1451                 struct flow_dissector_key_basic *key =
1452                         skb_flow_dissector_target(f->dissector,
1453                                                   FLOW_DISSECTOR_KEY_BASIC,
1454                                                   f->key);
1455                 struct flow_dissector_key_basic *mask =
1456                         skb_flow_dissector_target(f->dissector,
1457                                                   FLOW_DISSECTOR_KEY_BASIC,
1458                                                   f->mask);
1459                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1460                          ntohs(mask->n_proto));
1461                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1462                          ntohs(key->n_proto));
1463
1464                 if (mask->n_proto)
1465                         *match_level = MLX5_MATCH_L2;
1466         }
1467
1468         if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1469                 struct flow_dissector_key_vlan *key =
1470                         skb_flow_dissector_target(f->dissector,
1471                                                   FLOW_DISSECTOR_KEY_VLAN,
1472                                                   f->key);
1473                 struct flow_dissector_key_vlan *mask =
1474                         skb_flow_dissector_target(f->dissector,
1475                                                   FLOW_DISSECTOR_KEY_VLAN,
1476                                                   f->mask);
1477                 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1478                         if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1479                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1480                                          svlan_tag, 1);
1481                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1482                                          svlan_tag, 1);
1483                         } else {
1484                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1485                                          cvlan_tag, 1);
1486                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1487                                          cvlan_tag, 1);
1488                         }
1489
1490                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1491                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
1492
1493                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1494                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
1495
1496                         *match_level = MLX5_MATCH_L2;
1497                 }
1498         } else if (*match_level != MLX5_MATCH_NONE) {
1499                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1500                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1501                 *match_level = MLX5_MATCH_L2;
1502         }
1503
1504         if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CVLAN)) {
1505                 struct flow_dissector_key_vlan *key =
1506                         skb_flow_dissector_target(f->dissector,
1507                                                   FLOW_DISSECTOR_KEY_CVLAN,
1508                                                   f->key);
1509                 struct flow_dissector_key_vlan *mask =
1510                         skb_flow_dissector_target(f->dissector,
1511                                                   FLOW_DISSECTOR_KEY_CVLAN,
1512                                                   f->mask);
1513                 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1514                         if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1515                                 MLX5_SET(fte_match_set_misc, misc_c,
1516                                          outer_second_svlan_tag, 1);
1517                                 MLX5_SET(fte_match_set_misc, misc_v,
1518                                          outer_second_svlan_tag, 1);
1519                         } else {
1520                                 MLX5_SET(fte_match_set_misc, misc_c,
1521                                          outer_second_cvlan_tag, 1);
1522                                 MLX5_SET(fte_match_set_misc, misc_v,
1523                                          outer_second_cvlan_tag, 1);
1524                         }
1525
1526                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1527                                  mask->vlan_id);
1528                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
1529                                  key->vlan_id);
1530                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
1531                                  mask->vlan_priority);
1532                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
1533                                  key->vlan_priority);
1534
1535                         *match_level = MLX5_MATCH_L2;
1536                 }
1537         }
1538
1539         if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1540                 struct flow_dissector_key_eth_addrs *key =
1541                         skb_flow_dissector_target(f->dissector,
1542                                                   FLOW_DISSECTOR_KEY_ETH_ADDRS,
1543                                                   f->key);
1544                 struct flow_dissector_key_eth_addrs *mask =
1545                         skb_flow_dissector_target(f->dissector,
1546                                                   FLOW_DISSECTOR_KEY_ETH_ADDRS,
1547                                                   f->mask);
1548
1549                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1550                                              dmac_47_16),
1551                                 mask->dst);
1552                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1553                                              dmac_47_16),
1554                                 key->dst);
1555
1556                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1557                                              smac_47_16),
1558                                 mask->src);
1559                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1560                                              smac_47_16),
1561                                 key->src);
1562
1563                 if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
1564                         *match_level = MLX5_MATCH_L2;
1565         }
1566
1567         if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1568                 struct flow_dissector_key_control *key =
1569                         skb_flow_dissector_target(f->dissector,
1570                                                   FLOW_DISSECTOR_KEY_CONTROL,
1571                                                   f->key);
1572
1573                 struct flow_dissector_key_control *mask =
1574                         skb_flow_dissector_target(f->dissector,
1575                                                   FLOW_DISSECTOR_KEY_CONTROL,
1576                                                   f->mask);
1577                 addr_type = key->addr_type;
1578
1579                 /* the HW doesn't support frag first/later */
1580                 if (mask->flags & FLOW_DIS_FIRST_FRAG)
1581                         return -EOPNOTSUPP;
1582
1583                 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1584                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1585                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1586                                  key->flags & FLOW_DIS_IS_FRAGMENT);
1587
1588                         /* the HW doesn't need L3 inline to match on frag=no */
1589                         if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
1590                                 *match_level = MLX5_MATCH_L2;
1591         /* ***  L2 attributes parsing up to here *** */
1592                         else
1593                                 *match_level = MLX5_MATCH_L3;
1594                 }
1595         }
1596
1597         if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1598                 struct flow_dissector_key_basic *key =
1599                         skb_flow_dissector_target(f->dissector,
1600                                                   FLOW_DISSECTOR_KEY_BASIC,
1601                                                   f->key);
1602                 struct flow_dissector_key_basic *mask =
1603                         skb_flow_dissector_target(f->dissector,
1604                                                   FLOW_DISSECTOR_KEY_BASIC,
1605                                                   f->mask);
1606                 ip_proto = key->ip_proto;
1607
1608                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1609                          mask->ip_proto);
1610                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1611                          key->ip_proto);
1612
1613                 if (mask->ip_proto)
1614                         *match_level = MLX5_MATCH_L3;
1615         }
1616
1617         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1618                 struct flow_dissector_key_ipv4_addrs *key =
1619                         skb_flow_dissector_target(f->dissector,
1620                                                   FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1621                                                   f->key);
1622                 struct flow_dissector_key_ipv4_addrs *mask =
1623                         skb_flow_dissector_target(f->dissector,
1624                                                   FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1625                                                   f->mask);
1626
1627                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1628                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1629                        &mask->src, sizeof(mask->src));
1630                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1631                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1632                        &key->src, sizeof(key->src));
1633                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1634                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1635                        &mask->dst, sizeof(mask->dst));
1636                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1637                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1638                        &key->dst, sizeof(key->dst));
1639
1640                 if (mask->src || mask->dst)
1641                         *match_level = MLX5_MATCH_L3;
1642         }
1643
1644         if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1645                 struct flow_dissector_key_ipv6_addrs *key =
1646                         skb_flow_dissector_target(f->dissector,
1647                                                   FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1648                                                   f->key);
1649                 struct flow_dissector_key_ipv6_addrs *mask =
1650                         skb_flow_dissector_target(f->dissector,
1651                                                   FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1652                                                   f->mask);
1653
1654                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1655                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1656                        &mask->src, sizeof(mask->src));
1657                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1658                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1659                        &key->src, sizeof(key->src));
1660
1661                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1662                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1663                        &mask->dst, sizeof(mask->dst));
1664                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1665                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1666                        &key->dst, sizeof(key->dst));
1667
1668                 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1669                     ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
1670                         *match_level = MLX5_MATCH_L3;
1671         }
1672
1673         if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1674                 struct flow_dissector_key_ip *key =
1675                         skb_flow_dissector_target(f->dissector,
1676                                                   FLOW_DISSECTOR_KEY_IP,
1677                                                   f->key);
1678                 struct flow_dissector_key_ip *mask =
1679                         skb_flow_dissector_target(f->dissector,
1680                                                   FLOW_DISSECTOR_KEY_IP,
1681                                                   f->mask);
1682
1683                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1684                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1685
1686                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1687                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos  >> 2);
1688
1689                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1690                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1691
1692                 if (mask->ttl &&
1693                     !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
1694                                                 ft_field_support.outer_ipv4_ttl)) {
1695                         NL_SET_ERR_MSG_MOD(extack,
1696                                            "Matching on TTL is not supported");
1697                         return -EOPNOTSUPP;
1698                 }
1699
1700                 if (mask->tos || mask->ttl)
1701                         *match_level = MLX5_MATCH_L3;
1702         }
1703
1704         /* ***  L3 attributes parsing up to here *** */
1705
1706         if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1707                 struct flow_dissector_key_ports *key =
1708                         skb_flow_dissector_target(f->dissector,
1709                                                   FLOW_DISSECTOR_KEY_PORTS,
1710                                                   f->key);
1711                 struct flow_dissector_key_ports *mask =
1712                         skb_flow_dissector_target(f->dissector,
1713                                                   FLOW_DISSECTOR_KEY_PORTS,
1714                                                   f->mask);
1715                 switch (ip_proto) {
1716                 case IPPROTO_TCP:
1717                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1718                                  tcp_sport, ntohs(mask->src));
1719                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1720                                  tcp_sport, ntohs(key->src));
1721
1722                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1723                                  tcp_dport, ntohs(mask->dst));
1724                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1725                                  tcp_dport, ntohs(key->dst));
1726                         break;
1727
1728                 case IPPROTO_UDP:
1729                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1730                                  udp_sport, ntohs(mask->src));
1731                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1732                                  udp_sport, ntohs(key->src));
1733
1734                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1735                                  udp_dport, ntohs(mask->dst));
1736                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1737                                  udp_dport, ntohs(key->dst));
1738                         break;
1739                 default:
1740                         NL_SET_ERR_MSG_MOD(extack,
1741                                            "Only UDP and TCP transports are supported for L4 matching");
1742                         netdev_err(priv->netdev,
1743                                    "Only UDP and TCP transport are supported\n");
1744                         return -EINVAL;
1745                 }
1746
1747                 if (mask->src || mask->dst)
1748                         *match_level = MLX5_MATCH_L4;
1749         }
1750
1751         if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1752                 struct flow_dissector_key_tcp *key =
1753                         skb_flow_dissector_target(f->dissector,
1754                                                   FLOW_DISSECTOR_KEY_TCP,
1755                                                   f->key);
1756                 struct flow_dissector_key_tcp *mask =
1757                         skb_flow_dissector_target(f->dissector,
1758                                                   FLOW_DISSECTOR_KEY_TCP,
1759                                                   f->mask);
1760
1761                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1762                          ntohs(mask->flags));
1763                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1764                          ntohs(key->flags));
1765
1766                 if (mask->flags)
1767                         *match_level = MLX5_MATCH_L4;
1768         }
1769
1770         return 0;
1771 }
1772
1773 static int parse_cls_flower(struct mlx5e_priv *priv,
1774                             struct mlx5e_tc_flow *flow,
1775                             struct mlx5_flow_spec *spec,
1776                             struct tc_cls_flower_offload *f)
1777 {
1778         struct netlink_ext_ack *extack = f->common.extack;
1779         struct mlx5_core_dev *dev = priv->mdev;
1780         struct mlx5_eswitch *esw = dev->priv.eswitch;
1781         struct mlx5e_rep_priv *rpriv = priv->ppriv;
1782         struct mlx5_eswitch_rep *rep;
1783         u8 match_level;
1784         int err;
1785
1786         err = __parse_cls_flower(priv, spec, f, &match_level);
1787
1788         if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1789                 rep = rpriv->rep;
1790                 if (rep->vport != FDB_UPLINK_VPORT &&
1791                     (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
1792                     esw->offloads.inline_mode < match_level)) {
1793                         NL_SET_ERR_MSG_MOD(extack,
1794                                            "Flow is not offloaded due to min inline setting");
1795                         netdev_warn(priv->netdev,
1796                                     "Flow is not offloaded due to min inline setting, required %d actual %d\n",
1797                                     match_level, esw->offloads.inline_mode);
1798                         return -EOPNOTSUPP;
1799                 }
1800         }
1801
1802         if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1803                 flow->esw_attr->match_level = match_level;
1804         else
1805                 flow->nic_attr->match_level = match_level;
1806
1807         return err;
1808 }
1809
1810 struct pedit_headers {
1811         struct ethhdr  eth;
1812         struct iphdr   ip4;
1813         struct ipv6hdr ip6;
1814         struct tcphdr  tcp;
1815         struct udphdr  udp;
1816 };
1817
1818 static int pedit_header_offsets[] = {
1819         [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1820         [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1821         [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1822         [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1823         [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1824 };
1825
1826 #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1827
1828 static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1829                          struct pedit_headers *masks,
1830                          struct pedit_headers *vals)
1831 {
1832         u32 *curr_pmask, *curr_pval;
1833
1834         if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1835                 goto out_err;
1836
1837         curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1838         curr_pval  = (u32 *)(pedit_header(vals, hdr_type) + offset);
1839
1840         if (*curr_pmask & mask)  /* disallow acting twice on the same location */
1841                 goto out_err;
1842
1843         *curr_pmask |= mask;
1844         *curr_pval  |= (val & mask);
1845
1846         return 0;
1847
1848 out_err:
1849         return -EOPNOTSUPP;
1850 }
1851
1852 struct mlx5_fields {
1853         u8  field;
1854         u8  size;
1855         u32 offset;
1856 };
1857
1858 #define OFFLOAD(fw_field, size, field, off) \
1859                 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1860
1861 static struct mlx5_fields fields[] = {
1862         OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1863         OFFLOAD(DMAC_15_0,  2, eth.h_dest[4], 0),
1864         OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1865         OFFLOAD(SMAC_15_0,  2, eth.h_source[4], 0),
1866         OFFLOAD(ETHERTYPE,  2, eth.h_proto, 0),
1867
1868         OFFLOAD(IP_TTL, 1, ip4.ttl,   0),
1869         OFFLOAD(SIPV4,  4, ip4.saddr, 0),
1870         OFFLOAD(DIPV4,  4, ip4.daddr, 0),
1871
1872         OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1873         OFFLOAD(SIPV6_95_64,  4, ip6.saddr.s6_addr32[1], 0),
1874         OFFLOAD(SIPV6_63_32,  4, ip6.saddr.s6_addr32[2], 0),
1875         OFFLOAD(SIPV6_31_0,   4, ip6.saddr.s6_addr32[3], 0),
1876         OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1877         OFFLOAD(DIPV6_95_64,  4, ip6.daddr.s6_addr32[1], 0),
1878         OFFLOAD(DIPV6_63_32,  4, ip6.daddr.s6_addr32[2], 0),
1879         OFFLOAD(DIPV6_31_0,   4, ip6.daddr.s6_addr32[3], 0),
1880         OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
1881
1882         OFFLOAD(TCP_SPORT, 2, tcp.source,  0),
1883         OFFLOAD(TCP_DPORT, 2, tcp.dest,    0),
1884         OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1885
1886         OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1887         OFFLOAD(UDP_DPORT, 2, udp.dest,   0),
1888 };
1889
1890 /* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1891  * max from the SW pedit action. On success, it says how many HW actions were
1892  * actually parsed.
1893  */
1894 static int offload_pedit_fields(struct pedit_headers *masks,
1895                                 struct pedit_headers *vals,
1896                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
1897                                 struct netlink_ext_ack *extack)
1898 {
1899         struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
1900         int i, action_size, nactions, max_actions, first, last, next_z;
1901         void *s_masks_p, *a_masks_p, *vals_p;
1902         struct mlx5_fields *f;
1903         u8 cmd, field_bsize;
1904         u32 s_mask, a_mask;
1905         unsigned long mask;
1906         __be32 mask_be32;
1907         __be16 mask_be16;
1908         void *action;
1909
1910         set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1911         add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1912         set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1913         add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1914
1915         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1916         action = parse_attr->mod_hdr_actions;
1917         max_actions = parse_attr->num_mod_hdr_actions;
1918         nactions = 0;
1919
1920         for (i = 0; i < ARRAY_SIZE(fields); i++) {
1921                 f = &fields[i];
1922                 /* avoid seeing bits set from previous iterations */
1923                 s_mask = 0;
1924                 a_mask = 0;
1925
1926                 s_masks_p = (void *)set_masks + f->offset;
1927                 a_masks_p = (void *)add_masks + f->offset;
1928
1929                 memcpy(&s_mask, s_masks_p, f->size);
1930                 memcpy(&a_mask, a_masks_p, f->size);
1931
1932                 if (!s_mask && !a_mask) /* nothing to offload here */
1933                         continue;
1934
1935                 if (s_mask && a_mask) {
1936                         NL_SET_ERR_MSG_MOD(extack,
1937                                            "can't set and add to the same HW field");
1938                         printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1939                         return -EOPNOTSUPP;
1940                 }
1941
1942                 if (nactions == max_actions) {
1943                         NL_SET_ERR_MSG_MOD(extack,
1944                                            "too many pedit actions, can't offload");
1945                         printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1946                         return -EOPNOTSUPP;
1947                 }
1948
1949                 if (s_mask) {
1950                         cmd  = MLX5_ACTION_TYPE_SET;
1951                         mask = s_mask;
1952                         vals_p = (void *)set_vals + f->offset;
1953                         /* clear to denote we consumed this field */
1954                         memset(s_masks_p, 0, f->size);
1955                 } else {
1956                         cmd  = MLX5_ACTION_TYPE_ADD;
1957                         mask = a_mask;
1958                         vals_p = (void *)add_vals + f->offset;
1959                         /* clear to denote we consumed this field */
1960                         memset(a_masks_p, 0, f->size);
1961                 }
1962
1963                 field_bsize = f->size * BITS_PER_BYTE;
1964
1965                 if (field_bsize == 32) {
1966                         mask_be32 = *(__be32 *)&mask;
1967                         mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1968                 } else if (field_bsize == 16) {
1969                         mask_be16 = *(__be16 *)&mask;
1970                         mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1971                 }
1972
1973                 first = find_first_bit(&mask, field_bsize);
1974                 next_z = find_next_zero_bit(&mask, field_bsize, first);
1975                 last  = find_last_bit(&mask, field_bsize);
1976                 if (first < next_z && next_z < last) {
1977                         NL_SET_ERR_MSG_MOD(extack,
1978                                            "rewrite of few sub-fields isn't supported");
1979                         printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
1980                                mask);
1981                         return -EOPNOTSUPP;
1982                 }
1983
1984                 MLX5_SET(set_action_in, action, action_type, cmd);
1985                 MLX5_SET(set_action_in, action, field, f->field);
1986
1987                 if (cmd == MLX5_ACTION_TYPE_SET) {
1988                         MLX5_SET(set_action_in, action, offset, first);
1989                         /* length is num of bits to be written, zero means length of 32 */
1990                         MLX5_SET(set_action_in, action, length, (last - first + 1));
1991                 }
1992
1993                 if (field_bsize == 32)
1994                         MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
1995                 else if (field_bsize == 16)
1996                         MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
1997                 else if (field_bsize == 8)
1998                         MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
1999
2000                 action += action_size;
2001                 nactions++;
2002         }
2003
2004         parse_attr->num_mod_hdr_actions = nactions;
2005         return 0;
2006 }
2007
2008 static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
2009                                  const struct tc_action *a, int namespace,
2010                                  struct mlx5e_tc_flow_parse_attr *parse_attr)
2011 {
2012         int nkeys, action_size, max_actions;
2013
2014         nkeys = tcf_pedit_nkeys(a);
2015         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2016
2017         if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2018                 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
2019         else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2020                 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
2021
2022         /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2023         max_actions = min(max_actions, nkeys * 16);
2024
2025         parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2026         if (!parse_attr->mod_hdr_actions)
2027                 return -ENOMEM;
2028
2029         parse_attr->num_mod_hdr_actions = max_actions;
2030         return 0;
2031 }
2032
2033 static const struct pedit_headers zero_masks = {};
2034
2035 static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2036                                  const struct tc_action *a, int namespace,
2037                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2038                                  struct netlink_ext_ack *extack)
2039 {
2040         struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
2041         int nkeys, i, err = -EOPNOTSUPP;
2042         u32 mask, val, offset;
2043         u8 cmd, htype;
2044
2045         nkeys = tcf_pedit_nkeys(a);
2046
2047         memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
2048         memset(vals,  0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
2049
2050         for (i = 0; i < nkeys; i++) {
2051                 htype = tcf_pedit_htype(a, i);
2052                 cmd = tcf_pedit_cmd(a, i);
2053                 err = -EOPNOTSUPP; /* can't be all optimistic */
2054
2055                 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
2056                         NL_SET_ERR_MSG_MOD(extack,
2057                                            "legacy pedit isn't offloaded");
2058                         goto out_err;
2059                 }
2060
2061                 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
2062                         NL_SET_ERR_MSG_MOD(extack, "pedit cmd isn't offloaded");
2063                         goto out_err;
2064                 }
2065
2066                 mask = tcf_pedit_mask(a, i);
2067                 val = tcf_pedit_val(a, i);
2068                 offset = tcf_pedit_offset(a, i);
2069
2070                 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
2071                 if (err)
2072                         goto out_err;
2073         }
2074
2075         err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
2076         if (err)
2077                 goto out_err;
2078
2079         err = offload_pedit_fields(masks, vals, parse_attr, extack);
2080         if (err < 0)
2081                 goto out_dealloc_parsed_actions;
2082
2083         for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2084                 cmd_masks = &masks[cmd];
2085                 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
2086                         NL_SET_ERR_MSG_MOD(extack,
2087                                            "attempt to offload an unsupported field");
2088                         netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
2089                         print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2090                                        16, 1, cmd_masks, sizeof(zero_masks), true);
2091                         err = -EOPNOTSUPP;
2092                         goto out_dealloc_parsed_actions;
2093                 }
2094         }
2095
2096         return 0;
2097
2098 out_dealloc_parsed_actions:
2099         kfree(parse_attr->mod_hdr_actions);
2100 out_err:
2101         return err;
2102 }
2103
2104 static bool csum_offload_supported(struct mlx5e_priv *priv,
2105                                    u32 action,
2106                                    u32 update_flags,
2107                                    struct netlink_ext_ack *extack)
2108 {
2109         u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2110                          TCA_CSUM_UPDATE_FLAG_UDP;
2111
2112         /*  The HW recalcs checksums only if re-writing headers */
2113         if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
2114                 NL_SET_ERR_MSG_MOD(extack,
2115                                    "TC csum action is only offloaded with pedit");
2116                 netdev_warn(priv->netdev,
2117                             "TC csum action is only offloaded with pedit\n");
2118                 return false;
2119         }
2120
2121         if (update_flags & ~prot_flags) {
2122                 NL_SET_ERR_MSG_MOD(extack,
2123                                    "can't offload TC csum action for some header/s");
2124                 netdev_warn(priv->netdev,
2125                             "can't offload TC csum action for some header/s - flags %#x\n",
2126                             update_flags);
2127                 return false;
2128         }
2129
2130         return true;
2131 }
2132
2133 static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
2134                                           struct tcf_exts *exts,
2135                                           struct netlink_ext_ack *extack)
2136 {
2137         const struct tc_action *a;
2138         bool modify_ip_header;
2139         LIST_HEAD(actions);
2140         u8 htype, ip_proto;
2141         void *headers_v;
2142         u16 ethertype;
2143         int nkeys, i;
2144
2145         headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2146         ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2147
2148         /* for non-IP we only re-write MACs, so we're okay */
2149         if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2150                 goto out_ok;
2151
2152         modify_ip_header = false;
2153         tcf_exts_for_each_action(i, a, exts) {
2154                 int k;
2155
2156                 if (!is_tcf_pedit(a))
2157                         continue;
2158
2159                 nkeys = tcf_pedit_nkeys(a);
2160                 for (k = 0; k < nkeys; k++) {
2161                         htype = tcf_pedit_htype(a, k);
2162                         if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
2163                             htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
2164                                 modify_ip_header = true;
2165                                 break;
2166                         }
2167                 }
2168         }
2169
2170         ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
2171         if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2172             ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
2173                 NL_SET_ERR_MSG_MOD(extack,
2174                                    "can't offload re-write of non TCP/UDP");
2175                 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2176                 return false;
2177         }
2178
2179 out_ok:
2180         return true;
2181 }
2182
2183 static bool actions_match_supported(struct mlx5e_priv *priv,
2184                                     struct tcf_exts *exts,
2185                                     struct mlx5e_tc_flow_parse_attr *parse_attr,
2186                                     struct mlx5e_tc_flow *flow,
2187                                     struct netlink_ext_ack *extack)
2188 {
2189         u32 actions;
2190
2191         if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2192                 actions = flow->esw_attr->action;
2193         else
2194                 actions = flow->nic_attr->action;
2195
2196         if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
2197             !(actions & MLX5_FLOW_CONTEXT_ACTION_DECAP))
2198                 return false;
2199
2200         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2201                 return modify_header_match_supported(&parse_attr->spec, exts,
2202                                                      extack);
2203
2204         return true;
2205 }
2206
2207 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2208 {
2209         struct mlx5_core_dev *fmdev, *pmdev;
2210         u64 fsystem_guid, psystem_guid;
2211
2212         fmdev = priv->mdev;
2213         pmdev = peer_priv->mdev;
2214
2215         fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2216         psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
2217
2218         return (fsystem_guid == psystem_guid);
2219 }
2220
2221 static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
2222                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
2223                                 struct mlx5e_tc_flow *flow,
2224                                 struct netlink_ext_ack *extack)
2225 {
2226         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
2227         const struct tc_action *a;
2228         LIST_HEAD(actions);
2229         u32 action = 0;
2230         int err, i;
2231
2232         if (!tcf_exts_has_actions(exts))
2233                 return -EINVAL;
2234
2235         attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2236
2237         tcf_exts_for_each_action(i, a, exts) {
2238                 if (is_tcf_gact_shot(a)) {
2239                         action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2240                         if (MLX5_CAP_FLOWTABLE(priv->mdev,
2241                                                flow_table_properties_nic_receive.flow_counter))
2242                                 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2243                         continue;
2244                 }
2245
2246                 if (is_tcf_pedit(a)) {
2247                         err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
2248                                                     parse_attr, extack);
2249                         if (err)
2250                                 return err;
2251
2252                         action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2253                                   MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2254                         continue;
2255                 }
2256
2257                 if (is_tcf_csum(a)) {
2258                         if (csum_offload_supported(priv, action,
2259                                                    tcf_csum_update_flags(a),
2260                                                    extack))
2261                                 continue;
2262
2263                         return -EOPNOTSUPP;
2264                 }
2265
2266                 if (is_tcf_mirred_egress_redirect(a)) {
2267                         struct net_device *peer_dev = tcf_mirred_dev(a);
2268
2269                         if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2270                             same_hw_devs(priv, netdev_priv(peer_dev))) {
2271                                 parse_attr->mirred_ifindex = peer_dev->ifindex;
2272                                 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
2273                                 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2274                                           MLX5_FLOW_CONTEXT_ACTION_COUNT;
2275                         } else {
2276                                 NL_SET_ERR_MSG_MOD(extack,
2277                                                    "device is not on same HW, can't offload");
2278                                 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2279                                             peer_dev->name);
2280                                 return -EINVAL;
2281                         }
2282                         continue;
2283                 }
2284
2285                 if (is_tcf_skbedit_mark(a)) {
2286                         u32 mark = tcf_skbedit_mark(a);
2287
2288                         if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
2289                                 NL_SET_ERR_MSG_MOD(extack,
2290                                                    "Bad flow mark - only 16 bit is supported");
2291                                 return -EINVAL;
2292                         }
2293
2294                         attr->flow_tag = mark;
2295                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2296                         continue;
2297                 }
2298
2299                 return -EINVAL;
2300         }
2301
2302         attr->action = action;
2303         if (!actions_match_supported(priv, exts, parse_attr, flow, extack))
2304                 return -EOPNOTSUPP;
2305
2306         return 0;
2307 }
2308
2309 static inline int cmp_encap_info(struct ip_tunnel_key *a,
2310                                  struct ip_tunnel_key *b)
2311 {
2312         return memcmp(a, b, sizeof(*a));
2313 }
2314
2315 static inline int hash_encap_info(struct ip_tunnel_key *key)
2316 {
2317         return jhash(key, sizeof(*key), 0);
2318 }
2319
2320 static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
2321                                    struct net_device *mirred_dev,
2322                                    struct net_device **out_dev,
2323                                    struct flowi4 *fl4,
2324                                    struct neighbour **out_n,
2325                                    u8 *out_ttl)
2326 {
2327         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2328         struct mlx5e_rep_priv *uplink_rpriv;
2329         struct rtable *rt;
2330         struct neighbour *n = NULL;
2331
2332 #if IS_ENABLED(CONFIG_INET)
2333         int ret;
2334
2335         rt = ip_route_output_key(dev_net(mirred_dev), fl4);
2336         ret = PTR_ERR_OR_ZERO(rt);
2337         if (ret)
2338                 return ret;
2339 #else
2340         return -EOPNOTSUPP;
2341 #endif
2342         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2343         /* if the egress device isn't on the same HW e-switch, we use the uplink */
2344         if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
2345                 *out_dev = uplink_rpriv->netdev;
2346         else
2347                 *out_dev = rt->dst.dev;
2348
2349         if (!(*out_ttl))
2350                 *out_ttl = ip4_dst_hoplimit(&rt->dst);
2351         n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
2352         ip_rt_put(rt);
2353         if (!n)
2354                 return -ENOMEM;
2355
2356         *out_n = n;
2357         return 0;
2358 }
2359
2360 static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2361                                   struct net_device *peer_netdev)
2362 {
2363         struct mlx5e_priv *peer_priv;
2364
2365         peer_priv = netdev_priv(peer_netdev);
2366
2367         return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2368                 (priv->netdev->netdev_ops == peer_netdev->netdev_ops) &&
2369                 same_hw_devs(priv, peer_priv) &&
2370                 MLX5_VPORT_MANAGER(peer_priv->mdev) &&
2371                 (peer_priv->mdev->priv.eswitch->mode == SRIOV_OFFLOADS));
2372 }
2373
2374 static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
2375                                    struct net_device *mirred_dev,
2376                                    struct net_device **out_dev,
2377                                    struct flowi6 *fl6,
2378                                    struct neighbour **out_n,
2379                                    u8 *out_ttl)
2380 {
2381         struct neighbour *n = NULL;
2382         struct dst_entry *dst;
2383
2384 #if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
2385         struct mlx5e_rep_priv *uplink_rpriv;
2386         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2387         int ret;
2388
2389         ret = ipv6_stub->ipv6_dst_lookup(dev_net(mirred_dev), NULL, &dst,
2390                                          fl6);
2391         if (ret < 0)
2392                 return ret;
2393
2394         if (!(*out_ttl))
2395                 *out_ttl = ip6_dst_hoplimit(dst);
2396
2397         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2398         /* if the egress device isn't on the same HW e-switch, we use the uplink */
2399         if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
2400                 *out_dev = uplink_rpriv->netdev;
2401         else
2402                 *out_dev = dst->dev;
2403 #else
2404         return -EOPNOTSUPP;
2405 #endif
2406
2407         n = dst_neigh_lookup(dst, &fl6->daddr);
2408         dst_release(dst);
2409         if (!n)
2410                 return -ENOMEM;
2411
2412         *out_n = n;
2413         return 0;
2414 }
2415
2416 static void gen_vxlan_header_ipv4(struct net_device *out_dev,
2417                                   char buf[], int encap_size,
2418                                   unsigned char h_dest[ETH_ALEN],
2419                                   u8 tos, u8 ttl,
2420                                   __be32 daddr,
2421                                   __be32 saddr,
2422                                   __be16 udp_dst_port,
2423                                   __be32 vx_vni)
2424 {
2425         struct ethhdr *eth = (struct ethhdr *)buf;
2426         struct iphdr  *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
2427         struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
2428         struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2429
2430         memset(buf, 0, encap_size);
2431
2432         ether_addr_copy(eth->h_dest, h_dest);
2433         ether_addr_copy(eth->h_source, out_dev->dev_addr);
2434         eth->h_proto = htons(ETH_P_IP);
2435
2436         ip->daddr = daddr;
2437         ip->saddr = saddr;
2438
2439         ip->tos = tos;
2440         ip->ttl = ttl;
2441         ip->protocol = IPPROTO_UDP;
2442         ip->version = 0x4;
2443         ip->ihl = 0x5;
2444
2445         udp->dest = udp_dst_port;
2446         vxh->vx_flags = VXLAN_HF_VNI;
2447         vxh->vx_vni = vxlan_vni_field(vx_vni);
2448 }
2449
2450 static void gen_vxlan_header_ipv6(struct net_device *out_dev,
2451                                   char buf[], int encap_size,
2452                                   unsigned char h_dest[ETH_ALEN],
2453                                   u8 tos, u8 ttl,
2454                                   struct in6_addr *daddr,
2455                                   struct in6_addr *saddr,
2456                                   __be16 udp_dst_port,
2457                                   __be32 vx_vni)
2458 {
2459         struct ethhdr *eth = (struct ethhdr *)buf;
2460         struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
2461         struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
2462         struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2463
2464         memset(buf, 0, encap_size);
2465
2466         ether_addr_copy(eth->h_dest, h_dest);
2467         ether_addr_copy(eth->h_source, out_dev->dev_addr);
2468         eth->h_proto = htons(ETH_P_IPV6);
2469
2470         ip6_flow_hdr(ip6h, tos, 0);
2471         /* the HW fills up ipv6 payload len */
2472         ip6h->nexthdr     = IPPROTO_UDP;
2473         ip6h->hop_limit   = ttl;
2474         ip6h->daddr       = *daddr;
2475         ip6h->saddr       = *saddr;
2476
2477         udp->dest = udp_dst_port;
2478         vxh->vx_flags = VXLAN_HF_VNI;
2479         vxh->vx_vni = vxlan_vni_field(vx_vni);
2480 }
2481
2482 static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
2483                                           struct net_device *mirred_dev,
2484                                           struct mlx5e_encap_entry *e)
2485 {
2486         int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
2487         int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
2488         struct ip_tunnel_key *tun_key = &e->tun_info.key;
2489         struct net_device *out_dev;
2490         struct neighbour *n = NULL;
2491         struct flowi4 fl4 = {};
2492         u8 nud_state, tos, ttl;
2493         char *encap_header;
2494         int err;
2495
2496         if (max_encap_size < ipv4_encap_size) {
2497                 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2498                                ipv4_encap_size, max_encap_size);
2499                 return -EOPNOTSUPP;
2500         }
2501
2502         encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
2503         if (!encap_header)
2504                 return -ENOMEM;
2505
2506         switch (e->tunnel_type) {
2507         case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
2508                 fl4.flowi4_proto = IPPROTO_UDP;
2509                 fl4.fl4_dport = tun_key->tp_dst;
2510                 break;
2511         default:
2512                 err = -EOPNOTSUPP;
2513                 goto free_encap;
2514         }
2515
2516         tos = tun_key->tos;
2517         ttl = tun_key->ttl;
2518
2519         fl4.flowi4_tos = tun_key->tos;
2520         fl4.daddr = tun_key->u.ipv4.dst;
2521         fl4.saddr = tun_key->u.ipv4.src;
2522
2523         err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
2524                                       &fl4, &n, &ttl);
2525         if (err)
2526                 goto free_encap;
2527
2528         /* used by mlx5e_detach_encap to lookup a neigh hash table
2529          * entry in the neigh hash table when a user deletes a rule
2530          */
2531         e->m_neigh.dev = n->dev;
2532         e->m_neigh.family = n->ops->family;
2533         memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2534         e->out_dev = out_dev;
2535
2536         /* It's importent to add the neigh to the hash table before checking
2537          * the neigh validity state. So if we'll get a notification, in case the
2538          * neigh changes it's validity state, we would find the relevant neigh
2539          * in the hash.
2540          */
2541         err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2542         if (err)
2543                 goto free_encap;
2544
2545         read_lock_bh(&n->lock);
2546         nud_state = n->nud_state;
2547         ether_addr_copy(e->h_dest, n->ha);
2548         read_unlock_bh(&n->lock);
2549
2550         switch (e->tunnel_type) {
2551         case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
2552                 gen_vxlan_header_ipv4(out_dev, encap_header,
2553                                       ipv4_encap_size, e->h_dest, tos, ttl,
2554                                       fl4.daddr,
2555                                       fl4.saddr, tun_key->tp_dst,
2556                                       tunnel_id_to_key32(tun_key->tun_id));
2557                 break;
2558         default:
2559                 err = -EOPNOTSUPP;
2560                 goto destroy_neigh_entry;
2561         }
2562         e->encap_size = ipv4_encap_size;
2563         e->encap_header = encap_header;
2564
2565         if (!(nud_state & NUD_VALID)) {
2566                 neigh_event_send(n, NULL);
2567                 err = -EAGAIN;
2568                 goto out;
2569         }
2570
2571         err = mlx5_packet_reformat_alloc(priv->mdev, e->tunnel_type,
2572                                          ipv4_encap_size, encap_header,
2573                                          MLX5_FLOW_NAMESPACE_FDB,
2574                                          &e->encap_id);
2575         if (err)
2576                 goto destroy_neigh_entry;
2577
2578         e->flags |= MLX5_ENCAP_ENTRY_VALID;
2579         mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
2580         neigh_release(n);
2581         return err;
2582
2583 destroy_neigh_entry:
2584         mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
2585 free_encap:
2586         kfree(encap_header);
2587 out:
2588         if (n)
2589                 neigh_release(n);
2590         return err;
2591 }
2592
2593 static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
2594                                           struct net_device *mirred_dev,
2595                                           struct mlx5e_encap_entry *e)
2596 {
2597         int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
2598         int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
2599         struct ip_tunnel_key *tun_key = &e->tun_info.key;
2600         struct net_device *out_dev;
2601         struct neighbour *n = NULL;
2602         struct flowi6 fl6 = {};
2603         u8 nud_state, tos, ttl;
2604         char *encap_header;
2605         int err;
2606
2607         if (max_encap_size < ipv6_encap_size) {
2608                 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2609                                ipv6_encap_size, max_encap_size);
2610                 return -EOPNOTSUPP;
2611         }
2612
2613         encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
2614         if (!encap_header)
2615                 return -ENOMEM;
2616
2617         switch (e->tunnel_type) {
2618         case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
2619                 fl6.flowi6_proto = IPPROTO_UDP;
2620                 fl6.fl6_dport = tun_key->tp_dst;
2621                 break;
2622         default:
2623                 err = -EOPNOTSUPP;
2624                 goto free_encap;
2625         }
2626
2627         tos = tun_key->tos;
2628         ttl = tun_key->ttl;
2629
2630         fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
2631         fl6.daddr = tun_key->u.ipv6.dst;
2632         fl6.saddr = tun_key->u.ipv6.src;
2633
2634         err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
2635                                       &fl6, &n, &ttl);
2636         if (err)
2637                 goto free_encap;
2638
2639         /* used by mlx5e_detach_encap to lookup a neigh hash table
2640          * entry in the neigh hash table when a user deletes a rule
2641          */
2642         e->m_neigh.dev = n->dev;
2643         e->m_neigh.family = n->ops->family;
2644         memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2645         e->out_dev = out_dev;
2646
2647         /* It's importent to add the neigh to the hash table before checking
2648          * the neigh validity state. So if we'll get a notification, in case the
2649          * neigh changes it's validity state, we would find the relevant neigh
2650          * in the hash.
2651          */
2652         err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2653         if (err)
2654                 goto free_encap;
2655
2656         read_lock_bh(&n->lock);
2657         nud_state = n->nud_state;
2658         ether_addr_copy(e->h_dest, n->ha);
2659         read_unlock_bh(&n->lock);
2660
2661         switch (e->tunnel_type) {
2662         case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
2663                 gen_vxlan_header_ipv6(out_dev, encap_header,
2664                                       ipv6_encap_size, e->h_dest, tos, ttl,
2665                                       &fl6.daddr,
2666                                       &fl6.saddr, tun_key->tp_dst,
2667                                       tunnel_id_to_key32(tun_key->tun_id));
2668                 break;
2669         default:
2670                 err = -EOPNOTSUPP;
2671                 goto destroy_neigh_entry;
2672         }
2673
2674         e->encap_size = ipv6_encap_size;
2675         e->encap_header = encap_header;
2676
2677         if (!(nud_state & NUD_VALID)) {
2678                 neigh_event_send(n, NULL);
2679                 err = -EAGAIN;
2680                 goto out;
2681         }
2682
2683         err = mlx5_packet_reformat_alloc(priv->mdev, e->tunnel_type,
2684                                          ipv6_encap_size, encap_header,
2685                                          MLX5_FLOW_NAMESPACE_FDB,
2686                                          &e->encap_id);
2687         if (err)
2688                 goto destroy_neigh_entry;
2689
2690         e->flags |= MLX5_ENCAP_ENTRY_VALID;
2691         mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
2692         neigh_release(n);
2693         return err;
2694
2695 destroy_neigh_entry:
2696         mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
2697 free_encap:
2698         kfree(encap_header);
2699 out:
2700         if (n)
2701                 neigh_release(n);
2702         return err;
2703 }
2704
2705 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2706                               struct ip_tunnel_info *tun_info,
2707                               struct net_device *mirred_dev,
2708                               struct net_device **encap_dev,
2709                               struct mlx5e_tc_flow *flow,
2710                               struct netlink_ext_ack *extack)
2711 {
2712         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2713         unsigned short family = ip_tunnel_info_af(tun_info);
2714         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2715         struct ip_tunnel_key *key = &tun_info->key;
2716         struct mlx5e_encap_entry *e;
2717         int tunnel_type, err = 0;
2718         uintptr_t hash_key;
2719         bool found = false;
2720
2721         /* udp dst port must be set */
2722         if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2723                 goto vxlan_encap_offload_err;
2724
2725         /* setting udp src port isn't supported */
2726         if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
2727 vxlan_encap_offload_err:
2728                 NL_SET_ERR_MSG_MOD(extack,
2729                                    "must set udp dst port and not set udp src port");
2730                 netdev_warn(priv->netdev,
2731                             "must set udp dst port and not set udp src port\n");
2732                 return -EOPNOTSUPP;
2733         }
2734
2735         if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, be16_to_cpu(key->tp_dst)) &&
2736             MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
2737                 tunnel_type = MLX5_REFORMAT_TYPE_L2_TO_VXLAN;
2738         } else {
2739                 NL_SET_ERR_MSG_MOD(extack,
2740                                    "port isn't an offloaded vxlan udp dport");
2741                 netdev_warn(priv->netdev,
2742                             "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
2743                 return -EOPNOTSUPP;
2744         }
2745
2746         hash_key = hash_encap_info(key);
2747
2748         hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2749                                    encap_hlist, hash_key) {
2750                 if (!cmp_encap_info(&e->tun_info.key, key)) {
2751                         found = true;
2752                         break;
2753                 }
2754         }
2755
2756         /* must verify if encap is valid or not */
2757         if (found)
2758                 goto attach_flow;
2759
2760         e = kzalloc(sizeof(*e), GFP_KERNEL);
2761         if (!e)
2762                 return -ENOMEM;
2763
2764         e->tun_info = *tun_info;
2765         e->tunnel_type = tunnel_type;
2766         INIT_LIST_HEAD(&e->flows);
2767
2768         if (family == AF_INET)
2769                 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
2770         else if (family == AF_INET6)
2771                 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
2772
2773         if (err && err != -EAGAIN)
2774                 goto out_err;
2775
2776         hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2777
2778 attach_flow:
2779         list_add(&flow->encap, &e->flows);
2780         *encap_dev = e->out_dev;
2781         if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2782                 attr->encap_id = e->encap_id;
2783         else
2784                 err = -EAGAIN;
2785
2786         return err;
2787
2788 out_err:
2789         kfree(e);
2790         return err;
2791 }
2792
2793 static int parse_tc_vlan_action(struct mlx5e_priv *priv,
2794                                 const struct tc_action *a,
2795                                 struct mlx5_esw_flow_attr *attr,
2796                                 u32 *action)
2797 {
2798         u8 vlan_idx = attr->total_vlan;
2799
2800         if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2801                 return -EOPNOTSUPP;
2802
2803         if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
2804                 if (vlan_idx) {
2805                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2806                                                                  MLX5_FS_VLAN_DEPTH))
2807                                 return -EOPNOTSUPP;
2808
2809                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2810                 } else {
2811                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2812                 }
2813         } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
2814                 attr->vlan_vid[vlan_idx] = tcf_vlan_push_vid(a);
2815                 attr->vlan_prio[vlan_idx] = tcf_vlan_push_prio(a);
2816                 attr->vlan_proto[vlan_idx] = tcf_vlan_push_proto(a);
2817                 if (!attr->vlan_proto[vlan_idx])
2818                         attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2819
2820                 if (vlan_idx) {
2821                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2822                                                                  MLX5_FS_VLAN_DEPTH))
2823                                 return -EOPNOTSUPP;
2824
2825                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2826                 } else {
2827                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
2828                             (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2829                              tcf_vlan_push_prio(a)))
2830                                 return -EOPNOTSUPP;
2831
2832                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
2833                 }
2834         } else { /* action is TCA_VLAN_ACT_MODIFY */
2835                 return -EOPNOTSUPP;
2836         }
2837
2838         attr->total_vlan = vlan_idx + 1;
2839
2840         return 0;
2841 }
2842
2843 static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
2844                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
2845                                 struct mlx5e_tc_flow *flow,
2846                                 struct netlink_ext_ack *extack)
2847 {
2848         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2849         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2850         struct mlx5e_rep_priv *rpriv = priv->ppriv;