2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
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32 #ifndef __MLX5_EN_STATS_H__
33 #define __MLX5_EN_STATS_H__
35 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
36 (*(u64 *)((char *)ptr + dsc[i].offset))
37 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
38 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
39 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
40 (*(u32 *)((char *)ptr + dsc[i].offset))
41 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
42 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
44 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
45 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
46 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
47 #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld)
50 char format[ETH_GSTRING_LEN];
51 size_t offset; /* Byte offset */
54 struct mlx5e_sw_stats {
61 u64 tx_tso_inner_packets;
62 u64 tx_tso_inner_bytes;
63 u64 tx_added_vlan_packets;
67 u64 rx_removed_vlan_packets;
68 u64 rx_csum_unnecessary;
71 u64 rx_csum_unnecessary_inner;
78 u64 tx_csum_partial_inner;
88 u64 rx_mpwqe_filler_cqes;
89 u64 rx_mpwqe_filler_strides;
90 u64 rx_buff_alloc_err;
91 u64 rx_cqe_compress_blks;
92 u64 rx_cqe_compress_pkts;
106 #ifdef CONFIG_MLX5_EN_TLS
108 u64 tx_tls_resync_bytes;
112 struct mlx5e_qcounter_stats {
113 u32 rx_out_of_buffer;
114 u32 rx_if_down_packets;
117 struct mlx5e_vnic_env_stats {
118 __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)];
121 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
122 vstats->query_vport_out, c)
124 struct mlx5e_vport_stats {
125 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
128 #define PPORT_802_3_GET(pstats, c) \
129 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
130 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
131 #define PPORT_2863_GET(pstats, c) \
132 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
133 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
134 #define PPORT_2819_GET(pstats, c) \
135 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
136 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
137 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \
138 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
139 counter_set.phys_layer_statistical_cntrs.c##_high)
140 #define PPORT_PER_PRIO_GET(pstats, prio, c) \
141 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
142 counter_set.eth_per_prio_grp_data_layout.c##_high)
143 #define NUM_PPORT_PRIO 8
144 #define PPORT_ETH_EXT_GET(pstats, c) \
145 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
146 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
148 struct mlx5e_pport_stats {
149 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
150 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
151 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
152 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
153 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
154 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
155 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
158 #define PCIE_PERF_GET(pcie_stats, c) \
159 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
160 counter_set.pcie_perf_cntrs_grp_data_layout.c)
162 #define PCIE_PERF_GET64(pcie_stats, c) \
163 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
164 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
166 struct mlx5e_pcie_stats {
167 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
170 struct mlx5e_rq_stats {
174 u64 csum_unnecessary;
175 u64 csum_unnecessary_inner;
179 u64 removed_vlan_packets;
185 u64 mpwqe_filler_cqes;
186 u64 mpwqe_filler_strides;
188 u64 cqe_compress_blks;
189 u64 cqe_compress_pkts;
199 struct mlx5e_sq_stats {
200 /* commonly accessed in data path */
206 u64 tso_inner_packets;
209 u64 csum_partial_inner;
210 u64 added_vlan_packets;
213 #ifdef CONFIG_MLX5_EN_TLS
215 u64 tls_resync_bytes;
217 /* less likely accessed in data path */
222 /* dirtied @completion */
223 u64 cqes ____cacheline_aligned_in_smp;
228 struct mlx5e_ch_stats {
237 struct mlx5e_sw_stats sw;
238 struct mlx5e_qcounter_stats qcnt;
239 struct mlx5e_vnic_env_stats vnic;
240 struct mlx5e_vport_stats vport;
241 struct mlx5e_pport_stats pport;
242 struct rtnl_link_stats64 vf_vport;
243 struct mlx5e_pcie_stats pcie;
247 MLX5E_NDO_UPDATE_STATS = BIT(0x1),
251 struct mlx5e_stats_grp {
252 u16 update_stats_mask;
253 int (*get_num_stats)(struct mlx5e_priv *priv);
254 int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx);
255 int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx);
256 void (*update_stats)(struct mlx5e_priv *priv);
259 extern const struct mlx5e_stats_grp mlx5e_stats_grps[];
260 extern const int mlx5e_num_stats_grps;
262 void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv);
264 #endif /* __MLX5_EN_STATS_H__ */