2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #ifndef __MLX5_EN_STATS_H__
33 #define __MLX5_EN_STATS_H__
35 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
36 (*(u64 *)((char *)ptr + dsc[i].offset))
37 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
38 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
39 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
40 (*(u32 *)((char *)ptr + dsc[i].offset))
41 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
42 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
44 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
45 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
46 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
47 #define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld)
48 #define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld)
49 #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld)
52 char format[ETH_GSTRING_LEN];
53 size_t offset; /* Byte offset */
56 struct mlx5e_sw_stats {
63 u64 tx_tso_inner_packets;
64 u64 tx_tso_inner_bytes;
65 u64 tx_added_vlan_packets;
69 u64 rx_removed_vlan_packets;
70 u64 rx_csum_unnecessary;
73 u64 rx_csum_unnecessary_inner;
82 u64 tx_csum_partial_inner;
96 u64 rx_mpwqe_filler_cqes;
97 u64 rx_mpwqe_filler_strides;
98 u64 rx_buff_alloc_err;
99 u64 rx_cqe_compress_blks;
100 u64 rx_cqe_compress_pkts;
114 #ifdef CONFIG_MLX5_EN_TLS
116 u64 tx_tls_resync_bytes;
120 struct mlx5e_qcounter_stats {
121 u32 rx_out_of_buffer;
122 u32 rx_if_down_packets;
125 struct mlx5e_vnic_env_stats {
126 __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)];
129 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
130 vstats->query_vport_out, c)
132 struct mlx5e_vport_stats {
133 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
136 #define PPORT_802_3_GET(pstats, c) \
137 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
138 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
139 #define PPORT_2863_GET(pstats, c) \
140 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
141 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
142 #define PPORT_2819_GET(pstats, c) \
143 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
144 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
145 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \
146 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
147 counter_set.phys_layer_statistical_cntrs.c##_high)
148 #define PPORT_PER_PRIO_GET(pstats, prio, c) \
149 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
150 counter_set.eth_per_prio_grp_data_layout.c##_high)
151 #define NUM_PPORT_PRIO 8
152 #define PPORT_ETH_EXT_GET(pstats, c) \
153 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
154 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
156 struct mlx5e_pport_stats {
157 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
158 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
159 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
160 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
161 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
162 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
163 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
166 #define PCIE_PERF_GET(pcie_stats, c) \
167 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
168 counter_set.pcie_perf_cntrs_grp_data_layout.c)
170 #define PCIE_PERF_GET64(pcie_stats, c) \
171 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
172 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
174 struct mlx5e_pcie_stats {
175 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
178 struct mlx5e_rq_stats {
182 u64 csum_unnecessary;
183 u64 csum_unnecessary_inner;
187 u64 removed_vlan_packets;
191 u64 mpwqe_filler_cqes;
192 u64 mpwqe_filler_strides;
194 u64 cqe_compress_blks;
195 u64 cqe_compress_pkts;
205 struct mlx5e_sq_stats {
206 /* commonly accessed in data path */
212 u64 tso_inner_packets;
215 u64 csum_partial_inner;
216 u64 added_vlan_packets;
219 #ifdef CONFIG_MLX5_EN_TLS
221 u64 tls_resync_bytes;
223 /* less likely accessed in data path */
228 /* dirtied @completion */
229 u64 cqes ____cacheline_aligned_in_smp;
234 struct mlx5e_xdpsq_stats {
238 /* dirtied @completion */
239 u64 cqes ____cacheline_aligned_in_smp;
242 struct mlx5e_ch_stats {
251 struct mlx5e_sw_stats sw;
252 struct mlx5e_qcounter_stats qcnt;
253 struct mlx5e_vnic_env_stats vnic;
254 struct mlx5e_vport_stats vport;
255 struct mlx5e_pport_stats pport;
256 struct rtnl_link_stats64 vf_vport;
257 struct mlx5e_pcie_stats pcie;
261 MLX5E_NDO_UPDATE_STATS = BIT(0x1),
265 struct mlx5e_stats_grp {
266 u16 update_stats_mask;
267 int (*get_num_stats)(struct mlx5e_priv *priv);
268 int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx);
269 int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx);
270 void (*update_stats)(struct mlx5e_priv *priv);
273 extern const struct mlx5e_stats_grp mlx5e_stats_grps[];
274 extern const int mlx5e_num_stats_grps;
276 void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv);
278 #endif /* __MLX5_EN_STATS_H__ */