2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include "en_accel/ipsec.h"
35 #include "en_accel/tls.h"
37 static const struct counter_desc sw_stats_desc[] = {
38 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
39 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
40 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
41 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
42 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
43 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
44 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
45 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
46 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) },
47 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_nop) },
49 #ifdef CONFIG_MLX5_EN_TLS
50 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) },
51 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) },
54 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
55 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
56 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_ecn_mark) },
57 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) },
58 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
59 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
60 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
61 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
62 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
63 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_redirect) },
64 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_xmit) },
65 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
66 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_err) },
67 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_cqe) },
68 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) },
69 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
70 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
71 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
72 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
73 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
74 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) },
75 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqes) },
76 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
77 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_udp_seg_rem) },
78 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) },
79 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_xmit) },
80 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_full) },
81 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_err) },
82 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_cqes) },
83 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
84 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_cqes) },
85 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_strides) },
86 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
87 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
88 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
89 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_page_reuse) },
90 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) },
91 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) },
92 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) },
93 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) },
94 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) },
95 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_congst_umr) },
96 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_err) },
97 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_events) },
98 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_poll) },
99 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_arm) },
100 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_aff_change) },
101 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) },
104 #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
106 static int mlx5e_grp_sw_get_num_stats(struct mlx5e_priv *priv)
108 return NUM_SW_COUNTERS;
111 static int mlx5e_grp_sw_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
115 for (i = 0; i < NUM_SW_COUNTERS; i++)
116 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
120 static int mlx5e_grp_sw_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
124 for (i = 0; i < NUM_SW_COUNTERS; i++)
125 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i);
129 void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv)
131 struct mlx5e_sw_stats temp, *s = &temp;
134 memset(s, 0, sizeof(*s));
136 for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++) {
137 struct mlx5e_channel_stats *channel_stats =
138 &priv->channel_stats[i];
139 struct mlx5e_xdpsq_stats *xdpsq_red_stats = &channel_stats->xdpsq;
140 struct mlx5e_xdpsq_stats *xdpsq_stats = &channel_stats->rq_xdpsq;
141 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
142 struct mlx5e_ch_stats *ch_stats = &channel_stats->ch;
145 s->rx_packets += rq_stats->packets;
146 s->rx_bytes += rq_stats->bytes;
147 s->rx_lro_packets += rq_stats->lro_packets;
148 s->rx_lro_bytes += rq_stats->lro_bytes;
149 s->rx_ecn_mark += rq_stats->ecn_mark;
150 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
151 s->rx_csum_none += rq_stats->csum_none;
152 s->rx_csum_complete += rq_stats->csum_complete;
153 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
154 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
155 s->rx_xdp_drop += rq_stats->xdp_drop;
156 s->rx_xdp_redirect += rq_stats->xdp_redirect;
157 s->rx_xdp_tx_xmit += xdpsq_stats->xmit;
158 s->rx_xdp_tx_full += xdpsq_stats->full;
159 s->rx_xdp_tx_err += xdpsq_stats->err;
160 s->rx_xdp_tx_cqe += xdpsq_stats->cqes;
161 s->rx_wqe_err += rq_stats->wqe_err;
162 s->rx_mpwqe_filler_cqes += rq_stats->mpwqe_filler_cqes;
163 s->rx_mpwqe_filler_strides += rq_stats->mpwqe_filler_strides;
164 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
165 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
166 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
167 s->rx_page_reuse += rq_stats->page_reuse;
168 s->rx_cache_reuse += rq_stats->cache_reuse;
169 s->rx_cache_full += rq_stats->cache_full;
170 s->rx_cache_empty += rq_stats->cache_empty;
171 s->rx_cache_busy += rq_stats->cache_busy;
172 s->rx_cache_waive += rq_stats->cache_waive;
173 s->rx_congst_umr += rq_stats->congst_umr;
174 s->rx_arfs_err += rq_stats->arfs_err;
175 s->ch_events += ch_stats->events;
176 s->ch_poll += ch_stats->poll;
177 s->ch_arm += ch_stats->arm;
178 s->ch_aff_change += ch_stats->aff_change;
179 s->ch_eq_rearm += ch_stats->eq_rearm;
181 s->tx_xdp_xmit += xdpsq_red_stats->xmit;
182 s->tx_xdp_full += xdpsq_red_stats->full;
183 s->tx_xdp_err += xdpsq_red_stats->err;
184 s->tx_xdp_cqes += xdpsq_red_stats->cqes;
186 for (j = 0; j < priv->max_opened_tc; j++) {
187 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
189 s->tx_packets += sq_stats->packets;
190 s->tx_bytes += sq_stats->bytes;
191 s->tx_tso_packets += sq_stats->tso_packets;
192 s->tx_tso_bytes += sq_stats->tso_bytes;
193 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
194 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
195 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
196 s->tx_nop += sq_stats->nop;
197 s->tx_queue_stopped += sq_stats->stopped;
198 s->tx_queue_wake += sq_stats->wake;
199 s->tx_udp_seg_rem += sq_stats->udp_seg_rem;
200 s->tx_queue_dropped += sq_stats->dropped;
201 s->tx_cqe_err += sq_stats->cqe_err;
202 s->tx_recover += sq_stats->recover;
203 s->tx_xmit_more += sq_stats->xmit_more;
204 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
205 s->tx_csum_none += sq_stats->csum_none;
206 s->tx_csum_partial += sq_stats->csum_partial;
207 #ifdef CONFIG_MLX5_EN_TLS
208 s->tx_tls_ooo += sq_stats->tls_ooo;
209 s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes;
211 s->tx_cqes += sq_stats->cqes;
215 memcpy(&priv->stats.sw, s, sizeof(*s));
218 static const struct counter_desc q_stats_desc[] = {
219 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
222 static const struct counter_desc drop_rq_stats_desc[] = {
223 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) },
226 #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
227 #define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc)
229 static int mlx5e_grp_q_get_num_stats(struct mlx5e_priv *priv)
234 num_stats += NUM_Q_COUNTERS;
236 if (priv->drop_rq_q_counter)
237 num_stats += NUM_DROP_RQ_COUNTERS;
242 static int mlx5e_grp_q_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
246 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
247 strcpy(data + (idx++) * ETH_GSTRING_LEN,
248 q_stats_desc[i].format);
250 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
251 strcpy(data + (idx++) * ETH_GSTRING_LEN,
252 drop_rq_stats_desc[i].format);
257 static int mlx5e_grp_q_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
261 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
262 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
264 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
265 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
266 drop_rq_stats_desc, i);
270 static void mlx5e_grp_q_update_stats(struct mlx5e_priv *priv)
272 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
273 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
275 if (priv->q_counter &&
276 !mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out,
278 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out,
280 if (priv->drop_rq_q_counter &&
281 !mlx5_core_query_q_counter(priv->mdev, priv->drop_rq_q_counter, 0,
283 qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out, out,
287 #define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c)
288 static const struct counter_desc vnic_env_stats_desc[] = {
289 { "rx_steer_missed_packets",
290 VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) },
293 #define NUM_VNIC_ENV_COUNTERS ARRAY_SIZE(vnic_env_stats_desc)
295 static int mlx5e_grp_vnic_env_get_num_stats(struct mlx5e_priv *priv)
297 return MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard) ?
298 NUM_VNIC_ENV_COUNTERS : 0;
301 static int mlx5e_grp_vnic_env_fill_strings(struct mlx5e_priv *priv, u8 *data,
306 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
309 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
310 strcpy(data + (idx++) * ETH_GSTRING_LEN,
311 vnic_env_stats_desc[i].format);
315 static int mlx5e_grp_vnic_env_fill_stats(struct mlx5e_priv *priv, u64 *data,
320 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
323 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
324 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out,
325 vnic_env_stats_desc, i);
329 static void mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
331 u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out;
332 int outlen = MLX5_ST_SZ_BYTES(query_vnic_env_out);
333 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0};
334 struct mlx5_core_dev *mdev = priv->mdev;
336 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
339 MLX5_SET(query_vnic_env_in, in, opcode,
340 MLX5_CMD_OP_QUERY_VNIC_ENV);
341 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
342 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
343 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
346 #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
347 static const struct counter_desc vport_stats_desc[] = {
348 { "rx_vport_unicast_packets",
349 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
350 { "rx_vport_unicast_bytes",
351 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
352 { "tx_vport_unicast_packets",
353 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
354 { "tx_vport_unicast_bytes",
355 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
356 { "rx_vport_multicast_packets",
357 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
358 { "rx_vport_multicast_bytes",
359 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
360 { "tx_vport_multicast_packets",
361 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
362 { "tx_vport_multicast_bytes",
363 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
364 { "rx_vport_broadcast_packets",
365 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
366 { "rx_vport_broadcast_bytes",
367 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
368 { "tx_vport_broadcast_packets",
369 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
370 { "tx_vport_broadcast_bytes",
371 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
372 { "rx_vport_rdma_unicast_packets",
373 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
374 { "rx_vport_rdma_unicast_bytes",
375 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
376 { "tx_vport_rdma_unicast_packets",
377 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
378 { "tx_vport_rdma_unicast_bytes",
379 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
380 { "rx_vport_rdma_multicast_packets",
381 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
382 { "rx_vport_rdma_multicast_bytes",
383 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
384 { "tx_vport_rdma_multicast_packets",
385 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
386 { "tx_vport_rdma_multicast_bytes",
387 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
390 #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
392 static int mlx5e_grp_vport_get_num_stats(struct mlx5e_priv *priv)
394 return NUM_VPORT_COUNTERS;
397 static int mlx5e_grp_vport_fill_strings(struct mlx5e_priv *priv, u8 *data,
402 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
403 strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format);
407 static int mlx5e_grp_vport_fill_stats(struct mlx5e_priv *priv, u64 *data,
412 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
413 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
414 vport_stats_desc, i);
418 static void mlx5e_grp_vport_update_stats(struct mlx5e_priv *priv)
420 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
421 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
422 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
423 struct mlx5_core_dev *mdev = priv->mdev;
425 MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER);
426 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
427 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
428 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
431 #define PPORT_802_3_OFF(c) \
432 MLX5_BYTE_OFF(ppcnt_reg, \
433 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
434 static const struct counter_desc pport_802_3_stats_desc[] = {
435 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
436 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
437 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
438 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
439 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
440 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
441 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
442 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
443 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
444 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
445 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
446 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
447 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
448 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
449 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
450 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
451 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
452 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
455 #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
457 static int mlx5e_grp_802_3_get_num_stats(struct mlx5e_priv *priv)
459 return NUM_PPORT_802_3_COUNTERS;
462 static int mlx5e_grp_802_3_fill_strings(struct mlx5e_priv *priv, u8 *data,
467 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
468 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format);
472 static int mlx5e_grp_802_3_fill_stats(struct mlx5e_priv *priv, u64 *data,
477 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
478 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
479 pport_802_3_stats_desc, i);
483 static void mlx5e_grp_802_3_update_stats(struct mlx5e_priv *priv)
485 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
486 struct mlx5_core_dev *mdev = priv->mdev;
487 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
488 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
491 MLX5_SET(ppcnt_reg, in, local_port, 1);
492 out = pstats->IEEE_802_3_counters;
493 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
494 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
497 #define PPORT_2863_OFF(c) \
498 MLX5_BYTE_OFF(ppcnt_reg, \
499 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
500 static const struct counter_desc pport_2863_stats_desc[] = {
501 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
502 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
503 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
506 #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
508 static int mlx5e_grp_2863_get_num_stats(struct mlx5e_priv *priv)
510 return NUM_PPORT_2863_COUNTERS;
513 static int mlx5e_grp_2863_fill_strings(struct mlx5e_priv *priv, u8 *data,
518 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
519 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format);
523 static int mlx5e_grp_2863_fill_stats(struct mlx5e_priv *priv, u64 *data,
528 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
529 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
530 pport_2863_stats_desc, i);
534 static void mlx5e_grp_2863_update_stats(struct mlx5e_priv *priv)
536 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
537 struct mlx5_core_dev *mdev = priv->mdev;
538 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
539 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
542 MLX5_SET(ppcnt_reg, in, local_port, 1);
543 out = pstats->RFC_2863_counters;
544 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
545 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
548 #define PPORT_2819_OFF(c) \
549 MLX5_BYTE_OFF(ppcnt_reg, \
550 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
551 static const struct counter_desc pport_2819_stats_desc[] = {
552 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
553 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
554 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
555 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
556 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
557 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
558 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
559 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
560 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
561 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
562 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
563 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
564 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
567 #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
569 static int mlx5e_grp_2819_get_num_stats(struct mlx5e_priv *priv)
571 return NUM_PPORT_2819_COUNTERS;
574 static int mlx5e_grp_2819_fill_strings(struct mlx5e_priv *priv, u8 *data,
579 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
580 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format);
584 static int mlx5e_grp_2819_fill_stats(struct mlx5e_priv *priv, u64 *data,
589 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
590 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
591 pport_2819_stats_desc, i);
595 static void mlx5e_grp_2819_update_stats(struct mlx5e_priv *priv)
597 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
598 struct mlx5_core_dev *mdev = priv->mdev;
599 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
600 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
603 MLX5_SET(ppcnt_reg, in, local_port, 1);
604 out = pstats->RFC_2819_counters;
605 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
606 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
609 #define PPORT_PHY_STATISTICAL_OFF(c) \
610 MLX5_BYTE_OFF(ppcnt_reg, \
611 counter_set.phys_layer_statistical_cntrs.c##_high)
612 static const struct counter_desc pport_phy_statistical_stats_desc[] = {
613 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) },
614 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) },
617 #define NUM_PPORT_PHY_STATISTICAL_COUNTERS ARRAY_SIZE(pport_phy_statistical_stats_desc)
619 static int mlx5e_grp_phy_get_num_stats(struct mlx5e_priv *priv)
621 /* "1" for link_down_events special counter */
622 return MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group) ?
623 NUM_PPORT_PHY_STATISTICAL_COUNTERS + 1 : 1;
626 static int mlx5e_grp_phy_fill_strings(struct mlx5e_priv *priv, u8 *data,
631 strcpy(data + (idx++) * ETH_GSTRING_LEN, "link_down_events_phy");
633 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
636 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
637 strcpy(data + (idx++) * ETH_GSTRING_LEN,
638 pport_phy_statistical_stats_desc[i].format);
642 static int mlx5e_grp_phy_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
646 /* link_down_events_phy has special handling since it is not stored in __be64 format */
647 data[idx++] = MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters,
648 counter_set.phys_layer_cntrs.link_down_events);
650 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
653 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
655 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
656 pport_phy_statistical_stats_desc, i);
660 static void mlx5e_grp_phy_update_stats(struct mlx5e_priv *priv)
662 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
663 struct mlx5_core_dev *mdev = priv->mdev;
664 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
665 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
668 MLX5_SET(ppcnt_reg, in, local_port, 1);
669 out = pstats->phy_counters;
670 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
671 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
673 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
676 out = pstats->phy_statistical_counters;
677 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
678 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
681 #define PPORT_ETH_EXT_OFF(c) \
682 MLX5_BYTE_OFF(ppcnt_reg, \
683 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
684 static const struct counter_desc pport_eth_ext_stats_desc[] = {
685 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) },
688 #define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc)
690 static int mlx5e_grp_eth_ext_get_num_stats(struct mlx5e_priv *priv)
692 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
693 return NUM_PPORT_ETH_EXT_COUNTERS;
698 static int mlx5e_grp_eth_ext_fill_strings(struct mlx5e_priv *priv, u8 *data,
703 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
704 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
705 strcpy(data + (idx++) * ETH_GSTRING_LEN,
706 pport_eth_ext_stats_desc[i].format);
710 static int mlx5e_grp_eth_ext_fill_stats(struct mlx5e_priv *priv, u64 *data,
715 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
716 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
718 MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
719 pport_eth_ext_stats_desc, i);
723 static void mlx5e_grp_eth_ext_update_stats(struct mlx5e_priv *priv)
725 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
726 struct mlx5_core_dev *mdev = priv->mdev;
727 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
728 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
731 if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters))
734 MLX5_SET(ppcnt_reg, in, local_port, 1);
735 out = pstats->eth_ext_counters;
736 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
737 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
740 #define PCIE_PERF_OFF(c) \
741 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)
742 static const struct counter_desc pcie_perf_stats_desc[] = {
743 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },
744 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
747 #define PCIE_PERF_OFF64(c) \
748 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
749 static const struct counter_desc pcie_perf_stats_desc64[] = {
750 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
753 static const struct counter_desc pcie_perf_stall_stats_desc[] = {
754 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
755 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
756 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
757 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
760 #define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc)
761 #define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64)
762 #define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc)
764 static int mlx5e_grp_pcie_get_num_stats(struct mlx5e_priv *priv)
768 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
769 num_stats += NUM_PCIE_PERF_COUNTERS;
771 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
772 num_stats += NUM_PCIE_PERF_COUNTERS64;
774 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
775 num_stats += NUM_PCIE_PERF_STALL_COUNTERS;
780 static int mlx5e_grp_pcie_fill_strings(struct mlx5e_priv *priv, u8 *data,
785 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
786 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
787 strcpy(data + (idx++) * ETH_GSTRING_LEN,
788 pcie_perf_stats_desc[i].format);
790 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
791 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
792 strcpy(data + (idx++) * ETH_GSTRING_LEN,
793 pcie_perf_stats_desc64[i].format);
795 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
796 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
797 strcpy(data + (idx++) * ETH_GSTRING_LEN,
798 pcie_perf_stall_stats_desc[i].format);
802 static int mlx5e_grp_pcie_fill_stats(struct mlx5e_priv *priv, u64 *data,
807 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
808 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
810 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
811 pcie_perf_stats_desc, i);
813 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
814 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
816 MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
817 pcie_perf_stats_desc64, i);
819 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
820 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
822 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
823 pcie_perf_stall_stats_desc, i);
827 static void mlx5e_grp_pcie_update_stats(struct mlx5e_priv *priv)
829 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
830 struct mlx5_core_dev *mdev = priv->mdev;
831 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
832 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
835 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
838 out = pcie_stats->pcie_perf_counters;
839 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
840 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
843 #define PPORT_PER_PRIO_OFF(c) \
844 MLX5_BYTE_OFF(ppcnt_reg, \
845 counter_set.eth_per_prio_grp_data_layout.c##_high)
846 static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
847 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
848 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
849 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
850 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
853 #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
855 static int mlx5e_grp_per_prio_traffic_get_num_stats(void)
857 return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO;
860 static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv,
866 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
867 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
868 sprintf(data + (idx++) * ETH_GSTRING_LEN,
869 pport_per_prio_traffic_stats_desc[i].format, prio);
875 static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv,
881 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
882 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
884 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
885 pport_per_prio_traffic_stats_desc, i);
891 static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
892 /* %s is "global" or "prio{i}" */
893 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
894 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
895 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
896 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
897 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
900 static const struct counter_desc pport_pfc_stall_stats_desc[] = {
901 { "tx_pause_storm_warning_events ", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) },
902 { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) },
905 #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
906 #define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \
907 MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \
908 MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
910 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
912 struct mlx5_core_dev *mdev = priv->mdev;
917 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
920 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
922 return err ? 0 : pfc_en_tx | pfc_en_rx;
925 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
927 struct mlx5_core_dev *mdev = priv->mdev;
932 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
935 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
937 return err ? false : rx_pause | tx_pause;
940 static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv)
942 return (mlx5e_query_global_pause_combined(priv) +
943 hweight8(mlx5e_query_pfc_combined(priv))) *
944 NUM_PPORT_PER_PRIO_PFC_COUNTERS +
945 NUM_PPORT_PFC_STALL_COUNTERS(priv);
948 static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
952 unsigned long pfc_combined;
955 pfc_combined = mlx5e_query_pfc_combined(priv);
956 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
957 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
958 char pfc_string[ETH_GSTRING_LEN];
960 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
961 sprintf(data + (idx++) * ETH_GSTRING_LEN,
962 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
966 if (mlx5e_query_global_pause_combined(priv)) {
967 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
968 sprintf(data + (idx++) * ETH_GSTRING_LEN,
969 pport_per_prio_pfc_stats_desc[i].format, "global");
973 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
974 strcpy(data + (idx++) * ETH_GSTRING_LEN,
975 pport_pfc_stall_stats_desc[i].format);
980 static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv,
984 unsigned long pfc_combined;
987 pfc_combined = mlx5e_query_pfc_combined(priv);
988 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
989 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
991 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
992 pport_per_prio_pfc_stats_desc, i);
996 if (mlx5e_query_global_pause_combined(priv)) {
997 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
999 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
1000 pport_per_prio_pfc_stats_desc, i);
1004 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
1005 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
1006 pport_pfc_stall_stats_desc, i);
1011 static int mlx5e_grp_per_prio_get_num_stats(struct mlx5e_priv *priv)
1013 return mlx5e_grp_per_prio_traffic_get_num_stats() +
1014 mlx5e_grp_per_prio_pfc_get_num_stats(priv);
1017 static int mlx5e_grp_per_prio_fill_strings(struct mlx5e_priv *priv, u8 *data,
1020 idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx);
1021 idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx);
1025 static int mlx5e_grp_per_prio_fill_stats(struct mlx5e_priv *priv, u64 *data,
1028 idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx);
1029 idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx);
1033 static void mlx5e_grp_per_prio_update_stats(struct mlx5e_priv *priv)
1035 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1036 struct mlx5_core_dev *mdev = priv->mdev;
1037 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1038 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1042 MLX5_SET(ppcnt_reg, in, local_port, 1);
1043 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
1044 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1045 out = pstats->per_prio_counters[prio];
1046 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1047 mlx5_core_access_reg(mdev, in, sz, out, sz,
1048 MLX5_REG_PPCNT, 0, 0);
1052 static const struct counter_desc mlx5e_pme_status_desc[] = {
1053 { "module_unplug", 8 },
1056 static const struct counter_desc mlx5e_pme_error_desc[] = {
1057 { "module_bus_stuck", 16 }, /* bus stuck (I2C or data shorted) */
1058 { "module_high_temp", 48 }, /* high temperature */
1059 { "module_bad_shorted", 56 }, /* bad or shorted cable/module */
1062 #define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc)
1063 #define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc)
1065 static int mlx5e_grp_pme_get_num_stats(struct mlx5e_priv *priv)
1067 return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS;
1070 static int mlx5e_grp_pme_fill_strings(struct mlx5e_priv *priv, u8 *data,
1075 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1076 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
1078 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1079 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
1084 static int mlx5e_grp_pme_fill_stats(struct mlx5e_priv *priv, u64 *data,
1087 struct mlx5_priv *mlx5_priv = &priv->mdev->priv;
1090 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1091 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
1092 mlx5e_pme_status_desc, i);
1094 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1095 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
1096 mlx5e_pme_error_desc, i);
1101 static int mlx5e_grp_ipsec_get_num_stats(struct mlx5e_priv *priv)
1103 return mlx5e_ipsec_get_count(priv);
1106 static int mlx5e_grp_ipsec_fill_strings(struct mlx5e_priv *priv, u8 *data,
1109 return idx + mlx5e_ipsec_get_strings(priv,
1110 data + idx * ETH_GSTRING_LEN);
1113 static int mlx5e_grp_ipsec_fill_stats(struct mlx5e_priv *priv, u64 *data,
1116 return idx + mlx5e_ipsec_get_stats(priv, data + idx);
1119 static void mlx5e_grp_ipsec_update_stats(struct mlx5e_priv *priv)
1121 mlx5e_ipsec_update_stats(priv);
1124 static int mlx5e_grp_tls_get_num_stats(struct mlx5e_priv *priv)
1126 return mlx5e_tls_get_count(priv);
1129 static int mlx5e_grp_tls_fill_strings(struct mlx5e_priv *priv, u8 *data,
1132 return idx + mlx5e_tls_get_strings(priv, data + idx * ETH_GSTRING_LEN);
1135 static int mlx5e_grp_tls_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
1137 return idx + mlx5e_tls_get_stats(priv, data + idx);
1140 static const struct counter_desc rq_stats_desc[] = {
1141 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
1142 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
1143 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
1144 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
1145 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
1146 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
1147 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
1148 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_redirect) },
1149 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
1150 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
1151 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, ecn_mark) },
1152 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
1153 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
1154 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) },
1155 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) },
1156 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
1157 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
1158 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
1159 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, page_reuse) },
1160 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) },
1161 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) },
1162 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) },
1163 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) },
1164 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) },
1165 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, congst_umr) },
1166 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_err) },
1169 static const struct counter_desc sq_stats_desc[] = {
1170 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
1171 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
1172 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
1173 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
1174 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
1175 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
1176 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
1177 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
1178 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
1179 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
1180 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
1181 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
1182 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
1183 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
1184 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) },
1185 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqes) },
1186 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
1187 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
1190 static const struct counter_desc rq_xdpsq_stats_desc[] = {
1191 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
1192 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) },
1193 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) },
1194 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
1197 static const struct counter_desc xdpsq_stats_desc[] = {
1198 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
1199 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) },
1200 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) },
1201 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
1204 static const struct counter_desc ch_stats_desc[] = {
1205 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, events) },
1206 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, poll) },
1207 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, arm) },
1208 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, aff_change) },
1209 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) },
1212 #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
1213 #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
1214 #define NUM_XDPSQ_STATS ARRAY_SIZE(xdpsq_stats_desc)
1215 #define NUM_RQ_XDPSQ_STATS ARRAY_SIZE(rq_xdpsq_stats_desc)
1216 #define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc)
1218 static int mlx5e_grp_channels_get_num_stats(struct mlx5e_priv *priv)
1220 int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1222 return (NUM_RQ_STATS * max_nch) +
1223 (NUM_CH_STATS * max_nch) +
1224 (NUM_SQ_STATS * max_nch * priv->max_opened_tc) +
1225 (NUM_RQ_XDPSQ_STATS * max_nch) +
1226 (NUM_XDPSQ_STATS * max_nch);
1229 static int mlx5e_grp_channels_fill_strings(struct mlx5e_priv *priv, u8 *data,
1232 int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1235 for (i = 0; i < max_nch; i++)
1236 for (j = 0; j < NUM_CH_STATS; j++)
1237 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1238 ch_stats_desc[j].format, i);
1240 for (i = 0; i < max_nch; i++) {
1241 for (j = 0; j < NUM_RQ_STATS; j++)
1242 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1243 rq_stats_desc[j].format, i);
1244 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
1245 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1246 rq_xdpsq_stats_desc[j].format, i);
1249 for (tc = 0; tc < priv->max_opened_tc; tc++)
1250 for (i = 0; i < max_nch; i++)
1251 for (j = 0; j < NUM_SQ_STATS; j++)
1252 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1253 sq_stats_desc[j].format,
1254 priv->channel_tc2txq[i][tc]);
1256 for (i = 0; i < max_nch; i++)
1257 for (j = 0; j < NUM_XDPSQ_STATS; j++)
1258 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1259 xdpsq_stats_desc[j].format, i);
1264 static int mlx5e_grp_channels_fill_stats(struct mlx5e_priv *priv, u64 *data,
1267 int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1270 for (i = 0; i < max_nch; i++)
1271 for (j = 0; j < NUM_CH_STATS; j++)
1273 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].ch,
1276 for (i = 0; i < max_nch; i++) {
1277 for (j = 0; j < NUM_RQ_STATS; j++)
1279 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq,
1281 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
1283 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq_xdpsq,
1284 rq_xdpsq_stats_desc, j);
1287 for (tc = 0; tc < priv->max_opened_tc; tc++)
1288 for (i = 0; i < max_nch; i++)
1289 for (j = 0; j < NUM_SQ_STATS; j++)
1291 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].sq[tc],
1294 for (i = 0; i < max_nch; i++)
1295 for (j = 0; j < NUM_XDPSQ_STATS; j++)
1297 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].xdpsq,
1298 xdpsq_stats_desc, j);
1303 /* The stats groups order is opposite to the update_stats() order calls */
1304 const struct mlx5e_stats_grp mlx5e_stats_grps[] = {
1306 .get_num_stats = mlx5e_grp_sw_get_num_stats,
1307 .fill_strings = mlx5e_grp_sw_fill_strings,
1308 .fill_stats = mlx5e_grp_sw_fill_stats,
1309 .update_stats = mlx5e_grp_sw_update_stats,
1312 .get_num_stats = mlx5e_grp_q_get_num_stats,
1313 .fill_strings = mlx5e_grp_q_fill_strings,
1314 .fill_stats = mlx5e_grp_q_fill_stats,
1315 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1316 .update_stats = mlx5e_grp_q_update_stats,
1319 .get_num_stats = mlx5e_grp_vnic_env_get_num_stats,
1320 .fill_strings = mlx5e_grp_vnic_env_fill_strings,
1321 .fill_stats = mlx5e_grp_vnic_env_fill_stats,
1322 .update_stats = mlx5e_grp_vnic_env_update_stats,
1325 .get_num_stats = mlx5e_grp_vport_get_num_stats,
1326 .fill_strings = mlx5e_grp_vport_fill_strings,
1327 .fill_stats = mlx5e_grp_vport_fill_stats,
1328 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1329 .update_stats = mlx5e_grp_vport_update_stats,
1332 .get_num_stats = mlx5e_grp_802_3_get_num_stats,
1333 .fill_strings = mlx5e_grp_802_3_fill_strings,
1334 .fill_stats = mlx5e_grp_802_3_fill_stats,
1335 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1336 .update_stats = mlx5e_grp_802_3_update_stats,
1339 .get_num_stats = mlx5e_grp_2863_get_num_stats,
1340 .fill_strings = mlx5e_grp_2863_fill_strings,
1341 .fill_stats = mlx5e_grp_2863_fill_stats,
1342 .update_stats = mlx5e_grp_2863_update_stats,
1345 .get_num_stats = mlx5e_grp_2819_get_num_stats,
1346 .fill_strings = mlx5e_grp_2819_fill_strings,
1347 .fill_stats = mlx5e_grp_2819_fill_stats,
1348 .update_stats = mlx5e_grp_2819_update_stats,
1351 .get_num_stats = mlx5e_grp_phy_get_num_stats,
1352 .fill_strings = mlx5e_grp_phy_fill_strings,
1353 .fill_stats = mlx5e_grp_phy_fill_stats,
1354 .update_stats = mlx5e_grp_phy_update_stats,
1357 .get_num_stats = mlx5e_grp_eth_ext_get_num_stats,
1358 .fill_strings = mlx5e_grp_eth_ext_fill_strings,
1359 .fill_stats = mlx5e_grp_eth_ext_fill_stats,
1360 .update_stats = mlx5e_grp_eth_ext_update_stats,
1363 .get_num_stats = mlx5e_grp_pcie_get_num_stats,
1364 .fill_strings = mlx5e_grp_pcie_fill_strings,
1365 .fill_stats = mlx5e_grp_pcie_fill_stats,
1366 .update_stats = mlx5e_grp_pcie_update_stats,
1369 .get_num_stats = mlx5e_grp_per_prio_get_num_stats,
1370 .fill_strings = mlx5e_grp_per_prio_fill_strings,
1371 .fill_stats = mlx5e_grp_per_prio_fill_stats,
1372 .update_stats = mlx5e_grp_per_prio_update_stats,
1375 .get_num_stats = mlx5e_grp_pme_get_num_stats,
1376 .fill_strings = mlx5e_grp_pme_fill_strings,
1377 .fill_stats = mlx5e_grp_pme_fill_stats,
1380 .get_num_stats = mlx5e_grp_ipsec_get_num_stats,
1381 .fill_strings = mlx5e_grp_ipsec_fill_strings,
1382 .fill_stats = mlx5e_grp_ipsec_fill_stats,
1383 .update_stats = mlx5e_grp_ipsec_update_stats,
1386 .get_num_stats = mlx5e_grp_tls_get_num_stats,
1387 .fill_strings = mlx5e_grp_tls_fill_strings,
1388 .fill_stats = mlx5e_grp_tls_fill_stats,
1391 .get_num_stats = mlx5e_grp_channels_get_num_stats,
1392 .fill_strings = mlx5e_grp_channels_fill_strings,
1393 .fill_stats = mlx5e_grp_channels_fill_stats,
1397 const int mlx5e_num_stats_grps = ARRAY_SIZE(mlx5e_stats_grps);