2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include "en_accel/ipsec.h"
36 static const struct counter_desc sw_stats_desc[] = {
37 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
38 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
39 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
40 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
41 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
42 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
43 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
44 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
45 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) },
46 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
47 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
48 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) },
49 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
50 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
51 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
52 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
53 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
54 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx) },
55 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
56 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) },
57 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
58 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
59 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
60 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
61 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
62 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
63 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) },
64 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) },
65 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
66 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler) },
67 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
68 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
69 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
70 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_page_reuse) },
71 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) },
72 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) },
73 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) },
74 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) },
75 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) },
76 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) },
77 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, link_down_events_phy) },
80 #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
82 static int mlx5e_grp_sw_get_num_stats(struct mlx5e_priv *priv)
84 return NUM_SW_COUNTERS;
87 static int mlx5e_grp_sw_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
91 for (i = 0; i < NUM_SW_COUNTERS; i++)
92 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
96 static int mlx5e_grp_sw_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
100 for (i = 0; i < NUM_SW_COUNTERS; i++)
101 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i);
105 static void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv)
107 struct mlx5e_sw_stats temp, *s = &temp;
108 struct mlx5e_rq_stats *rq_stats;
109 struct mlx5e_sq_stats *sq_stats;
110 struct mlx5e_ch_stats *ch_stats;
113 memset(s, 0, sizeof(*s));
114 for (i = 0; i < priv->channels.num; i++) {
115 struct mlx5e_channel *c = priv->channels.c[i];
117 rq_stats = &c->rq.stats;
118 ch_stats = &c->stats;
120 s->rx_packets += rq_stats->packets;
121 s->rx_bytes += rq_stats->bytes;
122 s->rx_lro_packets += rq_stats->lro_packets;
123 s->rx_lro_bytes += rq_stats->lro_bytes;
124 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
125 s->rx_csum_none += rq_stats->csum_none;
126 s->rx_csum_complete += rq_stats->csum_complete;
127 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
128 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
129 s->rx_xdp_drop += rq_stats->xdp_drop;
130 s->rx_xdp_tx += rq_stats->xdp_tx;
131 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
132 s->rx_wqe_err += rq_stats->wqe_err;
133 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
134 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
135 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
136 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
137 s->rx_page_reuse += rq_stats->page_reuse;
138 s->rx_cache_reuse += rq_stats->cache_reuse;
139 s->rx_cache_full += rq_stats->cache_full;
140 s->rx_cache_empty += rq_stats->cache_empty;
141 s->rx_cache_busy += rq_stats->cache_busy;
142 s->rx_cache_waive += rq_stats->cache_waive;
143 s->ch_eq_rearm += ch_stats->eq_rearm;
145 for (j = 0; j < priv->channels.params.num_tc; j++) {
146 sq_stats = &c->sq[j].stats;
148 s->tx_packets += sq_stats->packets;
149 s->tx_bytes += sq_stats->bytes;
150 s->tx_tso_packets += sq_stats->tso_packets;
151 s->tx_tso_bytes += sq_stats->tso_bytes;
152 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
153 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
154 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
155 s->tx_queue_stopped += sq_stats->stopped;
156 s->tx_queue_wake += sq_stats->wake;
157 s->tx_queue_dropped += sq_stats->dropped;
158 s->tx_cqe_err += sq_stats->cqe_err;
159 s->tx_recover += sq_stats->recover;
160 s->tx_xmit_more += sq_stats->xmit_more;
161 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
162 s->tx_csum_none += sq_stats->csum_none;
163 s->tx_csum_partial += sq_stats->csum_partial;
167 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
168 priv->stats.pport.phy_counters,
169 counter_set.phys_layer_cntrs.link_down_events);
170 memcpy(&priv->stats.sw, s, sizeof(*s));
173 static const struct counter_desc q_stats_desc[] = {
174 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
177 static const struct counter_desc drop_rq_stats_desc[] = {
178 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) },
181 #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
182 #define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc)
184 static int mlx5e_grp_q_get_num_stats(struct mlx5e_priv *priv)
189 num_stats += NUM_Q_COUNTERS;
191 if (priv->drop_rq_q_counter)
192 num_stats += NUM_DROP_RQ_COUNTERS;
197 static int mlx5e_grp_q_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
201 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
202 strcpy(data + (idx++) * ETH_GSTRING_LEN,
203 q_stats_desc[i].format);
205 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
206 strcpy(data + (idx++) * ETH_GSTRING_LEN,
207 drop_rq_stats_desc[i].format);
212 static int mlx5e_grp_q_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
216 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
217 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
219 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
220 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
221 drop_rq_stats_desc, i);
225 static void mlx5e_grp_q_update_stats(struct mlx5e_priv *priv)
227 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
228 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
230 if (priv->q_counter &&
231 !mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out,
233 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out,
235 if (priv->drop_rq_q_counter &&
236 !mlx5_core_query_q_counter(priv->mdev, priv->drop_rq_q_counter, 0,
238 qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out, out,
242 #define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c)
243 static const struct counter_desc vnic_env_stats_desc[] = {
244 { "rx_steer_missed_packets",
245 VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) },
248 #define NUM_VNIC_ENV_COUNTERS ARRAY_SIZE(vnic_env_stats_desc)
250 static int mlx5e_grp_vnic_env_get_num_stats(struct mlx5e_priv *priv)
252 return MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard) ?
253 NUM_VNIC_ENV_COUNTERS : 0;
256 static int mlx5e_grp_vnic_env_fill_strings(struct mlx5e_priv *priv, u8 *data,
261 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
264 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
265 strcpy(data + (idx++) * ETH_GSTRING_LEN,
266 vnic_env_stats_desc[i].format);
270 static int mlx5e_grp_vnic_env_fill_stats(struct mlx5e_priv *priv, u64 *data,
275 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
278 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
279 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out,
280 vnic_env_stats_desc, i);
284 static void mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
286 u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out;
287 int outlen = MLX5_ST_SZ_BYTES(query_vnic_env_out);
288 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0};
289 struct mlx5_core_dev *mdev = priv->mdev;
291 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
294 MLX5_SET(query_vnic_env_in, in, opcode,
295 MLX5_CMD_OP_QUERY_VNIC_ENV);
296 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
297 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
298 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
301 #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
302 static const struct counter_desc vport_stats_desc[] = {
303 { "rx_vport_unicast_packets",
304 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
305 { "rx_vport_unicast_bytes",
306 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
307 { "tx_vport_unicast_packets",
308 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
309 { "tx_vport_unicast_bytes",
310 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
311 { "rx_vport_multicast_packets",
312 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
313 { "rx_vport_multicast_bytes",
314 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
315 { "tx_vport_multicast_packets",
316 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
317 { "tx_vport_multicast_bytes",
318 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
319 { "rx_vport_broadcast_packets",
320 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
321 { "rx_vport_broadcast_bytes",
322 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
323 { "tx_vport_broadcast_packets",
324 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
325 { "tx_vport_broadcast_bytes",
326 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
327 { "rx_vport_rdma_unicast_packets",
328 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
329 { "rx_vport_rdma_unicast_bytes",
330 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
331 { "tx_vport_rdma_unicast_packets",
332 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
333 { "tx_vport_rdma_unicast_bytes",
334 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
335 { "rx_vport_rdma_multicast_packets",
336 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
337 { "rx_vport_rdma_multicast_bytes",
338 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
339 { "tx_vport_rdma_multicast_packets",
340 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
341 { "tx_vport_rdma_multicast_bytes",
342 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
345 #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
347 static int mlx5e_grp_vport_get_num_stats(struct mlx5e_priv *priv)
349 return NUM_VPORT_COUNTERS;
352 static int mlx5e_grp_vport_fill_strings(struct mlx5e_priv *priv, u8 *data,
357 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
358 strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format);
362 static int mlx5e_grp_vport_fill_stats(struct mlx5e_priv *priv, u64 *data,
367 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
368 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
369 vport_stats_desc, i);
373 static void mlx5e_grp_vport_update_stats(struct mlx5e_priv *priv)
375 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
376 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
377 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
378 struct mlx5_core_dev *mdev = priv->mdev;
380 MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER);
381 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
382 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
383 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
386 #define PPORT_802_3_OFF(c) \
387 MLX5_BYTE_OFF(ppcnt_reg, \
388 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
389 static const struct counter_desc pport_802_3_stats_desc[] = {
390 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
391 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
392 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
393 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
394 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
395 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
396 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
397 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
398 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
399 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
400 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
401 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
402 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
403 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
404 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
405 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
406 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
407 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
410 #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
412 static int mlx5e_grp_802_3_get_num_stats(struct mlx5e_priv *priv)
414 return NUM_PPORT_802_3_COUNTERS;
417 static int mlx5e_grp_802_3_fill_strings(struct mlx5e_priv *priv, u8 *data,
422 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
423 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format);
427 static int mlx5e_grp_802_3_fill_stats(struct mlx5e_priv *priv, u64 *data,
432 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
433 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
434 pport_802_3_stats_desc, i);
438 static void mlx5e_grp_802_3_update_stats(struct mlx5e_priv *priv)
440 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
441 struct mlx5_core_dev *mdev = priv->mdev;
442 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
443 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
446 MLX5_SET(ppcnt_reg, in, local_port, 1);
447 out = pstats->IEEE_802_3_counters;
448 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
449 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
452 #define PPORT_2863_OFF(c) \
453 MLX5_BYTE_OFF(ppcnt_reg, \
454 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
455 static const struct counter_desc pport_2863_stats_desc[] = {
456 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
457 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
458 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
461 #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
463 static int mlx5e_grp_2863_get_num_stats(struct mlx5e_priv *priv)
465 return NUM_PPORT_2863_COUNTERS;
468 static int mlx5e_grp_2863_fill_strings(struct mlx5e_priv *priv, u8 *data,
473 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
474 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format);
478 static int mlx5e_grp_2863_fill_stats(struct mlx5e_priv *priv, u64 *data,
483 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
484 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
485 pport_2863_stats_desc, i);
489 static void mlx5e_grp_2863_update_stats(struct mlx5e_priv *priv)
491 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
492 struct mlx5_core_dev *mdev = priv->mdev;
493 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
494 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
497 MLX5_SET(ppcnt_reg, in, local_port, 1);
498 out = pstats->RFC_2863_counters;
499 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
500 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
503 #define PPORT_2819_OFF(c) \
504 MLX5_BYTE_OFF(ppcnt_reg, \
505 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
506 static const struct counter_desc pport_2819_stats_desc[] = {
507 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
508 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
509 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
510 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
511 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
512 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
513 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
514 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
515 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
516 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
517 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
518 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
519 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
522 #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
524 static int mlx5e_grp_2819_get_num_stats(struct mlx5e_priv *priv)
526 return NUM_PPORT_2819_COUNTERS;
529 static int mlx5e_grp_2819_fill_strings(struct mlx5e_priv *priv, u8 *data,
534 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
535 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format);
539 static int mlx5e_grp_2819_fill_stats(struct mlx5e_priv *priv, u64 *data,
544 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
545 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
546 pport_2819_stats_desc, i);
550 static void mlx5e_grp_2819_update_stats(struct mlx5e_priv *priv)
552 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
553 struct mlx5_core_dev *mdev = priv->mdev;
554 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
555 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
558 MLX5_SET(ppcnt_reg, in, local_port, 1);
559 out = pstats->RFC_2819_counters;
560 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
561 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
564 #define PPORT_PHY_STATISTICAL_OFF(c) \
565 MLX5_BYTE_OFF(ppcnt_reg, \
566 counter_set.phys_layer_statistical_cntrs.c##_high)
567 static const struct counter_desc pport_phy_statistical_stats_desc[] = {
568 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) },
569 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) },
572 #define NUM_PPORT_PHY_COUNTERS ARRAY_SIZE(pport_phy_statistical_stats_desc)
574 static int mlx5e_grp_phy_get_num_stats(struct mlx5e_priv *priv)
576 return MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group) ?
577 NUM_PPORT_PHY_COUNTERS : 0;
580 static int mlx5e_grp_phy_fill_strings(struct mlx5e_priv *priv, u8 *data,
585 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
586 for (i = 0; i < NUM_PPORT_PHY_COUNTERS; i++)
587 strcpy(data + (idx++) * ETH_GSTRING_LEN,
588 pport_phy_statistical_stats_desc[i].format);
592 static int mlx5e_grp_phy_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
596 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
597 for (i = 0; i < NUM_PPORT_PHY_COUNTERS; i++)
599 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
600 pport_phy_statistical_stats_desc, i);
604 static void mlx5e_grp_phy_update_stats(struct mlx5e_priv *priv)
606 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
607 struct mlx5_core_dev *mdev = priv->mdev;
608 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
609 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
612 MLX5_SET(ppcnt_reg, in, local_port, 1);
613 out = pstats->phy_counters;
614 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
615 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
617 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
620 out = pstats->phy_statistical_counters;
621 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
622 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
625 #define PPORT_ETH_EXT_OFF(c) \
626 MLX5_BYTE_OFF(ppcnt_reg, \
627 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
628 static const struct counter_desc pport_eth_ext_stats_desc[] = {
629 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) },
632 #define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc)
634 static int mlx5e_grp_eth_ext_get_num_stats(struct mlx5e_priv *priv)
636 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
637 return NUM_PPORT_ETH_EXT_COUNTERS;
642 static int mlx5e_grp_eth_ext_fill_strings(struct mlx5e_priv *priv, u8 *data,
647 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
648 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
649 strcpy(data + (idx++) * ETH_GSTRING_LEN,
650 pport_eth_ext_stats_desc[i].format);
654 static int mlx5e_grp_eth_ext_fill_stats(struct mlx5e_priv *priv, u64 *data,
659 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
660 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
662 MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
663 pport_eth_ext_stats_desc, i);
667 static void mlx5e_grp_eth_ext_update_stats(struct mlx5e_priv *priv)
669 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
670 struct mlx5_core_dev *mdev = priv->mdev;
671 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
672 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
675 if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters))
678 MLX5_SET(ppcnt_reg, in, local_port, 1);
679 out = pstats->eth_ext_counters;
680 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
681 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
684 #define PCIE_PERF_OFF(c) \
685 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)
686 static const struct counter_desc pcie_perf_stats_desc[] = {
687 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },
688 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
691 #define PCIE_PERF_OFF64(c) \
692 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
693 static const struct counter_desc pcie_perf_stats_desc64[] = {
694 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
697 static const struct counter_desc pcie_perf_stall_stats_desc[] = {
698 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
699 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
700 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
701 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
704 #define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc)
705 #define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64)
706 #define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc)
708 static int mlx5e_grp_pcie_get_num_stats(struct mlx5e_priv *priv)
712 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
713 num_stats += NUM_PCIE_PERF_COUNTERS;
715 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
716 num_stats += NUM_PCIE_PERF_COUNTERS64;
718 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
719 num_stats += NUM_PCIE_PERF_STALL_COUNTERS;
724 static int mlx5e_grp_pcie_fill_strings(struct mlx5e_priv *priv, u8 *data,
729 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
730 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
731 strcpy(data + (idx++) * ETH_GSTRING_LEN,
732 pcie_perf_stats_desc[i].format);
734 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
735 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
736 strcpy(data + (idx++) * ETH_GSTRING_LEN,
737 pcie_perf_stats_desc64[i].format);
739 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
740 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
741 strcpy(data + (idx++) * ETH_GSTRING_LEN,
742 pcie_perf_stall_stats_desc[i].format);
746 static int mlx5e_grp_pcie_fill_stats(struct mlx5e_priv *priv, u64 *data,
751 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
752 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
754 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
755 pcie_perf_stats_desc, i);
757 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
758 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
760 MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
761 pcie_perf_stats_desc64, i);
763 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
764 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
766 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
767 pcie_perf_stall_stats_desc, i);
771 static void mlx5e_grp_pcie_update_stats(struct mlx5e_priv *priv)
773 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
774 struct mlx5_core_dev *mdev = priv->mdev;
775 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
776 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
779 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
782 out = pcie_stats->pcie_perf_counters;
783 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
784 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
787 #define PPORT_PER_PRIO_OFF(c) \
788 MLX5_BYTE_OFF(ppcnt_reg, \
789 counter_set.eth_per_prio_grp_data_layout.c##_high)
790 static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
791 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
792 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
793 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
794 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
797 #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
799 static int mlx5e_grp_per_prio_traffic_get_num_stats(struct mlx5e_priv *priv)
801 return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO;
804 static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv,
810 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
811 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
812 sprintf(data + (idx++) * ETH_GSTRING_LEN,
813 pport_per_prio_traffic_stats_desc[i].format, prio);
819 static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv,
825 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
826 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
828 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
829 pport_per_prio_traffic_stats_desc, i);
835 static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
836 /* %s is "global" or "prio{i}" */
837 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
838 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
839 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
840 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
841 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
844 static const struct counter_desc pport_pfc_stall_stats_desc[] = {
845 { "tx_pause_storm_warning_events ", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) },
846 { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) },
849 #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
850 #define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \
851 MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \
852 MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
854 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
856 struct mlx5_core_dev *mdev = priv->mdev;
861 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
864 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
866 return err ? 0 : pfc_en_tx | pfc_en_rx;
869 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
871 struct mlx5_core_dev *mdev = priv->mdev;
876 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
879 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
881 return err ? false : rx_pause | tx_pause;
884 static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv)
886 return (mlx5e_query_global_pause_combined(priv) +
887 hweight8(mlx5e_query_pfc_combined(priv))) *
888 NUM_PPORT_PER_PRIO_PFC_COUNTERS +
889 NUM_PPORT_PFC_STALL_COUNTERS(priv);
892 static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
896 unsigned long pfc_combined;
899 pfc_combined = mlx5e_query_pfc_combined(priv);
900 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
901 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
902 char pfc_string[ETH_GSTRING_LEN];
904 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
905 sprintf(data + (idx++) * ETH_GSTRING_LEN,
906 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
910 if (mlx5e_query_global_pause_combined(priv)) {
911 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
912 sprintf(data + (idx++) * ETH_GSTRING_LEN,
913 pport_per_prio_pfc_stats_desc[i].format, "global");
917 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
918 strcpy(data + (idx++) * ETH_GSTRING_LEN,
919 pport_pfc_stall_stats_desc[i].format);
924 static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv,
928 unsigned long pfc_combined;
931 pfc_combined = mlx5e_query_pfc_combined(priv);
932 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
933 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
935 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
936 pport_per_prio_pfc_stats_desc, i);
940 if (mlx5e_query_global_pause_combined(priv)) {
941 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
943 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
944 pport_per_prio_pfc_stats_desc, i);
948 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
949 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
950 pport_pfc_stall_stats_desc, i);
955 static int mlx5e_grp_per_prio_get_num_stats(struct mlx5e_priv *priv)
957 return mlx5e_grp_per_prio_traffic_get_num_stats(priv) +
958 mlx5e_grp_per_prio_pfc_get_num_stats(priv);
961 static int mlx5e_grp_per_prio_fill_strings(struct mlx5e_priv *priv, u8 *data,
964 idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx);
965 idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx);
969 static int mlx5e_grp_per_prio_fill_stats(struct mlx5e_priv *priv, u64 *data,
972 idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx);
973 idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx);
977 static void mlx5e_grp_per_prio_update_stats(struct mlx5e_priv *priv)
979 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
980 struct mlx5_core_dev *mdev = priv->mdev;
981 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
982 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
986 MLX5_SET(ppcnt_reg, in, local_port, 1);
987 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
988 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
989 out = pstats->per_prio_counters[prio];
990 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
991 mlx5_core_access_reg(mdev, in, sz, out, sz,
992 MLX5_REG_PPCNT, 0, 0);
996 static const struct counter_desc mlx5e_pme_status_desc[] = {
997 { "module_unplug", 8 },
1000 static const struct counter_desc mlx5e_pme_error_desc[] = {
1001 { "module_bus_stuck", 16 }, /* bus stuck (I2C or data shorted) */
1002 { "module_high_temp", 48 }, /* high temperature */
1003 { "module_bad_shorted", 56 }, /* bad or shorted cable/module */
1006 #define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc)
1007 #define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc)
1009 static int mlx5e_grp_pme_get_num_stats(struct mlx5e_priv *priv)
1011 return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS;
1014 static int mlx5e_grp_pme_fill_strings(struct mlx5e_priv *priv, u8 *data,
1019 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1020 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
1022 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1023 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
1028 static int mlx5e_grp_pme_fill_stats(struct mlx5e_priv *priv, u64 *data,
1031 struct mlx5_priv *mlx5_priv = &priv->mdev->priv;
1034 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1035 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
1036 mlx5e_pme_status_desc, i);
1038 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1039 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
1040 mlx5e_pme_error_desc, i);
1045 static int mlx5e_grp_ipsec_get_num_stats(struct mlx5e_priv *priv)
1047 return mlx5e_ipsec_get_count(priv);
1050 static int mlx5e_grp_ipsec_fill_strings(struct mlx5e_priv *priv, u8 *data,
1053 return idx + mlx5e_ipsec_get_strings(priv,
1054 data + idx * ETH_GSTRING_LEN);
1057 static int mlx5e_grp_ipsec_fill_stats(struct mlx5e_priv *priv, u64 *data,
1060 return idx + mlx5e_ipsec_get_stats(priv, data + idx);
1063 static void mlx5e_grp_ipsec_update_stats(struct mlx5e_priv *priv)
1065 mlx5e_ipsec_update_stats(priv);
1068 static const struct counter_desc rq_stats_desc[] = {
1069 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
1070 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
1071 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
1072 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
1073 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
1074 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
1075 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
1076 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx) },
1077 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx_full) },
1078 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
1079 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
1080 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
1081 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
1082 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler) },
1083 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
1084 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
1085 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
1086 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, page_reuse) },
1087 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) },
1088 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) },
1089 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) },
1090 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) },
1091 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) },
1094 static const struct counter_desc sq_stats_desc[] = {
1095 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
1096 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
1097 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
1098 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
1099 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
1100 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
1101 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
1102 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
1103 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
1104 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
1105 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
1106 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
1107 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
1108 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
1109 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
1110 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
1111 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) },
1114 static const struct counter_desc ch_stats_desc[] = {
1115 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) },
1118 #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
1119 #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
1120 #define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc)
1122 static int mlx5e_grp_channels_get_num_stats(struct mlx5e_priv *priv)
1124 return (NUM_RQ_STATS * priv->channels.num) +
1125 (NUM_CH_STATS * priv->channels.num) +
1126 (NUM_SQ_STATS * priv->channels.num * priv->channels.params.num_tc);
1129 static int mlx5e_grp_channels_fill_strings(struct mlx5e_priv *priv, u8 *data,
1134 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1137 for (i = 0; i < priv->channels.num; i++)
1138 for (j = 0; j < NUM_CH_STATS; j++)
1139 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1140 ch_stats_desc[j].format, i);
1142 for (i = 0; i < priv->channels.num; i++)
1143 for (j = 0; j < NUM_RQ_STATS; j++)
1144 sprintf(data + (idx++) * ETH_GSTRING_LEN, rq_stats_desc[j].format, i);
1146 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
1147 for (i = 0; i < priv->channels.num; i++)
1148 for (j = 0; j < NUM_SQ_STATS; j++)
1149 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1150 sq_stats_desc[j].format,
1151 priv->channel_tc2txq[i][tc]);
1156 static int mlx5e_grp_channels_fill_stats(struct mlx5e_priv *priv, u64 *data,
1159 struct mlx5e_channels *channels = &priv->channels;
1162 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1165 for (i = 0; i < channels->num; i++)
1166 for (j = 0; j < NUM_CH_STATS; j++)
1168 MLX5E_READ_CTR64_CPU(&channels->c[i]->stats,
1171 for (i = 0; i < channels->num; i++)
1172 for (j = 0; j < NUM_RQ_STATS; j++)
1174 MLX5E_READ_CTR64_CPU(&channels->c[i]->rq.stats,
1177 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
1178 for (i = 0; i < channels->num; i++)
1179 for (j = 0; j < NUM_SQ_STATS; j++)
1181 MLX5E_READ_CTR64_CPU(&channels->c[i]->sq[tc].stats,
1187 /* The stats groups order is opposite to the update_stats() order calls */
1188 const struct mlx5e_stats_grp mlx5e_stats_grps[] = {
1190 .get_num_stats = mlx5e_grp_sw_get_num_stats,
1191 .fill_strings = mlx5e_grp_sw_fill_strings,
1192 .fill_stats = mlx5e_grp_sw_fill_stats,
1193 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1194 .update_stats = mlx5e_grp_sw_update_stats,
1197 .get_num_stats = mlx5e_grp_q_get_num_stats,
1198 .fill_strings = mlx5e_grp_q_fill_strings,
1199 .fill_stats = mlx5e_grp_q_fill_stats,
1200 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1201 .update_stats = mlx5e_grp_q_update_stats,
1204 .get_num_stats = mlx5e_grp_vnic_env_get_num_stats,
1205 .fill_strings = mlx5e_grp_vnic_env_fill_strings,
1206 .fill_stats = mlx5e_grp_vnic_env_fill_stats,
1207 .update_stats = mlx5e_grp_vnic_env_update_stats,
1210 .get_num_stats = mlx5e_grp_vport_get_num_stats,
1211 .fill_strings = mlx5e_grp_vport_fill_strings,
1212 .fill_stats = mlx5e_grp_vport_fill_stats,
1213 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1214 .update_stats = mlx5e_grp_vport_update_stats,
1217 .get_num_stats = mlx5e_grp_802_3_get_num_stats,
1218 .fill_strings = mlx5e_grp_802_3_fill_strings,
1219 .fill_stats = mlx5e_grp_802_3_fill_stats,
1220 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1221 .update_stats = mlx5e_grp_802_3_update_stats,
1224 .get_num_stats = mlx5e_grp_2863_get_num_stats,
1225 .fill_strings = mlx5e_grp_2863_fill_strings,
1226 .fill_stats = mlx5e_grp_2863_fill_stats,
1227 .update_stats = mlx5e_grp_2863_update_stats,
1230 .get_num_stats = mlx5e_grp_2819_get_num_stats,
1231 .fill_strings = mlx5e_grp_2819_fill_strings,
1232 .fill_stats = mlx5e_grp_2819_fill_stats,
1233 .update_stats = mlx5e_grp_2819_update_stats,
1236 .get_num_stats = mlx5e_grp_phy_get_num_stats,
1237 .fill_strings = mlx5e_grp_phy_fill_strings,
1238 .fill_stats = mlx5e_grp_phy_fill_stats,
1239 .update_stats = mlx5e_grp_phy_update_stats,
1242 .get_num_stats = mlx5e_grp_eth_ext_get_num_stats,
1243 .fill_strings = mlx5e_grp_eth_ext_fill_strings,
1244 .fill_stats = mlx5e_grp_eth_ext_fill_stats,
1245 .update_stats = mlx5e_grp_eth_ext_update_stats,
1248 .get_num_stats = mlx5e_grp_pcie_get_num_stats,
1249 .fill_strings = mlx5e_grp_pcie_fill_strings,
1250 .fill_stats = mlx5e_grp_pcie_fill_stats,
1251 .update_stats = mlx5e_grp_pcie_update_stats,
1254 .get_num_stats = mlx5e_grp_per_prio_get_num_stats,
1255 .fill_strings = mlx5e_grp_per_prio_fill_strings,
1256 .fill_stats = mlx5e_grp_per_prio_fill_stats,
1257 .update_stats = mlx5e_grp_per_prio_update_stats,
1260 .get_num_stats = mlx5e_grp_pme_get_num_stats,
1261 .fill_strings = mlx5e_grp_pme_fill_strings,
1262 .fill_stats = mlx5e_grp_pme_fill_stats,
1265 .get_num_stats = mlx5e_grp_ipsec_get_num_stats,
1266 .fill_strings = mlx5e_grp_ipsec_fill_strings,
1267 .fill_stats = mlx5e_grp_ipsec_fill_stats,
1268 .update_stats = mlx5e_grp_ipsec_update_stats,
1271 .get_num_stats = mlx5e_grp_channels_get_num_stats,
1272 .fill_strings = mlx5e_grp_channels_fill_strings,
1273 .fill_stats = mlx5e_grp_channels_fill_stats,
1277 const int mlx5e_num_stats_grps = ARRAY_SIZE(mlx5e_stats_grps);