2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include "en_accel/ipsec.h"
35 #include "en_accel/tls.h"
37 static const struct counter_desc sw_stats_desc[] = {
38 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
39 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
40 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
41 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
42 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
43 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
44 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
45 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
46 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) },
48 #ifdef CONFIG_MLX5_EN_TLS
49 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) },
50 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) },
53 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
54 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
55 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) },
56 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
57 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
58 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
59 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
60 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
61 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx) },
62 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
63 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) },
64 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
65 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
66 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
67 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
68 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
69 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
70 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) },
71 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) },
72 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
73 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler) },
74 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
75 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
76 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
77 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_page_reuse) },
78 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) },
79 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) },
80 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) },
81 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) },
82 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) },
83 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) },
84 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, link_down_events_phy) },
87 #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
89 static int mlx5e_grp_sw_get_num_stats(struct mlx5e_priv *priv)
91 return NUM_SW_COUNTERS;
94 static int mlx5e_grp_sw_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
98 for (i = 0; i < NUM_SW_COUNTERS; i++)
99 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
103 static int mlx5e_grp_sw_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
107 for (i = 0; i < NUM_SW_COUNTERS; i++)
108 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i);
112 static void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv)
114 struct mlx5e_sw_stats temp, *s = &temp;
115 struct mlx5e_rq_stats *rq_stats;
116 struct mlx5e_sq_stats *sq_stats;
117 struct mlx5e_ch_stats *ch_stats;
120 memset(s, 0, sizeof(*s));
121 for (i = 0; i < priv->channels.num; i++) {
122 struct mlx5e_channel *c = priv->channels.c[i];
124 rq_stats = &c->rq.stats;
125 ch_stats = &c->stats;
127 s->rx_packets += rq_stats->packets;
128 s->rx_bytes += rq_stats->bytes;
129 s->rx_lro_packets += rq_stats->lro_packets;
130 s->rx_lro_bytes += rq_stats->lro_bytes;
131 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
132 s->rx_csum_none += rq_stats->csum_none;
133 s->rx_csum_complete += rq_stats->csum_complete;
134 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
135 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
136 s->rx_xdp_drop += rq_stats->xdp_drop;
137 s->rx_xdp_tx += rq_stats->xdp_tx;
138 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
139 s->rx_wqe_err += rq_stats->wqe_err;
140 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
141 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
142 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
143 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
144 s->rx_page_reuse += rq_stats->page_reuse;
145 s->rx_cache_reuse += rq_stats->cache_reuse;
146 s->rx_cache_full += rq_stats->cache_full;
147 s->rx_cache_empty += rq_stats->cache_empty;
148 s->rx_cache_busy += rq_stats->cache_busy;
149 s->rx_cache_waive += rq_stats->cache_waive;
150 s->ch_eq_rearm += ch_stats->eq_rearm;
152 for (j = 0; j < priv->channels.params.num_tc; j++) {
153 sq_stats = &c->sq[j].stats;
155 s->tx_packets += sq_stats->packets;
156 s->tx_bytes += sq_stats->bytes;
157 s->tx_tso_packets += sq_stats->tso_packets;
158 s->tx_tso_bytes += sq_stats->tso_bytes;
159 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
160 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
161 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
162 s->tx_queue_stopped += sq_stats->stopped;
163 s->tx_queue_wake += sq_stats->wake;
164 s->tx_queue_dropped += sq_stats->dropped;
165 s->tx_cqe_err += sq_stats->cqe_err;
166 s->tx_recover += sq_stats->recover;
167 s->tx_xmit_more += sq_stats->xmit_more;
168 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
169 s->tx_csum_none += sq_stats->csum_none;
170 s->tx_csum_partial += sq_stats->csum_partial;
171 #ifdef CONFIG_MLX5_EN_TLS
172 s->tx_tls_ooo += sq_stats->tls_ooo;
173 s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes;
178 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
179 priv->stats.pport.phy_counters,
180 counter_set.phys_layer_cntrs.link_down_events);
181 memcpy(&priv->stats.sw, s, sizeof(*s));
184 static const struct counter_desc q_stats_desc[] = {
185 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
188 static const struct counter_desc drop_rq_stats_desc[] = {
189 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) },
192 #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
193 #define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc)
195 static int mlx5e_grp_q_get_num_stats(struct mlx5e_priv *priv)
200 num_stats += NUM_Q_COUNTERS;
202 if (priv->drop_rq_q_counter)
203 num_stats += NUM_DROP_RQ_COUNTERS;
208 static int mlx5e_grp_q_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
212 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
213 strcpy(data + (idx++) * ETH_GSTRING_LEN,
214 q_stats_desc[i].format);
216 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
217 strcpy(data + (idx++) * ETH_GSTRING_LEN,
218 drop_rq_stats_desc[i].format);
223 static int mlx5e_grp_q_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
227 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
228 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
230 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
231 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
232 drop_rq_stats_desc, i);
236 static void mlx5e_grp_q_update_stats(struct mlx5e_priv *priv)
238 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
239 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
241 if (priv->q_counter &&
242 !mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out,
244 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out,
246 if (priv->drop_rq_q_counter &&
247 !mlx5_core_query_q_counter(priv->mdev, priv->drop_rq_q_counter, 0,
249 qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out, out,
253 #define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c)
254 static const struct counter_desc vnic_env_stats_desc[] = {
255 { "rx_steer_missed_packets",
256 VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) },
259 #define NUM_VNIC_ENV_COUNTERS ARRAY_SIZE(vnic_env_stats_desc)
261 static int mlx5e_grp_vnic_env_get_num_stats(struct mlx5e_priv *priv)
263 return MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard) ?
264 NUM_VNIC_ENV_COUNTERS : 0;
267 static int mlx5e_grp_vnic_env_fill_strings(struct mlx5e_priv *priv, u8 *data,
272 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
275 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
276 strcpy(data + (idx++) * ETH_GSTRING_LEN,
277 vnic_env_stats_desc[i].format);
281 static int mlx5e_grp_vnic_env_fill_stats(struct mlx5e_priv *priv, u64 *data,
286 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
289 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
290 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out,
291 vnic_env_stats_desc, i);
295 static void mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
297 u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out;
298 int outlen = MLX5_ST_SZ_BYTES(query_vnic_env_out);
299 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0};
300 struct mlx5_core_dev *mdev = priv->mdev;
302 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
305 MLX5_SET(query_vnic_env_in, in, opcode,
306 MLX5_CMD_OP_QUERY_VNIC_ENV);
307 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
308 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
309 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
312 #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
313 static const struct counter_desc vport_stats_desc[] = {
314 { "rx_vport_unicast_packets",
315 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
316 { "rx_vport_unicast_bytes",
317 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
318 { "tx_vport_unicast_packets",
319 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
320 { "tx_vport_unicast_bytes",
321 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
322 { "rx_vport_multicast_packets",
323 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
324 { "rx_vport_multicast_bytes",
325 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
326 { "tx_vport_multicast_packets",
327 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
328 { "tx_vport_multicast_bytes",
329 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
330 { "rx_vport_broadcast_packets",
331 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
332 { "rx_vport_broadcast_bytes",
333 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
334 { "tx_vport_broadcast_packets",
335 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
336 { "tx_vport_broadcast_bytes",
337 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
338 { "rx_vport_rdma_unicast_packets",
339 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
340 { "rx_vport_rdma_unicast_bytes",
341 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
342 { "tx_vport_rdma_unicast_packets",
343 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
344 { "tx_vport_rdma_unicast_bytes",
345 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
346 { "rx_vport_rdma_multicast_packets",
347 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
348 { "rx_vport_rdma_multicast_bytes",
349 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
350 { "tx_vport_rdma_multicast_packets",
351 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
352 { "tx_vport_rdma_multicast_bytes",
353 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
356 #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
358 static int mlx5e_grp_vport_get_num_stats(struct mlx5e_priv *priv)
360 return NUM_VPORT_COUNTERS;
363 static int mlx5e_grp_vport_fill_strings(struct mlx5e_priv *priv, u8 *data,
368 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
369 strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format);
373 static int mlx5e_grp_vport_fill_stats(struct mlx5e_priv *priv, u64 *data,
378 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
379 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
380 vport_stats_desc, i);
384 static void mlx5e_grp_vport_update_stats(struct mlx5e_priv *priv)
386 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
387 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
388 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
389 struct mlx5_core_dev *mdev = priv->mdev;
391 MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER);
392 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
393 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
394 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
397 #define PPORT_802_3_OFF(c) \
398 MLX5_BYTE_OFF(ppcnt_reg, \
399 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
400 static const struct counter_desc pport_802_3_stats_desc[] = {
401 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
402 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
403 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
404 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
405 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
406 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
407 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
408 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
409 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
410 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
411 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
412 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
413 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
414 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
415 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
416 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
417 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
418 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
421 #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
423 static int mlx5e_grp_802_3_get_num_stats(struct mlx5e_priv *priv)
425 return NUM_PPORT_802_3_COUNTERS;
428 static int mlx5e_grp_802_3_fill_strings(struct mlx5e_priv *priv, u8 *data,
433 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
434 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format);
438 static int mlx5e_grp_802_3_fill_stats(struct mlx5e_priv *priv, u64 *data,
443 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
444 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
445 pport_802_3_stats_desc, i);
449 static void mlx5e_grp_802_3_update_stats(struct mlx5e_priv *priv)
451 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
452 struct mlx5_core_dev *mdev = priv->mdev;
453 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
454 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
457 MLX5_SET(ppcnt_reg, in, local_port, 1);
458 out = pstats->IEEE_802_3_counters;
459 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
460 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
463 #define PPORT_2863_OFF(c) \
464 MLX5_BYTE_OFF(ppcnt_reg, \
465 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
466 static const struct counter_desc pport_2863_stats_desc[] = {
467 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
468 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
469 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
472 #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
474 static int mlx5e_grp_2863_get_num_stats(struct mlx5e_priv *priv)
476 return NUM_PPORT_2863_COUNTERS;
479 static int mlx5e_grp_2863_fill_strings(struct mlx5e_priv *priv, u8 *data,
484 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
485 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format);
489 static int mlx5e_grp_2863_fill_stats(struct mlx5e_priv *priv, u64 *data,
494 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
495 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
496 pport_2863_stats_desc, i);
500 static void mlx5e_grp_2863_update_stats(struct mlx5e_priv *priv)
502 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
503 struct mlx5_core_dev *mdev = priv->mdev;
504 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
505 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
508 MLX5_SET(ppcnt_reg, in, local_port, 1);
509 out = pstats->RFC_2863_counters;
510 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
511 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
514 #define PPORT_2819_OFF(c) \
515 MLX5_BYTE_OFF(ppcnt_reg, \
516 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
517 static const struct counter_desc pport_2819_stats_desc[] = {
518 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
519 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
520 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
521 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
522 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
523 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
524 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
525 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
526 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
527 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
528 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
529 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
530 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
533 #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
535 static int mlx5e_grp_2819_get_num_stats(struct mlx5e_priv *priv)
537 return NUM_PPORT_2819_COUNTERS;
540 static int mlx5e_grp_2819_fill_strings(struct mlx5e_priv *priv, u8 *data,
545 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
546 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format);
550 static int mlx5e_grp_2819_fill_stats(struct mlx5e_priv *priv, u64 *data,
555 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
556 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
557 pport_2819_stats_desc, i);
561 static void mlx5e_grp_2819_update_stats(struct mlx5e_priv *priv)
563 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
564 struct mlx5_core_dev *mdev = priv->mdev;
565 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
566 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
569 MLX5_SET(ppcnt_reg, in, local_port, 1);
570 out = pstats->RFC_2819_counters;
571 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
572 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
575 #define PPORT_PHY_STATISTICAL_OFF(c) \
576 MLX5_BYTE_OFF(ppcnt_reg, \
577 counter_set.phys_layer_statistical_cntrs.c##_high)
578 static const struct counter_desc pport_phy_statistical_stats_desc[] = {
579 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) },
580 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) },
583 #define NUM_PPORT_PHY_COUNTERS ARRAY_SIZE(pport_phy_statistical_stats_desc)
585 static int mlx5e_grp_phy_get_num_stats(struct mlx5e_priv *priv)
587 return MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group) ?
588 NUM_PPORT_PHY_COUNTERS : 0;
591 static int mlx5e_grp_phy_fill_strings(struct mlx5e_priv *priv, u8 *data,
596 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
597 for (i = 0; i < NUM_PPORT_PHY_COUNTERS; i++)
598 strcpy(data + (idx++) * ETH_GSTRING_LEN,
599 pport_phy_statistical_stats_desc[i].format);
603 static int mlx5e_grp_phy_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
607 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
608 for (i = 0; i < NUM_PPORT_PHY_COUNTERS; i++)
610 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
611 pport_phy_statistical_stats_desc, i);
615 static void mlx5e_grp_phy_update_stats(struct mlx5e_priv *priv)
617 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
618 struct mlx5_core_dev *mdev = priv->mdev;
619 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
620 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
623 MLX5_SET(ppcnt_reg, in, local_port, 1);
624 out = pstats->phy_counters;
625 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
626 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
628 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
631 out = pstats->phy_statistical_counters;
632 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
633 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
636 #define PPORT_ETH_EXT_OFF(c) \
637 MLX5_BYTE_OFF(ppcnt_reg, \
638 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
639 static const struct counter_desc pport_eth_ext_stats_desc[] = {
640 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) },
643 #define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc)
645 static int mlx5e_grp_eth_ext_get_num_stats(struct mlx5e_priv *priv)
647 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
648 return NUM_PPORT_ETH_EXT_COUNTERS;
653 static int mlx5e_grp_eth_ext_fill_strings(struct mlx5e_priv *priv, u8 *data,
658 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
659 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
660 strcpy(data + (idx++) * ETH_GSTRING_LEN,
661 pport_eth_ext_stats_desc[i].format);
665 static int mlx5e_grp_eth_ext_fill_stats(struct mlx5e_priv *priv, u64 *data,
670 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
671 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
673 MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
674 pport_eth_ext_stats_desc, i);
678 static void mlx5e_grp_eth_ext_update_stats(struct mlx5e_priv *priv)
680 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
681 struct mlx5_core_dev *mdev = priv->mdev;
682 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
683 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
686 if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters))
689 MLX5_SET(ppcnt_reg, in, local_port, 1);
690 out = pstats->eth_ext_counters;
691 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
692 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
695 #define PCIE_PERF_OFF(c) \
696 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)
697 static const struct counter_desc pcie_perf_stats_desc[] = {
698 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },
699 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
702 #define PCIE_PERF_OFF64(c) \
703 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
704 static const struct counter_desc pcie_perf_stats_desc64[] = {
705 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
708 static const struct counter_desc pcie_perf_stall_stats_desc[] = {
709 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
710 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
711 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
712 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
715 #define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc)
716 #define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64)
717 #define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc)
719 static int mlx5e_grp_pcie_get_num_stats(struct mlx5e_priv *priv)
723 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
724 num_stats += NUM_PCIE_PERF_COUNTERS;
726 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
727 num_stats += NUM_PCIE_PERF_COUNTERS64;
729 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
730 num_stats += NUM_PCIE_PERF_STALL_COUNTERS;
735 static int mlx5e_grp_pcie_fill_strings(struct mlx5e_priv *priv, u8 *data,
740 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
741 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
742 strcpy(data + (idx++) * ETH_GSTRING_LEN,
743 pcie_perf_stats_desc[i].format);
745 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
746 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
747 strcpy(data + (idx++) * ETH_GSTRING_LEN,
748 pcie_perf_stats_desc64[i].format);
750 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
751 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
752 strcpy(data + (idx++) * ETH_GSTRING_LEN,
753 pcie_perf_stall_stats_desc[i].format);
757 static int mlx5e_grp_pcie_fill_stats(struct mlx5e_priv *priv, u64 *data,
762 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
763 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
765 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
766 pcie_perf_stats_desc, i);
768 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
769 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
771 MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
772 pcie_perf_stats_desc64, i);
774 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
775 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
777 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
778 pcie_perf_stall_stats_desc, i);
782 static void mlx5e_grp_pcie_update_stats(struct mlx5e_priv *priv)
784 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
785 struct mlx5_core_dev *mdev = priv->mdev;
786 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
787 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
790 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
793 out = pcie_stats->pcie_perf_counters;
794 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
795 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
798 #define PPORT_PER_PRIO_OFF(c) \
799 MLX5_BYTE_OFF(ppcnt_reg, \
800 counter_set.eth_per_prio_grp_data_layout.c##_high)
801 static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
802 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
803 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
804 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
805 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
808 #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
810 static int mlx5e_grp_per_prio_traffic_get_num_stats(struct mlx5e_priv *priv)
812 return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO;
815 static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv,
821 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
822 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
823 sprintf(data + (idx++) * ETH_GSTRING_LEN,
824 pport_per_prio_traffic_stats_desc[i].format, prio);
830 static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv,
836 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
837 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
839 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
840 pport_per_prio_traffic_stats_desc, i);
846 static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
847 /* %s is "global" or "prio{i}" */
848 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
849 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
850 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
851 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
852 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
855 static const struct counter_desc pport_pfc_stall_stats_desc[] = {
856 { "tx_pause_storm_warning_events ", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) },
857 { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) },
860 #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
861 #define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \
862 MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \
863 MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
865 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
867 struct mlx5_core_dev *mdev = priv->mdev;
872 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
875 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
877 return err ? 0 : pfc_en_tx | pfc_en_rx;
880 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
882 struct mlx5_core_dev *mdev = priv->mdev;
887 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
890 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
892 return err ? false : rx_pause | tx_pause;
895 static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv)
897 return (mlx5e_query_global_pause_combined(priv) +
898 hweight8(mlx5e_query_pfc_combined(priv))) *
899 NUM_PPORT_PER_PRIO_PFC_COUNTERS +
900 NUM_PPORT_PFC_STALL_COUNTERS(priv);
903 static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
907 unsigned long pfc_combined;
910 pfc_combined = mlx5e_query_pfc_combined(priv);
911 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
912 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
913 char pfc_string[ETH_GSTRING_LEN];
915 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
916 sprintf(data + (idx++) * ETH_GSTRING_LEN,
917 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
921 if (mlx5e_query_global_pause_combined(priv)) {
922 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
923 sprintf(data + (idx++) * ETH_GSTRING_LEN,
924 pport_per_prio_pfc_stats_desc[i].format, "global");
928 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
929 strcpy(data + (idx++) * ETH_GSTRING_LEN,
930 pport_pfc_stall_stats_desc[i].format);
935 static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv,
939 unsigned long pfc_combined;
942 pfc_combined = mlx5e_query_pfc_combined(priv);
943 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
944 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
946 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
947 pport_per_prio_pfc_stats_desc, i);
951 if (mlx5e_query_global_pause_combined(priv)) {
952 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
954 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
955 pport_per_prio_pfc_stats_desc, i);
959 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
960 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
961 pport_pfc_stall_stats_desc, i);
966 static int mlx5e_grp_per_prio_get_num_stats(struct mlx5e_priv *priv)
968 return mlx5e_grp_per_prio_traffic_get_num_stats(priv) +
969 mlx5e_grp_per_prio_pfc_get_num_stats(priv);
972 static int mlx5e_grp_per_prio_fill_strings(struct mlx5e_priv *priv, u8 *data,
975 idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx);
976 idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx);
980 static int mlx5e_grp_per_prio_fill_stats(struct mlx5e_priv *priv, u64 *data,
983 idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx);
984 idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx);
988 static void mlx5e_grp_per_prio_update_stats(struct mlx5e_priv *priv)
990 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
991 struct mlx5_core_dev *mdev = priv->mdev;
992 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
993 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
997 MLX5_SET(ppcnt_reg, in, local_port, 1);
998 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
999 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1000 out = pstats->per_prio_counters[prio];
1001 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1002 mlx5_core_access_reg(mdev, in, sz, out, sz,
1003 MLX5_REG_PPCNT, 0, 0);
1007 static const struct counter_desc mlx5e_pme_status_desc[] = {
1008 { "module_unplug", 8 },
1011 static const struct counter_desc mlx5e_pme_error_desc[] = {
1012 { "module_bus_stuck", 16 }, /* bus stuck (I2C or data shorted) */
1013 { "module_high_temp", 48 }, /* high temperature */
1014 { "module_bad_shorted", 56 }, /* bad or shorted cable/module */
1017 #define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc)
1018 #define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc)
1020 static int mlx5e_grp_pme_get_num_stats(struct mlx5e_priv *priv)
1022 return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS;
1025 static int mlx5e_grp_pme_fill_strings(struct mlx5e_priv *priv, u8 *data,
1030 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1031 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
1033 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1034 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
1039 static int mlx5e_grp_pme_fill_stats(struct mlx5e_priv *priv, u64 *data,
1042 struct mlx5_priv *mlx5_priv = &priv->mdev->priv;
1045 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1046 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
1047 mlx5e_pme_status_desc, i);
1049 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1050 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
1051 mlx5e_pme_error_desc, i);
1056 static int mlx5e_grp_ipsec_get_num_stats(struct mlx5e_priv *priv)
1058 return mlx5e_ipsec_get_count(priv);
1061 static int mlx5e_grp_ipsec_fill_strings(struct mlx5e_priv *priv, u8 *data,
1064 return idx + mlx5e_ipsec_get_strings(priv,
1065 data + idx * ETH_GSTRING_LEN);
1068 static int mlx5e_grp_ipsec_fill_stats(struct mlx5e_priv *priv, u64 *data,
1071 return idx + mlx5e_ipsec_get_stats(priv, data + idx);
1074 static void mlx5e_grp_ipsec_update_stats(struct mlx5e_priv *priv)
1076 mlx5e_ipsec_update_stats(priv);
1079 static int mlx5e_grp_tls_get_num_stats(struct mlx5e_priv *priv)
1081 return mlx5e_tls_get_count(priv);
1084 static int mlx5e_grp_tls_fill_strings(struct mlx5e_priv *priv, u8 *data,
1087 return idx + mlx5e_tls_get_strings(priv, data + idx * ETH_GSTRING_LEN);
1090 static int mlx5e_grp_tls_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
1092 return idx + mlx5e_tls_get_stats(priv, data + idx);
1095 static const struct counter_desc rq_stats_desc[] = {
1096 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
1097 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
1098 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
1099 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
1100 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
1101 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
1102 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
1103 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx) },
1104 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx_full) },
1105 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
1106 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
1107 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
1108 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
1109 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler) },
1110 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
1111 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
1112 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
1113 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, page_reuse) },
1114 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) },
1115 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) },
1116 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) },
1117 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) },
1118 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) },
1121 static const struct counter_desc sq_stats_desc[] = {
1122 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
1123 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
1124 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
1125 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
1126 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
1127 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
1128 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
1129 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
1130 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
1131 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
1132 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
1133 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
1134 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
1135 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
1136 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
1137 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
1138 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) },
1141 static const struct counter_desc ch_stats_desc[] = {
1142 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) },
1145 #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
1146 #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
1147 #define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc)
1149 static int mlx5e_grp_channels_get_num_stats(struct mlx5e_priv *priv)
1151 return (NUM_RQ_STATS * priv->channels.num) +
1152 (NUM_CH_STATS * priv->channels.num) +
1153 (NUM_SQ_STATS * priv->channels.num * priv->channels.params.num_tc);
1156 static int mlx5e_grp_channels_fill_strings(struct mlx5e_priv *priv, u8 *data,
1161 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1164 for (i = 0; i < priv->channels.num; i++)
1165 for (j = 0; j < NUM_CH_STATS; j++)
1166 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1167 ch_stats_desc[j].format, i);
1169 for (i = 0; i < priv->channels.num; i++)
1170 for (j = 0; j < NUM_RQ_STATS; j++)
1171 sprintf(data + (idx++) * ETH_GSTRING_LEN, rq_stats_desc[j].format, i);
1173 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
1174 for (i = 0; i < priv->channels.num; i++)
1175 for (j = 0; j < NUM_SQ_STATS; j++)
1176 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1177 sq_stats_desc[j].format,
1178 priv->channel_tc2txq[i][tc]);
1183 static int mlx5e_grp_channels_fill_stats(struct mlx5e_priv *priv, u64 *data,
1186 struct mlx5e_channels *channels = &priv->channels;
1189 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1192 for (i = 0; i < channels->num; i++)
1193 for (j = 0; j < NUM_CH_STATS; j++)
1195 MLX5E_READ_CTR64_CPU(&channels->c[i]->stats,
1198 for (i = 0; i < channels->num; i++)
1199 for (j = 0; j < NUM_RQ_STATS; j++)
1201 MLX5E_READ_CTR64_CPU(&channels->c[i]->rq.stats,
1204 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
1205 for (i = 0; i < channels->num; i++)
1206 for (j = 0; j < NUM_SQ_STATS; j++)
1208 MLX5E_READ_CTR64_CPU(&channels->c[i]->sq[tc].stats,
1214 /* The stats groups order is opposite to the update_stats() order calls */
1215 const struct mlx5e_stats_grp mlx5e_stats_grps[] = {
1217 .get_num_stats = mlx5e_grp_sw_get_num_stats,
1218 .fill_strings = mlx5e_grp_sw_fill_strings,
1219 .fill_stats = mlx5e_grp_sw_fill_stats,
1220 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1221 .update_stats = mlx5e_grp_sw_update_stats,
1224 .get_num_stats = mlx5e_grp_q_get_num_stats,
1225 .fill_strings = mlx5e_grp_q_fill_strings,
1226 .fill_stats = mlx5e_grp_q_fill_stats,
1227 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1228 .update_stats = mlx5e_grp_q_update_stats,
1231 .get_num_stats = mlx5e_grp_vnic_env_get_num_stats,
1232 .fill_strings = mlx5e_grp_vnic_env_fill_strings,
1233 .fill_stats = mlx5e_grp_vnic_env_fill_stats,
1234 .update_stats = mlx5e_grp_vnic_env_update_stats,
1237 .get_num_stats = mlx5e_grp_vport_get_num_stats,
1238 .fill_strings = mlx5e_grp_vport_fill_strings,
1239 .fill_stats = mlx5e_grp_vport_fill_stats,
1240 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1241 .update_stats = mlx5e_grp_vport_update_stats,
1244 .get_num_stats = mlx5e_grp_802_3_get_num_stats,
1245 .fill_strings = mlx5e_grp_802_3_fill_strings,
1246 .fill_stats = mlx5e_grp_802_3_fill_stats,
1247 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1248 .update_stats = mlx5e_grp_802_3_update_stats,
1251 .get_num_stats = mlx5e_grp_2863_get_num_stats,
1252 .fill_strings = mlx5e_grp_2863_fill_strings,
1253 .fill_stats = mlx5e_grp_2863_fill_stats,
1254 .update_stats = mlx5e_grp_2863_update_stats,
1257 .get_num_stats = mlx5e_grp_2819_get_num_stats,
1258 .fill_strings = mlx5e_grp_2819_fill_strings,
1259 .fill_stats = mlx5e_grp_2819_fill_stats,
1260 .update_stats = mlx5e_grp_2819_update_stats,
1263 .get_num_stats = mlx5e_grp_phy_get_num_stats,
1264 .fill_strings = mlx5e_grp_phy_fill_strings,
1265 .fill_stats = mlx5e_grp_phy_fill_stats,
1266 .update_stats = mlx5e_grp_phy_update_stats,
1269 .get_num_stats = mlx5e_grp_eth_ext_get_num_stats,
1270 .fill_strings = mlx5e_grp_eth_ext_fill_strings,
1271 .fill_stats = mlx5e_grp_eth_ext_fill_stats,
1272 .update_stats = mlx5e_grp_eth_ext_update_stats,
1275 .get_num_stats = mlx5e_grp_pcie_get_num_stats,
1276 .fill_strings = mlx5e_grp_pcie_fill_strings,
1277 .fill_stats = mlx5e_grp_pcie_fill_stats,
1278 .update_stats = mlx5e_grp_pcie_update_stats,
1281 .get_num_stats = mlx5e_grp_per_prio_get_num_stats,
1282 .fill_strings = mlx5e_grp_per_prio_fill_strings,
1283 .fill_stats = mlx5e_grp_per_prio_fill_stats,
1284 .update_stats = mlx5e_grp_per_prio_update_stats,
1287 .get_num_stats = mlx5e_grp_pme_get_num_stats,
1288 .fill_strings = mlx5e_grp_pme_fill_strings,
1289 .fill_stats = mlx5e_grp_pme_fill_stats,
1292 .get_num_stats = mlx5e_grp_ipsec_get_num_stats,
1293 .fill_strings = mlx5e_grp_ipsec_fill_strings,
1294 .fill_stats = mlx5e_grp_ipsec_fill_stats,
1295 .update_stats = mlx5e_grp_ipsec_update_stats,
1298 .get_num_stats = mlx5e_grp_tls_get_num_stats,
1299 .fill_strings = mlx5e_grp_tls_fill_strings,
1300 .fill_stats = mlx5e_grp_tls_fill_stats,
1303 .get_num_stats = mlx5e_grp_channels_get_num_stats,
1304 .fill_strings = mlx5e_grp_channels_fill_strings,
1305 .fill_stats = mlx5e_grp_channels_fill_stats,
1309 const int mlx5e_num_stats_grps = ARRAY_SIZE(mlx5e_stats_grps);