2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include "en_accel/ipsec.h"
35 #include "en_accel/tls.h"
37 static const struct counter_desc sw_stats_desc[] = {
38 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
39 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
40 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
41 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
42 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
43 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
44 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
45 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
46 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) },
48 #ifdef CONFIG_MLX5_EN_TLS
49 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) },
50 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) },
53 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
54 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
55 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) },
56 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
57 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
58 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
59 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
60 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
61 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx) },
62 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
63 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) },
64 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
65 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
66 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
67 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
68 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
69 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) },
70 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
71 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) },
72 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
73 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler) },
74 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
75 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
76 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
77 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_page_reuse) },
78 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) },
79 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) },
80 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) },
81 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) },
82 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) },
83 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) },
86 #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
88 static int mlx5e_grp_sw_get_num_stats(struct mlx5e_priv *priv)
90 return NUM_SW_COUNTERS;
93 static int mlx5e_grp_sw_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
97 for (i = 0; i < NUM_SW_COUNTERS; i++)
98 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
102 static int mlx5e_grp_sw_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
106 for (i = 0; i < NUM_SW_COUNTERS; i++)
107 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i);
111 void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv)
113 struct mlx5e_sw_stats temp, *s = &temp;
116 memset(s, 0, sizeof(*s));
118 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++) {
119 struct mlx5e_channel_stats *channel_stats =
120 &priv->channel_stats[i];
121 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
122 struct mlx5e_ch_stats *ch_stats = &channel_stats->ch;
125 s->rx_packets += rq_stats->packets;
126 s->rx_bytes += rq_stats->bytes;
127 s->rx_lro_packets += rq_stats->lro_packets;
128 s->rx_lro_bytes += rq_stats->lro_bytes;
129 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
130 s->rx_csum_none += rq_stats->csum_none;
131 s->rx_csum_complete += rq_stats->csum_complete;
132 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
133 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
134 s->rx_xdp_drop += rq_stats->xdp_drop;
135 s->rx_xdp_tx += rq_stats->xdp_tx;
136 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
137 s->rx_wqe_err += rq_stats->wqe_err;
138 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
139 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
140 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
141 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
142 s->rx_page_reuse += rq_stats->page_reuse;
143 s->rx_cache_reuse += rq_stats->cache_reuse;
144 s->rx_cache_full += rq_stats->cache_full;
145 s->rx_cache_empty += rq_stats->cache_empty;
146 s->rx_cache_busy += rq_stats->cache_busy;
147 s->rx_cache_waive += rq_stats->cache_waive;
148 s->ch_eq_rearm += ch_stats->eq_rearm;
150 for (j = 0; j < priv->max_opened_tc; j++) {
151 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
153 s->tx_packets += sq_stats->packets;
154 s->tx_bytes += sq_stats->bytes;
155 s->tx_tso_packets += sq_stats->tso_packets;
156 s->tx_tso_bytes += sq_stats->tso_bytes;
157 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
158 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
159 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
160 s->tx_queue_stopped += sq_stats->stopped;
161 s->tx_queue_wake += sq_stats->wake;
162 s->tx_queue_dropped += sq_stats->dropped;
163 s->tx_cqe_err += sq_stats->cqe_err;
164 s->tx_recover += sq_stats->recover;
165 s->tx_xmit_more += sq_stats->xmit_more;
166 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
167 s->tx_csum_none += sq_stats->csum_none;
168 s->tx_csum_partial += sq_stats->csum_partial;
169 #ifdef CONFIG_MLX5_EN_TLS
170 s->tx_tls_ooo += sq_stats->tls_ooo;
171 s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes;
176 memcpy(&priv->stats.sw, s, sizeof(*s));
179 static const struct counter_desc q_stats_desc[] = {
180 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
183 static const struct counter_desc drop_rq_stats_desc[] = {
184 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) },
187 #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
188 #define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc)
190 static int mlx5e_grp_q_get_num_stats(struct mlx5e_priv *priv)
195 num_stats += NUM_Q_COUNTERS;
197 if (priv->drop_rq_q_counter)
198 num_stats += NUM_DROP_RQ_COUNTERS;
203 static int mlx5e_grp_q_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
207 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
208 strcpy(data + (idx++) * ETH_GSTRING_LEN,
209 q_stats_desc[i].format);
211 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
212 strcpy(data + (idx++) * ETH_GSTRING_LEN,
213 drop_rq_stats_desc[i].format);
218 static int mlx5e_grp_q_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
222 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
223 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
225 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
226 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
227 drop_rq_stats_desc, i);
231 static void mlx5e_grp_q_update_stats(struct mlx5e_priv *priv)
233 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
234 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
236 if (priv->q_counter &&
237 !mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out,
239 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out,
241 if (priv->drop_rq_q_counter &&
242 !mlx5_core_query_q_counter(priv->mdev, priv->drop_rq_q_counter, 0,
244 qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out, out,
248 #define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c)
249 static const struct counter_desc vnic_env_stats_desc[] = {
250 { "rx_steer_missed_packets",
251 VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) },
254 #define NUM_VNIC_ENV_COUNTERS ARRAY_SIZE(vnic_env_stats_desc)
256 static int mlx5e_grp_vnic_env_get_num_stats(struct mlx5e_priv *priv)
258 return MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard) ?
259 NUM_VNIC_ENV_COUNTERS : 0;
262 static int mlx5e_grp_vnic_env_fill_strings(struct mlx5e_priv *priv, u8 *data,
267 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
270 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
271 strcpy(data + (idx++) * ETH_GSTRING_LEN,
272 vnic_env_stats_desc[i].format);
276 static int mlx5e_grp_vnic_env_fill_stats(struct mlx5e_priv *priv, u64 *data,
281 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
284 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
285 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out,
286 vnic_env_stats_desc, i);
290 static void mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
292 u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out;
293 int outlen = MLX5_ST_SZ_BYTES(query_vnic_env_out);
294 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0};
295 struct mlx5_core_dev *mdev = priv->mdev;
297 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
300 MLX5_SET(query_vnic_env_in, in, opcode,
301 MLX5_CMD_OP_QUERY_VNIC_ENV);
302 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
303 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
304 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
307 #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
308 static const struct counter_desc vport_stats_desc[] = {
309 { "rx_vport_unicast_packets",
310 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
311 { "rx_vport_unicast_bytes",
312 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
313 { "tx_vport_unicast_packets",
314 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
315 { "tx_vport_unicast_bytes",
316 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
317 { "rx_vport_multicast_packets",
318 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
319 { "rx_vport_multicast_bytes",
320 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
321 { "tx_vport_multicast_packets",
322 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
323 { "tx_vport_multicast_bytes",
324 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
325 { "rx_vport_broadcast_packets",
326 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
327 { "rx_vport_broadcast_bytes",
328 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
329 { "tx_vport_broadcast_packets",
330 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
331 { "tx_vport_broadcast_bytes",
332 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
333 { "rx_vport_rdma_unicast_packets",
334 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
335 { "rx_vport_rdma_unicast_bytes",
336 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
337 { "tx_vport_rdma_unicast_packets",
338 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
339 { "tx_vport_rdma_unicast_bytes",
340 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
341 { "rx_vport_rdma_multicast_packets",
342 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
343 { "rx_vport_rdma_multicast_bytes",
344 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
345 { "tx_vport_rdma_multicast_packets",
346 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
347 { "tx_vport_rdma_multicast_bytes",
348 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
351 #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
353 static int mlx5e_grp_vport_get_num_stats(struct mlx5e_priv *priv)
355 return NUM_VPORT_COUNTERS;
358 static int mlx5e_grp_vport_fill_strings(struct mlx5e_priv *priv, u8 *data,
363 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
364 strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format);
368 static int mlx5e_grp_vport_fill_stats(struct mlx5e_priv *priv, u64 *data,
373 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
374 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
375 vport_stats_desc, i);
379 static void mlx5e_grp_vport_update_stats(struct mlx5e_priv *priv)
381 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
382 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
383 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
384 struct mlx5_core_dev *mdev = priv->mdev;
386 MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER);
387 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
388 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
389 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
392 #define PPORT_802_3_OFF(c) \
393 MLX5_BYTE_OFF(ppcnt_reg, \
394 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
395 static const struct counter_desc pport_802_3_stats_desc[] = {
396 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
397 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
398 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
399 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
400 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
401 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
402 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
403 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
404 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
405 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
406 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
407 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
408 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
409 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
410 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
411 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
412 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
413 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
416 #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
418 static int mlx5e_grp_802_3_get_num_stats(struct mlx5e_priv *priv)
420 return NUM_PPORT_802_3_COUNTERS;
423 static int mlx5e_grp_802_3_fill_strings(struct mlx5e_priv *priv, u8 *data,
428 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
429 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format);
433 static int mlx5e_grp_802_3_fill_stats(struct mlx5e_priv *priv, u64 *data,
438 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
439 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
440 pport_802_3_stats_desc, i);
444 static void mlx5e_grp_802_3_update_stats(struct mlx5e_priv *priv)
446 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
447 struct mlx5_core_dev *mdev = priv->mdev;
448 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
449 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
452 MLX5_SET(ppcnt_reg, in, local_port, 1);
453 out = pstats->IEEE_802_3_counters;
454 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
455 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
458 #define PPORT_2863_OFF(c) \
459 MLX5_BYTE_OFF(ppcnt_reg, \
460 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
461 static const struct counter_desc pport_2863_stats_desc[] = {
462 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
463 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
464 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
467 #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
469 static int mlx5e_grp_2863_get_num_stats(struct mlx5e_priv *priv)
471 return NUM_PPORT_2863_COUNTERS;
474 static int mlx5e_grp_2863_fill_strings(struct mlx5e_priv *priv, u8 *data,
479 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
480 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format);
484 static int mlx5e_grp_2863_fill_stats(struct mlx5e_priv *priv, u64 *data,
489 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
490 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
491 pport_2863_stats_desc, i);
495 static void mlx5e_grp_2863_update_stats(struct mlx5e_priv *priv)
497 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
498 struct mlx5_core_dev *mdev = priv->mdev;
499 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
500 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
503 MLX5_SET(ppcnt_reg, in, local_port, 1);
504 out = pstats->RFC_2863_counters;
505 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
506 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
509 #define PPORT_2819_OFF(c) \
510 MLX5_BYTE_OFF(ppcnt_reg, \
511 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
512 static const struct counter_desc pport_2819_stats_desc[] = {
513 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
514 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
515 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
516 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
517 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
518 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
519 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
520 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
521 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
522 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
523 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
524 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
525 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
528 #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
530 static int mlx5e_grp_2819_get_num_stats(struct mlx5e_priv *priv)
532 return NUM_PPORT_2819_COUNTERS;
535 static int mlx5e_grp_2819_fill_strings(struct mlx5e_priv *priv, u8 *data,
540 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
541 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format);
545 static int mlx5e_grp_2819_fill_stats(struct mlx5e_priv *priv, u64 *data,
550 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
551 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
552 pport_2819_stats_desc, i);
556 static void mlx5e_grp_2819_update_stats(struct mlx5e_priv *priv)
558 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
559 struct mlx5_core_dev *mdev = priv->mdev;
560 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
561 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
564 MLX5_SET(ppcnt_reg, in, local_port, 1);
565 out = pstats->RFC_2819_counters;
566 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
567 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
570 #define PPORT_PHY_STATISTICAL_OFF(c) \
571 MLX5_BYTE_OFF(ppcnt_reg, \
572 counter_set.phys_layer_statistical_cntrs.c##_high)
573 static const struct counter_desc pport_phy_statistical_stats_desc[] = {
574 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) },
575 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) },
578 #define NUM_PPORT_PHY_STATISTICAL_COUNTERS ARRAY_SIZE(pport_phy_statistical_stats_desc)
580 static int mlx5e_grp_phy_get_num_stats(struct mlx5e_priv *priv)
582 /* "1" for link_down_events special counter */
583 return MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group) ?
584 NUM_PPORT_PHY_STATISTICAL_COUNTERS + 1 : 1;
587 static int mlx5e_grp_phy_fill_strings(struct mlx5e_priv *priv, u8 *data,
592 strcpy(data + (idx++) * ETH_GSTRING_LEN, "link_down_events_phy");
594 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
597 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
598 strcpy(data + (idx++) * ETH_GSTRING_LEN,
599 pport_phy_statistical_stats_desc[i].format);
603 static int mlx5e_grp_phy_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
607 /* link_down_events_phy has special handling since it is not stored in __be64 format */
608 data[idx++] = MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters,
609 counter_set.phys_layer_cntrs.link_down_events);
611 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
614 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
616 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
617 pport_phy_statistical_stats_desc, i);
621 static void mlx5e_grp_phy_update_stats(struct mlx5e_priv *priv)
623 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
624 struct mlx5_core_dev *mdev = priv->mdev;
625 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
626 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
629 MLX5_SET(ppcnt_reg, in, local_port, 1);
630 out = pstats->phy_counters;
631 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
632 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
634 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
637 out = pstats->phy_statistical_counters;
638 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
639 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
642 #define PPORT_ETH_EXT_OFF(c) \
643 MLX5_BYTE_OFF(ppcnt_reg, \
644 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
645 static const struct counter_desc pport_eth_ext_stats_desc[] = {
646 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) },
649 #define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc)
651 static int mlx5e_grp_eth_ext_get_num_stats(struct mlx5e_priv *priv)
653 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
654 return NUM_PPORT_ETH_EXT_COUNTERS;
659 static int mlx5e_grp_eth_ext_fill_strings(struct mlx5e_priv *priv, u8 *data,
664 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
665 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
666 strcpy(data + (idx++) * ETH_GSTRING_LEN,
667 pport_eth_ext_stats_desc[i].format);
671 static int mlx5e_grp_eth_ext_fill_stats(struct mlx5e_priv *priv, u64 *data,
676 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
677 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
679 MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
680 pport_eth_ext_stats_desc, i);
684 static void mlx5e_grp_eth_ext_update_stats(struct mlx5e_priv *priv)
686 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
687 struct mlx5_core_dev *mdev = priv->mdev;
688 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
689 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
692 if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters))
695 MLX5_SET(ppcnt_reg, in, local_port, 1);
696 out = pstats->eth_ext_counters;
697 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
698 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
701 #define PCIE_PERF_OFF(c) \
702 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)
703 static const struct counter_desc pcie_perf_stats_desc[] = {
704 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },
705 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
708 #define PCIE_PERF_OFF64(c) \
709 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
710 static const struct counter_desc pcie_perf_stats_desc64[] = {
711 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
714 static const struct counter_desc pcie_perf_stall_stats_desc[] = {
715 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
716 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
717 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
718 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
721 #define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc)
722 #define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64)
723 #define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc)
725 static int mlx5e_grp_pcie_get_num_stats(struct mlx5e_priv *priv)
729 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
730 num_stats += NUM_PCIE_PERF_COUNTERS;
732 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
733 num_stats += NUM_PCIE_PERF_COUNTERS64;
735 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
736 num_stats += NUM_PCIE_PERF_STALL_COUNTERS;
741 static int mlx5e_grp_pcie_fill_strings(struct mlx5e_priv *priv, u8 *data,
746 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
747 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
748 strcpy(data + (idx++) * ETH_GSTRING_LEN,
749 pcie_perf_stats_desc[i].format);
751 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
752 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
753 strcpy(data + (idx++) * ETH_GSTRING_LEN,
754 pcie_perf_stats_desc64[i].format);
756 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
757 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
758 strcpy(data + (idx++) * ETH_GSTRING_LEN,
759 pcie_perf_stall_stats_desc[i].format);
763 static int mlx5e_grp_pcie_fill_stats(struct mlx5e_priv *priv, u64 *data,
768 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
769 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
771 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
772 pcie_perf_stats_desc, i);
774 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
775 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
777 MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
778 pcie_perf_stats_desc64, i);
780 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
781 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
783 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
784 pcie_perf_stall_stats_desc, i);
788 static void mlx5e_grp_pcie_update_stats(struct mlx5e_priv *priv)
790 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
791 struct mlx5_core_dev *mdev = priv->mdev;
792 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
793 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
796 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
799 out = pcie_stats->pcie_perf_counters;
800 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
801 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
804 #define PPORT_PER_PRIO_OFF(c) \
805 MLX5_BYTE_OFF(ppcnt_reg, \
806 counter_set.eth_per_prio_grp_data_layout.c##_high)
807 static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
808 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
809 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
810 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
811 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
814 #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
816 static int mlx5e_grp_per_prio_traffic_get_num_stats(struct mlx5e_priv *priv)
818 return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO;
821 static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv,
827 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
828 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
829 sprintf(data + (idx++) * ETH_GSTRING_LEN,
830 pport_per_prio_traffic_stats_desc[i].format, prio);
836 static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv,
842 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
843 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
845 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
846 pport_per_prio_traffic_stats_desc, i);
852 static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
853 /* %s is "global" or "prio{i}" */
854 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
855 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
856 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
857 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
858 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
861 static const struct counter_desc pport_pfc_stall_stats_desc[] = {
862 { "tx_pause_storm_warning_events ", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) },
863 { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) },
866 #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
867 #define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \
868 MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \
869 MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
871 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
873 struct mlx5_core_dev *mdev = priv->mdev;
878 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
881 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
883 return err ? 0 : pfc_en_tx | pfc_en_rx;
886 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
888 struct mlx5_core_dev *mdev = priv->mdev;
893 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
896 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
898 return err ? false : rx_pause | tx_pause;
901 static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv)
903 return (mlx5e_query_global_pause_combined(priv) +
904 hweight8(mlx5e_query_pfc_combined(priv))) *
905 NUM_PPORT_PER_PRIO_PFC_COUNTERS +
906 NUM_PPORT_PFC_STALL_COUNTERS(priv);
909 static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
913 unsigned long pfc_combined;
916 pfc_combined = mlx5e_query_pfc_combined(priv);
917 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
918 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
919 char pfc_string[ETH_GSTRING_LEN];
921 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
922 sprintf(data + (idx++) * ETH_GSTRING_LEN,
923 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
927 if (mlx5e_query_global_pause_combined(priv)) {
928 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
929 sprintf(data + (idx++) * ETH_GSTRING_LEN,
930 pport_per_prio_pfc_stats_desc[i].format, "global");
934 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
935 strcpy(data + (idx++) * ETH_GSTRING_LEN,
936 pport_pfc_stall_stats_desc[i].format);
941 static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv,
945 unsigned long pfc_combined;
948 pfc_combined = mlx5e_query_pfc_combined(priv);
949 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
950 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
952 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
953 pport_per_prio_pfc_stats_desc, i);
957 if (mlx5e_query_global_pause_combined(priv)) {
958 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
960 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
961 pport_per_prio_pfc_stats_desc, i);
965 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
966 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
967 pport_pfc_stall_stats_desc, i);
972 static int mlx5e_grp_per_prio_get_num_stats(struct mlx5e_priv *priv)
974 return mlx5e_grp_per_prio_traffic_get_num_stats(priv) +
975 mlx5e_grp_per_prio_pfc_get_num_stats(priv);
978 static int mlx5e_grp_per_prio_fill_strings(struct mlx5e_priv *priv, u8 *data,
981 idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx);
982 idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx);
986 static int mlx5e_grp_per_prio_fill_stats(struct mlx5e_priv *priv, u64 *data,
989 idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx);
990 idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx);
994 static void mlx5e_grp_per_prio_update_stats(struct mlx5e_priv *priv)
996 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
997 struct mlx5_core_dev *mdev = priv->mdev;
998 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
999 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1003 MLX5_SET(ppcnt_reg, in, local_port, 1);
1004 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
1005 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1006 out = pstats->per_prio_counters[prio];
1007 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1008 mlx5_core_access_reg(mdev, in, sz, out, sz,
1009 MLX5_REG_PPCNT, 0, 0);
1013 static const struct counter_desc mlx5e_pme_status_desc[] = {
1014 { "module_unplug", 8 },
1017 static const struct counter_desc mlx5e_pme_error_desc[] = {
1018 { "module_bus_stuck", 16 }, /* bus stuck (I2C or data shorted) */
1019 { "module_high_temp", 48 }, /* high temperature */
1020 { "module_bad_shorted", 56 }, /* bad or shorted cable/module */
1023 #define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc)
1024 #define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc)
1026 static int mlx5e_grp_pme_get_num_stats(struct mlx5e_priv *priv)
1028 return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS;
1031 static int mlx5e_grp_pme_fill_strings(struct mlx5e_priv *priv, u8 *data,
1036 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1037 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
1039 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1040 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
1045 static int mlx5e_grp_pme_fill_stats(struct mlx5e_priv *priv, u64 *data,
1048 struct mlx5_priv *mlx5_priv = &priv->mdev->priv;
1051 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1052 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
1053 mlx5e_pme_status_desc, i);
1055 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1056 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
1057 mlx5e_pme_error_desc, i);
1062 static int mlx5e_grp_ipsec_get_num_stats(struct mlx5e_priv *priv)
1064 return mlx5e_ipsec_get_count(priv);
1067 static int mlx5e_grp_ipsec_fill_strings(struct mlx5e_priv *priv, u8 *data,
1070 return idx + mlx5e_ipsec_get_strings(priv,
1071 data + idx * ETH_GSTRING_LEN);
1074 static int mlx5e_grp_ipsec_fill_stats(struct mlx5e_priv *priv, u64 *data,
1077 return idx + mlx5e_ipsec_get_stats(priv, data + idx);
1080 static void mlx5e_grp_ipsec_update_stats(struct mlx5e_priv *priv)
1082 mlx5e_ipsec_update_stats(priv);
1085 static int mlx5e_grp_tls_get_num_stats(struct mlx5e_priv *priv)
1087 return mlx5e_tls_get_count(priv);
1090 static int mlx5e_grp_tls_fill_strings(struct mlx5e_priv *priv, u8 *data,
1093 return idx + mlx5e_tls_get_strings(priv, data + idx * ETH_GSTRING_LEN);
1096 static int mlx5e_grp_tls_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
1098 return idx + mlx5e_tls_get_stats(priv, data + idx);
1101 static const struct counter_desc rq_stats_desc[] = {
1102 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
1103 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
1104 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
1105 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
1106 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
1107 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
1108 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
1109 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx) },
1110 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx_full) },
1111 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
1112 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
1113 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
1114 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
1115 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler) },
1116 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
1117 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
1118 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
1119 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, page_reuse) },
1120 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) },
1121 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) },
1122 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) },
1123 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) },
1124 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) },
1127 static const struct counter_desc sq_stats_desc[] = {
1128 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
1129 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
1130 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
1131 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
1132 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
1133 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
1134 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
1135 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
1136 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
1137 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
1138 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
1139 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
1140 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
1141 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
1142 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) },
1143 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
1144 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
1147 static const struct counter_desc ch_stats_desc[] = {
1148 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) },
1151 #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
1152 #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
1153 #define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc)
1155 static int mlx5e_grp_channels_get_num_stats(struct mlx5e_priv *priv)
1157 int max_nch = priv->profile->max_nch(priv->mdev);
1159 return (NUM_RQ_STATS * max_nch) +
1160 (NUM_CH_STATS * max_nch) +
1161 (NUM_SQ_STATS * max_nch * priv->max_opened_tc);
1164 static int mlx5e_grp_channels_fill_strings(struct mlx5e_priv *priv, u8 *data,
1167 int max_nch = priv->profile->max_nch(priv->mdev);
1170 for (i = 0; i < max_nch; i++)
1171 for (j = 0; j < NUM_CH_STATS; j++)
1172 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1173 ch_stats_desc[j].format, i);
1175 for (i = 0; i < max_nch; i++)
1176 for (j = 0; j < NUM_RQ_STATS; j++)
1177 sprintf(data + (idx++) * ETH_GSTRING_LEN, rq_stats_desc[j].format, i);
1179 for (tc = 0; tc < priv->max_opened_tc; tc++)
1180 for (i = 0; i < max_nch; i++)
1181 for (j = 0; j < NUM_SQ_STATS; j++)
1182 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1183 sq_stats_desc[j].format,
1184 priv->channel_tc2txq[i][tc]);
1189 static int mlx5e_grp_channels_fill_stats(struct mlx5e_priv *priv, u64 *data,
1192 int max_nch = priv->profile->max_nch(priv->mdev);
1195 for (i = 0; i < max_nch; i++)
1196 for (j = 0; j < NUM_CH_STATS; j++)
1198 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].ch,
1201 for (i = 0; i < max_nch; i++)
1202 for (j = 0; j < NUM_RQ_STATS; j++)
1204 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq,
1207 for (tc = 0; tc < priv->max_opened_tc; tc++)
1208 for (i = 0; i < max_nch; i++)
1209 for (j = 0; j < NUM_SQ_STATS; j++)
1211 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].sq[tc],
1217 /* The stats groups order is opposite to the update_stats() order calls */
1218 const struct mlx5e_stats_grp mlx5e_stats_grps[] = {
1220 .get_num_stats = mlx5e_grp_sw_get_num_stats,
1221 .fill_strings = mlx5e_grp_sw_fill_strings,
1222 .fill_stats = mlx5e_grp_sw_fill_stats,
1223 .update_stats = mlx5e_grp_sw_update_stats,
1226 .get_num_stats = mlx5e_grp_q_get_num_stats,
1227 .fill_strings = mlx5e_grp_q_fill_strings,
1228 .fill_stats = mlx5e_grp_q_fill_stats,
1229 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1230 .update_stats = mlx5e_grp_q_update_stats,
1233 .get_num_stats = mlx5e_grp_vnic_env_get_num_stats,
1234 .fill_strings = mlx5e_grp_vnic_env_fill_strings,
1235 .fill_stats = mlx5e_grp_vnic_env_fill_stats,
1236 .update_stats = mlx5e_grp_vnic_env_update_stats,
1239 .get_num_stats = mlx5e_grp_vport_get_num_stats,
1240 .fill_strings = mlx5e_grp_vport_fill_strings,
1241 .fill_stats = mlx5e_grp_vport_fill_stats,
1242 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1243 .update_stats = mlx5e_grp_vport_update_stats,
1246 .get_num_stats = mlx5e_grp_802_3_get_num_stats,
1247 .fill_strings = mlx5e_grp_802_3_fill_strings,
1248 .fill_stats = mlx5e_grp_802_3_fill_stats,
1249 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1250 .update_stats = mlx5e_grp_802_3_update_stats,
1253 .get_num_stats = mlx5e_grp_2863_get_num_stats,
1254 .fill_strings = mlx5e_grp_2863_fill_strings,
1255 .fill_stats = mlx5e_grp_2863_fill_stats,
1256 .update_stats = mlx5e_grp_2863_update_stats,
1259 .get_num_stats = mlx5e_grp_2819_get_num_stats,
1260 .fill_strings = mlx5e_grp_2819_fill_strings,
1261 .fill_stats = mlx5e_grp_2819_fill_stats,
1262 .update_stats = mlx5e_grp_2819_update_stats,
1265 .get_num_stats = mlx5e_grp_phy_get_num_stats,
1266 .fill_strings = mlx5e_grp_phy_fill_strings,
1267 .fill_stats = mlx5e_grp_phy_fill_stats,
1268 .update_stats = mlx5e_grp_phy_update_stats,
1271 .get_num_stats = mlx5e_grp_eth_ext_get_num_stats,
1272 .fill_strings = mlx5e_grp_eth_ext_fill_strings,
1273 .fill_stats = mlx5e_grp_eth_ext_fill_stats,
1274 .update_stats = mlx5e_grp_eth_ext_update_stats,
1277 .get_num_stats = mlx5e_grp_pcie_get_num_stats,
1278 .fill_strings = mlx5e_grp_pcie_fill_strings,
1279 .fill_stats = mlx5e_grp_pcie_fill_stats,
1280 .update_stats = mlx5e_grp_pcie_update_stats,
1283 .get_num_stats = mlx5e_grp_per_prio_get_num_stats,
1284 .fill_strings = mlx5e_grp_per_prio_fill_strings,
1285 .fill_stats = mlx5e_grp_per_prio_fill_stats,
1286 .update_stats = mlx5e_grp_per_prio_update_stats,
1289 .get_num_stats = mlx5e_grp_pme_get_num_stats,
1290 .fill_strings = mlx5e_grp_pme_fill_strings,
1291 .fill_stats = mlx5e_grp_pme_fill_stats,
1294 .get_num_stats = mlx5e_grp_ipsec_get_num_stats,
1295 .fill_strings = mlx5e_grp_ipsec_fill_strings,
1296 .fill_stats = mlx5e_grp_ipsec_fill_stats,
1297 .update_stats = mlx5e_grp_ipsec_update_stats,
1300 .get_num_stats = mlx5e_grp_tls_get_num_stats,
1301 .fill_strings = mlx5e_grp_tls_fill_strings,
1302 .fill_stats = mlx5e_grp_tls_fill_stats,
1305 .get_num_stats = mlx5e_grp_channels_get_num_stats,
1306 .fill_strings = mlx5e_grp_channels_fill_strings,
1307 .fill_stats = mlx5e_grp_channels_fill_stats,
1311 const int mlx5e_num_stats_grps = ARRAY_SIZE(mlx5e_stats_grps);