2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include "en_accel/ipsec.h"
35 #include "en_accel/tls.h"
37 static const struct counter_desc sw_stats_desc[] = {
38 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
39 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
40 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
41 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
42 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
43 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
44 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
45 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
46 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) },
48 #ifdef CONFIG_MLX5_EN_TLS
49 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) },
50 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) },
53 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
54 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
55 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) },
56 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
57 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
58 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
59 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
60 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
61 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx) },
62 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
63 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) },
64 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
65 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
66 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
67 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
68 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
69 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
70 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) },
71 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) },
72 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
73 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler) },
74 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
75 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
76 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
77 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_page_reuse) },
78 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) },
79 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) },
80 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) },
81 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) },
82 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) },
83 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) },
86 #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
88 static int mlx5e_grp_sw_get_num_stats(struct mlx5e_priv *priv)
90 return NUM_SW_COUNTERS;
93 static int mlx5e_grp_sw_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
97 for (i = 0; i < NUM_SW_COUNTERS; i++)
98 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
102 static int mlx5e_grp_sw_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
106 for (i = 0; i < NUM_SW_COUNTERS; i++)
107 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i);
111 static void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv)
113 struct mlx5e_sw_stats temp, *s = &temp;
114 struct mlx5e_rq_stats *rq_stats;
115 struct mlx5e_sq_stats *sq_stats;
116 struct mlx5e_ch_stats *ch_stats;
119 memset(s, 0, sizeof(*s));
120 for (i = 0; i < priv->channels.num; i++) {
121 struct mlx5e_channel *c = priv->channels.c[i];
123 rq_stats = &c->rq.stats;
124 ch_stats = &c->stats;
126 s->rx_packets += rq_stats->packets;
127 s->rx_bytes += rq_stats->bytes;
128 s->rx_lro_packets += rq_stats->lro_packets;
129 s->rx_lro_bytes += rq_stats->lro_bytes;
130 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
131 s->rx_csum_none += rq_stats->csum_none;
132 s->rx_csum_complete += rq_stats->csum_complete;
133 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
134 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
135 s->rx_xdp_drop += rq_stats->xdp_drop;
136 s->rx_xdp_tx += rq_stats->xdp_tx;
137 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
138 s->rx_wqe_err += rq_stats->wqe_err;
139 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
140 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
141 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
142 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
143 s->rx_page_reuse += rq_stats->page_reuse;
144 s->rx_cache_reuse += rq_stats->cache_reuse;
145 s->rx_cache_full += rq_stats->cache_full;
146 s->rx_cache_empty += rq_stats->cache_empty;
147 s->rx_cache_busy += rq_stats->cache_busy;
148 s->rx_cache_waive += rq_stats->cache_waive;
149 s->ch_eq_rearm += ch_stats->eq_rearm;
151 for (j = 0; j < priv->channels.params.num_tc; j++) {
152 sq_stats = &c->sq[j].stats;
154 s->tx_packets += sq_stats->packets;
155 s->tx_bytes += sq_stats->bytes;
156 s->tx_tso_packets += sq_stats->tso_packets;
157 s->tx_tso_bytes += sq_stats->tso_bytes;
158 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
159 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
160 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
161 s->tx_queue_stopped += sq_stats->stopped;
162 s->tx_queue_wake += sq_stats->wake;
163 s->tx_queue_dropped += sq_stats->dropped;
164 s->tx_cqe_err += sq_stats->cqe_err;
165 s->tx_recover += sq_stats->recover;
166 s->tx_xmit_more += sq_stats->xmit_more;
167 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
168 s->tx_csum_none += sq_stats->csum_none;
169 s->tx_csum_partial += sq_stats->csum_partial;
170 #ifdef CONFIG_MLX5_EN_TLS
171 s->tx_tls_ooo += sq_stats->tls_ooo;
172 s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes;
177 memcpy(&priv->stats.sw, s, sizeof(*s));
180 static const struct counter_desc q_stats_desc[] = {
181 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
184 static const struct counter_desc drop_rq_stats_desc[] = {
185 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) },
188 #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
189 #define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc)
191 static int mlx5e_grp_q_get_num_stats(struct mlx5e_priv *priv)
196 num_stats += NUM_Q_COUNTERS;
198 if (priv->drop_rq_q_counter)
199 num_stats += NUM_DROP_RQ_COUNTERS;
204 static int mlx5e_grp_q_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
208 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
209 strcpy(data + (idx++) * ETH_GSTRING_LEN,
210 q_stats_desc[i].format);
212 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
213 strcpy(data + (idx++) * ETH_GSTRING_LEN,
214 drop_rq_stats_desc[i].format);
219 static int mlx5e_grp_q_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
223 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
224 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
226 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
227 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
228 drop_rq_stats_desc, i);
232 static void mlx5e_grp_q_update_stats(struct mlx5e_priv *priv)
234 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
235 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
237 if (priv->q_counter &&
238 !mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out,
240 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out,
242 if (priv->drop_rq_q_counter &&
243 !mlx5_core_query_q_counter(priv->mdev, priv->drop_rq_q_counter, 0,
245 qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out, out,
249 #define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c)
250 static const struct counter_desc vnic_env_stats_desc[] = {
251 { "rx_steer_missed_packets",
252 VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) },
255 #define NUM_VNIC_ENV_COUNTERS ARRAY_SIZE(vnic_env_stats_desc)
257 static int mlx5e_grp_vnic_env_get_num_stats(struct mlx5e_priv *priv)
259 return MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard) ?
260 NUM_VNIC_ENV_COUNTERS : 0;
263 static int mlx5e_grp_vnic_env_fill_strings(struct mlx5e_priv *priv, u8 *data,
268 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
271 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
272 strcpy(data + (idx++) * ETH_GSTRING_LEN,
273 vnic_env_stats_desc[i].format);
277 static int mlx5e_grp_vnic_env_fill_stats(struct mlx5e_priv *priv, u64 *data,
282 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
285 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
286 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out,
287 vnic_env_stats_desc, i);
291 static void mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
293 u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out;
294 int outlen = MLX5_ST_SZ_BYTES(query_vnic_env_out);
295 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0};
296 struct mlx5_core_dev *mdev = priv->mdev;
298 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
301 MLX5_SET(query_vnic_env_in, in, opcode,
302 MLX5_CMD_OP_QUERY_VNIC_ENV);
303 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
304 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
305 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
308 #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
309 static const struct counter_desc vport_stats_desc[] = {
310 { "rx_vport_unicast_packets",
311 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
312 { "rx_vport_unicast_bytes",
313 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
314 { "tx_vport_unicast_packets",
315 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
316 { "tx_vport_unicast_bytes",
317 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
318 { "rx_vport_multicast_packets",
319 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
320 { "rx_vport_multicast_bytes",
321 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
322 { "tx_vport_multicast_packets",
323 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
324 { "tx_vport_multicast_bytes",
325 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
326 { "rx_vport_broadcast_packets",
327 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
328 { "rx_vport_broadcast_bytes",
329 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
330 { "tx_vport_broadcast_packets",
331 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
332 { "tx_vport_broadcast_bytes",
333 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
334 { "rx_vport_rdma_unicast_packets",
335 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
336 { "rx_vport_rdma_unicast_bytes",
337 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
338 { "tx_vport_rdma_unicast_packets",
339 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
340 { "tx_vport_rdma_unicast_bytes",
341 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
342 { "rx_vport_rdma_multicast_packets",
343 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
344 { "rx_vport_rdma_multicast_bytes",
345 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
346 { "tx_vport_rdma_multicast_packets",
347 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
348 { "tx_vport_rdma_multicast_bytes",
349 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
352 #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
354 static int mlx5e_grp_vport_get_num_stats(struct mlx5e_priv *priv)
356 return NUM_VPORT_COUNTERS;
359 static int mlx5e_grp_vport_fill_strings(struct mlx5e_priv *priv, u8 *data,
364 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
365 strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format);
369 static int mlx5e_grp_vport_fill_stats(struct mlx5e_priv *priv, u64 *data,
374 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
375 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
376 vport_stats_desc, i);
380 static void mlx5e_grp_vport_update_stats(struct mlx5e_priv *priv)
382 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
383 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
384 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
385 struct mlx5_core_dev *mdev = priv->mdev;
387 MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER);
388 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
389 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
390 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
393 #define PPORT_802_3_OFF(c) \
394 MLX5_BYTE_OFF(ppcnt_reg, \
395 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
396 static const struct counter_desc pport_802_3_stats_desc[] = {
397 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
398 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
399 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
400 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
401 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
402 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
403 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
404 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
405 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
406 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
407 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
408 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
409 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
410 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
411 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
412 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
413 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
414 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
417 #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
419 static int mlx5e_grp_802_3_get_num_stats(struct mlx5e_priv *priv)
421 return NUM_PPORT_802_3_COUNTERS;
424 static int mlx5e_grp_802_3_fill_strings(struct mlx5e_priv *priv, u8 *data,
429 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
430 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format);
434 static int mlx5e_grp_802_3_fill_stats(struct mlx5e_priv *priv, u64 *data,
439 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
440 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
441 pport_802_3_stats_desc, i);
445 static void mlx5e_grp_802_3_update_stats(struct mlx5e_priv *priv)
447 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
448 struct mlx5_core_dev *mdev = priv->mdev;
449 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
450 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
453 MLX5_SET(ppcnt_reg, in, local_port, 1);
454 out = pstats->IEEE_802_3_counters;
455 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
456 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
459 #define PPORT_2863_OFF(c) \
460 MLX5_BYTE_OFF(ppcnt_reg, \
461 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
462 static const struct counter_desc pport_2863_stats_desc[] = {
463 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
464 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
465 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
468 #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
470 static int mlx5e_grp_2863_get_num_stats(struct mlx5e_priv *priv)
472 return NUM_PPORT_2863_COUNTERS;
475 static int mlx5e_grp_2863_fill_strings(struct mlx5e_priv *priv, u8 *data,
480 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
481 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format);
485 static int mlx5e_grp_2863_fill_stats(struct mlx5e_priv *priv, u64 *data,
490 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
491 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
492 pport_2863_stats_desc, i);
496 static void mlx5e_grp_2863_update_stats(struct mlx5e_priv *priv)
498 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
499 struct mlx5_core_dev *mdev = priv->mdev;
500 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
501 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
504 MLX5_SET(ppcnt_reg, in, local_port, 1);
505 out = pstats->RFC_2863_counters;
506 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
507 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
510 #define PPORT_2819_OFF(c) \
511 MLX5_BYTE_OFF(ppcnt_reg, \
512 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
513 static const struct counter_desc pport_2819_stats_desc[] = {
514 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
515 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
516 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
517 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
518 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
519 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
520 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
521 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
522 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
523 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
524 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
525 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
526 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
529 #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
531 static int mlx5e_grp_2819_get_num_stats(struct mlx5e_priv *priv)
533 return NUM_PPORT_2819_COUNTERS;
536 static int mlx5e_grp_2819_fill_strings(struct mlx5e_priv *priv, u8 *data,
541 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
542 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format);
546 static int mlx5e_grp_2819_fill_stats(struct mlx5e_priv *priv, u64 *data,
551 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
552 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
553 pport_2819_stats_desc, i);
557 static void mlx5e_grp_2819_update_stats(struct mlx5e_priv *priv)
559 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
560 struct mlx5_core_dev *mdev = priv->mdev;
561 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
562 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
565 MLX5_SET(ppcnt_reg, in, local_port, 1);
566 out = pstats->RFC_2819_counters;
567 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
568 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
571 #define PPORT_PHY_STATISTICAL_OFF(c) \
572 MLX5_BYTE_OFF(ppcnt_reg, \
573 counter_set.phys_layer_statistical_cntrs.c##_high)
574 static const struct counter_desc pport_phy_statistical_stats_desc[] = {
575 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) },
576 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) },
579 #define NUM_PPORT_PHY_STATISTICAL_COUNTERS ARRAY_SIZE(pport_phy_statistical_stats_desc)
581 static int mlx5e_grp_phy_get_num_stats(struct mlx5e_priv *priv)
583 /* "1" for link_down_events special counter */
584 return MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group) ?
585 NUM_PPORT_PHY_STATISTICAL_COUNTERS + 1 : 1;
588 static int mlx5e_grp_phy_fill_strings(struct mlx5e_priv *priv, u8 *data,
593 strcpy(data + (idx++) * ETH_GSTRING_LEN, "link_down_events_phy");
595 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
598 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
599 strcpy(data + (idx++) * ETH_GSTRING_LEN,
600 pport_phy_statistical_stats_desc[i].format);
604 static int mlx5e_grp_phy_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
608 /* link_down_events_phy has special handling since it is not stored in __be64 format */
609 data[idx++] = MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters,
610 counter_set.phys_layer_cntrs.link_down_events);
612 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
615 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
617 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
618 pport_phy_statistical_stats_desc, i);
622 static void mlx5e_grp_phy_update_stats(struct mlx5e_priv *priv)
624 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
625 struct mlx5_core_dev *mdev = priv->mdev;
626 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
627 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
630 MLX5_SET(ppcnt_reg, in, local_port, 1);
631 out = pstats->phy_counters;
632 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
633 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
635 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
638 out = pstats->phy_statistical_counters;
639 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
640 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
643 #define PPORT_ETH_EXT_OFF(c) \
644 MLX5_BYTE_OFF(ppcnt_reg, \
645 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
646 static const struct counter_desc pport_eth_ext_stats_desc[] = {
647 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) },
650 #define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc)
652 static int mlx5e_grp_eth_ext_get_num_stats(struct mlx5e_priv *priv)
654 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
655 return NUM_PPORT_ETH_EXT_COUNTERS;
660 static int mlx5e_grp_eth_ext_fill_strings(struct mlx5e_priv *priv, u8 *data,
665 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
666 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
667 strcpy(data + (idx++) * ETH_GSTRING_LEN,
668 pport_eth_ext_stats_desc[i].format);
672 static int mlx5e_grp_eth_ext_fill_stats(struct mlx5e_priv *priv, u64 *data,
677 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
678 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
680 MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
681 pport_eth_ext_stats_desc, i);
685 static void mlx5e_grp_eth_ext_update_stats(struct mlx5e_priv *priv)
687 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
688 struct mlx5_core_dev *mdev = priv->mdev;
689 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
690 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
693 if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters))
696 MLX5_SET(ppcnt_reg, in, local_port, 1);
697 out = pstats->eth_ext_counters;
698 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
699 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
702 #define PCIE_PERF_OFF(c) \
703 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)
704 static const struct counter_desc pcie_perf_stats_desc[] = {
705 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },
706 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
709 #define PCIE_PERF_OFF64(c) \
710 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
711 static const struct counter_desc pcie_perf_stats_desc64[] = {
712 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
715 static const struct counter_desc pcie_perf_stall_stats_desc[] = {
716 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
717 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
718 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
719 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
722 #define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc)
723 #define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64)
724 #define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc)
726 static int mlx5e_grp_pcie_get_num_stats(struct mlx5e_priv *priv)
730 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
731 num_stats += NUM_PCIE_PERF_COUNTERS;
733 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
734 num_stats += NUM_PCIE_PERF_COUNTERS64;
736 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
737 num_stats += NUM_PCIE_PERF_STALL_COUNTERS;
742 static int mlx5e_grp_pcie_fill_strings(struct mlx5e_priv *priv, u8 *data,
747 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
748 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
749 strcpy(data + (idx++) * ETH_GSTRING_LEN,
750 pcie_perf_stats_desc[i].format);
752 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
753 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
754 strcpy(data + (idx++) * ETH_GSTRING_LEN,
755 pcie_perf_stats_desc64[i].format);
757 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
758 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
759 strcpy(data + (idx++) * ETH_GSTRING_LEN,
760 pcie_perf_stall_stats_desc[i].format);
764 static int mlx5e_grp_pcie_fill_stats(struct mlx5e_priv *priv, u64 *data,
769 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
770 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
772 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
773 pcie_perf_stats_desc, i);
775 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
776 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
778 MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
779 pcie_perf_stats_desc64, i);
781 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
782 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
784 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
785 pcie_perf_stall_stats_desc, i);
789 static void mlx5e_grp_pcie_update_stats(struct mlx5e_priv *priv)
791 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
792 struct mlx5_core_dev *mdev = priv->mdev;
793 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
794 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
797 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
800 out = pcie_stats->pcie_perf_counters;
801 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
802 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
805 #define PPORT_PER_PRIO_OFF(c) \
806 MLX5_BYTE_OFF(ppcnt_reg, \
807 counter_set.eth_per_prio_grp_data_layout.c##_high)
808 static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
809 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
810 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
811 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
812 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
815 #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
817 static int mlx5e_grp_per_prio_traffic_get_num_stats(struct mlx5e_priv *priv)
819 return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO;
822 static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv,
828 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
829 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
830 sprintf(data + (idx++) * ETH_GSTRING_LEN,
831 pport_per_prio_traffic_stats_desc[i].format, prio);
837 static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv,
843 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
844 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
846 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
847 pport_per_prio_traffic_stats_desc, i);
853 static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
854 /* %s is "global" or "prio{i}" */
855 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
856 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
857 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
858 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
859 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
862 static const struct counter_desc pport_pfc_stall_stats_desc[] = {
863 { "tx_pause_storm_warning_events ", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) },
864 { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) },
867 #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
868 #define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \
869 MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \
870 MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
872 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
874 struct mlx5_core_dev *mdev = priv->mdev;
879 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
882 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
884 return err ? 0 : pfc_en_tx | pfc_en_rx;
887 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
889 struct mlx5_core_dev *mdev = priv->mdev;
894 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
897 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
899 return err ? false : rx_pause | tx_pause;
902 static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv)
904 return (mlx5e_query_global_pause_combined(priv) +
905 hweight8(mlx5e_query_pfc_combined(priv))) *
906 NUM_PPORT_PER_PRIO_PFC_COUNTERS +
907 NUM_PPORT_PFC_STALL_COUNTERS(priv);
910 static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
914 unsigned long pfc_combined;
917 pfc_combined = mlx5e_query_pfc_combined(priv);
918 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
919 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
920 char pfc_string[ETH_GSTRING_LEN];
922 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
923 sprintf(data + (idx++) * ETH_GSTRING_LEN,
924 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
928 if (mlx5e_query_global_pause_combined(priv)) {
929 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
930 sprintf(data + (idx++) * ETH_GSTRING_LEN,
931 pport_per_prio_pfc_stats_desc[i].format, "global");
935 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
936 strcpy(data + (idx++) * ETH_GSTRING_LEN,
937 pport_pfc_stall_stats_desc[i].format);
942 static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv,
946 unsigned long pfc_combined;
949 pfc_combined = mlx5e_query_pfc_combined(priv);
950 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
951 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
953 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
954 pport_per_prio_pfc_stats_desc, i);
958 if (mlx5e_query_global_pause_combined(priv)) {
959 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
961 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
962 pport_per_prio_pfc_stats_desc, i);
966 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
967 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
968 pport_pfc_stall_stats_desc, i);
973 static int mlx5e_grp_per_prio_get_num_stats(struct mlx5e_priv *priv)
975 return mlx5e_grp_per_prio_traffic_get_num_stats(priv) +
976 mlx5e_grp_per_prio_pfc_get_num_stats(priv);
979 static int mlx5e_grp_per_prio_fill_strings(struct mlx5e_priv *priv, u8 *data,
982 idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx);
983 idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx);
987 static int mlx5e_grp_per_prio_fill_stats(struct mlx5e_priv *priv, u64 *data,
990 idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx);
991 idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx);
995 static void mlx5e_grp_per_prio_update_stats(struct mlx5e_priv *priv)
997 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
998 struct mlx5_core_dev *mdev = priv->mdev;
999 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1000 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1004 MLX5_SET(ppcnt_reg, in, local_port, 1);
1005 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
1006 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1007 out = pstats->per_prio_counters[prio];
1008 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1009 mlx5_core_access_reg(mdev, in, sz, out, sz,
1010 MLX5_REG_PPCNT, 0, 0);
1014 static const struct counter_desc mlx5e_pme_status_desc[] = {
1015 { "module_unplug", 8 },
1018 static const struct counter_desc mlx5e_pme_error_desc[] = {
1019 { "module_bus_stuck", 16 }, /* bus stuck (I2C or data shorted) */
1020 { "module_high_temp", 48 }, /* high temperature */
1021 { "module_bad_shorted", 56 }, /* bad or shorted cable/module */
1024 #define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc)
1025 #define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc)
1027 static int mlx5e_grp_pme_get_num_stats(struct mlx5e_priv *priv)
1029 return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS;
1032 static int mlx5e_grp_pme_fill_strings(struct mlx5e_priv *priv, u8 *data,
1037 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1038 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
1040 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1041 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
1046 static int mlx5e_grp_pme_fill_stats(struct mlx5e_priv *priv, u64 *data,
1049 struct mlx5_priv *mlx5_priv = &priv->mdev->priv;
1052 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1053 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
1054 mlx5e_pme_status_desc, i);
1056 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1057 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
1058 mlx5e_pme_error_desc, i);
1063 static int mlx5e_grp_ipsec_get_num_stats(struct mlx5e_priv *priv)
1065 return mlx5e_ipsec_get_count(priv);
1068 static int mlx5e_grp_ipsec_fill_strings(struct mlx5e_priv *priv, u8 *data,
1071 return idx + mlx5e_ipsec_get_strings(priv,
1072 data + idx * ETH_GSTRING_LEN);
1075 static int mlx5e_grp_ipsec_fill_stats(struct mlx5e_priv *priv, u64 *data,
1078 return idx + mlx5e_ipsec_get_stats(priv, data + idx);
1081 static void mlx5e_grp_ipsec_update_stats(struct mlx5e_priv *priv)
1083 mlx5e_ipsec_update_stats(priv);
1086 static int mlx5e_grp_tls_get_num_stats(struct mlx5e_priv *priv)
1088 return mlx5e_tls_get_count(priv);
1091 static int mlx5e_grp_tls_fill_strings(struct mlx5e_priv *priv, u8 *data,
1094 return idx + mlx5e_tls_get_strings(priv, data + idx * ETH_GSTRING_LEN);
1097 static int mlx5e_grp_tls_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
1099 return idx + mlx5e_tls_get_stats(priv, data + idx);
1102 static const struct counter_desc rq_stats_desc[] = {
1103 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
1104 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
1105 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
1106 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
1107 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
1108 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
1109 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
1110 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx) },
1111 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx_full) },
1112 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
1113 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
1114 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
1115 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
1116 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler) },
1117 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
1118 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
1119 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
1120 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, page_reuse) },
1121 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) },
1122 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) },
1123 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) },
1124 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) },
1125 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) },
1128 static const struct counter_desc sq_stats_desc[] = {
1129 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
1130 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
1131 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
1132 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
1133 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
1134 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
1135 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
1136 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
1137 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
1138 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
1139 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
1140 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
1141 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
1142 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
1143 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
1144 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
1145 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) },
1148 static const struct counter_desc ch_stats_desc[] = {
1149 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) },
1152 #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
1153 #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
1154 #define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc)
1156 static int mlx5e_grp_channels_get_num_stats(struct mlx5e_priv *priv)
1158 return (NUM_RQ_STATS * priv->channels.num) +
1159 (NUM_CH_STATS * priv->channels.num) +
1160 (NUM_SQ_STATS * priv->channels.num * priv->channels.params.num_tc);
1163 static int mlx5e_grp_channels_fill_strings(struct mlx5e_priv *priv, u8 *data,
1168 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1171 for (i = 0; i < priv->channels.num; i++)
1172 for (j = 0; j < NUM_CH_STATS; j++)
1173 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1174 ch_stats_desc[j].format, i);
1176 for (i = 0; i < priv->channels.num; i++)
1177 for (j = 0; j < NUM_RQ_STATS; j++)
1178 sprintf(data + (idx++) * ETH_GSTRING_LEN, rq_stats_desc[j].format, i);
1180 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
1181 for (i = 0; i < priv->channels.num; i++)
1182 for (j = 0; j < NUM_SQ_STATS; j++)
1183 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1184 sq_stats_desc[j].format,
1185 priv->channel_tc2txq[i][tc]);
1190 static int mlx5e_grp_channels_fill_stats(struct mlx5e_priv *priv, u64 *data,
1193 struct mlx5e_channels *channels = &priv->channels;
1196 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1199 for (i = 0; i < channels->num; i++)
1200 for (j = 0; j < NUM_CH_STATS; j++)
1202 MLX5E_READ_CTR64_CPU(&channels->c[i]->stats,
1205 for (i = 0; i < channels->num; i++)
1206 for (j = 0; j < NUM_RQ_STATS; j++)
1208 MLX5E_READ_CTR64_CPU(&channels->c[i]->rq.stats,
1211 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
1212 for (i = 0; i < channels->num; i++)
1213 for (j = 0; j < NUM_SQ_STATS; j++)
1215 MLX5E_READ_CTR64_CPU(&channels->c[i]->sq[tc].stats,
1221 /* The stats groups order is opposite to the update_stats() order calls */
1222 const struct mlx5e_stats_grp mlx5e_stats_grps[] = {
1224 .get_num_stats = mlx5e_grp_sw_get_num_stats,
1225 .fill_strings = mlx5e_grp_sw_fill_strings,
1226 .fill_stats = mlx5e_grp_sw_fill_stats,
1227 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1228 .update_stats = mlx5e_grp_sw_update_stats,
1231 .get_num_stats = mlx5e_grp_q_get_num_stats,
1232 .fill_strings = mlx5e_grp_q_fill_strings,
1233 .fill_stats = mlx5e_grp_q_fill_stats,
1234 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1235 .update_stats = mlx5e_grp_q_update_stats,
1238 .get_num_stats = mlx5e_grp_vnic_env_get_num_stats,
1239 .fill_strings = mlx5e_grp_vnic_env_fill_strings,
1240 .fill_stats = mlx5e_grp_vnic_env_fill_stats,
1241 .update_stats = mlx5e_grp_vnic_env_update_stats,
1244 .get_num_stats = mlx5e_grp_vport_get_num_stats,
1245 .fill_strings = mlx5e_grp_vport_fill_strings,
1246 .fill_stats = mlx5e_grp_vport_fill_stats,
1247 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1248 .update_stats = mlx5e_grp_vport_update_stats,
1251 .get_num_stats = mlx5e_grp_802_3_get_num_stats,
1252 .fill_strings = mlx5e_grp_802_3_fill_strings,
1253 .fill_stats = mlx5e_grp_802_3_fill_stats,
1254 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1255 .update_stats = mlx5e_grp_802_3_update_stats,
1258 .get_num_stats = mlx5e_grp_2863_get_num_stats,
1259 .fill_strings = mlx5e_grp_2863_fill_strings,
1260 .fill_stats = mlx5e_grp_2863_fill_stats,
1261 .update_stats = mlx5e_grp_2863_update_stats,
1264 .get_num_stats = mlx5e_grp_2819_get_num_stats,
1265 .fill_strings = mlx5e_grp_2819_fill_strings,
1266 .fill_stats = mlx5e_grp_2819_fill_stats,
1267 .update_stats = mlx5e_grp_2819_update_stats,
1270 .get_num_stats = mlx5e_grp_phy_get_num_stats,
1271 .fill_strings = mlx5e_grp_phy_fill_strings,
1272 .fill_stats = mlx5e_grp_phy_fill_stats,
1273 .update_stats = mlx5e_grp_phy_update_stats,
1276 .get_num_stats = mlx5e_grp_eth_ext_get_num_stats,
1277 .fill_strings = mlx5e_grp_eth_ext_fill_strings,
1278 .fill_stats = mlx5e_grp_eth_ext_fill_stats,
1279 .update_stats = mlx5e_grp_eth_ext_update_stats,
1282 .get_num_stats = mlx5e_grp_pcie_get_num_stats,
1283 .fill_strings = mlx5e_grp_pcie_fill_strings,
1284 .fill_stats = mlx5e_grp_pcie_fill_stats,
1285 .update_stats = mlx5e_grp_pcie_update_stats,
1288 .get_num_stats = mlx5e_grp_per_prio_get_num_stats,
1289 .fill_strings = mlx5e_grp_per_prio_fill_strings,
1290 .fill_stats = mlx5e_grp_per_prio_fill_stats,
1291 .update_stats = mlx5e_grp_per_prio_update_stats,
1294 .get_num_stats = mlx5e_grp_pme_get_num_stats,
1295 .fill_strings = mlx5e_grp_pme_fill_strings,
1296 .fill_stats = mlx5e_grp_pme_fill_stats,
1299 .get_num_stats = mlx5e_grp_ipsec_get_num_stats,
1300 .fill_strings = mlx5e_grp_ipsec_fill_strings,
1301 .fill_stats = mlx5e_grp_ipsec_fill_stats,
1302 .update_stats = mlx5e_grp_ipsec_update_stats,
1305 .get_num_stats = mlx5e_grp_tls_get_num_stats,
1306 .fill_strings = mlx5e_grp_tls_fill_strings,
1307 .fill_stats = mlx5e_grp_tls_fill_stats,
1310 .get_num_stats = mlx5e_grp_channels_get_num_stats,
1311 .fill_strings = mlx5e_grp_channels_fill_strings,
1312 .fill_stats = mlx5e_grp_channels_fill_stats,
1316 const int mlx5e_num_stats_grps = ARRAY_SIZE(mlx5e_stats_grps);