drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/ip.h>
  34 #include <linux/ipv6.h>
  35 #include <linux/tcp.h>
  36 #include <linux/bpf_trace.h>
  37 #include <net/busy_poll.h>
  38 #include "en.h"
  39 #include "en_tc.h"
  40 #include "eswitch.h"
  41
  42 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
  43 {
  44         return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
  45 }
  46
  47 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
  48                                        void *data)
  49 {
  50         u32 ci = cqcc & cq->wq.sz_m1;
  51
  52         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
  53 }
  54
  55 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  56                                          struct mlx5e_cq *cq, u32 cqcc)
  57 {
  58         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
  59         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
  60         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
  61         rq->stats.cqe_compress_blks++;
  62 }
  63
  64 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
  65 {
  66         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
  67         cq->mini_arr_idx = 0;
  68 }
  69
  70 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
  71 {
  72         u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
  73         u32 wq_sz = 1 << cq->wq.log_sz;
  74         u32 ci = cqcc & cq->wq.sz_m1;
  75         u32 ci_top = min_t(u32, wq_sz, ci + n);
  76
  77         for (; ci < ci_top; ci++, n--) {
  78                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  79
  80                 cqe->op_own = op_own;
  81         }
  82
  83         if (unlikely(ci == wq_sz)) {
  84                 op_own = !op_own;
  85                 for (ci = 0; ci < n; ci++) {
  86                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  87
  88                         cqe->op_own = op_own;
  89                 }
  90         }
  91 }
  92
  93 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
  94                                         struct mlx5e_cq *cq, u32 cqcc)
  95 {
  96         u16 wqe_cnt_step;
  97
  98         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
  99         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
 100         cq->title.op_own      &= 0xf0;
 101         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.log_sz);
 102         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
 103
 104         wqe_cnt_step =
 105                 rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 106                 mpwrq_get_cqe_consumed_strides(&cq->title) : 1;
 107         cq->decmprs_wqe_counter =
 108                 (cq->decmprs_wqe_counter + wqe_cnt_step) & rq->wq.sz_m1;
 109 }
 110
 111 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 112                                                 struct mlx5e_cq *cq, u32 cqcc)
 113 {
 114         mlx5e_decompress_cqe(rq, cq, cqcc);
 115         cq->title.rss_hash_type   = 0;
 116         cq->title.rss_hash_result = 0;
 117 }
 118
 119 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 120                                              struct mlx5e_cq *cq,
 121                                              int update_owner_only,
 122                                              int budget_rem)
 123 {
 124         u32 cqcc = cq->wq.cc + update_owner_only;
 125         u32 cqe_count;
 126         u32 i;
 127
 128         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
 129
 130         for (i = update_owner_only; i < cqe_count;
 131              i++, cq->mini_arr_idx++, cqcc++) {
 132                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 133                         mlx5e_read_mini_arr_slot(cq, cqcc);
 134
 135                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
 136                 rq->handle_rx_cqe(rq, &cq->title);
 137         }
 138         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
 139         cq->wq.cc = cqcc;
 140         cq->decmprs_left -= cqe_count;
 141         rq->stats.cqe_compress_pkts += cqe_count;
 142
 143         return cqe_count;
 144 }
 145
 146 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 147                                               struct mlx5e_cq *cq,
 148                                               int budget_rem)
 149 {
 150         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
 151         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
 152         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
 153         rq->handle_rx_cqe(rq, &cq->title);
 154         cq->mini_arr_idx++;
 155
 156         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
 157 }
 158
 159 void mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val)
 160 {
 161         bool was_opened;
 162
 163         if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
 164                 return;
 165
 166         if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) == val)
 167                 return;
 168
 169         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 170         if (was_opened)
 171                 mlx5e_close_locked(priv->netdev);
 172
 173         MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, val);
 174
 175         if (was_opened)
 176                 mlx5e_open_locked(priv->netdev);
 177
 178 }
 179
 180 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
 181
 182 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 183                                       struct mlx5e_dma_info *dma_info)
 184 {
 185         struct mlx5e_page_cache *cache = &rq->page_cache;
 186         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 187
 188         if (tail_next == cache->head) {
 189                 rq->stats.cache_full++;
 190                 return false;
 191         }
 192
 193         if (unlikely(page_is_pfmemalloc(dma_info->page)))
 194                 return false;
 195
 196         cache->page_cache[cache->tail] = *dma_info;
 197         cache->tail = tail_next;
 198         return true;
 199 }
 200
 201 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 202                                       struct mlx5e_dma_info *dma_info)
 203 {
 204         struct mlx5e_page_cache *cache = &rq->page_cache;
 205
 206         if (unlikely(cache->head == cache->tail)) {
 207                 rq->stats.cache_empty++;
 208                 return false;
 209         }
 210
 211         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 212                 rq->stats.cache_busy++;
 213                 return false;
 214         }
 215
 216         *dma_info = cache->page_cache[cache->head];
 217         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 218         rq->stats.cache_reuse++;
 219
 220         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 221                                    RQ_PAGE_SIZE(rq),
 222                                    DMA_FROM_DEVICE);
 223         return true;
 224 }
 225
 226 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
 227                                           struct mlx5e_dma_info *dma_info)
 228 {
 229         struct page *page;
 230
 231         if (mlx5e_rx_cache_get(rq, dma_info))
 232                 return 0;
 233
 234         page = dev_alloc_pages(rq->buff.page_order);
 235         if (unlikely(!page))
 236                 return -ENOMEM;
 237
 238         dma_info->page = page;
 239         dma_info->addr = dma_map_page(rq->pdev, page, 0,
 240                                       RQ_PAGE_SIZE(rq), rq->buff.map_dir);
 241         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 242                 put_page(page);
 243                 return -ENOMEM;
 244         }
 245
 246         return 0;
 247 }
 248
 249 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 250                         bool recycle)
 251 {
 252         if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
 253                 return;
 254
 255         dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
 256                        rq->buff.map_dir);
 257         put_page(dma_info->page);
 258 }
 259
 260 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
 261 {
 262         struct mlx5e_dma_info *di = &rq->dma_info[ix];
 263
 264         if (unlikely(mlx5e_page_alloc_mapped(rq, di)))
 265                 return -ENOMEM;
 266
 267         wqe->data.addr = cpu_to_be64(di->addr + rq->rx_headroom);
 268         return 0;
 269 }
 270
 271 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 272 {
 273         struct mlx5e_dma_info *di = &rq->dma_info[ix];
 274
 275         mlx5e_page_release(rq, di, true);
 276 }
 277
 278 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
 279 {
 280         return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
 281 }
 282
 283 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
 284                                             struct sk_buff *skb,
 285                                             struct mlx5e_mpw_info *wi,
 286                                             u32 page_idx, u32 frag_offset,
 287                                             u32 len)
 288 {
 289         unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz);
 290
 291         dma_sync_single_for_cpu(rq->pdev,
 292                                 wi->umr.dma_info[page_idx].addr + frag_offset,
 293                                 len, DMA_FROM_DEVICE);
 294         wi->skbs_frags[page_idx]++;
 295         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 296                         wi->umr.dma_info[page_idx].page, frag_offset,
 297                         len, truesize);
 298 }
 299
 300 static inline void
 301 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
 302                             struct sk_buff *skb,
 303                             struct mlx5e_mpw_info *wi,
 304                             u32 page_idx, u32 offset,
 305                             u32 headlen)
 306 {
 307         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
 308         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
 309         unsigned int len;
 310
 311          /* Aligning len to sizeof(long) optimizes memcpy performance */
 312         len = ALIGN(headlen_pg, sizeof(long));
 313         dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
 314                                 DMA_FROM_DEVICE);
 315         skb_copy_to_linear_data_offset(skb, 0,
 316                                        page_address(dma_info->page) + offset,
 317                                        len);
 318         if (unlikely(offset + headlen > PAGE_SIZE)) {
 319                 dma_info++;
 320                 headlen_pg = len;
 321                 len = ALIGN(headlen - headlen_pg, sizeof(long));
 322                 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
 323                                         DMA_FROM_DEVICE);
 324                 skb_copy_to_linear_data_offset(skb, headlen_pg,
 325                                                page_address(dma_info->page),
 326                                                len);
 327         }
 328 }
 329
 330 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
 331 {
 332         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 333         struct mlx5e_sq *sq = &rq->channel->icosq;
 334         struct mlx5_wq_cyc *wq = &sq->wq;
 335         struct mlx5e_umr_wqe *wqe;
 336         u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
 337         u16 pi;
 338
 339         /* fill sq edge with nops to avoid wqe wrap around */
 340         while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
 341                 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
 342                 sq->db.ico_wqe[pi].num_wqebbs = 1;
 343                 mlx5e_send_nop(sq, false);
 344         }
 345
 346         wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 347         memcpy(wqe, &wi->umr.wqe, sizeof(*wqe));
 348         wqe->ctrl.opmod_idx_opcode =
 349                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 350                             MLX5_OPCODE_UMR);
 351
 352         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 353         sq->db.ico_wqe[pi].num_wqebbs = num_wqebbs;
 354         sq->pc += num_wqebbs;
 355         mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
 356 }
 357
 358 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq,
 359                                     struct mlx5e_rx_wqe *wqe,
 360                                     u16 ix)
 361 {
 362         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 363         u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, ix) << PAGE_SHIFT;
 364         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
 365         int err;
 366         int i;
 367
 368         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
 369                 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
 370
 371                 err = mlx5e_page_alloc_mapped(rq, dma_info);
 372                 if (unlikely(err))
 373                         goto err_unmap;
 374                 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 375                 page_ref_add(dma_info->page, pg_strides);
 376                 wi->skbs_frags[i] = 0;
 377         }
 378
 379         wi->consumed_strides = 0;
 380         wqe->data.addr = cpu_to_be64(dma_offset);
 381
 382         return 0;
 383
 384 err_unmap:
 385         while (--i >= 0) {
 386                 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
 387
 388                 page_ref_sub(dma_info->page, pg_strides);
 389                 mlx5e_page_release(rq, dma_info, true);
 390         }
 391
 392         return err;
 393 }
 394
 395 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
 396 {
 397         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
 398         int i;
 399
 400         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
 401                 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
 402
 403                 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]);
 404                 mlx5e_page_release(rq, dma_info, true);
 405         }
 406 }
 407
 408 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
 409 {
 410         struct mlx5_wq_ll *wq = &rq->wq;
 411         struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 412
 413         clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
 414
 415         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) {
 416                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 417                 return;
 418         }
 419
 420         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 421
 422         /* ensure wqes are visible to device before updating doorbell record */
 423         dma_wmb();
 424
 425         mlx5_wq_ll_update_db_record(wq);
 426 }
 427
 428 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
 429 {
 430         int err;
 431
 432         err = mlx5e_alloc_rx_umr_mpwqe(rq, wqe, ix);
 433         if (unlikely(err))
 434                 return err;
 435         set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
 436         mlx5e_post_umr_wqe(rq, ix);
 437         return -EBUSY;
 438 }
 439
 440 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 441 {
 442         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 443
 444         mlx5e_free_rx_mpwqe(rq, wi);
 445 }
 446
 447 #define RQ_CANNOT_POST(rq) \
 448         (!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state) || \
 449          test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 450
 451 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 452 {
 453         struct mlx5_wq_ll *wq = &rq->wq;
 454
 455         if (unlikely(RQ_CANNOT_POST(rq)))
 456                 return false;
 457
 458         while (!mlx5_wq_ll_is_full(wq)) {
 459                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 460                 int err;
 461
 462                 err = rq->alloc_wqe(rq, wqe, wq->head);
 463                 if (err == -EBUSY)
 464                         return true;
 465                 if (unlikely(err)) {
 466                         rq->stats.buff_alloc_err++;
 467                         break;
 468                 }
 469
 470                 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 471         }
 472
 473         /* ensure wqes are visible to device before updating doorbell record */
 474         dma_wmb();
 475
 476         mlx5_wq_ll_update_db_record(wq);
 477
 478         return !mlx5_wq_ll_is_full(wq);
 479 }
 480
 481 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 482                                  u32 cqe_bcnt)
 483 {
 484         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 485         struct iphdr    *ipv4;
 486         struct ipv6hdr  *ipv6;
 487         struct tcphdr   *tcp;
 488         int network_depth = 0;
 489         __be16 proto;
 490         u16 tot_len;
 491
 492         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 493         int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA  == l4_hdr_type) ||
 494                        (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type));
 495
 496         skb->mac_len = ETH_HLEN;
 497         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 498
 499         ipv4 = (struct iphdr *)(skb->data + network_depth);
 500         ipv6 = (struct ipv6hdr *)(skb->data + network_depth);
 501         tot_len = cqe_bcnt - network_depth;
 502
 503         if (proto == htons(ETH_P_IP)) {
 504                 tcp = (struct tcphdr *)(skb->data + network_depth +
 505                                         sizeof(struct iphdr));
 506                 ipv6 = NULL;
 507                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 508         } else {
 509                 tcp = (struct tcphdr *)(skb->data + network_depth +
 510                                         sizeof(struct ipv6hdr));
 511                 ipv4 = NULL;
 512                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 513         }
 514
 515         if (get_cqe_lro_tcppsh(cqe))
 516                 tcp->psh                = 1;
 517
 518         if (tcp_ack) {
 519                 tcp->ack                = 1;
 520                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 521                 tcp->window             = cqe->lro_tcp_win;
 522         }
 523
 524         if (ipv4) {
 525                 ipv4->ttl               = cqe->lro_min_ttl;
 526                 ipv4->tot_len           = cpu_to_be16(tot_len);
 527                 ipv4->check             = 0;
 528                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 529                                                        ipv4->ihl);
 530         } else {
 531                 ipv6->hop_limit         = cqe->lro_min_ttl;
 532                 ipv6->payload_len       = cpu_to_be16(tot_len -
 533                                                       sizeof(struct ipv6hdr));
 534         }
 535 }
 536
 537 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 538                                       struct sk_buff *skb)
 539 {
 540         u8 cht = cqe->rss_hash_type;
 541         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 542                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 543                                             PKT_HASH_TYPE_NONE;
 544         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 545 }
 546
 547 static inline bool is_first_ethertype_ip(struct sk_buff *skb)
 548 {
 549         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
 550
 551         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
 552 }
 553
 554 static inline void mlx5e_handle_csum(struct net_device *netdev,
 555                                      struct mlx5_cqe64 *cqe,
 556                                      struct mlx5e_rq *rq,
 557                                      struct sk_buff *skb,
 558                                      bool   lro)
 559 {
 560         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 561                 goto csum_none;
 562
 563         if (lro) {
 564                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 565                 return;
 566         }
 567
 568         if (is_first_ethertype_ip(skb)) {
 569                 skb->ip_summed = CHECKSUM_COMPLETE;
 570                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 571                 rq->stats.csum_complete++;
 572                 return;
 573         }
 574
 575         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 576                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 577                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 578                 if (cqe_is_tunneled(cqe)) {
 579                         skb->csum_level = 1;
 580                         skb->encapsulation = 1;
 581                         rq->stats.csum_unnecessary_inner++;
 582                 }
 583                 return;
 584         }
 585 csum_none:
 586         skb->ip_summed = CHECKSUM_NONE;
 587         rq->stats.csum_none++;
 588 }
 589
 590 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 591                                       u32 cqe_bcnt,
 592                                       struct mlx5e_rq *rq,
 593                                       struct sk_buff *skb)
 594 {
 595         struct net_device *netdev = rq->netdev;
 596         struct mlx5e_tstamp *tstamp = rq->tstamp;
 597         int lro_num_seg;
 598
 599         lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 600         if (lro_num_seg > 1) {
 601                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 602                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 603                 rq->stats.lro_packets++;
 604                 rq->stats.lro_bytes += cqe_bcnt;
 605         }
 606
 607         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
 608                 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
 609
 610         skb_record_rx_queue(skb, rq->ix);
 611
 612         if (likely(netdev->features & NETIF_F_RXHASH))
 613                 mlx5e_skb_set_hash(cqe, skb);
 614
 615         if (cqe_has_vlan(cqe))
 616                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 617                                        be16_to_cpu(cqe->vlan_info));
 618
 619         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 620
 621         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 622         skb->protocol = eth_type_trans(skb, netdev);
 623 }
 624
 625 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 626                                          struct mlx5_cqe64 *cqe,
 627                                          u32 cqe_bcnt,
 628                                          struct sk_buff *skb)
 629 {
 630         rq->stats.packets++;
 631         rq->stats.bytes += cqe_bcnt;
 632         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 633 }
 634
 635 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_sq *sq)
 636 {
 637         struct mlx5_wq_cyc *wq = &sq->wq;
 638         struct mlx5e_tx_wqe *wqe;
 639         u16 pi = (sq->pc - MLX5E_XDP_TX_WQEBBS) & wq->sz_m1; /* last pi */
 640
 641         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 642
 643         wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
 644         mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
 645 }
 646
 647 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
 648                                         struct mlx5e_dma_info *di,
 649                                         const struct xdp_buff *xdp)
 650 {
 651         struct mlx5e_sq          *sq   = &rq->channel->xdp_sq;
 652         struct mlx5_wq_cyc       *wq   = &sq->wq;
 653         u16                      pi    = sq->pc & wq->sz_m1;
 654         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 655         struct mlx5e_sq_wqe_info *wi   = &sq->db.xdp.wqe_info[pi];
 656
 657         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
 658         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
 659         struct mlx5_wqe_data_seg *dseg;
 660
 661         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
 662         dma_addr_t dma_addr  = di->addr + data_offset + MLX5E_XDP_MIN_INLINE;
 663         unsigned int dma_len = xdp->data_end - xdp->data;
 664
 665         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE ||
 666                      MLX5E_SW2HW_MTU(rq->netdev->mtu) < dma_len)) {
 667                 rq->stats.xdp_drop++;
 668                 mlx5e_page_release(rq, di, true);
 669                 return false;
 670         }
 671
 672         if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_XDP_TX_WQEBBS))) {
 673                 if (sq->db.xdp.doorbell) {
 674                         /* SQ is full, ring doorbell */
 675                         mlx5e_xmit_xdp_doorbell(sq);
 676                         sq->db.xdp.doorbell = false;
 677                 }
 678                 rq->stats.xdp_tx_full++;
 679                 mlx5e_page_release(rq, di, true);
 680                 return false;
 681         }
 682
 683         dma_len -= MLX5E_XDP_MIN_INLINE;
 684         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len,
 685                                    PCI_DMA_TODEVICE);
 686
 687         memset(wqe, 0, sizeof(*wqe));
 688
 689         /* copy the inline part */
 690         memcpy(eseg->inline_hdr_start, xdp->data, MLX5E_XDP_MIN_INLINE);
 691         eseg->inline_hdr_sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
 692
 693         dseg = (struct mlx5_wqe_data_seg *)cseg + (MLX5E_XDP_TX_DS_COUNT - 1);
 694
 695         /* write the dma part */
 696         dseg->addr       = cpu_to_be64(dma_addr);
 697         dseg->byte_count = cpu_to_be32(dma_len);
 698         dseg->lkey       = sq->mkey_be;
 699
 700         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
 701         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | MLX5E_XDP_TX_DS_COUNT);
 702
 703         sq->db.xdp.di[pi] = *di;
 704         wi->opcode     = MLX5_OPCODE_SEND;
 705         wi->num_wqebbs = MLX5E_XDP_TX_WQEBBS;
 706         sq->pc += MLX5E_XDP_TX_WQEBBS;
 707
 708         sq->db.xdp.doorbell = true;
 709         rq->stats.xdp_tx++;
 710         return true;
 711 }
 712
 713 /* returns true if packet was consumed by xdp */
 714 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq,
 715                                    struct mlx5e_dma_info *di,
 716                                    void *va, u16 *rx_headroom, u32 *len)
 717 {
 718         const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
 719         struct xdp_buff xdp;
 720         u32 act;
 721
 722         if (!prog)
 723                 return false;
 724
 725         xdp.data = va + *rx_headroom;
 726         xdp.data_end = xdp.data + *len;
 727         xdp.data_hard_start = va;
 728
 729         act = bpf_prog_run_xdp(prog, &xdp);
 730         switch (act) {
 731         case XDP_PASS:
 732                 *rx_headroom = xdp.data - xdp.data_hard_start;
 733                 *len = xdp.data_end - xdp.data;
 734                 return false;
 735         case XDP_TX:
 736                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
 737                         trace_xdp_exception(rq->netdev, prog, act);
 738                 return true;
 739         default:
 740                 bpf_warn_invalid_xdp_action(act);
 741         case XDP_ABORTED:
 742                 trace_xdp_exception(rq->netdev, prog, act);
 743         case XDP_DROP:
 744                 rq->stats.xdp_drop++;
 745                 mlx5e_page_release(rq, di, true);
 746                 return true;
 747         }
 748 }
 749
 750 static inline
 751 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 752                              u16 wqe_counter, u32 cqe_bcnt)
 753 {
 754         struct mlx5e_dma_info *di;
 755         struct sk_buff *skb;
 756         void *va, *data;
 757         u16 rx_headroom = rq->rx_headroom;
 758         bool consumed;
 759
 760         di             = &rq->dma_info[wqe_counter];
 761         va             = page_address(di->page);
 762         data           = va + rx_headroom;
 763
 764         dma_sync_single_range_for_cpu(rq->pdev,
 765                                       di->addr,
 766                                       rx_headroom,
 767                                       rq->buff.wqe_sz,
 768                                       DMA_FROM_DEVICE);
 769         prefetch(data);
 770
 771         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 772                 rq->stats.wqe_err++;
 773                 mlx5e_page_release(rq, di, true);
 774                 return NULL;
 775         }
 776
 777         rcu_read_lock();
 778         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
 779         rcu_read_unlock();
 780         if (consumed)
 781                 return NULL; /* page/packet was consumed by XDP */
 782
 783         skb = build_skb(va, RQ_PAGE_SIZE(rq));
 784         if (unlikely(!skb)) {
 785                 rq->stats.buff_alloc_err++;
 786                 mlx5e_page_release(rq, di, true);
 787                 return NULL;
 788         }
 789
 790         /* queue up for recycling ..*/
 791         page_ref_inc(di->page);
 792         mlx5e_page_release(rq, di, true);
 793
 794         skb_reserve(skb, rx_headroom);
 795         skb_put(skb, cqe_bcnt);
 796
 797         return skb;
 798 }
 799
 800 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 801 {
 802         struct mlx5e_rx_wqe *wqe;
 803         __be16 wqe_counter_be;
 804         struct sk_buff *skb;
 805         u16 wqe_counter;
 806         u32 cqe_bcnt;
 807
 808         wqe_counter_be = cqe->wqe_counter;
 809         wqe_counter    = be16_to_cpu(wqe_counter_be);
 810         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 811         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 812
 813         skb = skb_from_cqe(rq, cqe, wqe_counter, cqe_bcnt);
 814         if (!skb)
 815                 goto wq_ll_pop;
 816
 817         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 818         napi_gro_receive(rq->cq.napi, skb);
 819
 820 wq_ll_pop:
 821         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 822                        &wqe->next.next_wqe_index);
 823 }
 824
 825 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 826 {
 827         struct net_device *netdev = rq->netdev;
 828         struct mlx5e_priv *priv = netdev_priv(netdev);
 829         struct mlx5_eswitch_rep *rep = priv->ppriv;
 830         struct mlx5e_rx_wqe *wqe;
 831         struct sk_buff *skb;
 832         __be16 wqe_counter_be;
 833         u16 wqe_counter;
 834         u32 cqe_bcnt;
 835
 836         wqe_counter_be = cqe->wqe_counter;
 837         wqe_counter    = be16_to_cpu(wqe_counter_be);
 838         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 839         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 840
 841         skb = skb_from_cqe(rq, cqe, wqe_counter, cqe_bcnt);
 842         if (!skb)
 843                 goto wq_ll_pop;
 844
 845         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 846
 847         if (rep->vlan && skb_vlan_tag_present(skb))
 848                 skb_vlan_pop(skb);
 849
 850         napi_gro_receive(rq->cq.napi, skb);
 851
 852 wq_ll_pop:
 853         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 854                        &wqe->next.next_wqe_index);
 855 }
 856
 857 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
 858                                            struct mlx5_cqe64 *cqe,
 859                                            struct mlx5e_mpw_info *wi,
 860                                            u32 cqe_bcnt,
 861                                            struct sk_buff *skb)
 862 {
 863         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
 864         u32 wqe_offset     = stride_ix * rq->mpwqe_stride_sz;
 865         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
 866         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
 867         u32 head_page_idx  = page_idx;
 868         u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
 869         u32 frag_offset    = head_offset + headlen;
 870         u16 byte_cnt       = cqe_bcnt - headlen;
 871
 872         if (unlikely(frag_offset >= PAGE_SIZE)) {
 873                 page_idx++;
 874                 frag_offset -= PAGE_SIZE;
 875         }
 876
 877         while (byte_cnt) {
 878                 u32 pg_consumed_bytes =
 879                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
 880
 881                 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
 882                                          pg_consumed_bytes);
 883                 byte_cnt -= pg_consumed_bytes;
 884                 frag_offset = 0;
 885                 page_idx++;
 886         }
 887         /* copy header */
 888         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
 889                                     head_offset, headlen);
 890         /* skb linear part was allocated with headlen and aligned to long */
 891         skb->tail += headlen;
 892         skb->len  += headlen;
 893 }
 894
 895 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 896 {
 897         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
 898         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
 899         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
 900         struct mlx5e_rx_wqe  *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
 901         struct sk_buff *skb;
 902         u16 cqe_bcnt;
 903
 904         wi->consumed_strides += cstrides;
 905
 906         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 907                 rq->stats.wqe_err++;
 908                 goto mpwrq_cqe_out;
 909         }
 910
 911         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
 912                 rq->stats.mpwqe_filler++;
 913                 goto mpwrq_cqe_out;
 914         }
 915
 916         skb = napi_alloc_skb(rq->cq.napi,
 917                              ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
 918                                    sizeof(long)));
 919         if (unlikely(!skb)) {
 920                 rq->stats.buff_alloc_err++;
 921                 goto mpwrq_cqe_out;
 922         }
 923
 924         prefetch(skb->data);
 925         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
 926
 927         mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
 928         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 929         napi_gro_receive(rq->cq.napi, skb);
 930
 931 mpwrq_cqe_out:
 932         if (likely(wi->consumed_strides < rq->mpwqe_num_strides))
 933                 return;
 934
 935         mlx5e_free_rx_mpwqe(rq, wi);
 936         mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
 937 }
 938
 939 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
 940 {
 941         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
 942         struct mlx5e_sq *xdp_sq = &rq->channel->xdp_sq;
 943         int work_done = 0;
 944
 945         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 946                 return 0;
 947
 948         if (cq->decmprs_left)
 949                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
 950
 951         for (; work_done < budget; work_done++) {
 952                 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq);
 953
 954                 if (!cqe)
 955                         break;
 956
 957                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
 958                         work_done +=
 959                                 mlx5e_decompress_cqes_start(rq, cq,
 960                                                             budget - work_done);
 961                         continue;
 962                 }
 963
 964                 mlx5_cqwq_pop(&cq->wq);
 965
 966                 rq->handle_rx_cqe(rq, cqe);
 967         }
 968
 969         if (xdp_sq->db.xdp.doorbell) {
 970                 mlx5e_xmit_xdp_doorbell(xdp_sq);
 971                 xdp_sq->db.xdp.doorbell = false;
 972         }
 973
 974         mlx5_cqwq_update_db_record(&cq->wq);
 975
 976         /* ensure cq space is freed before enabling more cqes */
 977         wmb();
 978
 979         return work_done;
 980 }