drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <linux/bpf_trace.h>
  38 #include <net/busy_poll.h>
  39 #include <net/ip6_checksum.h>
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "eswitch.h"
  43 #include "en_rep.h"
  44 #include "ipoib/ipoib.h"
  45 #include "en_accel/ipsec_rxtx.h"
  46 #include "lib/clock.h"
  47
  48 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  49 {
  50         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  51 }
  52
  53 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
  54                                        void *data)
  55 {
  56         u32 ci = cqcc & cq->wq.sz_m1;
  57
  58         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
  59 }
  60
  61 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  62                                          struct mlx5e_cq *cq, u32 cqcc)
  63 {
  64         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
  65         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
  66         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
  67         rq->stats.cqe_compress_blks++;
  68 }
  69
  70 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
  71 {
  72         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
  73         cq->mini_arr_idx = 0;
  74 }
  75
  76 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
  77 {
  78         u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
  79         u32 wq_sz = 1 << cq->wq.log_sz;
  80         u32 ci = cqcc & cq->wq.sz_m1;
  81         u32 ci_top = min_t(u32, wq_sz, ci + n);
  82
  83         for (; ci < ci_top; ci++, n--) {
  84                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  85
  86                 cqe->op_own = op_own;
  87         }
  88
  89         if (unlikely(ci == wq_sz)) {
  90                 op_own = !op_own;
  91                 for (ci = 0; ci < n; ci++) {
  92                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  93
  94                         cqe->op_own = op_own;
  95                 }
  96         }
  97 }
  98
  99 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 100                                         struct mlx5e_cq *cq, u32 cqcc)
 101 {
 102         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
 103         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
 104         cq->title.op_own      &= 0xf0;
 105         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.log_sz);
 106         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
 107
 108         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 109                 cq->decmprs_wqe_counter +=
 110                         mpwrq_get_cqe_consumed_strides(&cq->title);
 111         else
 112                 cq->decmprs_wqe_counter =
 113                         (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1;
 114 }
 115
 116 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 117                                                 struct mlx5e_cq *cq, u32 cqcc)
 118 {
 119         mlx5e_decompress_cqe(rq, cq, cqcc);
 120         cq->title.rss_hash_type   = 0;
 121         cq->title.rss_hash_result = 0;
 122 }
 123
 124 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 125                                              struct mlx5e_cq *cq,
 126                                              int update_owner_only,
 127                                              int budget_rem)
 128 {
 129         u32 cqcc = cq->wq.cc + update_owner_only;
 130         u32 cqe_count;
 131         u32 i;
 132
 133         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
 134
 135         for (i = update_owner_only; i < cqe_count;
 136              i++, cq->mini_arr_idx++, cqcc++) {
 137                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 138                         mlx5e_read_mini_arr_slot(cq, cqcc);
 139
 140                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
 141                 rq->handle_rx_cqe(rq, &cq->title);
 142         }
 143         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
 144         cq->wq.cc = cqcc;
 145         cq->decmprs_left -= cqe_count;
 146         rq->stats.cqe_compress_pkts += cqe_count;
 147
 148         return cqe_count;
 149 }
 150
 151 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 152                                               struct mlx5e_cq *cq,
 153                                               int budget_rem)
 154 {
 155         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
 156         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
 157         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
 158         rq->handle_rx_cqe(rq, &cq->title);
 159         cq->mini_arr_idx++;
 160
 161         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
 162 }
 163
 164 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
 165
 166 static inline bool mlx5e_page_is_reserved(struct page *page)
 167 {
 168         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 169 }
 170
 171 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 172                                       struct mlx5e_dma_info *dma_info)
 173 {
 174         struct mlx5e_page_cache *cache = &rq->page_cache;
 175         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 176
 177         if (tail_next == cache->head) {
 178                 rq->stats.cache_full++;
 179                 return false;
 180         }
 181
 182         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 183                 rq->stats.cache_waive++;
 184                 return false;
 185         }
 186
 187         cache->page_cache[cache->tail] = *dma_info;
 188         cache->tail = tail_next;
 189         return true;
 190 }
 191
 192 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 193                                       struct mlx5e_dma_info *dma_info)
 194 {
 195         struct mlx5e_page_cache *cache = &rq->page_cache;
 196
 197         if (unlikely(cache->head == cache->tail)) {
 198                 rq->stats.cache_empty++;
 199                 return false;
 200         }
 201
 202         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 203                 rq->stats.cache_busy++;
 204                 return false;
 205         }
 206
 207         *dma_info = cache->page_cache[cache->head];
 208         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 209         rq->stats.cache_reuse++;
 210
 211         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 212                                    RQ_PAGE_SIZE(rq),
 213                                    DMA_FROM_DEVICE);
 214         return true;
 215 }
 216
 217 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
 218                                           struct mlx5e_dma_info *dma_info)
 219 {
 220         if (mlx5e_rx_cache_get(rq, dma_info))
 221                 return 0;
 222
 223         dma_info->page = dev_alloc_pages(rq->buff.page_order);
 224         if (unlikely(!dma_info->page))
 225                 return -ENOMEM;
 226
 227         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 228                                       RQ_PAGE_SIZE(rq), rq->buff.map_dir);
 229         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 230                 put_page(dma_info->page);
 231                 dma_info->page = NULL;
 232                 return -ENOMEM;
 233         }
 234
 235         return 0;
 236 }
 237
 238 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 239                         bool recycle)
 240 {
 241         if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
 242                 return;
 243
 244         dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
 245                        rq->buff.map_dir);
 246         put_page(dma_info->page);
 247 }
 248
 249 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,
 250                                     struct mlx5e_wqe_frag_info *wi)
 251 {
 252         return rq->wqe.page_reuse && wi->di.page &&
 253                 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) &&
 254                 !mlx5e_page_is_reserved(wi->di.page);
 255 }
 256
 257 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
 258 {
 259         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 260
 261         /* check if page exists, hence can be reused */
 262         if (!wi->di.page) {
 263                 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di)))
 264                         return -ENOMEM;
 265                 wi->offset = 0;
 266         }
 267
 268         wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom);
 269         return 0;
 270 }
 271
 272 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 273                                      struct mlx5e_wqe_frag_info *wi)
 274 {
 275         mlx5e_page_release(rq, &wi->di, true);
 276         wi->di.page = NULL;
 277 }
 278
 279 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq,
 280                                            struct mlx5e_wqe_frag_info *wi)
 281 {
 282         if (mlx5e_page_reuse(rq, wi)) {
 283                 rq->stats.page_reuse++;
 284                 return;
 285         }
 286
 287         mlx5e_free_rx_wqe(rq, wi);
 288 }
 289
 290 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 291 {
 292         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 293
 294         if (wi->di.page)
 295                 mlx5e_free_rx_wqe(rq, wi);
 296 }
 297
 298 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
 299 {
 300         return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
 301 }
 302
 303 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
 304                                             struct sk_buff *skb,
 305                                             struct mlx5e_mpw_info *wi,
 306                                             u32 page_idx, u32 frag_offset,
 307                                             u32 len)
 308 {
 309         unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz));
 310
 311         dma_sync_single_for_cpu(rq->pdev,
 312                                 wi->umr.dma_info[page_idx].addr + frag_offset,
 313                                 len, DMA_FROM_DEVICE);
 314         wi->skbs_frags[page_idx]++;
 315         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 316                         wi->umr.dma_info[page_idx].page, frag_offset,
 317                         len, truesize);
 318 }
 319
 320 static inline void
 321 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
 322                             struct sk_buff *skb,
 323                             struct mlx5e_mpw_info *wi,
 324                             u32 page_idx, u32 offset,
 325                             u32 headlen)
 326 {
 327         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
 328         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
 329         unsigned int len;
 330
 331          /* Aligning len to sizeof(long) optimizes memcpy performance */
 332         len = ALIGN(headlen_pg, sizeof(long));
 333         dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
 334                                 DMA_FROM_DEVICE);
 335         skb_copy_to_linear_data_offset(skb, 0,
 336                                        page_address(dma_info->page) + offset,
 337                                        len);
 338         if (unlikely(offset + headlen > PAGE_SIZE)) {
 339                 dma_info++;
 340                 headlen_pg = len;
 341                 len = ALIGN(headlen - headlen_pg, sizeof(long));
 342                 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
 343                                         DMA_FROM_DEVICE);
 344                 skb_copy_to_linear_data_offset(skb, headlen_pg,
 345                                                page_address(dma_info->page),
 346                                                len);
 347         }
 348 }
 349
 350 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
 351 {
 352         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 353         struct mlx5e_icosq *sq = &rq->channel->icosq;
 354         struct mlx5_wq_cyc *wq = &sq->wq;
 355         struct mlx5e_umr_wqe *wqe;
 356         u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
 357         u16 pi;
 358
 359         /* fill sq edge with nops to avoid wqe wrap around */
 360         while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
 361                 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
 362                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 363         }
 364
 365         wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 366         memcpy(wqe, &wi->umr.wqe, sizeof(*wqe));
 367         wqe->ctrl.opmod_idx_opcode =
 368                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 369                             MLX5_OPCODE_UMR);
 370
 371         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 372         sq->pc += num_wqebbs;
 373         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl);
 374 }
 375
 376 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq,
 377                                     u16 ix)
 378 {
 379         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 380         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
 381         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 382         int err;
 383         int i;
 384
 385         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 386                 err = mlx5e_page_alloc_mapped(rq, dma_info);
 387                 if (unlikely(err))
 388                         goto err_unmap;
 389                 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 390                 page_ref_add(dma_info->page, pg_strides);
 391         }
 392
 393         memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE);
 394         wi->consumed_strides = 0;
 395
 396         return 0;
 397
 398 err_unmap:
 399         while (--i >= 0) {
 400                 dma_info--;
 401                 page_ref_sub(dma_info->page, pg_strides);
 402                 mlx5e_page_release(rq, dma_info, true);
 403         }
 404
 405         return err;
 406 }
 407
 408 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
 409 {
 410         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
 411         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 412         int i;
 413
 414         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 415                 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]);
 416                 mlx5e_page_release(rq, dma_info, true);
 417         }
 418 }
 419
 420 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
 421 {
 422         struct mlx5_wq_ll *wq = &rq->wq;
 423         struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 424
 425         rq->mpwqe.umr_in_progress = false;
 426
 427         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 428
 429         /* ensure wqes are visible to device before updating doorbell record */
 430         dma_wmb();
 431
 432         mlx5_wq_ll_update_db_record(wq);
 433 }
 434
 435 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 436 {
 437         int err;
 438
 439         err = mlx5e_alloc_rx_umr_mpwqe(rq, ix);
 440         if (unlikely(err)) {
 441                 rq->stats.buff_alloc_err++;
 442                 return err;
 443         }
 444         rq->mpwqe.umr_in_progress = true;
 445         mlx5e_post_umr_wqe(rq, ix);
 446         return 0;
 447 }
 448
 449 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 450 {
 451         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 452
 453         mlx5e_free_rx_mpwqe(rq, wi);
 454 }
 455
 456 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 457 {
 458         struct mlx5_wq_ll *wq = &rq->wq;
 459         int err;
 460
 461         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
 462                 return false;
 463
 464         if (mlx5_wq_ll_is_full(wq))
 465                 return false;
 466
 467         do {
 468                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 469
 470                 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head);
 471                 if (unlikely(err)) {
 472                         rq->stats.buff_alloc_err++;
 473                         break;
 474                 }
 475
 476                 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 477         } while (!mlx5_wq_ll_is_full(wq));
 478
 479         /* ensure wqes are visible to device before updating doorbell record */
 480         dma_wmb();
 481
 482         mlx5_wq_ll_update_db_record(wq);
 483
 484         return !!err;
 485 }
 486
 487 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
 488                                              struct mlx5e_icosq *sq,
 489                                              struct mlx5e_rq *rq,
 490                                              struct mlx5_cqe64 *cqe)
 491 {
 492         struct mlx5_wq_cyc *wq = &sq->wq;
 493         u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;
 494         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
 495
 496         mlx5_cqwq_pop(&cq->wq);
 497
 498         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
 499                 netdev_WARN_ONCE(cq->channel->netdev,
 500                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
 501                 return;
 502         }
 503
 504         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
 505                 mlx5e_post_rx_mpwqe(rq);
 506                 return;
 507         }
 508
 509         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
 510                 netdev_WARN_ONCE(cq->channel->netdev,
 511                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
 512 }
 513
 514 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
 515 {
 516         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 517         struct mlx5_cqe64 *cqe;
 518
 519         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
 520                 return;
 521
 522         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 523         if (likely(!cqe))
 524                 return;
 525
 526         /* by design, there's only a single cqe */
 527         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
 528
 529         mlx5_cqwq_update_db_record(&cq->wq);
 530 }
 531
 532 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 533 {
 534         struct mlx5_wq_ll *wq = &rq->wq;
 535
 536         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
 537                 return false;
 538
 539         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
 540
 541         if (mlx5_wq_ll_is_full(wq))
 542                 return false;
 543
 544         if (!rq->mpwqe.umr_in_progress)
 545                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
 546
 547         return true;
 548 }
 549
 550 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 551 {
 552         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 553         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 554                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 555
 556         tcp->check                      = 0;
 557         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 558
 559         if (tcp_ack) {
 560                 tcp->ack                = 1;
 561                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 562                 tcp->window             = cqe->lro_tcp_win;
 563         }
 564 }
 565
 566 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 567                                  u32 cqe_bcnt)
 568 {
 569         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 570         struct tcphdr   *tcp;
 571         int network_depth = 0;
 572         __wsum check;
 573         __be16 proto;
 574         u16 tot_len;
 575         void *ip_p;
 576
 577         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 578
 579         tot_len = cqe_bcnt - network_depth;
 580         ip_p = skb->data + network_depth;
 581
 582         if (proto == htons(ETH_P_IP)) {
 583                 struct iphdr *ipv4 = ip_p;
 584
 585                 tcp = ip_p + sizeof(struct iphdr);
 586                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 587
 588                 ipv4->ttl               = cqe->lro_min_ttl;
 589                 ipv4->tot_len           = cpu_to_be16(tot_len);
 590                 ipv4->check             = 0;
 591                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 592                                                        ipv4->ihl);
 593
 594                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 595                 check = csum_partial(tcp, tcp->doff * 4,
 596                                      csum_unfold((__force __sum16)cqe->check_sum));
 597                 /* Almost done, don't forget the pseudo header */
 598                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 599                                                tot_len - sizeof(struct iphdr),
 600                                                IPPROTO_TCP, check);
 601         } else {
 602                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 603                 struct ipv6hdr *ipv6 = ip_p;
 604
 605                 tcp = ip_p + sizeof(struct ipv6hdr);
 606                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 607
 608                 ipv6->hop_limit         = cqe->lro_min_ttl;
 609                 ipv6->payload_len       = cpu_to_be16(payload_len);
 610
 611                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 612                 check = csum_partial(tcp, tcp->doff * 4,
 613                                      csum_unfold((__force __sum16)cqe->check_sum));
 614                 /* Almost done, don't forget the pseudo header */
 615                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 616                                              IPPROTO_TCP, check);
 617         }
 618 }
 619
 620 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 621                                       struct sk_buff *skb)
 622 {
 623         u8 cht = cqe->rss_hash_type;
 624         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 625                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 626                                             PKT_HASH_TYPE_NONE;
 627         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 628 }
 629
 630 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
 631 {
 632         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
 633
 634         ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
 635         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
 636 }
 637
 638 static inline void mlx5e_handle_csum(struct net_device *netdev,
 639                                      struct mlx5_cqe64 *cqe,
 640                                      struct mlx5e_rq *rq,
 641                                      struct sk_buff *skb,
 642                                      bool   lro)
 643 {
 644         int network_depth = 0;
 645
 646         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 647                 goto csum_none;
 648
 649         if (lro) {
 650                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 651                 rq->stats.csum_unnecessary++;
 652                 return;
 653         }
 654
 655         if (likely(is_last_ethertype_ip(skb, &network_depth))) {
 656                 skb->ip_summed = CHECKSUM_COMPLETE;
 657                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 658                 if (network_depth > ETH_HLEN)
 659                         /* CQE csum is calculated from the IP header and does
 660                          * not cover VLAN headers (if present). This will add
 661                          * the checksum manually.
 662                          */
 663                         skb->csum = csum_partial(skb->data + ETH_HLEN,
 664                                                  network_depth - ETH_HLEN,
 665                                                  skb->csum);
 666                 rq->stats.csum_complete++;
 667                 return;
 668         }
 669
 670         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 671                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 672                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 673                 if (cqe_is_tunneled(cqe)) {
 674                         skb->csum_level = 1;
 675                         skb->encapsulation = 1;
 676                         rq->stats.csum_unnecessary_inner++;
 677                         return;
 678                 }
 679                 rq->stats.csum_unnecessary++;
 680                 return;
 681         }
 682 csum_none:
 683         skb->ip_summed = CHECKSUM_NONE;
 684         rq->stats.csum_none++;
 685 }
 686
 687 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 688                                       u32 cqe_bcnt,
 689                                       struct mlx5e_rq *rq,
 690                                       struct sk_buff *skb)
 691 {
 692         struct net_device *netdev = rq->netdev;
 693         int lro_num_seg;
 694
 695         skb->mac_len = ETH_HLEN;
 696         lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 697         if (lro_num_seg > 1) {
 698                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 699                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 700                 /* Subtract one since we already counted this as one
 701                  * "regular" packet in mlx5e_complete_rx_cqe()
 702                  */
 703                 rq->stats.packets += lro_num_seg - 1;
 704                 rq->stats.lro_packets++;
 705                 rq->stats.lro_bytes += cqe_bcnt;
 706         }
 707
 708         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
 709                 skb_hwtstamps(skb)->hwtstamp =
 710                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
 711
 712         skb_record_rx_queue(skb, rq->ix);
 713
 714         if (likely(netdev->features & NETIF_F_RXHASH))
 715                 mlx5e_skb_set_hash(cqe, skb);
 716
 717         if (cqe_has_vlan(cqe)) {
 718                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 719                                        be16_to_cpu(cqe->vlan_info));
 720                 rq->stats.removed_vlan_packets++;
 721         }
 722
 723         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 724
 725         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 726         skb->protocol = eth_type_trans(skb, netdev);
 727 }
 728
 729 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 730                                          struct mlx5_cqe64 *cqe,
 731                                          u32 cqe_bcnt,
 732                                          struct sk_buff *skb)
 733 {
 734         rq->stats.packets++;
 735         rq->stats.bytes += cqe_bcnt;
 736         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 737 }
 738
 739 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
 740 {
 741         struct mlx5_wq_cyc *wq = &sq->wq;
 742         struct mlx5e_tx_wqe *wqe;
 743         u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */
 744
 745         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 746
 747         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
 748 }
 749
 750 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
 751                                         struct mlx5e_dma_info *di,
 752                                         const struct xdp_buff *xdp)
 753 {
 754         struct mlx5e_xdpsq       *sq   = &rq->xdpsq;
 755         struct mlx5_wq_cyc       *wq   = &sq->wq;
 756         u16                       pi   = sq->pc & wq->sz_m1;
 757         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 758
 759         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
 760         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
 761         struct mlx5_wqe_data_seg *dseg;
 762
 763         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
 764         dma_addr_t dma_addr  = di->addr + data_offset;
 765         unsigned int dma_len = xdp->data_end - xdp->data;
 766
 767         prefetchw(wqe);
 768
 769         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE ||
 770                      MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) {
 771                 rq->stats.xdp_drop++;
 772                 return false;
 773         }
 774
 775         if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
 776                 if (sq->db.doorbell) {
 777                         /* SQ is full, ring doorbell */
 778                         mlx5e_xmit_xdp_doorbell(sq);
 779                         sq->db.doorbell = false;
 780                 }
 781                 rq->stats.xdp_tx_full++;
 782                 return false;
 783         }
 784
 785         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
 786
 787         cseg->fm_ce_se = 0;
 788
 789         dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
 790
 791         /* copy the inline part if required */
 792         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
 793                 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
 794                 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
 795                 dma_len  -= MLX5E_XDP_MIN_INLINE;
 796                 dma_addr += MLX5E_XDP_MIN_INLINE;
 797                 dseg++;
 798         }
 799
 800         /* write the dma part */
 801         dseg->addr       = cpu_to_be64(dma_addr);
 802         dseg->byte_count = cpu_to_be32(dma_len);
 803
 804         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
 805
 806         /* move page to reference to sq responsibility,
 807          * and mark so it's not put back in page-cache.
 808          */
 809         rq->wqe.xdp_xmit = true;
 810         sq->db.di[pi] = *di;
 811         sq->pc++;
 812
 813         sq->db.doorbell = true;
 814
 815         rq->stats.xdp_tx++;
 816         return true;
 817 }
 818
 819 /* returns true if packet was consumed by xdp */
 820 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq,
 821                                    struct mlx5e_dma_info *di,
 822                                    void *va, u16 *rx_headroom, u32 *len)
 823 {
 824         const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
 825         struct xdp_buff xdp;
 826         u32 act;
 827
 828         if (!prog)
 829                 return false;
 830
 831         xdp.data = va + *rx_headroom;
 832         xdp_set_data_meta_invalid(&xdp);
 833         xdp.data_end = xdp.data + *len;
 834         xdp.data_hard_start = va;
 835         xdp.rxq = &rq->xdp_rxq;
 836
 837         act = bpf_prog_run_xdp(prog, &xdp);
 838         switch (act) {
 839         case XDP_PASS:
 840                 *rx_headroom = xdp.data - xdp.data_hard_start;
 841                 *len = xdp.data_end - xdp.data;
 842                 return false;
 843         case XDP_TX:
 844                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
 845                         trace_xdp_exception(rq->netdev, prog, act);
 846                 return true;
 847         default:
 848                 bpf_warn_invalid_xdp_action(act);
 849         case XDP_ABORTED:
 850                 trace_xdp_exception(rq->netdev, prog, act);
 851         case XDP_DROP:
 852                 rq->stats.xdp_drop++;
 853                 return true;
 854         }
 855 }
 856
 857 static inline
 858 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 859                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 860 {
 861         struct mlx5e_dma_info *di = &wi->di;
 862         u16 rx_headroom = rq->buff.headroom;
 863         struct sk_buff *skb;
 864         void *va, *data;
 865         bool consumed;
 866         u32 frag_size;
 867
 868         va             = page_address(di->page) + wi->offset;
 869         data           = va + rx_headroom;
 870         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
 871
 872         dma_sync_single_range_for_cpu(rq->pdev,
 873                                       di->addr + wi->offset,
 874                                       0, frag_size,
 875                                       DMA_FROM_DEVICE);
 876         prefetch(data);
 877         wi->offset += frag_size;
 878
 879         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 880                 rq->stats.wqe_err++;
 881                 return NULL;
 882         }
 883
 884         rcu_read_lock();
 885         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
 886         rcu_read_unlock();
 887         if (consumed)
 888                 return NULL; /* page/packet was consumed by XDP */
 889
 890         skb = build_skb(va, frag_size);
 891         if (unlikely(!skb)) {
 892                 rq->stats.buff_alloc_err++;
 893                 return NULL;
 894         }
 895
 896         /* queue up for recycling/reuse */
 897         page_ref_inc(di->page);
 898
 899         skb_reserve(skb, rx_headroom);
 900         skb_put(skb, cqe_bcnt);
 901
 902         return skb;
 903 }
 904
 905 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 906 {
 907         struct mlx5e_wqe_frag_info *wi;
 908         struct mlx5e_rx_wqe *wqe;
 909         __be16 wqe_counter_be;
 910         struct sk_buff *skb;
 911         u16 wqe_counter;
 912         u32 cqe_bcnt;
 913
 914         wqe_counter_be = cqe->wqe_counter;
 915         wqe_counter    = be16_to_cpu(wqe_counter_be);
 916         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 917         wi             = &rq->wqe.frag_info[wqe_counter];
 918         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 919
 920         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 921         if (!skb) {
 922                 /* probably for XDP */
 923                 if (rq->wqe.xdp_xmit) {
 924                         wi->di.page = NULL;
 925                         rq->wqe.xdp_xmit = false;
 926                         /* do not return page to cache, it will be returned on XDP_TX completion */
 927                         goto wq_ll_pop;
 928                 }
 929                 /* probably an XDP_DROP, save the page-reuse checks */
 930                 mlx5e_free_rx_wqe(rq, wi);
 931                 goto wq_ll_pop;
 932         }
 933
 934         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 935         napi_gro_receive(rq->cq.napi, skb);
 936
 937         mlx5e_free_rx_wqe_reuse(rq, wi);
 938 wq_ll_pop:
 939         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 940                        &wqe->next.next_wqe_index);
 941 }
 942
 943 #ifdef CONFIG_MLX5_ESWITCH
 944 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 945 {
 946         struct net_device *netdev = rq->netdev;
 947         struct mlx5e_priv *priv = netdev_priv(netdev);
 948         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
 949         struct mlx5_eswitch_rep *rep = rpriv->rep;
 950         struct mlx5e_wqe_frag_info *wi;
 951         struct mlx5e_rx_wqe *wqe;
 952         struct sk_buff *skb;
 953         __be16 wqe_counter_be;
 954         u16 wqe_counter;
 955         u32 cqe_bcnt;
 956
 957         wqe_counter_be = cqe->wqe_counter;
 958         wqe_counter    = be16_to_cpu(wqe_counter_be);
 959         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 960         wi             = &rq->wqe.frag_info[wqe_counter];
 961         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 962
 963         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 964         if (!skb) {
 965                 if (rq->wqe.xdp_xmit) {
 966                         wi->di.page = NULL;
 967                         rq->wqe.xdp_xmit = false;
 968                         /* do not return page to cache, it will be returned on XDP_TX completion */
 969                         goto wq_ll_pop;
 970                 }
 971                 /* probably an XDP_DROP, save the page-reuse checks */
 972                 mlx5e_free_rx_wqe(rq, wi);
 973                 goto wq_ll_pop;
 974         }
 975
 976         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 977
 978         if (rep->vlan && skb_vlan_tag_present(skb))
 979                 skb_vlan_pop(skb);
 980
 981         napi_gro_receive(rq->cq.napi, skb);
 982
 983         mlx5e_free_rx_wqe_reuse(rq, wi);
 984 wq_ll_pop:
 985         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 986                        &wqe->next.next_wqe_index);
 987 }
 988 #endif
 989
 990 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
 991                                            struct mlx5_cqe64 *cqe,
 992                                            struct mlx5e_mpw_info *wi,
 993                                            u32 cqe_bcnt,
 994                                            struct sk_buff *skb)
 995 {
 996         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
 997         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
 998         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
 999         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1000         u32 head_page_idx  = page_idx;
1001         u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
1002         u32 frag_offset    = head_offset + headlen;
1003         u16 byte_cnt       = cqe_bcnt - headlen;
1004
1005         if (unlikely(frag_offset >= PAGE_SIZE)) {
1006                 page_idx++;
1007                 frag_offset -= PAGE_SIZE;
1008         }
1009
1010         while (byte_cnt) {
1011                 u32 pg_consumed_bytes =
1012                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1013
1014                 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
1015                                          pg_consumed_bytes);
1016                 byte_cnt -= pg_consumed_bytes;
1017                 frag_offset = 0;
1018                 page_idx++;
1019         }
1020         /* copy header */
1021         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
1022                                     head_offset, headlen);
1023         /* skb linear part was allocated with headlen and aligned to long */
1024         skb->tail += headlen;
1025         skb->len  += headlen;
1026 }
1027
1028 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1029 {
1030         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1031         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1032         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1033         struct mlx5e_rx_wqe  *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
1034         struct sk_buff *skb;
1035         u16 cqe_bcnt;
1036
1037         wi->consumed_strides += cstrides;
1038
1039         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1040                 rq->stats.wqe_err++;
1041                 goto mpwrq_cqe_out;
1042         }
1043
1044         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1045                 rq->stats.mpwqe_filler++;
1046                 goto mpwrq_cqe_out;
1047         }
1048
1049         skb = napi_alloc_skb(rq->cq.napi,
1050                              ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
1051                                    sizeof(long)));
1052         if (unlikely(!skb)) {
1053                 rq->stats.buff_alloc_err++;
1054                 goto mpwrq_cqe_out;
1055         }
1056
1057         prefetchw(skb->data);
1058         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1059
1060         mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
1061         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1062         napi_gro_receive(rq->cq.napi, skb);
1063
1064 mpwrq_cqe_out:
1065         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1066                 return;
1067
1068         mlx5e_free_rx_mpwqe(rq, wi);
1069         mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1070 }
1071
1072 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1073 {
1074         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1075         struct mlx5e_xdpsq *xdpsq;
1076         struct mlx5_cqe64 *cqe;
1077         int work_done = 0;
1078
1079         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
1080                 return 0;
1081
1082         if (cq->decmprs_left)
1083                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1084
1085         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1086         if (!cqe)
1087                 return 0;
1088
1089         xdpsq = &rq->xdpsq;
1090
1091         do {
1092                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1093                         work_done +=
1094                                 mlx5e_decompress_cqes_start(rq, cq,
1095                                                             budget - work_done);
1096                         continue;
1097                 }
1098
1099                 mlx5_cqwq_pop(&cq->wq);
1100
1101                 rq->handle_rx_cqe(rq, cqe);
1102         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1103
1104         if (xdpsq->db.doorbell) {
1105                 mlx5e_xmit_xdp_doorbell(xdpsq);
1106                 xdpsq->db.doorbell = false;
1107         }
1108
1109         mlx5_cqwq_update_db_record(&cq->wq);
1110
1111         /* ensure cq space is freed before enabling more cqes */
1112         wmb();
1113
1114         return work_done;
1115 }
1116
1117 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1118 {
1119         struct mlx5e_xdpsq *sq;
1120         struct mlx5_cqe64 *cqe;
1121         struct mlx5e_rq *rq;
1122         u16 sqcc;
1123         int i;
1124
1125         sq = container_of(cq, struct mlx5e_xdpsq, cq);
1126
1127         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
1128                 return false;
1129
1130         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1131         if (!cqe)
1132                 return false;
1133
1134         rq = container_of(sq, struct mlx5e_rq, xdpsq);
1135
1136         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1137          * otherwise a cq overrun may occur
1138          */
1139         sqcc = sq->cc;
1140
1141         i = 0;
1142         do {
1143                 u16 wqe_counter;
1144                 bool last_wqe;
1145
1146                 mlx5_cqwq_pop(&cq->wq);
1147
1148                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1149
1150                 do {
1151                         struct mlx5e_dma_info *di;
1152                         u16 ci;
1153
1154                         last_wqe = (sqcc == wqe_counter);
1155
1156                         ci = sqcc & sq->wq.sz_m1;
1157                         di = &sq->db.di[ci];
1158
1159                         sqcc++;
1160                         /* Recycle RX page */
1161                         mlx5e_page_release(rq, di, true);
1162                 } while (!last_wqe);
1163         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1164
1165         mlx5_cqwq_update_db_record(&cq->wq);
1166
1167         /* ensure cq space is freed before enabling more cqes */
1168         wmb();
1169
1170         sq->cc = sqcc;
1171         return (i == MLX5E_TX_CQ_POLL_BUDGET);
1172 }
1173
1174 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1175 {
1176         struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1177         struct mlx5e_dma_info *di;
1178         u16 ci;
1179
1180         while (sq->cc != sq->pc) {
1181                 ci = sq->cc & sq->wq.sz_m1;
1182                 di = &sq->db.di[ci];
1183                 sq->cc++;
1184
1185                 mlx5e_page_release(rq, di, false);
1186         }
1187 }
1188
1189 #ifdef CONFIG_MLX5_CORE_IPOIB
1190
1191 #define MLX5_IB_GRH_DGID_OFFSET 24
1192 #define MLX5_GID_SIZE           16
1193
1194 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1195                                          struct mlx5_cqe64 *cqe,
1196                                          u32 cqe_bcnt,
1197                                          struct sk_buff *skb)
1198 {
1199         struct hwtstamp_config *tstamp;
1200         struct net_device *netdev;
1201         struct mlx5e_priv *priv;
1202         char *pseudo_header;
1203         u32 qpn;
1204         u8 *dgid;
1205         u8 g;
1206
1207         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1208         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1209
1210         /* No mapping present, cannot process SKB. This might happen if a child
1211          * interface is going down while having unprocessed CQEs on parent RQ
1212          */
1213         if (unlikely(!netdev)) {
1214                 /* TODO: add drop counters support */
1215                 skb->dev = NULL;
1216                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1217                 return;
1218         }
1219
1220         priv = mlx5i_epriv(netdev);
1221         tstamp = &priv->tstamp;
1222
1223         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1224         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1225         if ((!g) || dgid[0] != 0xff)
1226                 skb->pkt_type = PACKET_HOST;
1227         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1228                 skb->pkt_type = PACKET_BROADCAST;
1229         else
1230                 skb->pkt_type = PACKET_MULTICAST;
1231
1232         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1233          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1234          */
1235
1236         skb_pull(skb, MLX5_IB_GRH_BYTES);
1237
1238         skb->protocol = *((__be16 *)(skb->data));
1239
1240         skb->ip_summed = CHECKSUM_COMPLETE;
1241         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1242
1243         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1244                 skb_hwtstamps(skb)->hwtstamp =
1245                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1246
1247         skb_record_rx_queue(skb, rq->ix);
1248
1249         if (likely(netdev->features & NETIF_F_RXHASH))
1250                 mlx5e_skb_set_hash(cqe, skb);
1251
1252         /* 20 bytes of ipoib header and 4 for encap existing */
1253         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1254         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1255         skb_reset_mac_header(skb);
1256         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1257
1258         skb->dev = netdev;
1259
1260         rq->stats.csum_complete++;
1261         rq->stats.packets++;
1262         rq->stats.bytes += cqe_bcnt;
1263 }
1264
1265 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1266 {
1267         struct mlx5e_wqe_frag_info *wi;
1268         struct mlx5e_rx_wqe *wqe;
1269         __be16 wqe_counter_be;
1270         struct sk_buff *skb;
1271         u16 wqe_counter;
1272         u32 cqe_bcnt;
1273
1274         wqe_counter_be = cqe->wqe_counter;
1275         wqe_counter    = be16_to_cpu(wqe_counter_be);
1276         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1277         wi             = &rq->wqe.frag_info[wqe_counter];
1278         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1279
1280         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1281         if (!skb)
1282                 goto wq_free_wqe;
1283
1284         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1285         if (unlikely(!skb->dev)) {
1286                 dev_kfree_skb_any(skb);
1287                 goto wq_free_wqe;
1288         }
1289         napi_gro_receive(rq->cq.napi, skb);
1290
1291 wq_free_wqe:
1292         mlx5e_free_rx_wqe_reuse(rq, wi);
1293         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1294                        &wqe->next.next_wqe_index);
1295 }
1296
1297 #endif /* CONFIG_MLX5_CORE_IPOIB */
1298
1299 #ifdef CONFIG_MLX5_EN_IPSEC
1300
1301 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1302 {
1303         struct mlx5e_wqe_frag_info *wi;
1304         struct mlx5e_rx_wqe *wqe;
1305         __be16 wqe_counter_be;
1306         struct sk_buff *skb;
1307         u16 wqe_counter;
1308         u32 cqe_bcnt;
1309
1310         wqe_counter_be = cqe->wqe_counter;
1311         wqe_counter    = be16_to_cpu(wqe_counter_be);
1312         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1313         wi             = &rq->wqe.frag_info[wqe_counter];
1314         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1315
1316         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1317         if (unlikely(!skb)) {
1318                 /* a DROP, save the page-reuse checks */
1319                 mlx5e_free_rx_wqe(rq, wi);
1320                 goto wq_ll_pop;
1321         }
1322         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1323         if (unlikely(!skb)) {
1324                 mlx5e_free_rx_wqe(rq, wi);
1325                 goto wq_ll_pop;
1326         }
1327
1328         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1329         napi_gro_receive(rq->cq.napi, skb);
1330
1331         mlx5e_free_rx_wqe_reuse(rq, wi);
1332 wq_ll_pop:
1333         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1334                        &wqe->next.next_wqe_index);
1335 }
1336
1337 #endif /* CONFIG_MLX5_EN_IPSEC */