2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/prefetch.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/bpf_trace.h>
38 #include <net/busy_poll.h>
43 #include "ipoib/ipoib.h"
44 #include "en_accel/ipsec_rxtx.h"
46 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
48 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
51 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
54 u32 ci = cqcc & cq->wq.sz_m1;
56 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
59 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
60 struct mlx5e_cq *cq, u32 cqcc)
62 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
63 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
64 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
65 rq->stats.cqe_compress_blks++;
68 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
70 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
74 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
76 u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
77 u32 wq_sz = 1 << cq->wq.log_sz;
78 u32 ci = cqcc & cq->wq.sz_m1;
79 u32 ci_top = min_t(u32, wq_sz, ci + n);
81 for (; ci < ci_top; ci++, n--) {
82 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
87 if (unlikely(ci == wq_sz)) {
89 for (ci = 0; ci < n; ci++) {
90 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
97 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
98 struct mlx5e_cq *cq, u32 cqcc)
100 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
101 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
102 cq->title.op_own &= 0xf0;
103 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz);
104 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
106 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
107 cq->decmprs_wqe_counter +=
108 mpwrq_get_cqe_consumed_strides(&cq->title);
110 cq->decmprs_wqe_counter =
111 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1;
114 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
115 struct mlx5e_cq *cq, u32 cqcc)
117 mlx5e_decompress_cqe(rq, cq, cqcc);
118 cq->title.rss_hash_type = 0;
119 cq->title.rss_hash_result = 0;
122 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
124 int update_owner_only,
127 u32 cqcc = cq->wq.cc + update_owner_only;
131 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
133 for (i = update_owner_only; i < cqe_count;
134 i++, cq->mini_arr_idx++, cqcc++) {
135 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
136 mlx5e_read_mini_arr_slot(cq, cqcc);
138 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
139 rq->handle_rx_cqe(rq, &cq->title);
141 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
143 cq->decmprs_left -= cqe_count;
144 rq->stats.cqe_compress_pkts += cqe_count;
149 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
153 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
154 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
155 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
156 rq->handle_rx_cqe(rq, &cq->title);
159 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
162 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
164 static inline bool mlx5e_page_is_reserved(struct page *page)
166 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_node_id();
169 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
170 struct mlx5e_dma_info *dma_info)
172 struct mlx5e_page_cache *cache = &rq->page_cache;
173 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
175 if (tail_next == cache->head) {
176 rq->stats.cache_full++;
180 if (unlikely(page_is_pfmemalloc(dma_info->page)))
183 cache->page_cache[cache->tail] = *dma_info;
184 cache->tail = tail_next;
188 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
189 struct mlx5e_dma_info *dma_info)
191 struct mlx5e_page_cache *cache = &rq->page_cache;
193 if (unlikely(cache->head == cache->tail)) {
194 rq->stats.cache_empty++;
198 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
199 rq->stats.cache_busy++;
203 *dma_info = cache->page_cache[cache->head];
204 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
205 rq->stats.cache_reuse++;
207 dma_sync_single_for_device(rq->pdev, dma_info->addr,
213 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
214 struct mlx5e_dma_info *dma_info)
218 if (mlx5e_rx_cache_get(rq, dma_info))
221 page = dev_alloc_pages(rq->buff.page_order);
225 dma_info->page = page;
226 dma_info->addr = dma_map_page(rq->pdev, page, 0,
227 RQ_PAGE_SIZE(rq), rq->buff.map_dir);
228 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
236 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
239 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
242 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
244 put_page(dma_info->page);
247 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,
248 struct mlx5e_wqe_frag_info *wi)
250 return rq->wqe.page_reuse && wi->di.page &&
251 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) &&
252 !mlx5e_page_is_reserved(wi->di.page);
255 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
257 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
259 /* check if page exists, hence can be reused */
261 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di)))
266 wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset +
271 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
272 struct mlx5e_wqe_frag_info *wi)
274 mlx5e_page_release(rq, &wi->di, true);
278 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq,
279 struct mlx5e_wqe_frag_info *wi)
281 if (mlx5e_page_reuse(rq, wi)) {
282 rq->stats.page_reuse++;
286 mlx5e_free_rx_wqe(rq, wi);
289 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
291 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
294 mlx5e_free_rx_wqe(rq, wi);
297 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
299 return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
302 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
304 struct mlx5e_mpw_info *wi,
305 u32 page_idx, u32 frag_offset,
308 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz);
310 dma_sync_single_for_cpu(rq->pdev,
311 wi->umr.dma_info[page_idx].addr + frag_offset,
312 len, DMA_FROM_DEVICE);
313 wi->skbs_frags[page_idx]++;
314 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
315 wi->umr.dma_info[page_idx].page, frag_offset,
320 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
322 struct mlx5e_mpw_info *wi,
323 u32 page_idx, u32 offset,
326 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
327 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
330 /* Aligning len to sizeof(long) optimizes memcpy performance */
331 len = ALIGN(headlen_pg, sizeof(long));
332 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
334 skb_copy_to_linear_data_offset(skb, 0,
335 page_address(dma_info->page) + offset,
337 if (unlikely(offset + headlen > PAGE_SIZE)) {
340 len = ALIGN(headlen - headlen_pg, sizeof(long));
341 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
343 skb_copy_to_linear_data_offset(skb, headlen_pg,
344 page_address(dma_info->page),
349 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
351 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
352 struct mlx5e_icosq *sq = &rq->channel->icosq;
353 struct mlx5_wq_cyc *wq = &sq->wq;
354 struct mlx5e_umr_wqe *wqe;
355 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
358 /* fill sq edge with nops to avoid wqe wrap around */
359 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
360 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
361 sq->db.ico_wqe[pi].num_wqebbs = 1;
362 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
365 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
366 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe));
367 wqe->ctrl.opmod_idx_opcode =
368 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
371 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
372 sq->db.ico_wqe[pi].num_wqebbs = num_wqebbs;
373 sq->pc += num_wqebbs;
374 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl);
377 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq,
378 struct mlx5e_rx_wqe *wqe,
381 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
382 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, ix) << PAGE_SHIFT;
383 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
387 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
388 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
390 err = mlx5e_page_alloc_mapped(rq, dma_info);
393 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
394 page_ref_add(dma_info->page, pg_strides);
395 wi->skbs_frags[i] = 0;
398 wi->consumed_strides = 0;
399 wqe->data.addr = cpu_to_be64(dma_offset);
405 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
407 page_ref_sub(dma_info->page, pg_strides);
408 mlx5e_page_release(rq, dma_info, true);
414 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
416 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
419 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
420 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
422 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]);
423 mlx5e_page_release(rq, dma_info, true);
427 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
429 struct mlx5_wq_ll *wq = &rq->wq;
430 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
432 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
434 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) {
435 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
439 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
441 /* ensure wqes are visible to device before updating doorbell record */
444 mlx5_wq_ll_update_db_record(wq);
447 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
451 err = mlx5e_alloc_rx_umr_mpwqe(rq, wqe, ix);
454 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
455 mlx5e_post_umr_wqe(rq, ix);
459 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
461 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
463 mlx5e_free_rx_mpwqe(rq, wi);
466 #define RQ_CANNOT_POST(rq) \
467 (!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state) || \
468 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
470 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
472 struct mlx5_wq_ll *wq = &rq->wq;
474 if (unlikely(RQ_CANNOT_POST(rq)))
477 while (!mlx5_wq_ll_is_full(wq)) {
478 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
481 err = rq->alloc_wqe(rq, wqe, wq->head);
485 rq->stats.buff_alloc_err++;
489 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
492 /* ensure wqes are visible to device before updating doorbell record */
495 mlx5_wq_ll_update_db_record(wq);
497 return !mlx5_wq_ll_is_full(wq);
500 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
503 struct ethhdr *eth = (struct ethhdr *)(skb->data);
505 struct ipv6hdr *ipv6;
507 int network_depth = 0;
511 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
512 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) ||
513 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type));
515 skb->mac_len = ETH_HLEN;
516 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
518 ipv4 = (struct iphdr *)(skb->data + network_depth);
519 ipv6 = (struct ipv6hdr *)(skb->data + network_depth);
520 tot_len = cqe_bcnt - network_depth;
522 if (proto == htons(ETH_P_IP)) {
523 tcp = (struct tcphdr *)(skb->data + network_depth +
524 sizeof(struct iphdr));
526 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
528 tcp = (struct tcphdr *)(skb->data + network_depth +
529 sizeof(struct ipv6hdr));
531 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
534 if (get_cqe_lro_tcppsh(cqe))
539 tcp->ack_seq = cqe->lro_ack_seq_num;
540 tcp->window = cqe->lro_tcp_win;
544 ipv4->ttl = cqe->lro_min_ttl;
545 ipv4->tot_len = cpu_to_be16(tot_len);
547 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
550 ipv6->hop_limit = cqe->lro_min_ttl;
551 ipv6->payload_len = cpu_to_be16(tot_len -
552 sizeof(struct ipv6hdr));
556 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
559 u8 cht = cqe->rss_hash_type;
560 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
561 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
563 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
566 static inline bool is_first_ethertype_ip(struct sk_buff *skb)
568 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
570 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
573 static inline void mlx5e_handle_csum(struct net_device *netdev,
574 struct mlx5_cqe64 *cqe,
579 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
583 skb->ip_summed = CHECKSUM_UNNECESSARY;
587 if (is_first_ethertype_ip(skb)) {
588 skb->ip_summed = CHECKSUM_COMPLETE;
589 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
590 rq->stats.csum_complete++;
594 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
595 (cqe->hds_ip_ext & CQE_L4_OK))) {
596 skb->ip_summed = CHECKSUM_UNNECESSARY;
597 if (cqe_is_tunneled(cqe)) {
599 skb->encapsulation = 1;
600 rq->stats.csum_unnecessary_inner++;
605 skb->ip_summed = CHECKSUM_NONE;
606 rq->stats.csum_none++;
609 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
614 struct net_device *netdev = rq->netdev;
615 struct mlx5e_tstamp *tstamp = rq->tstamp;
618 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
619 if (lro_num_seg > 1) {
620 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
621 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
622 /* Subtract one since we already counted this as one
623 * "regular" packet in mlx5e_complete_rx_cqe()
625 rq->stats.packets += lro_num_seg - 1;
626 rq->stats.lro_packets++;
627 rq->stats.lro_bytes += cqe_bcnt;
630 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
631 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
633 skb_record_rx_queue(skb, rq->ix);
635 if (likely(netdev->features & NETIF_F_RXHASH))
636 mlx5e_skb_set_hash(cqe, skb);
638 if (cqe_has_vlan(cqe))
639 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
640 be16_to_cpu(cqe->vlan_info));
642 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
644 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
645 skb->protocol = eth_type_trans(skb, netdev);
648 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
649 struct mlx5_cqe64 *cqe,
654 rq->stats.bytes += cqe_bcnt;
655 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
658 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
660 struct mlx5_wq_cyc *wq = &sq->wq;
661 struct mlx5e_tx_wqe *wqe;
662 u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */
664 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
666 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
669 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
670 struct mlx5e_dma_info *di,
671 const struct xdp_buff *xdp)
673 struct mlx5e_xdpsq *sq = &rq->xdpsq;
674 struct mlx5_wq_cyc *wq = &sq->wq;
675 u16 pi = sq->pc & wq->sz_m1;
676 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
678 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
679 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
680 struct mlx5_wqe_data_seg *dseg;
682 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
683 dma_addr_t dma_addr = di->addr + data_offset;
684 unsigned int dma_len = xdp->data_end - xdp->data;
688 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE ||
689 MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) {
690 rq->stats.xdp_drop++;
694 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
695 if (sq->db.doorbell) {
696 /* SQ is full, ring doorbell */
697 mlx5e_xmit_xdp_doorbell(sq);
698 sq->db.doorbell = false;
700 rq->stats.xdp_tx_full++;
704 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
708 dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
710 /* copy the inline part if required */
711 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
712 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
713 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
714 dma_len -= MLX5E_XDP_MIN_INLINE;
715 dma_addr += MLX5E_XDP_MIN_INLINE;
719 /* write the dma part */
720 dseg->addr = cpu_to_be64(dma_addr);
721 dseg->byte_count = cpu_to_be32(dma_len);
723 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
725 /* move page to reference to sq responsibility,
726 * and mark so it's not put back in page-cache.
728 rq->wqe.xdp_xmit = true;
732 sq->db.doorbell = true;
738 /* returns true if packet was consumed by xdp */
739 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq,
740 struct mlx5e_dma_info *di,
741 void *va, u16 *rx_headroom, u32 *len)
743 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
750 xdp.data = va + *rx_headroom;
751 xdp.data_end = xdp.data + *len;
752 xdp.data_hard_start = va;
754 act = bpf_prog_run_xdp(prog, &xdp);
757 *rx_headroom = xdp.data - xdp.data_hard_start;
758 *len = xdp.data_end - xdp.data;
761 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
762 trace_xdp_exception(rq->netdev, prog, act);
765 bpf_warn_invalid_xdp_action(act);
767 trace_xdp_exception(rq->netdev, prog, act);
769 rq->stats.xdp_drop++;
775 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
776 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
778 struct mlx5e_dma_info *di = &wi->di;
781 u16 rx_headroom = rq->rx_headroom;
785 va = page_address(di->page) + wi->offset;
786 data = va + rx_headroom;
787 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
789 dma_sync_single_range_for_cpu(rq->pdev,
790 di->addr + wi->offset,
794 wi->offset += frag_size;
796 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
802 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
805 return NULL; /* page/packet was consumed by XDP */
807 skb = build_skb(va, frag_size);
808 if (unlikely(!skb)) {
809 rq->stats.buff_alloc_err++;
813 /* queue up for recycling/reuse */
814 page_ref_inc(di->page);
816 skb_reserve(skb, rx_headroom);
817 skb_put(skb, cqe_bcnt);
822 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
824 struct mlx5e_wqe_frag_info *wi;
825 struct mlx5e_rx_wqe *wqe;
826 __be16 wqe_counter_be;
831 wqe_counter_be = cqe->wqe_counter;
832 wqe_counter = be16_to_cpu(wqe_counter_be);
833 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
834 wi = &rq->wqe.frag_info[wqe_counter];
835 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
837 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
839 /* probably for XDP */
840 if (rq->wqe.xdp_xmit) {
842 rq->wqe.xdp_xmit = false;
843 /* do not return page to cache, it will be returned on XDP_TX completion */
846 /* probably an XDP_DROP, save the page-reuse checks */
847 mlx5e_free_rx_wqe(rq, wi);
851 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
852 napi_gro_receive(rq->cq.napi, skb);
854 mlx5e_free_rx_wqe_reuse(rq, wi);
856 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
857 &wqe->next.next_wqe_index);
860 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
862 struct net_device *netdev = rq->netdev;
863 struct mlx5e_priv *priv = netdev_priv(netdev);
864 struct mlx5e_rep_priv *rpriv = priv->ppriv;
865 struct mlx5_eswitch_rep *rep = rpriv->rep;
866 struct mlx5e_wqe_frag_info *wi;
867 struct mlx5e_rx_wqe *wqe;
869 __be16 wqe_counter_be;
873 wqe_counter_be = cqe->wqe_counter;
874 wqe_counter = be16_to_cpu(wqe_counter_be);
875 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
876 wi = &rq->wqe.frag_info[wqe_counter];
877 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
879 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
881 if (rq->wqe.xdp_xmit) {
883 rq->wqe.xdp_xmit = false;
884 /* do not return page to cache, it will be returned on XDP_TX completion */
887 /* probably an XDP_DROP, save the page-reuse checks */
888 mlx5e_free_rx_wqe(rq, wi);
892 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
894 if (rep->vlan && skb_vlan_tag_present(skb))
897 napi_gro_receive(rq->cq.napi, skb);
899 mlx5e_free_rx_wqe_reuse(rq, wi);
901 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
902 &wqe->next.next_wqe_index);
905 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
906 struct mlx5_cqe64 *cqe,
907 struct mlx5e_mpw_info *wi,
911 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
912 u32 wqe_offset = stride_ix * rq->mpwqe_stride_sz;
913 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
914 u32 page_idx = wqe_offset >> PAGE_SHIFT;
915 u32 head_page_idx = page_idx;
916 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
917 u32 frag_offset = head_offset + headlen;
918 u16 byte_cnt = cqe_bcnt - headlen;
920 if (unlikely(frag_offset >= PAGE_SIZE)) {
922 frag_offset -= PAGE_SIZE;
926 u32 pg_consumed_bytes =
927 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
929 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
931 byte_cnt -= pg_consumed_bytes;
936 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
937 head_offset, headlen);
938 /* skb linear part was allocated with headlen and aligned to long */
939 skb->tail += headlen;
943 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
945 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
946 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
947 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
948 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
952 wi->consumed_strides += cstrides;
954 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
959 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
960 rq->stats.mpwqe_filler++;
964 skb = napi_alloc_skb(rq->cq.napi,
965 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
967 if (unlikely(!skb)) {
968 rq->stats.buff_alloc_err++;
972 prefetchw(skb->data);
973 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
975 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
976 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
977 napi_gro_receive(rq->cq.napi, skb);
980 if (likely(wi->consumed_strides < rq->mpwqe_num_strides))
983 mlx5e_free_rx_mpwqe(rq, wi);
984 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
987 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
989 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
990 struct mlx5e_xdpsq *xdpsq = &rq->xdpsq;
993 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
996 if (cq->decmprs_left)
997 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
999 for (; work_done < budget; work_done++) {
1000 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_cqe(&cq->wq);
1005 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1007 mlx5e_decompress_cqes_start(rq, cq,
1008 budget - work_done);
1012 mlx5_cqwq_pop(&cq->wq);
1014 rq->handle_rx_cqe(rq, cqe);
1017 if (xdpsq->db.doorbell) {
1018 mlx5e_xmit_xdp_doorbell(xdpsq);
1019 xdpsq->db.doorbell = false;
1022 mlx5_cqwq_update_db_record(&cq->wq);
1024 /* ensure cq space is freed before enabling more cqes */
1030 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1032 struct mlx5e_xdpsq *sq;
1033 struct mlx5e_rq *rq;
1037 sq = container_of(cq, struct mlx5e_xdpsq, cq);
1039 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
1042 rq = container_of(sq, struct mlx5e_rq, xdpsq);
1044 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1045 * otherwise a cq overrun may occur
1049 for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) {
1050 struct mlx5_cqe64 *cqe;
1054 cqe = mlx5_cqwq_get_cqe(&cq->wq);
1058 mlx5_cqwq_pop(&cq->wq);
1060 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1063 struct mlx5e_dma_info *di;
1066 last_wqe = (sqcc == wqe_counter);
1068 ci = sqcc & sq->wq.sz_m1;
1069 di = &sq->db.di[ci];
1072 /* Recycle RX page */
1073 mlx5e_page_release(rq, di, true);
1074 } while (!last_wqe);
1077 mlx5_cqwq_update_db_record(&cq->wq);
1079 /* ensure cq space is freed before enabling more cqes */
1083 return (i == MLX5E_TX_CQ_POLL_BUDGET);
1086 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1088 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1089 struct mlx5e_dma_info *di;
1092 while (sq->cc != sq->pc) {
1093 ci = sq->cc & sq->wq.sz_m1;
1094 di = &sq->db.di[ci];
1097 mlx5e_page_release(rq, di, false);
1101 #ifdef CONFIG_MLX5_CORE_IPOIB
1103 #define MLX5_IB_GRH_DGID_OFFSET 24
1104 #define MLX5_GID_SIZE 16
1106 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1107 struct mlx5_cqe64 *cqe,
1109 struct sk_buff *skb)
1111 struct net_device *netdev = rq->netdev;
1112 struct mlx5e_tstamp *tstamp = rq->tstamp;
1113 char *pseudo_header;
1117 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1118 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1119 if ((!g) || dgid[0] != 0xff)
1120 skb->pkt_type = PACKET_HOST;
1121 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1122 skb->pkt_type = PACKET_BROADCAST;
1124 skb->pkt_type = PACKET_MULTICAST;
1126 /* TODO: IB/ipoib: Allow mcast packets from other VFs
1127 * 68996a6e760e5c74654723eeb57bf65628ae87f4
1130 skb_pull(skb, MLX5_IB_GRH_BYTES);
1132 skb->protocol = *((__be16 *)(skb->data));
1134 skb->ip_summed = CHECKSUM_COMPLETE;
1135 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1137 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1138 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
1140 skb_record_rx_queue(skb, rq->ix);
1142 if (likely(netdev->features & NETIF_F_RXHASH))
1143 mlx5e_skb_set_hash(cqe, skb);
1145 /* 20 bytes of ipoib header and 4 for encap existing */
1146 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1147 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1148 skb_reset_mac_header(skb);
1149 skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1153 rq->stats.csum_complete++;
1154 rq->stats.packets++;
1155 rq->stats.bytes += cqe_bcnt;
1158 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1160 struct mlx5e_wqe_frag_info *wi;
1161 struct mlx5e_rx_wqe *wqe;
1162 __be16 wqe_counter_be;
1163 struct sk_buff *skb;
1167 wqe_counter_be = cqe->wqe_counter;
1168 wqe_counter = be16_to_cpu(wqe_counter_be);
1169 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1170 wi = &rq->wqe.frag_info[wqe_counter];
1171 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1173 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1177 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1178 napi_gro_receive(rq->cq.napi, skb);
1181 mlx5e_free_rx_wqe_reuse(rq, wi);
1182 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1183 &wqe->next.next_wqe_index);
1186 #endif /* CONFIG_MLX5_CORE_IPOIB */
1188 #ifdef CONFIG_MLX5_EN_IPSEC
1190 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1192 struct mlx5e_wqe_frag_info *wi;
1193 struct mlx5e_rx_wqe *wqe;
1194 __be16 wqe_counter_be;
1195 struct sk_buff *skb;
1199 wqe_counter_be = cqe->wqe_counter;
1200 wqe_counter = be16_to_cpu(wqe_counter_be);
1201 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1202 wi = &rq->wqe.frag_info[wqe_counter];
1203 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1205 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1206 if (unlikely(!skb)) {
1207 /* a DROP, save the page-reuse checks */
1208 mlx5e_free_rx_wqe(rq, wi);
1211 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1212 if (unlikely(!skb)) {
1213 mlx5e_free_rx_wqe(rq, wi);
1217 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1218 napi_gro_receive(rq->cq.napi, skb);
1220 mlx5e_free_rx_wqe_reuse(rq, wi);
1222 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1223 &wqe->next.next_wqe_index);
1226 #endif /* CONFIG_MLX5_EN_IPSEC */