drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <linux/bpf_trace.h>
  38 #include <net/busy_poll.h>
  39 #include <net/ip6_checksum.h>
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "eswitch.h"
  43 #include "en_rep.h"
  44 #include "ipoib/ipoib.h"
  45 #include "en_accel/ipsec_rxtx.h"
  46 #include "lib/clock.h"
  47
  48 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  49 {
  50         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  51 }
  52
  53 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
  54                                        void *data)
  55 {
  56         u32 ci = cqcc & cq->wq.fbc.sz_m1;
  57
  58         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
  59 }
  60
  61 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  62                                          struct mlx5e_cq *cq, u32 cqcc)
  63 {
  64         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
  65         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
  66         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
  67         rq->stats.cqe_compress_blks++;
  68 }
  69
  70 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
  71 {
  72         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
  73         cq->mini_arr_idx = 0;
  74 }
  75
  76 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
  77 {
  78         struct mlx5_frag_buf_ctrl *fbc = &cq->wq.fbc;
  79         u8 op_own = (cqcc >> fbc->log_sz) & 1;
  80         u32 wq_sz = 1 << fbc->log_sz;
  81         u32 ci = cqcc & fbc->sz_m1;
  82         u32 ci_top = min_t(u32, wq_sz, ci + n);
  83
  84         for (; ci < ci_top; ci++, n--) {
  85                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  86
  87                 cqe->op_own = op_own;
  88         }
  89
  90         if (unlikely(ci == wq_sz)) {
  91                 op_own = !op_own;
  92                 for (ci = 0; ci < n; ci++) {
  93                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  94
  95                         cqe->op_own = op_own;
  96                 }
  97         }
  98 }
  99
 100 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 101                                         struct mlx5e_cq *cq, u32 cqcc)
 102 {
 103         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
 104         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
 105         cq->title.op_own      &= 0xf0;
 106         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
 107         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
 108
 109         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 110                 cq->decmprs_wqe_counter +=
 111                         mpwrq_get_cqe_consumed_strides(&cq->title);
 112         else
 113                 cq->decmprs_wqe_counter =
 114                         (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1;
 115 }
 116
 117 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 118                                                 struct mlx5e_cq *cq, u32 cqcc)
 119 {
 120         mlx5e_decompress_cqe(rq, cq, cqcc);
 121         cq->title.rss_hash_type   = 0;
 122         cq->title.rss_hash_result = 0;
 123 }
 124
 125 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 126                                              struct mlx5e_cq *cq,
 127                                              int update_owner_only,
 128                                              int budget_rem)
 129 {
 130         u32 cqcc = cq->wq.cc + update_owner_only;
 131         u32 cqe_count;
 132         u32 i;
 133
 134         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
 135
 136         for (i = update_owner_only; i < cqe_count;
 137              i++, cq->mini_arr_idx++, cqcc++) {
 138                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 139                         mlx5e_read_mini_arr_slot(cq, cqcc);
 140
 141                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
 142                 rq->handle_rx_cqe(rq, &cq->title);
 143         }
 144         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
 145         cq->wq.cc = cqcc;
 146         cq->decmprs_left -= cqe_count;
 147         rq->stats.cqe_compress_pkts += cqe_count;
 148
 149         return cqe_count;
 150 }
 151
 152 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 153                                               struct mlx5e_cq *cq,
 154                                               int budget_rem)
 155 {
 156         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
 157         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
 158         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
 159         rq->handle_rx_cqe(rq, &cq->title);
 160         cq->mini_arr_idx++;
 161
 162         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
 163 }
 164
 165 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
 166
 167 static inline bool mlx5e_page_is_reserved(struct page *page)
 168 {
 169         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 170 }
 171
 172 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 173                                       struct mlx5e_dma_info *dma_info)
 174 {
 175         struct mlx5e_page_cache *cache = &rq->page_cache;
 176         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 177
 178         if (tail_next == cache->head) {
 179                 rq->stats.cache_full++;
 180                 return false;
 181         }
 182
 183         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 184                 rq->stats.cache_waive++;
 185                 return false;
 186         }
 187
 188         cache->page_cache[cache->tail] = *dma_info;
 189         cache->tail = tail_next;
 190         return true;
 191 }
 192
 193 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 194                                       struct mlx5e_dma_info *dma_info)
 195 {
 196         struct mlx5e_page_cache *cache = &rq->page_cache;
 197
 198         if (unlikely(cache->head == cache->tail)) {
 199                 rq->stats.cache_empty++;
 200                 return false;
 201         }
 202
 203         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 204                 rq->stats.cache_busy++;
 205                 return false;
 206         }
 207
 208         *dma_info = cache->page_cache[cache->head];
 209         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 210         rq->stats.cache_reuse++;
 211
 212         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 213                                    RQ_PAGE_SIZE(rq),
 214                                    DMA_FROM_DEVICE);
 215         return true;
 216 }
 217
 218 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
 219                                           struct mlx5e_dma_info *dma_info)
 220 {
 221         if (mlx5e_rx_cache_get(rq, dma_info))
 222                 return 0;
 223
 224         dma_info->page = dev_alloc_pages(rq->buff.page_order);
 225         if (unlikely(!dma_info->page))
 226                 return -ENOMEM;
 227
 228         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 229                                       RQ_PAGE_SIZE(rq), rq->buff.map_dir);
 230         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 231                 put_page(dma_info->page);
 232                 dma_info->page = NULL;
 233                 return -ENOMEM;
 234         }
 235
 236         return 0;
 237 }
 238
 239 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 240                         bool recycle)
 241 {
 242         if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
 243                 return;
 244
 245         dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
 246                        rq->buff.map_dir);
 247         put_page(dma_info->page);
 248 }
 249
 250 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,
 251                                     struct mlx5e_wqe_frag_info *wi)
 252 {
 253         return rq->wqe.page_reuse && wi->di.page &&
 254                 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) &&
 255                 !mlx5e_page_is_reserved(wi->di.page);
 256 }
 257
 258 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
 259 {
 260         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 261
 262         /* check if page exists, hence can be reused */
 263         if (!wi->di.page) {
 264                 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di)))
 265                         return -ENOMEM;
 266                 wi->offset = 0;
 267         }
 268
 269         wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom);
 270         return 0;
 271 }
 272
 273 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 274                                      struct mlx5e_wqe_frag_info *wi)
 275 {
 276         mlx5e_page_release(rq, &wi->di, true);
 277         wi->di.page = NULL;
 278 }
 279
 280 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq,
 281                                            struct mlx5e_wqe_frag_info *wi)
 282 {
 283         if (mlx5e_page_reuse(rq, wi)) {
 284                 rq->stats.page_reuse++;
 285                 return;
 286         }
 287
 288         mlx5e_free_rx_wqe(rq, wi);
 289 }
 290
 291 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 292 {
 293         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 294
 295         if (wi->di.page)
 296                 mlx5e_free_rx_wqe(rq, wi);
 297 }
 298
 299 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
 300 {
 301         return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
 302 }
 303
 304 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
 305                                             struct sk_buff *skb,
 306                                             struct mlx5e_mpw_info *wi,
 307                                             u32 page_idx, u32 frag_offset,
 308                                             u32 len)
 309 {
 310         unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz));
 311
 312         dma_sync_single_for_cpu(rq->pdev,
 313                                 wi->umr.dma_info[page_idx].addr + frag_offset,
 314                                 len, DMA_FROM_DEVICE);
 315         wi->skbs_frags[page_idx]++;
 316         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 317                         wi->umr.dma_info[page_idx].page, frag_offset,
 318                         len, truesize);
 319 }
 320
 321 static inline void
 322 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
 323                             struct sk_buff *skb,
 324                             struct mlx5e_mpw_info *wi,
 325                             u32 page_idx, u32 offset,
 326                             u32 headlen)
 327 {
 328         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
 329         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
 330         unsigned int len;
 331
 332          /* Aligning len to sizeof(long) optimizes memcpy performance */
 333         len = ALIGN(headlen_pg, sizeof(long));
 334         dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
 335                                 DMA_FROM_DEVICE);
 336         skb_copy_to_linear_data(skb, page_address(dma_info->page) + offset, len);
 337
 338         if (unlikely(offset + headlen > PAGE_SIZE)) {
 339                 dma_info++;
 340                 headlen_pg = len;
 341                 len = ALIGN(headlen - headlen_pg, sizeof(long));
 342                 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
 343                                         DMA_FROM_DEVICE);
 344                 skb_copy_to_linear_data_offset(skb, headlen_pg,
 345                                                page_address(dma_info->page),
 346                                                len);
 347         }
 348 }
 349
 350 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
 351 {
 352         const bool no_xdp_xmit =
 353                 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 354         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
 355         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
 356         int i;
 357
 358         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
 359                 page_ref_sub(dma_info[i].page, pg_strides - wi->skbs_frags[i]);
 360                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
 361                         mlx5e_page_release(rq, &dma_info[i], true);
 362         }
 363 }
 364
 365 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
 366 {
 367         struct mlx5_wq_ll *wq = &rq->wq;
 368         struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 369
 370         rq->mpwqe.umr_in_progress = false;
 371
 372         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 373
 374         /* ensure wqes are visible to device before updating doorbell record */
 375         dma_wmb();
 376
 377         mlx5_wq_ll_update_db_record(wq);
 378 }
 379
 380 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 381 {
 382         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 383         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
 384         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 385         struct mlx5e_icosq *sq = &rq->channel->icosq;
 386         struct mlx5_wq_cyc *wq = &sq->wq;
 387         struct mlx5e_umr_wqe *umr_wqe;
 388         int cpy = offsetof(struct mlx5e_umr_wqe, inline_mtts);
 389         int err;
 390         u16 pi;
 391         int i;
 392
 393         /* fill sq edge with nops to avoid wqe wrap around */
 394         while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
 395                 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
 396                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 397         }
 398
 399         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 400         memcpy(umr_wqe, &wi->umr.wqe, cpy);
 401         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 402                 err = mlx5e_page_alloc_mapped(rq, dma_info);
 403                 if (unlikely(err))
 404                         goto err_unmap;
 405                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 406                 page_ref_add(dma_info->page, pg_strides);
 407         }
 408
 409         memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE);
 410         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 411         wi->consumed_strides = 0;
 412
 413         rq->mpwqe.umr_in_progress = true;
 414
 415         umr_wqe->ctrl.opmod_idx_opcode =
 416                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 417                             MLX5_OPCODE_UMR);
 418
 419         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 420         sq->pc += MLX5E_UMR_WQEBBS;
 421         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
 422
 423         return 0;
 424
 425 err_unmap:
 426         while (--i >= 0) {
 427                 dma_info--;
 428                 page_ref_sub(dma_info->page, pg_strides);
 429                 mlx5e_page_release(rq, dma_info, true);
 430         }
 431         rq->stats.buff_alloc_err++;
 432
 433         return err;
 434 }
 435
 436 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 437 {
 438         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 439
 440         mlx5e_free_rx_mpwqe(rq, wi);
 441 }
 442
 443 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 444 {
 445         struct mlx5_wq_ll *wq = &rq->wq;
 446         int err;
 447
 448         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
 449                 return false;
 450
 451         if (mlx5_wq_ll_is_full(wq))
 452                 return false;
 453
 454         do {
 455                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 456
 457                 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head);
 458                 if (unlikely(err)) {
 459                         rq->stats.buff_alloc_err++;
 460                         break;
 461                 }
 462
 463                 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 464         } while (!mlx5_wq_ll_is_full(wq));
 465
 466         /* ensure wqes are visible to device before updating doorbell record */
 467         dma_wmb();
 468
 469         mlx5_wq_ll_update_db_record(wq);
 470
 471         return !!err;
 472 }
 473
 474 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
 475                                              struct mlx5e_icosq *sq,
 476                                              struct mlx5e_rq *rq,
 477                                              struct mlx5_cqe64 *cqe)
 478 {
 479         struct mlx5_wq_cyc *wq = &sq->wq;
 480         u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;
 481         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
 482
 483         mlx5_cqwq_pop(&cq->wq);
 484
 485         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
 486                 netdev_WARN_ONCE(cq->channel->netdev,
 487                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
 488                 return;
 489         }
 490
 491         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
 492                 mlx5e_post_rx_mpwqe(rq);
 493                 return;
 494         }
 495
 496         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
 497                 netdev_WARN_ONCE(cq->channel->netdev,
 498                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
 499 }
 500
 501 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
 502 {
 503         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 504         struct mlx5_cqe64 *cqe;
 505
 506         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
 507                 return;
 508
 509         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 510         if (likely(!cqe))
 511                 return;
 512
 513         /* by design, there's only a single cqe */
 514         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
 515
 516         mlx5_cqwq_update_db_record(&cq->wq);
 517 }
 518
 519 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 520 {
 521         struct mlx5_wq_ll *wq = &rq->wq;
 522
 523         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
 524                 return false;
 525
 526         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
 527
 528         if (mlx5_wq_ll_is_full(wq))
 529                 return false;
 530
 531         if (!rq->mpwqe.umr_in_progress)
 532                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
 533
 534         return false;
 535 }
 536
 537 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 538 {
 539         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 540         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 541                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 542
 543         tcp->check                      = 0;
 544         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 545
 546         if (tcp_ack) {
 547                 tcp->ack                = 1;
 548                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 549                 tcp->window             = cqe->lro_tcp_win;
 550         }
 551 }
 552
 553 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 554                                  u32 cqe_bcnt)
 555 {
 556         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 557         struct tcphdr   *tcp;
 558         int network_depth = 0;
 559         __wsum check;
 560         __be16 proto;
 561         u16 tot_len;
 562         void *ip_p;
 563
 564         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 565
 566         tot_len = cqe_bcnt - network_depth;
 567         ip_p = skb->data + network_depth;
 568
 569         if (proto == htons(ETH_P_IP)) {
 570                 struct iphdr *ipv4 = ip_p;
 571
 572                 tcp = ip_p + sizeof(struct iphdr);
 573                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 574
 575                 ipv4->ttl               = cqe->lro_min_ttl;
 576                 ipv4->tot_len           = cpu_to_be16(tot_len);
 577                 ipv4->check             = 0;
 578                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 579                                                        ipv4->ihl);
 580
 581                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 582                 check = csum_partial(tcp, tcp->doff * 4,
 583                                      csum_unfold((__force __sum16)cqe->check_sum));
 584                 /* Almost done, don't forget the pseudo header */
 585                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 586                                                tot_len - sizeof(struct iphdr),
 587                                                IPPROTO_TCP, check);
 588         } else {
 589                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 590                 struct ipv6hdr *ipv6 = ip_p;
 591
 592                 tcp = ip_p + sizeof(struct ipv6hdr);
 593                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 594
 595                 ipv6->hop_limit         = cqe->lro_min_ttl;
 596                 ipv6->payload_len       = cpu_to_be16(payload_len);
 597
 598                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 599                 check = csum_partial(tcp, tcp->doff * 4,
 600                                      csum_unfold((__force __sum16)cqe->check_sum));
 601                 /* Almost done, don't forget the pseudo header */
 602                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 603                                              IPPROTO_TCP, check);
 604         }
 605 }
 606
 607 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 608                                       struct sk_buff *skb)
 609 {
 610         u8 cht = cqe->rss_hash_type;
 611         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 612                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 613                                             PKT_HASH_TYPE_NONE;
 614         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 615 }
 616
 617 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
 618 {
 619         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
 620
 621         ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
 622         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
 623 }
 624
 625 static inline void mlx5e_handle_csum(struct net_device *netdev,
 626                                      struct mlx5_cqe64 *cqe,
 627                                      struct mlx5e_rq *rq,
 628                                      struct sk_buff *skb,
 629                                      bool   lro)
 630 {
 631         int network_depth = 0;
 632
 633         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 634                 goto csum_none;
 635
 636         if (lro) {
 637                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 638                 rq->stats.csum_unnecessary++;
 639                 return;
 640         }
 641
 642         if (likely(is_last_ethertype_ip(skb, &network_depth))) {
 643                 skb->ip_summed = CHECKSUM_COMPLETE;
 644                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 645                 if (network_depth > ETH_HLEN)
 646                         /* CQE csum is calculated from the IP header and does
 647                          * not cover VLAN headers (if present). This will add
 648                          * the checksum manually.
 649                          */
 650                         skb->csum = csum_partial(skb->data + ETH_HLEN,
 651                                                  network_depth - ETH_HLEN,
 652                                                  skb->csum);
 653                 rq->stats.csum_complete++;
 654                 return;
 655         }
 656
 657         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 658                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 659                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 660                 if (cqe_is_tunneled(cqe)) {
 661                         skb->csum_level = 1;
 662                         skb->encapsulation = 1;
 663                         rq->stats.csum_unnecessary_inner++;
 664                         return;
 665                 }
 666                 rq->stats.csum_unnecessary++;
 667                 return;
 668         }
 669 csum_none:
 670         skb->ip_summed = CHECKSUM_NONE;
 671         rq->stats.csum_none++;
 672 }
 673
 674 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 675                                       u32 cqe_bcnt,
 676                                       struct mlx5e_rq *rq,
 677                                       struct sk_buff *skb)
 678 {
 679         struct net_device *netdev = rq->netdev;
 680         int lro_num_seg;
 681
 682         skb->mac_len = ETH_HLEN;
 683         lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 684         if (lro_num_seg > 1) {
 685                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 686                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 687                 /* Subtract one since we already counted this as one
 688                  * "regular" packet in mlx5e_complete_rx_cqe()
 689                  */
 690                 rq->stats.packets += lro_num_seg - 1;
 691                 rq->stats.lro_packets++;
 692                 rq->stats.lro_bytes += cqe_bcnt;
 693         }
 694
 695         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
 696                 skb_hwtstamps(skb)->hwtstamp =
 697                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
 698
 699         skb_record_rx_queue(skb, rq->ix);
 700
 701         if (likely(netdev->features & NETIF_F_RXHASH))
 702                 mlx5e_skb_set_hash(cqe, skb);
 703
 704         if (cqe_has_vlan(cqe)) {
 705                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 706                                        be16_to_cpu(cqe->vlan_info));
 707                 rq->stats.removed_vlan_packets++;
 708         }
 709
 710         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 711
 712         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 713         skb->protocol = eth_type_trans(skb, netdev);
 714 }
 715
 716 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 717                                          struct mlx5_cqe64 *cqe,
 718                                          u32 cqe_bcnt,
 719                                          struct sk_buff *skb)
 720 {
 721         rq->stats.packets++;
 722         rq->stats.bytes += cqe_bcnt;
 723         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 724 }
 725
 726 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
 727 {
 728         struct mlx5_wq_cyc *wq = &sq->wq;
 729         struct mlx5e_tx_wqe *wqe;
 730         u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */
 731
 732         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 733
 734         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
 735 }
 736
 737 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
 738                                         struct mlx5e_dma_info *di,
 739                                         const struct xdp_buff *xdp)
 740 {
 741         struct mlx5e_xdpsq       *sq   = &rq->xdpsq;
 742         struct mlx5_wq_cyc       *wq   = &sq->wq;
 743         u16                       pi   = sq->pc & wq->sz_m1;
 744         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 745
 746         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
 747         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
 748         struct mlx5_wqe_data_seg *dseg;
 749
 750         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
 751         dma_addr_t dma_addr  = di->addr + data_offset;
 752         unsigned int dma_len = xdp->data_end - xdp->data;
 753
 754         prefetchw(wqe);
 755
 756         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || rq->hw_mtu < dma_len)) {
 757                 rq->stats.xdp_drop++;
 758                 return false;
 759         }
 760
 761         if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
 762                 if (sq->db.doorbell) {
 763                         /* SQ is full, ring doorbell */
 764                         mlx5e_xmit_xdp_doorbell(sq);
 765                         sq->db.doorbell = false;
 766                 }
 767                 rq->stats.xdp_tx_full++;
 768                 return false;
 769         }
 770
 771         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
 772
 773         cseg->fm_ce_se = 0;
 774
 775         dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
 776
 777         /* copy the inline part if required */
 778         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
 779                 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
 780                 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
 781                 dma_len  -= MLX5E_XDP_MIN_INLINE;
 782                 dma_addr += MLX5E_XDP_MIN_INLINE;
 783                 dseg++;
 784         }
 785
 786         /* write the dma part */
 787         dseg->addr       = cpu_to_be64(dma_addr);
 788         dseg->byte_count = cpu_to_be32(dma_len);
 789
 790         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
 791
 792         /* move page to reference to sq responsibility,
 793          * and mark so it's not put back in page-cache.
 794          */
 795         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
 796         sq->db.di[pi] = *di;
 797         sq->pc++;
 798
 799         sq->db.doorbell = true;
 800
 801         rq->stats.xdp_tx++;
 802         return true;
 803 }
 804
 805 /* returns true if packet was consumed by xdp */
 806 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq,
 807                                    struct mlx5e_dma_info *di,
 808                                    void *va, u16 *rx_headroom, u32 *len)
 809 {
 810         const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
 811         struct xdp_buff xdp;
 812         u32 act;
 813
 814         if (!prog)
 815                 return false;
 816
 817         xdp.data = va + *rx_headroom;
 818         xdp_set_data_meta_invalid(&xdp);
 819         xdp.data_end = xdp.data + *len;
 820         xdp.data_hard_start = va;
 821         xdp.rxq = &rq->xdp_rxq;
 822
 823         act = bpf_prog_run_xdp(prog, &xdp);
 824         switch (act) {
 825         case XDP_PASS:
 826                 *rx_headroom = xdp.data - xdp.data_hard_start;
 827                 *len = xdp.data_end - xdp.data;
 828                 return false;
 829         case XDP_TX:
 830                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
 831                         trace_xdp_exception(rq->netdev, prog, act);
 832                 return true;
 833         default:
 834                 bpf_warn_invalid_xdp_action(act);
 835         case XDP_ABORTED:
 836                 trace_xdp_exception(rq->netdev, prog, act);
 837         case XDP_DROP:
 838                 rq->stats.xdp_drop++;
 839                 return true;
 840         }
 841 }
 842
 843 static inline
 844 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
 845                                        u32 frag_size, u16 headroom,
 846                                        u32 cqe_bcnt)
 847 {
 848         struct sk_buff *skb = build_skb(va, frag_size);
 849
 850         if (unlikely(!skb)) {
 851                 rq->stats.buff_alloc_err++;
 852                 return NULL;
 853         }
 854
 855         skb_reserve(skb, headroom);
 856         skb_put(skb, cqe_bcnt);
 857
 858         return skb;
 859 }
 860
 861 static inline
 862 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 863                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 864 {
 865         struct mlx5e_dma_info *di = &wi->di;
 866         u16 rx_headroom = rq->buff.headroom;
 867         struct sk_buff *skb;
 868         void *va, *data;
 869         bool consumed;
 870         u32 frag_size;
 871
 872         va             = page_address(di->page) + wi->offset;
 873         data           = va + rx_headroom;
 874         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
 875
 876         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
 877                                       frag_size, DMA_FROM_DEVICE);
 878         prefetch(data);
 879         wi->offset += frag_size;
 880
 881         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 882                 rq->stats.wqe_err++;
 883                 return NULL;
 884         }
 885
 886         rcu_read_lock();
 887         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
 888         rcu_read_unlock();
 889         if (consumed)
 890                 return NULL; /* page/packet was consumed by XDP */
 891
 892         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
 893         if (unlikely(!skb))
 894                 return NULL;
 895
 896         /* queue up for recycling/reuse */
 897         page_ref_inc(di->page);
 898
 899         return skb;
 900 }
 901
 902 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 903 {
 904         struct mlx5e_wqe_frag_info *wi;
 905         struct mlx5e_rx_wqe *wqe;
 906         __be16 wqe_counter_be;
 907         struct sk_buff *skb;
 908         u16 wqe_counter;
 909         u32 cqe_bcnt;
 910
 911         wqe_counter_be = cqe->wqe_counter;
 912         wqe_counter    = be16_to_cpu(wqe_counter_be);
 913         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 914         wi             = &rq->wqe.frag_info[wqe_counter];
 915         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 916
 917         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 918         if (!skb) {
 919                 /* probably for XDP */
 920                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
 921                         wi->di.page = NULL;
 922                         /* do not return page to cache, it will be returned on XDP_TX completion */
 923                         goto wq_ll_pop;
 924                 }
 925                 /* probably an XDP_DROP, save the page-reuse checks */
 926                 mlx5e_free_rx_wqe(rq, wi);
 927                 goto wq_ll_pop;
 928         }
 929
 930         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 931         napi_gro_receive(rq->cq.napi, skb);
 932
 933         mlx5e_free_rx_wqe_reuse(rq, wi);
 934 wq_ll_pop:
 935         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 936                        &wqe->next.next_wqe_index);
 937 }
 938
 939 #ifdef CONFIG_MLX5_ESWITCH
 940 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 941 {
 942         struct net_device *netdev = rq->netdev;
 943         struct mlx5e_priv *priv = netdev_priv(netdev);
 944         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
 945         struct mlx5_eswitch_rep *rep = rpriv->rep;
 946         struct mlx5e_wqe_frag_info *wi;
 947         struct mlx5e_rx_wqe *wqe;
 948         struct sk_buff *skb;
 949         __be16 wqe_counter_be;
 950         u16 wqe_counter;
 951         u32 cqe_bcnt;
 952
 953         wqe_counter_be = cqe->wqe_counter;
 954         wqe_counter    = be16_to_cpu(wqe_counter_be);
 955         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 956         wi             = &rq->wqe.frag_info[wqe_counter];
 957         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 958
 959         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 960         if (!skb) {
 961                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
 962                         wi->di.page = NULL;
 963                         /* do not return page to cache, it will be returned on XDP_TX completion */
 964                         goto wq_ll_pop;
 965                 }
 966                 /* probably an XDP_DROP, save the page-reuse checks */
 967                 mlx5e_free_rx_wqe(rq, wi);
 968                 goto wq_ll_pop;
 969         }
 970
 971         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 972
 973         if (rep->vlan && skb_vlan_tag_present(skb))
 974                 skb_vlan_pop(skb);
 975
 976         napi_gro_receive(rq->cq.napi, skb);
 977
 978         mlx5e_free_rx_wqe_reuse(rq, wi);
 979 wq_ll_pop:
 980         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 981                        &wqe->next.next_wqe_index);
 982 }
 983 #endif
 984
 985 struct sk_buff *
 986 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
 987                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
 988 {
 989         u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
 990         u32 frag_offset    = head_offset + headlen;
 991         u16 byte_cnt       = cqe_bcnt - headlen;
 992         u32 head_page_idx  = page_idx;
 993         struct sk_buff *skb;
 994
 995         skb = napi_alloc_skb(rq->cq.napi,
 996                              ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, sizeof(long)));
 997         if (unlikely(!skb)) {
 998                 rq->stats.buff_alloc_err++;
 999                 return NULL;
1000         }
1001
1002         prefetchw(skb->data);
1003
1004         if (unlikely(frag_offset >= PAGE_SIZE)) {
1005                 page_idx++;
1006                 frag_offset -= PAGE_SIZE;
1007         }
1008
1009         while (byte_cnt) {
1010                 u32 pg_consumed_bytes =
1011                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1012
1013                 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
1014                                          pg_consumed_bytes);
1015                 byte_cnt -= pg_consumed_bytes;
1016                 frag_offset = 0;
1017                 page_idx++;
1018         }
1019         /* copy header */
1020         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
1021                                     head_offset, headlen);
1022         /* skb linear part was allocated with headlen and aligned to long */
1023         skb->tail += headlen;
1024         skb->len  += headlen;
1025
1026         return skb;
1027 }
1028
1029 struct sk_buff *
1030 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1031                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1032 {
1033         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1034         u16 rx_headroom = rq->buff.headroom;
1035         u32 cqe_bcnt32 = cqe_bcnt;
1036         struct sk_buff *skb;
1037         void *va, *data;
1038         u32 frag_size;
1039         bool consumed;
1040
1041         va             = page_address(di->page) + head_offset;
1042         data           = va + rx_headroom;
1043         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1044
1045         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1046                                       frag_size, DMA_FROM_DEVICE);
1047         prefetch(data);
1048
1049         rcu_read_lock();
1050         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1051         rcu_read_unlock();
1052         if (consumed) {
1053                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1054                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1055                 return NULL; /* page/packet was consumed by XDP */
1056         }
1057
1058         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1059         if (unlikely(!skb))
1060                 return NULL;
1061
1062         /* queue up for recycling/reuse */
1063         wi->skbs_frags[page_idx]++;
1064
1065         return skb;
1066 }
1067
1068 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1069 {
1070         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1071         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1072         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1073         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1074         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1075         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1076         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1077         struct mlx5e_rx_wqe *wqe;
1078         struct sk_buff *skb;
1079         u16 cqe_bcnt;
1080
1081         wi->consumed_strides += cstrides;
1082
1083         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1084                 rq->stats.wqe_err++;
1085                 goto mpwrq_cqe_out;
1086         }
1087
1088         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1089                 rq->stats.mpwqe_filler++;
1090                 goto mpwrq_cqe_out;
1091         }
1092
1093         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1094
1095         skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1096                                            page_idx);
1097         if (!skb)
1098                 goto mpwrq_cqe_out;
1099
1100         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1101         napi_gro_receive(rq->cq.napi, skb);
1102
1103 mpwrq_cqe_out:
1104         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1105                 return;
1106
1107         wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
1108         mlx5e_free_rx_mpwqe(rq, wi);
1109         mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1110 }
1111
1112 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1113 {
1114         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1115         struct mlx5e_xdpsq *xdpsq;
1116         struct mlx5_cqe64 *cqe;
1117         int work_done = 0;
1118
1119         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
1120                 return 0;
1121
1122         if (cq->decmprs_left)
1123                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1124
1125         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1126         if (!cqe)
1127                 return 0;
1128
1129         xdpsq = &rq->xdpsq;
1130
1131         do {
1132                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1133                         work_done +=
1134                                 mlx5e_decompress_cqes_start(rq, cq,
1135                                                             budget - work_done);
1136                         continue;
1137                 }
1138
1139                 mlx5_cqwq_pop(&cq->wq);
1140
1141                 rq->handle_rx_cqe(rq, cqe);
1142         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1143
1144         if (xdpsq->db.doorbell) {
1145                 mlx5e_xmit_xdp_doorbell(xdpsq);
1146                 xdpsq->db.doorbell = false;
1147         }
1148
1149         mlx5_cqwq_update_db_record(&cq->wq);
1150
1151         /* ensure cq space is freed before enabling more cqes */
1152         wmb();
1153
1154         return work_done;
1155 }
1156
1157 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1158 {
1159         struct mlx5e_xdpsq *sq;
1160         struct mlx5_cqe64 *cqe;
1161         struct mlx5e_rq *rq;
1162         u16 sqcc;
1163         int i;
1164
1165         sq = container_of(cq, struct mlx5e_xdpsq, cq);
1166
1167         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
1168                 return false;
1169
1170         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1171         if (!cqe)
1172                 return false;
1173
1174         rq = container_of(sq, struct mlx5e_rq, xdpsq);
1175
1176         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1177          * otherwise a cq overrun may occur
1178          */
1179         sqcc = sq->cc;
1180
1181         i = 0;
1182         do {
1183                 u16 wqe_counter;
1184                 bool last_wqe;
1185
1186                 mlx5_cqwq_pop(&cq->wq);
1187
1188                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1189
1190                 do {
1191                         struct mlx5e_dma_info *di;
1192                         u16 ci;
1193
1194                         last_wqe = (sqcc == wqe_counter);
1195
1196                         ci = sqcc & sq->wq.sz_m1;
1197                         di = &sq->db.di[ci];
1198
1199                         sqcc++;
1200                         /* Recycle RX page */
1201                         mlx5e_page_release(rq, di, true);
1202                 } while (!last_wqe);
1203         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1204
1205         mlx5_cqwq_update_db_record(&cq->wq);
1206
1207         /* ensure cq space is freed before enabling more cqes */
1208         wmb();
1209
1210         sq->cc = sqcc;
1211         return (i == MLX5E_TX_CQ_POLL_BUDGET);
1212 }
1213
1214 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1215 {
1216         struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1217         struct mlx5e_dma_info *di;
1218         u16 ci;
1219
1220         while (sq->cc != sq->pc) {
1221                 ci = sq->cc & sq->wq.sz_m1;
1222                 di = &sq->db.di[ci];
1223                 sq->cc++;
1224
1225                 mlx5e_page_release(rq, di, false);
1226         }
1227 }
1228
1229 #ifdef CONFIG_MLX5_CORE_IPOIB
1230
1231 #define MLX5_IB_GRH_DGID_OFFSET 24
1232 #define MLX5_GID_SIZE           16
1233
1234 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1235                                          struct mlx5_cqe64 *cqe,
1236                                          u32 cqe_bcnt,
1237                                          struct sk_buff *skb)
1238 {
1239         struct hwtstamp_config *tstamp;
1240         struct net_device *netdev;
1241         struct mlx5e_priv *priv;
1242         char *pseudo_header;
1243         u32 qpn;
1244         u8 *dgid;
1245         u8 g;
1246
1247         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1248         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1249
1250         /* No mapping present, cannot process SKB. This might happen if a child
1251          * interface is going down while having unprocessed CQEs on parent RQ
1252          */
1253         if (unlikely(!netdev)) {
1254                 /* TODO: add drop counters support */
1255                 skb->dev = NULL;
1256                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1257                 return;
1258         }
1259
1260         priv = mlx5i_epriv(netdev);
1261         tstamp = &priv->tstamp;
1262
1263         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1264         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1265         if ((!g) || dgid[0] != 0xff)
1266                 skb->pkt_type = PACKET_HOST;
1267         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1268                 skb->pkt_type = PACKET_BROADCAST;
1269         else
1270                 skb->pkt_type = PACKET_MULTICAST;
1271
1272         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1273          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1274          */
1275
1276         skb_pull(skb, MLX5_IB_GRH_BYTES);
1277
1278         skb->protocol = *((__be16 *)(skb->data));
1279
1280         skb->ip_summed = CHECKSUM_COMPLETE;
1281         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1282
1283         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1284                 skb_hwtstamps(skb)->hwtstamp =
1285                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1286
1287         skb_record_rx_queue(skb, rq->ix);
1288
1289         if (likely(netdev->features & NETIF_F_RXHASH))
1290                 mlx5e_skb_set_hash(cqe, skb);
1291
1292         /* 20 bytes of ipoib header and 4 for encap existing */
1293         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1294         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1295         skb_reset_mac_header(skb);
1296         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1297
1298         skb->dev = netdev;
1299
1300         rq->stats.csum_complete++;
1301         rq->stats.packets++;
1302         rq->stats.bytes += cqe_bcnt;
1303 }
1304
1305 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1306 {
1307         struct mlx5e_wqe_frag_info *wi;
1308         struct mlx5e_rx_wqe *wqe;
1309         __be16 wqe_counter_be;
1310         struct sk_buff *skb;
1311         u16 wqe_counter;
1312         u32 cqe_bcnt;
1313
1314         wqe_counter_be = cqe->wqe_counter;
1315         wqe_counter    = be16_to_cpu(wqe_counter_be);
1316         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1317         wi             = &rq->wqe.frag_info[wqe_counter];
1318         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1319
1320         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1321         if (!skb)
1322                 goto wq_free_wqe;
1323
1324         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1325         if (unlikely(!skb->dev)) {
1326                 dev_kfree_skb_any(skb);
1327                 goto wq_free_wqe;
1328         }
1329         napi_gro_receive(rq->cq.napi, skb);
1330
1331 wq_free_wqe:
1332         mlx5e_free_rx_wqe_reuse(rq, wi);
1333         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1334                        &wqe->next.next_wqe_index);
1335 }
1336
1337 #endif /* CONFIG_MLX5_CORE_IPOIB */
1338
1339 #ifdef CONFIG_MLX5_EN_IPSEC
1340
1341 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1342 {
1343         struct mlx5e_wqe_frag_info *wi;
1344         struct mlx5e_rx_wqe *wqe;
1345         __be16 wqe_counter_be;
1346         struct sk_buff *skb;
1347         u16 wqe_counter;
1348         u32 cqe_bcnt;
1349
1350         wqe_counter_be = cqe->wqe_counter;
1351         wqe_counter    = be16_to_cpu(wqe_counter_be);
1352         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1353         wi             = &rq->wqe.frag_info[wqe_counter];
1354         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1355
1356         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1357         if (unlikely(!skb)) {
1358                 /* a DROP, save the page-reuse checks */
1359                 mlx5e_free_rx_wqe(rq, wi);
1360                 goto wq_ll_pop;
1361         }
1362         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1363         if (unlikely(!skb)) {
1364                 mlx5e_free_rx_wqe(rq, wi);
1365                 goto wq_ll_pop;
1366         }
1367
1368         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1369         napi_gro_receive(rq->cq.napi, skb);
1370
1371         mlx5e_free_rx_wqe_reuse(rq, wi);
1372 wq_ll_pop:
1373         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1374                        &wqe->next.next_wqe_index);
1375 }
1376
1377 #endif /* CONFIG_MLX5_EN_IPSEC */