drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <linux/bpf_trace.h>
  38 #include <net/busy_poll.h>
  39 #include <net/ip6_checksum.h>
  40 #include <net/page_pool.h>
  41 #include "en.h"
  42 #include "en_tc.h"
  43 #include "eswitch.h"
  44 #include "en_rep.h"
  45 #include "ipoib/ipoib.h"
  46 #include "en_accel/ipsec_rxtx.h"
  47 #include "en_accel/tls_rxtx.h"
  48 #include "lib/clock.h"
  49
  50 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  51 {
  52         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  53 }
  54
  55 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
  56                                        void *data)
  57 {
  58         u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc);
  59
  60         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
  61 }
  62
  63 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  64                                          struct mlx5e_cq *cq, u32 cqcc)
  65 {
  66         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
  67         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
  68         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
  69         rq->stats->cqe_compress_blks++;
  70 }
  71
  72 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
  73 {
  74         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
  75         cq->mini_arr_idx = 0;
  76 }
  77
  78 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
  79 {
  80         struct mlx5_cqwq *wq = &cq->wq;
  81
  82         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
  83         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
  84         u32 wq_sz  = mlx5_cqwq_get_size(wq);
  85         u32 ci_top = min_t(u32, wq_sz, ci + n);
  86
  87         for (; ci < ci_top; ci++, n--) {
  88                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  89
  90                 cqe->op_own = op_own;
  91         }
  92
  93         if (unlikely(ci == wq_sz)) {
  94                 op_own = !op_own;
  95                 for (ci = 0; ci < n; ci++) {
  96                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  97
  98                         cqe->op_own = op_own;
  99                 }
 100         }
 101 }
 102
 103 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 104                                         struct mlx5e_cq *cq, u32 cqcc)
 105 {
 106         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
 107         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
 108         cq->title.op_own      &= 0xf0;
 109         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
 110         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
 111
 112         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 113                 cq->decmprs_wqe_counter +=
 114                         mpwrq_get_cqe_consumed_strides(&cq->title);
 115         else
 116                 cq->decmprs_wqe_counter =
 117                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cq->decmprs_wqe_counter + 1);
 118 }
 119
 120 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 121                                                 struct mlx5e_cq *cq, u32 cqcc)
 122 {
 123         mlx5e_decompress_cqe(rq, cq, cqcc);
 124         cq->title.rss_hash_type   = 0;
 125         cq->title.rss_hash_result = 0;
 126 }
 127
 128 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 129                                              struct mlx5e_cq *cq,
 130                                              int update_owner_only,
 131                                              int budget_rem)
 132 {
 133         u32 cqcc = cq->wq.cc + update_owner_only;
 134         u32 cqe_count;
 135         u32 i;
 136
 137         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
 138
 139         for (i = update_owner_only; i < cqe_count;
 140              i++, cq->mini_arr_idx++, cqcc++) {
 141                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 142                         mlx5e_read_mini_arr_slot(cq, cqcc);
 143
 144                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
 145                 rq->handle_rx_cqe(rq, &cq->title);
 146         }
 147         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
 148         cq->wq.cc = cqcc;
 149         cq->decmprs_left -= cqe_count;
 150         rq->stats->cqe_compress_pkts += cqe_count;
 151
 152         return cqe_count;
 153 }
 154
 155 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 156                                               struct mlx5e_cq *cq,
 157                                               int budget_rem)
 158 {
 159         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
 160         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
 161         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
 162         rq->handle_rx_cqe(rq, &cq->title);
 163         cq->mini_arr_idx++;
 164
 165         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
 166 }
 167
 168 static inline bool mlx5e_page_is_reserved(struct page *page)
 169 {
 170         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 171 }
 172
 173 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 174                                       struct mlx5e_dma_info *dma_info)
 175 {
 176         struct mlx5e_page_cache *cache = &rq->page_cache;
 177         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 178         struct mlx5e_rq_stats *stats = rq->stats;
 179
 180         if (tail_next == cache->head) {
 181                 stats->cache_full++;
 182                 return false;
 183         }
 184
 185         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 186                 stats->cache_waive++;
 187                 return false;
 188         }
 189
 190         cache->page_cache[cache->tail] = *dma_info;
 191         cache->tail = tail_next;
 192         return true;
 193 }
 194
 195 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 196                                       struct mlx5e_dma_info *dma_info)
 197 {
 198         struct mlx5e_page_cache *cache = &rq->page_cache;
 199         struct mlx5e_rq_stats *stats = rq->stats;
 200
 201         if (unlikely(cache->head == cache->tail)) {
 202                 stats->cache_empty++;
 203                 return false;
 204         }
 205
 206         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 207                 stats->cache_busy++;
 208                 return false;
 209         }
 210
 211         *dma_info = cache->page_cache[cache->head];
 212         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 213         stats->cache_reuse++;
 214
 215         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 216                                    PAGE_SIZE,
 217                                    DMA_FROM_DEVICE);
 218         return true;
 219 }
 220
 221 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
 222                                           struct mlx5e_dma_info *dma_info)
 223 {
 224         if (mlx5e_rx_cache_get(rq, dma_info))
 225                 return 0;
 226
 227         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
 228         if (unlikely(!dma_info->page))
 229                 return -ENOMEM;
 230
 231         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 232                                       PAGE_SIZE, rq->buff.map_dir);
 233         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 234                 put_page(dma_info->page);
 235                 dma_info->page = NULL;
 236                 return -ENOMEM;
 237         }
 238
 239         return 0;
 240 }
 241
 242 static void mlx5e_page_dma_unmap(struct mlx5e_rq *rq,
 243                                         struct mlx5e_dma_info *dma_info)
 244 {
 245         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
 246 }
 247
 248 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 249                         bool recycle)
 250 {
 251         if (likely(recycle)) {
 252                 if (mlx5e_rx_cache_put(rq, dma_info))
 253                         return;
 254
 255                 mlx5e_page_dma_unmap(rq, dma_info);
 256                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 257         } else {
 258                 mlx5e_page_dma_unmap(rq, dma_info);
 259                 put_page(dma_info->page);
 260         }
 261 }
 262
 263 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
 264                                     struct mlx5e_wqe_frag_info *frag)
 265 {
 266         int err = 0;
 267
 268         if (!frag->offset)
 269                 /* On first frag (offset == 0), replenish page (dma_info actually).
 270                  * Other frags that point to the same dma_info (with a different
 271                  * offset) should just use the new one without replenishing again
 272                  * by themselves.
 273                  */
 274                 err = mlx5e_page_alloc_mapped(rq, frag->di);
 275
 276         return err;
 277 }
 278
 279 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
 280                                      struct mlx5e_wqe_frag_info *frag)
 281 {
 282         if (frag->last_in_page)
 283                 mlx5e_page_release(rq, frag->di, true);
 284 }
 285
 286 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
 287 {
 288         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
 289 }
 290
 291 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
 292                               u16 ix)
 293 {
 294         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
 295         int err;
 296         int i;
 297
 298         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
 299                 err = mlx5e_get_rx_frag(rq, frag);
 300                 if (unlikely(err))
 301                         goto free_frags;
 302
 303                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
 304                                                 frag->offset + rq->buff.headroom);
 305         }
 306
 307         return 0;
 308
 309 free_frags:
 310         while (--i >= 0)
 311                 mlx5e_put_rx_frag(rq, --frag);
 312
 313         return err;
 314 }
 315
 316 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 317                                      struct mlx5e_wqe_frag_info *wi)
 318 {
 319         int i;
 320
 321         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
 322                 mlx5e_put_rx_frag(rq, wi);
 323 }
 324
 325 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 326 {
 327         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
 328
 329         mlx5e_free_rx_wqe(rq, wi);
 330 }
 331
 332 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
 333 {
 334         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 335         int err;
 336         int i;
 337
 338         for (i = 0; i < wqe_bulk; i++) {
 339                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
 340
 341                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
 342                 if (unlikely(err))
 343                         goto free_wqes;
 344         }
 345
 346         return 0;
 347
 348 free_wqes:
 349         while (--i >= 0)
 350                 mlx5e_dealloc_rx_wqe(rq, ix + i);
 351
 352         return err;
 353 }
 354
 355 static inline void
 356 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
 357                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
 358                    unsigned int truesize)
 359 {
 360         dma_sync_single_for_cpu(rq->pdev,
 361                                 di->addr + frag_offset,
 362                                 len, DMA_FROM_DEVICE);
 363         page_ref_inc(di->page);
 364         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 365                         di->page, frag_offset, len, truesize);
 366 }
 367
 368 static inline void
 369 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
 370                       struct mlx5e_dma_info *dma_info,
 371                       int offset_from, int offset_to, u32 headlen)
 372 {
 373         const void *from = page_address(dma_info->page) + offset_from;
 374         /* Aligning len to sizeof(long) optimizes memcpy performance */
 375         unsigned int len = ALIGN(headlen, sizeof(long));
 376
 377         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
 378                                 DMA_FROM_DEVICE);
 379         skb_copy_to_linear_data_offset(skb, offset_to, from, len);
 380 }
 381
 382 static inline void
 383 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
 384                             struct sk_buff *skb,
 385                             struct mlx5e_dma_info *dma_info,
 386                             u32 offset, u32 headlen)
 387 {
 388         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
 389
 390         mlx5e_copy_skb_header(pdev, skb, dma_info, offset, 0, headlen_pg);
 391
 392         if (unlikely(offset + headlen > PAGE_SIZE)) {
 393                 dma_info++;
 394                 mlx5e_copy_skb_header(pdev, skb, dma_info, 0, headlen_pg,
 395                                       headlen - headlen_pg);
 396         }
 397 }
 398
 399 static void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
 400 {
 401         const bool no_xdp_xmit =
 402                 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 403         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
 404         int i;
 405
 406         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
 407                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
 408                         mlx5e_page_release(rq, &dma_info[i], true);
 409 }
 410
 411 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
 412 {
 413         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 414         struct mlx5e_rx_wqe_ll *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 415
 416         rq->mpwqe.umr_in_progress = false;
 417
 418         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 419
 420         /* ensure wqes are visible to device before updating doorbell record */
 421         dma_wmb();
 422
 423         mlx5_wq_ll_update_db_record(wq);
 424 }
 425
 426 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
 427 {
 428         return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
 429 }
 430
 431 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
 432                                               struct mlx5_wq_cyc *wq,
 433                                               u16 pi, u16 frag_pi)
 434 {
 435         struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
 436         u8 nnops = mlx5_wq_cyc_get_frag_size(wq) - frag_pi;
 437
 438         edge_wi = wi + nnops;
 439
 440         /* fill sq frag edge with nops to avoid wqe wrapping two pages */
 441         for (; wi < edge_wi; wi++) {
 442                 wi->opcode = MLX5_OPCODE_NOP;
 443                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 444         }
 445 }
 446
 447 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 448 {
 449         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 450         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 451         struct mlx5e_icosq *sq = &rq->channel->icosq;
 452         struct mlx5_wq_cyc *wq = &sq->wq;
 453         struct mlx5e_umr_wqe *umr_wqe;
 454         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
 455         u16 pi, frag_pi;
 456         int err;
 457         int i;
 458
 459         pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 460         frag_pi = mlx5_wq_cyc_ctr2fragix(wq, sq->pc);
 461
 462         if (unlikely(frag_pi + MLX5E_UMR_WQEBBS > mlx5_wq_cyc_get_frag_size(wq))) {
 463                 mlx5e_fill_icosq_frag_edge(sq, wq, pi, frag_pi);
 464                 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 465         }
 466
 467         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 468         if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
 469                 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
 470                        offsetof(struct mlx5e_umr_wqe, inline_mtts));
 471
 472         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 473                 err = mlx5e_page_alloc_mapped(rq, dma_info);
 474                 if (unlikely(err))
 475                         goto err_unmap;
 476                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 477         }
 478
 479         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 480         wi->consumed_strides = 0;
 481
 482         rq->mpwqe.umr_in_progress = true;
 483
 484         umr_wqe->ctrl.opmod_idx_opcode =
 485                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 486                             MLX5_OPCODE_UMR);
 487         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
 488
 489         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 490         sq->pc += MLX5E_UMR_WQEBBS;
 491         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
 492
 493         return 0;
 494
 495 err_unmap:
 496         while (--i >= 0) {
 497                 dma_info--;
 498                 mlx5e_page_release(rq, dma_info, true);
 499         }
 500         rq->stats->buff_alloc_err++;
 501
 502         return err;
 503 }
 504
 505 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 506 {
 507         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 508
 509         mlx5e_free_rx_mpwqe(rq, wi);
 510 }
 511
 512 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 513 {
 514         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 515         u8 wqe_bulk;
 516         int err;
 517
 518         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 519                 return false;
 520
 521         wqe_bulk = rq->wqe.info.wqe_bulk;
 522
 523         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
 524                 return false;
 525
 526         do {
 527                 u16 head = mlx5_wq_cyc_get_head(wq);
 528
 529                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
 530                 if (unlikely(err)) {
 531                         rq->stats->buff_alloc_err++;
 532                         break;
 533                 }
 534
 535                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
 536         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
 537
 538         /* ensure wqes are visible to device before updating doorbell record */
 539         dma_wmb();
 540
 541         mlx5_wq_cyc_update_db_record(wq);
 542
 543         return !!err;
 544 }
 545
 546 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
 547                                              struct mlx5e_icosq *sq,
 548                                              struct mlx5e_rq *rq,
 549                                              struct mlx5_cqe64 *cqe)
 550 {
 551         struct mlx5_wq_cyc *wq = &sq->wq;
 552         u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
 553         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
 554
 555         mlx5_cqwq_pop(&cq->wq);
 556
 557         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
 558                 netdev_WARN_ONCE(cq->channel->netdev,
 559                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
 560                 return;
 561         }
 562
 563         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
 564                 mlx5e_post_rx_mpwqe(rq);
 565                 return;
 566         }
 567
 568         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
 569                 netdev_WARN_ONCE(cq->channel->netdev,
 570                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
 571 }
 572
 573 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
 574 {
 575         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 576         struct mlx5_cqe64 *cqe;
 577
 578         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
 579                 return;
 580
 581         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 582         if (likely(!cqe))
 583                 return;
 584
 585         /* by design, there's only a single cqe */
 586         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
 587
 588         mlx5_cqwq_update_db_record(&cq->wq);
 589 }
 590
 591 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 592 {
 593         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 594
 595         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 596                 return false;
 597
 598         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
 599
 600         if (mlx5_wq_ll_is_full(wq))
 601                 return false;
 602
 603         if (!rq->mpwqe.umr_in_progress)
 604                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
 605         else
 606                 rq->stats->congst_umr += mlx5_wq_ll_missing(wq) > 2;
 607
 608         return false;
 609 }
 610
 611 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 612 {
 613         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 614         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 615                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 616
 617         tcp->check                      = 0;
 618         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 619
 620         if (tcp_ack) {
 621                 tcp->ack                = 1;
 622                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 623                 tcp->window             = cqe->lro_tcp_win;
 624         }
 625 }
 626
 627 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 628                                  u32 cqe_bcnt)
 629 {
 630         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 631         struct tcphdr   *tcp;
 632         int network_depth = 0;
 633         __wsum check;
 634         __be16 proto;
 635         u16 tot_len;
 636         void *ip_p;
 637
 638         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 639
 640         tot_len = cqe_bcnt - network_depth;
 641         ip_p = skb->data + network_depth;
 642
 643         if (proto == htons(ETH_P_IP)) {
 644                 struct iphdr *ipv4 = ip_p;
 645
 646                 tcp = ip_p + sizeof(struct iphdr);
 647                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 648
 649                 ipv4->ttl               = cqe->lro_min_ttl;
 650                 ipv4->tot_len           = cpu_to_be16(tot_len);
 651                 ipv4->check             = 0;
 652                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 653                                                        ipv4->ihl);
 654
 655                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 656                 check = csum_partial(tcp, tcp->doff * 4,
 657                                      csum_unfold((__force __sum16)cqe->check_sum));
 658                 /* Almost done, don't forget the pseudo header */
 659                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 660                                                tot_len - sizeof(struct iphdr),
 661                                                IPPROTO_TCP, check);
 662         } else {
 663                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 664                 struct ipv6hdr *ipv6 = ip_p;
 665
 666                 tcp = ip_p + sizeof(struct ipv6hdr);
 667                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 668
 669                 ipv6->hop_limit         = cqe->lro_min_ttl;
 670                 ipv6->payload_len       = cpu_to_be16(payload_len);
 671
 672                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 673                 check = csum_partial(tcp, tcp->doff * 4,
 674                                      csum_unfold((__force __sum16)cqe->check_sum));
 675                 /* Almost done, don't forget the pseudo header */
 676                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 677                                              IPPROTO_TCP, check);
 678         }
 679 }
 680
 681 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 682                                       struct sk_buff *skb)
 683 {
 684         u8 cht = cqe->rss_hash_type;
 685         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 686                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 687                                             PKT_HASH_TYPE_NONE;
 688         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 689 }
 690
 691 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
 692 {
 693         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
 694
 695         ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
 696         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
 697 }
 698
 699 static __be32 mlx5e_get_fcs(struct sk_buff *skb)
 700 {
 701         int last_frag_sz, bytes_in_prev, nr_frags;
 702         u8 *fcs_p1, *fcs_p2;
 703         skb_frag_t *last_frag;
 704         __be32 fcs_bytes;
 705
 706         if (!skb_is_nonlinear(skb))
 707                 return *(__be32 *)(skb->data + skb->len - ETH_FCS_LEN);
 708
 709         nr_frags = skb_shinfo(skb)->nr_frags;
 710         last_frag = &skb_shinfo(skb)->frags[nr_frags - 1];
 711         last_frag_sz = skb_frag_size(last_frag);
 712
 713         /* If all FCS data is in last frag */
 714         if (last_frag_sz >= ETH_FCS_LEN)
 715                 return *(__be32 *)(skb_frag_address(last_frag) +
 716                                    last_frag_sz - ETH_FCS_LEN);
 717
 718         fcs_p2 = (u8 *)skb_frag_address(last_frag);
 719         bytes_in_prev = ETH_FCS_LEN - last_frag_sz;
 720
 721         /* Find where the other part of the FCS is - Linear or another frag */
 722         if (nr_frags == 1) {
 723                 fcs_p1 = skb_tail_pointer(skb);
 724         } else {
 725                 skb_frag_t *prev_frag = &skb_shinfo(skb)->frags[nr_frags - 2];
 726
 727                 fcs_p1 = skb_frag_address(prev_frag) +
 728                             skb_frag_size(prev_frag);
 729         }
 730         fcs_p1 -= bytes_in_prev;
 731
 732         memcpy(&fcs_bytes, fcs_p1, bytes_in_prev);
 733         memcpy(((u8 *)&fcs_bytes) + bytes_in_prev, fcs_p2, last_frag_sz);
 734
 735         return fcs_bytes;
 736 }
 737
 738 static inline void mlx5e_handle_csum(struct net_device *netdev,
 739                                      struct mlx5_cqe64 *cqe,
 740                                      struct mlx5e_rq *rq,
 741                                      struct sk_buff *skb,
 742                                      bool   lro)
 743 {
 744         struct mlx5e_rq_stats *stats = rq->stats;
 745         int network_depth = 0;
 746
 747         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 748                 goto csum_none;
 749
 750         if (lro) {
 751                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 752                 stats->csum_unnecessary++;
 753                 return;
 754         }
 755
 756         if (likely(is_last_ethertype_ip(skb, &network_depth))) {
 757                 skb->ip_summed = CHECKSUM_COMPLETE;
 758                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 759                 if (network_depth > ETH_HLEN)
 760                         /* CQE csum is calculated from the IP header and does
 761                          * not cover VLAN headers (if present). This will add
 762                          * the checksum manually.
 763                          */
 764                         skb->csum = csum_partial(skb->data + ETH_HLEN,
 765                                                  network_depth - ETH_HLEN,
 766                                                  skb->csum);
 767                 if (unlikely(netdev->features & NETIF_F_RXFCS))
 768                         skb->csum = csum_add(skb->csum,
 769                                              (__force __wsum)mlx5e_get_fcs(skb));
 770                 stats->csum_complete++;
 771                 return;
 772         }
 773
 774         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 775                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 776                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 777                 if (cqe_is_tunneled(cqe)) {
 778                         skb->csum_level = 1;
 779                         skb->encapsulation = 1;
 780                         stats->csum_unnecessary_inner++;
 781                         return;
 782                 }
 783                 stats->csum_unnecessary++;
 784                 return;
 785         }
 786 csum_none:
 787         skb->ip_summed = CHECKSUM_NONE;
 788         stats->csum_none++;
 789 }
 790
 791 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 792                                       u32 cqe_bcnt,
 793                                       struct mlx5e_rq *rq,
 794                                       struct sk_buff *skb)
 795 {
 796         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 797         struct mlx5e_rq_stats *stats = rq->stats;
 798         struct net_device *netdev = rq->netdev;
 799
 800         skb->mac_len = ETH_HLEN;
 801
 802 #ifdef CONFIG_MLX5_EN_TLS
 803         mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
 804 #endif
 805
 806         if (lro_num_seg > 1) {
 807                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 808                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 809                 /* Subtract one since we already counted this as one
 810                  * "regular" packet in mlx5e_complete_rx_cqe()
 811                  */
 812                 stats->packets += lro_num_seg - 1;
 813                 stats->lro_packets++;
 814                 stats->lro_bytes += cqe_bcnt;
 815         }
 816
 817         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
 818                 skb_hwtstamps(skb)->hwtstamp =
 819                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
 820
 821         skb_record_rx_queue(skb, rq->ix);
 822
 823         if (likely(netdev->features & NETIF_F_RXHASH))
 824                 mlx5e_skb_set_hash(cqe, skb);
 825
 826         if (cqe_has_vlan(cqe)) {
 827                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 828                                        be16_to_cpu(cqe->vlan_info));
 829                 stats->removed_vlan_packets++;
 830         }
 831
 832         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 833
 834         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 835         skb->protocol = eth_type_trans(skb, netdev);
 836 }
 837
 838 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 839                                          struct mlx5_cqe64 *cqe,
 840                                          u32 cqe_bcnt,
 841                                          struct sk_buff *skb)
 842 {
 843         struct mlx5e_rq_stats *stats = rq->stats;
 844
 845         stats->packets++;
 846         stats->bytes += cqe_bcnt;
 847         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 848 }
 849
 850 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
 851 {
 852         struct mlx5_wq_cyc *wq = &sq->wq;
 853         struct mlx5e_tx_wqe *wqe;
 854         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc - 1); /* last pi */
 855
 856         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 857
 858         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
 859 }
 860
 861 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
 862                                         struct mlx5e_dma_info *di,
 863                                         const struct xdp_buff *xdp)
 864 {
 865         struct mlx5e_xdpsq       *sq   = &rq->xdpsq;
 866         struct mlx5_wq_cyc       *wq   = &sq->wq;
 867         u16                       pi   = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 868         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 869
 870         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
 871         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
 872         struct mlx5_wqe_data_seg *dseg;
 873
 874         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
 875         dma_addr_t dma_addr  = di->addr + data_offset;
 876         unsigned int dma_len = xdp->data_end - xdp->data;
 877
 878         struct mlx5e_rq_stats *stats = rq->stats;
 879
 880         prefetchw(wqe);
 881
 882         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || rq->hw_mtu < dma_len)) {
 883                 stats->xdp_drop++;
 884                 return false;
 885         }
 886
 887         if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
 888                 if (sq->db.doorbell) {
 889                         /* SQ is full, ring doorbell */
 890                         mlx5e_xmit_xdp_doorbell(sq);
 891                         sq->db.doorbell = false;
 892                 }
 893                 stats->xdp_tx_full++;
 894                 return false;
 895         }
 896
 897         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
 898
 899         cseg->fm_ce_se = 0;
 900
 901         dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
 902
 903         /* copy the inline part if required */
 904         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
 905                 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
 906                 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
 907                 dma_len  -= MLX5E_XDP_MIN_INLINE;
 908                 dma_addr += MLX5E_XDP_MIN_INLINE;
 909                 dseg++;
 910         }
 911
 912         /* write the dma part */
 913         dseg->addr       = cpu_to_be64(dma_addr);
 914         dseg->byte_count = cpu_to_be32(dma_len);
 915
 916         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
 917
 918         /* move page to reference to sq responsibility,
 919          * and mark so it's not put back in page-cache.
 920          */
 921         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
 922         sq->db.di[pi] = *di;
 923         sq->pc++;
 924
 925         sq->db.doorbell = true;
 926
 927         stats->xdp_tx++;
 928         return true;
 929 }
 930
 931 /* returns true if packet was consumed by xdp */
 932 static inline bool mlx5e_xdp_handle(struct mlx5e_rq *rq,
 933                                     struct mlx5e_dma_info *di,
 934                                     void *va, u16 *rx_headroom, u32 *len)
 935 {
 936         struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
 937         struct xdp_buff xdp;
 938         u32 act;
 939         int err;
 940
 941         if (!prog)
 942                 return false;
 943
 944         xdp.data = va + *rx_headroom;
 945         xdp_set_data_meta_invalid(&xdp);
 946         xdp.data_end = xdp.data + *len;
 947         xdp.data_hard_start = va;
 948         xdp.rxq = &rq->xdp_rxq;
 949
 950         act = bpf_prog_run_xdp(prog, &xdp);
 951         switch (act) {
 952         case XDP_PASS:
 953                 *rx_headroom = xdp.data - xdp.data_hard_start;
 954                 *len = xdp.data_end - xdp.data;
 955                 return false;
 956         case XDP_TX:
 957                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
 958                         trace_xdp_exception(rq->netdev, prog, act);
 959                 return true;
 960         case XDP_REDIRECT:
 961                 /* When XDP enabled then page-refcnt==1 here */
 962                 err = xdp_do_redirect(rq->netdev, &xdp, prog);
 963                 if (!err) {
 964                         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags);
 965                         rq->xdpsq.db.redirect_flush = true;
 966                         mlx5e_page_dma_unmap(rq, di);
 967                 }
 968                 return true;
 969         default:
 970                 bpf_warn_invalid_xdp_action(act);
 971         case XDP_ABORTED:
 972                 trace_xdp_exception(rq->netdev, prog, act);
 973         case XDP_DROP:
 974                 rq->stats->xdp_drop++;
 975                 return true;
 976         }
 977 }
 978
 979 static inline
 980 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
 981                                        u32 frag_size, u16 headroom,
 982                                        u32 cqe_bcnt)
 983 {
 984         struct sk_buff *skb = build_skb(va, frag_size);
 985
 986         if (unlikely(!skb)) {
 987                 rq->stats->buff_alloc_err++;
 988                 return NULL;
 989         }
 990
 991         skb_reserve(skb, headroom);
 992         skb_put(skb, cqe_bcnt);
 993
 994         return skb;
 995 }
 996
 997 struct sk_buff *
 998 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 999                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1000 {
1001         struct mlx5e_dma_info *di = wi->di;
1002         u16 rx_headroom = rq->buff.headroom;
1003         struct sk_buff *skb;
1004         void *va, *data;
1005         bool consumed;
1006         u32 frag_size;
1007
1008         va             = page_address(di->page) + wi->offset;
1009         data           = va + rx_headroom;
1010         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1011
1012         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1013                                       frag_size, DMA_FROM_DEVICE);
1014         prefetchw(va); /* xdp_frame data area */
1015         prefetch(data);
1016
1017         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1018                 rq->stats->wqe_err++;
1019                 return NULL;
1020         }
1021
1022         rcu_read_lock();
1023         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
1024         rcu_read_unlock();
1025         if (consumed)
1026                 return NULL; /* page/packet was consumed by XDP */
1027
1028         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1029         if (unlikely(!skb))
1030                 return NULL;
1031
1032         /* queue up for recycling/reuse */
1033         page_ref_inc(di->page);
1034
1035         return skb;
1036 }
1037
1038 struct sk_buff *
1039 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1040                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1041 {
1042         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1043         struct mlx5e_wqe_frag_info *head_wi = wi;
1044         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1045         u16 frag_headlen = headlen;
1046         u16 byte_cnt     = cqe_bcnt - headlen;
1047         struct sk_buff *skb;
1048
1049         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1050                 rq->stats->wqe_err++;
1051                 return NULL;
1052         }
1053
1054         /* XDP is not supported in this configuration, as incoming packets
1055          * might spread among multiple pages.
1056          */
1057         skb = napi_alloc_skb(rq->cq.napi,
1058                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1059         if (unlikely(!skb)) {
1060                 rq->stats->buff_alloc_err++;
1061                 return NULL;
1062         }
1063
1064         prefetchw(skb->data);
1065
1066         while (byte_cnt) {
1067                 u16 frag_consumed_bytes =
1068                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1069
1070                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1071                                    frag_consumed_bytes, frag_info->frag_stride);
1072                 byte_cnt -= frag_consumed_bytes;
1073                 frag_headlen = 0;
1074                 frag_info++;
1075                 wi++;
1076         }
1077
1078         /* copy header */
1079         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset,
1080                               0, headlen);
1081         /* skb linear part was allocated with headlen and aligned to long */
1082         skb->tail += headlen;
1083         skb->len  += headlen;
1084
1085         return skb;
1086 }
1087
1088 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1089 {
1090         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1091         struct mlx5e_wqe_frag_info *wi;
1092         struct sk_buff *skb;
1093         u32 cqe_bcnt;
1094         u16 ci;
1095
1096         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1097         wi       = get_frag(rq, ci);
1098         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1099
1100         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1101         if (!skb) {
1102                 /* probably for XDP */
1103                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1104                         /* do not return page to cache,
1105                          * it will be returned on XDP_TX completion.
1106                          */
1107                         goto wq_cyc_pop;
1108                 }
1109                 goto free_wqe;
1110         }
1111
1112         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1113         napi_gro_receive(rq->cq.napi, skb);
1114
1115 free_wqe:
1116         mlx5e_free_rx_wqe(rq, wi);
1117 wq_cyc_pop:
1118         mlx5_wq_cyc_pop(wq);
1119 }
1120
1121 #ifdef CONFIG_MLX5_ESWITCH
1122 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1123 {
1124         struct net_device *netdev = rq->netdev;
1125         struct mlx5e_priv *priv = netdev_priv(netdev);
1126         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1127         struct mlx5_eswitch_rep *rep = rpriv->rep;
1128         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1129         struct mlx5e_wqe_frag_info *wi;
1130         struct sk_buff *skb;
1131         u32 cqe_bcnt;
1132         u16 ci;
1133
1134         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1135         wi       = get_frag(rq, ci);
1136         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1137
1138         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1139         if (!skb) {
1140                 /* probably for XDP */
1141                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1142                         /* do not return page to cache,
1143                          * it will be returned on XDP_TX completion.
1144                          */
1145                         goto wq_cyc_pop;
1146                 }
1147                 goto free_wqe;
1148         }
1149
1150         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1151
1152         if (rep->vlan && skb_vlan_tag_present(skb))
1153                 skb_vlan_pop(skb);
1154
1155         napi_gro_receive(rq->cq.napi, skb);
1156
1157 free_wqe:
1158         mlx5e_free_rx_wqe(rq, wi);
1159 wq_cyc_pop:
1160         mlx5_wq_cyc_pop(wq);
1161 }
1162 #endif
1163
1164 struct sk_buff *
1165 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1166                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1167 {
1168         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1169         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1170         u32 frag_offset    = head_offset + headlen;
1171         u32 byte_cnt       = cqe_bcnt - headlen;
1172         struct mlx5e_dma_info *head_di = di;
1173         struct sk_buff *skb;
1174
1175         skb = napi_alloc_skb(rq->cq.napi,
1176                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1177         if (unlikely(!skb)) {
1178                 rq->stats->buff_alloc_err++;
1179                 return NULL;
1180         }
1181
1182         prefetchw(skb->data);
1183
1184         if (unlikely(frag_offset >= PAGE_SIZE)) {
1185                 di++;
1186                 frag_offset -= PAGE_SIZE;
1187         }
1188
1189         while (byte_cnt) {
1190                 u32 pg_consumed_bytes =
1191                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1192                 unsigned int truesize =
1193                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1194
1195                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1196                                    pg_consumed_bytes, truesize);
1197                 byte_cnt -= pg_consumed_bytes;
1198                 frag_offset = 0;
1199                 di++;
1200         }
1201         /* copy header */
1202         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1203                                     head_offset, headlen);
1204         /* skb linear part was allocated with headlen and aligned to long */
1205         skb->tail += headlen;
1206         skb->len  += headlen;
1207
1208         return skb;
1209 }
1210
1211 struct sk_buff *
1212 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1213                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1214 {
1215         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1216         u16 rx_headroom = rq->buff.headroom;
1217         u32 cqe_bcnt32 = cqe_bcnt;
1218         struct sk_buff *skb;
1219         void *va, *data;
1220         u32 frag_size;
1221         bool consumed;
1222
1223         va             = page_address(di->page) + head_offset;
1224         data           = va + rx_headroom;
1225         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1226
1227         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1228                                       frag_size, DMA_FROM_DEVICE);
1229         prefetch(data);
1230
1231         rcu_read_lock();
1232         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1233         rcu_read_unlock();
1234         if (consumed) {
1235                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1236                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1237                 return NULL; /* page/packet was consumed by XDP */
1238         }
1239
1240         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1241         if (unlikely(!skb))
1242                 return NULL;
1243
1244         /* queue up for recycling/reuse */
1245         page_ref_inc(di->page);
1246
1247         return skb;
1248 }
1249
1250 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1251 {
1252         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1253         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1254         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1255         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1256         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1257         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1258         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1259         struct mlx5e_rx_wqe_ll *wqe;
1260         struct mlx5_wq_ll *wq;
1261         struct sk_buff *skb;
1262         u16 cqe_bcnt;
1263
1264         wi->consumed_strides += cstrides;
1265
1266         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1267                 rq->stats->wqe_err++;
1268                 goto mpwrq_cqe_out;
1269         }
1270
1271         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1272                 struct mlx5e_rq_stats *stats = rq->stats;
1273
1274                 stats->mpwqe_filler_cqes++;
1275                 stats->mpwqe_filler_strides += cstrides;
1276                 goto mpwrq_cqe_out;
1277         }
1278
1279         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1280
1281         skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1282                                            page_idx);
1283         if (!skb)
1284                 goto mpwrq_cqe_out;
1285
1286         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1287         napi_gro_receive(rq->cq.napi, skb);
1288
1289 mpwrq_cqe_out:
1290         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1291                 return;
1292
1293         wq  = &rq->mpwqe.wq;
1294         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1295         mlx5e_free_rx_mpwqe(rq, wi);
1296         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1297 }
1298
1299 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1300 {
1301         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1302         struct mlx5e_xdpsq *xdpsq;
1303         struct mlx5_cqe64 *cqe;
1304         int work_done = 0;
1305
1306         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1307                 return 0;
1308
1309         if (cq->decmprs_left)
1310                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1311
1312         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1313         if (!cqe)
1314                 return 0;
1315
1316         xdpsq = &rq->xdpsq;
1317
1318         do {
1319                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1320                         work_done +=
1321                                 mlx5e_decompress_cqes_start(rq, cq,
1322                                                             budget - work_done);
1323                         continue;
1324                 }
1325
1326                 mlx5_cqwq_pop(&cq->wq);
1327
1328                 rq->handle_rx_cqe(rq, cqe);
1329         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1330
1331         if (xdpsq->db.doorbell) {
1332                 mlx5e_xmit_xdp_doorbell(xdpsq);
1333                 xdpsq->db.doorbell = false;
1334         }
1335
1336         if (xdpsq->db.redirect_flush) {
1337                 xdp_do_flush_map();
1338                 xdpsq->db.redirect_flush = false;
1339         }
1340
1341         mlx5_cqwq_update_db_record(&cq->wq);
1342
1343         /* ensure cq space is freed before enabling more cqes */
1344         wmb();
1345
1346         return work_done;
1347 }
1348
1349 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1350 {
1351         struct mlx5e_xdpsq *sq;
1352         struct mlx5_cqe64 *cqe;
1353         struct mlx5e_rq *rq;
1354         u16 sqcc;
1355         int i;
1356
1357         sq = container_of(cq, struct mlx5e_xdpsq, cq);
1358
1359         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
1360                 return false;
1361
1362         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1363         if (!cqe)
1364                 return false;
1365
1366         rq = container_of(sq, struct mlx5e_rq, xdpsq);
1367
1368         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1369          * otherwise a cq overrun may occur
1370          */
1371         sqcc = sq->cc;
1372
1373         i = 0;
1374         do {
1375                 u16 wqe_counter;
1376                 bool last_wqe;
1377
1378                 mlx5_cqwq_pop(&cq->wq);
1379
1380                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1381
1382                 do {
1383                         struct mlx5e_dma_info *di;
1384                         u16 ci;
1385
1386                         last_wqe = (sqcc == wqe_counter);
1387
1388                         ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
1389                         di = &sq->db.di[ci];
1390
1391                         sqcc++;
1392                         /* Recycle RX page */
1393                         mlx5e_page_release(rq, di, true);
1394                 } while (!last_wqe);
1395         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1396
1397         rq->stats->xdp_tx_cqe += i;
1398
1399         mlx5_cqwq_update_db_record(&cq->wq);
1400
1401         /* ensure cq space is freed before enabling more cqes */
1402         wmb();
1403
1404         sq->cc = sqcc;
1405         return (i == MLX5E_TX_CQ_POLL_BUDGET);
1406 }
1407
1408 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1409 {
1410         struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1411         struct mlx5e_dma_info *di;
1412         u16 ci;
1413
1414         while (sq->cc != sq->pc) {
1415                 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc);
1416                 di = &sq->db.di[ci];
1417                 sq->cc++;
1418
1419                 mlx5e_page_release(rq, di, false);
1420         }
1421 }
1422
1423 #ifdef CONFIG_MLX5_CORE_IPOIB
1424
1425 #define MLX5_IB_GRH_DGID_OFFSET 24
1426 #define MLX5_GID_SIZE           16
1427
1428 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1429                                          struct mlx5_cqe64 *cqe,
1430                                          u32 cqe_bcnt,
1431                                          struct sk_buff *skb)
1432 {
1433         struct mlx5e_rq_stats *stats = rq->stats;
1434         struct hwtstamp_config *tstamp;
1435         struct net_device *netdev;
1436         struct mlx5e_priv *priv;
1437         char *pseudo_header;
1438         u32 qpn;
1439         u8 *dgid;
1440         u8 g;
1441
1442         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1443         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1444
1445         /* No mapping present, cannot process SKB. This might happen if a child
1446          * interface is going down while having unprocessed CQEs on parent RQ
1447          */
1448         if (unlikely(!netdev)) {
1449                 /* TODO: add drop counters support */
1450                 skb->dev = NULL;
1451                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1452                 return;
1453         }
1454
1455         priv = mlx5i_epriv(netdev);
1456         tstamp = &priv->tstamp;
1457
1458         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1459         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1460         if ((!g) || dgid[0] != 0xff)
1461                 skb->pkt_type = PACKET_HOST;
1462         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1463                 skb->pkt_type = PACKET_BROADCAST;
1464         else
1465                 skb->pkt_type = PACKET_MULTICAST;
1466
1467         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1468          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1469          */
1470
1471         skb_pull(skb, MLX5_IB_GRH_BYTES);
1472
1473         skb->protocol = *((__be16 *)(skb->data));
1474
1475         skb->ip_summed = CHECKSUM_COMPLETE;
1476         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1477
1478         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1479                 skb_hwtstamps(skb)->hwtstamp =
1480                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1481
1482         skb_record_rx_queue(skb, rq->ix);
1483
1484         if (likely(netdev->features & NETIF_F_RXHASH))
1485                 mlx5e_skb_set_hash(cqe, skb);
1486
1487         /* 20 bytes of ipoib header and 4 for encap existing */
1488         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1489         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1490         skb_reset_mac_header(skb);
1491         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1492
1493         skb->dev = netdev;
1494
1495         stats->csum_complete++;
1496         stats->packets++;
1497         stats->bytes += cqe_bcnt;
1498 }
1499
1500 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1501 {
1502         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1503         struct mlx5e_wqe_frag_info *wi;
1504         struct sk_buff *skb;
1505         u32 cqe_bcnt;
1506         u16 ci;
1507
1508         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1509         wi       = get_frag(rq, ci);
1510         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1511
1512         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1513         if (!skb)
1514                 goto wq_free_wqe;
1515
1516         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1517         if (unlikely(!skb->dev)) {
1518                 dev_kfree_skb_any(skb);
1519                 goto wq_free_wqe;
1520         }
1521         napi_gro_receive(rq->cq.napi, skb);
1522
1523 wq_free_wqe:
1524         mlx5e_free_rx_wqe(rq, wi);
1525         mlx5_wq_cyc_pop(wq);
1526 }
1527
1528 #endif /* CONFIG_MLX5_CORE_IPOIB */
1529
1530 #ifdef CONFIG_MLX5_EN_IPSEC
1531
1532 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1533 {
1534         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1535         struct mlx5e_wqe_frag_info *wi;
1536         struct sk_buff *skb;
1537         u32 cqe_bcnt;
1538         u16 ci;
1539
1540         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1541         wi       = get_frag(rq, ci);
1542         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1543
1544         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1545         if (unlikely(!skb)) {
1546                 /* a DROP, save the page-reuse checks */
1547                 mlx5e_free_rx_wqe(rq, wi);
1548                 goto wq_cyc_pop;
1549         }
1550         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1551         if (unlikely(!skb)) {
1552                 mlx5e_free_rx_wqe(rq, wi);
1553                 goto wq_cyc_pop;
1554         }
1555
1556         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1557         napi_gro_receive(rq->cq.napi, skb);
1558
1559         mlx5e_free_rx_wqe(rq, wi);
1560 wq_cyc_pop:
1561         mlx5_wq_cyc_pop(wq);
1562 }
1563
1564 #endif /* CONFIG_MLX5_EN_IPSEC */