net/mlx5e: Avoid reset netdev stats on configuration changes
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_rx.c
1 /*
2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/prefetch.h>
34 #include <linux/ip.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/bpf_trace.h>
38 #include <net/busy_poll.h>
39 #include <net/ip6_checksum.h>
40 #include <net/page_pool.h>
41 #include "en.h"
42 #include "en_tc.h"
43 #include "eswitch.h"
44 #include "en_rep.h"
45 #include "ipoib/ipoib.h"
46 #include "en_accel/ipsec_rxtx.h"
47 #include "lib/clock.h"
48
49 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
50 {
51         return config->rx_filter == HWTSTAMP_FILTER_ALL;
52 }
53
54 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
55                                        void *data)
56 {
57         u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc);
58
59         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
60 }
61
62 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
63                                          struct mlx5e_cq *cq, u32 cqcc)
64 {
65         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
66         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
67         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
68         rq->stats->cqe_compress_blks++;
69 }
70
71 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
72 {
73         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
74         cq->mini_arr_idx = 0;
75 }
76
77 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
78 {
79         struct mlx5_cqwq *wq = &cq->wq;
80
81         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
82         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
83         u32 wq_sz  = mlx5_cqwq_get_size(wq);
84         u32 ci_top = min_t(u32, wq_sz, ci + n);
85
86         for (; ci < ci_top; ci++, n--) {
87                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
88
89                 cqe->op_own = op_own;
90         }
91
92         if (unlikely(ci == wq_sz)) {
93                 op_own = !op_own;
94                 for (ci = 0; ci < n; ci++) {
95                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
96
97                         cqe->op_own = op_own;
98                 }
99         }
100 }
101
102 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
103                                         struct mlx5e_cq *cq, u32 cqcc)
104 {
105         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
106         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
107         cq->title.op_own      &= 0xf0;
108         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
109         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
110
111         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
112                 cq->decmprs_wqe_counter +=
113                         mpwrq_get_cqe_consumed_strides(&cq->title);
114         else
115                 cq->decmprs_wqe_counter =
116                         mlx5_wq_ll_ctr2ix(&rq->wq, cq->decmprs_wqe_counter + 1);
117 }
118
119 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
120                                                 struct mlx5e_cq *cq, u32 cqcc)
121 {
122         mlx5e_decompress_cqe(rq, cq, cqcc);
123         cq->title.rss_hash_type   = 0;
124         cq->title.rss_hash_result = 0;
125 }
126
127 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
128                                              struct mlx5e_cq *cq,
129                                              int update_owner_only,
130                                              int budget_rem)
131 {
132         u32 cqcc = cq->wq.cc + update_owner_only;
133         u32 cqe_count;
134         u32 i;
135
136         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
137
138         for (i = update_owner_only; i < cqe_count;
139              i++, cq->mini_arr_idx++, cqcc++) {
140                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
141                         mlx5e_read_mini_arr_slot(cq, cqcc);
142
143                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
144                 rq->handle_rx_cqe(rq, &cq->title);
145         }
146         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
147         cq->wq.cc = cqcc;
148         cq->decmprs_left -= cqe_count;
149         rq->stats->cqe_compress_pkts += cqe_count;
150
151         return cqe_count;
152 }
153
154 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
155                                               struct mlx5e_cq *cq,
156                                               int budget_rem)
157 {
158         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
159         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
160         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
161         rq->handle_rx_cqe(rq, &cq->title);
162         cq->mini_arr_idx++;
163
164         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
165 }
166
167 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
168
169 static inline bool mlx5e_page_is_reserved(struct page *page)
170 {
171         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
172 }
173
174 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
175                                       struct mlx5e_dma_info *dma_info)
176 {
177         struct mlx5e_page_cache *cache = &rq->page_cache;
178         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
179         struct mlx5e_rq_stats *stats = rq->stats;
180
181         if (tail_next == cache->head) {
182                 stats->cache_full++;
183                 return false;
184         }
185
186         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
187                 stats->cache_waive++;
188                 return false;
189         }
190
191         cache->page_cache[cache->tail] = *dma_info;
192         cache->tail = tail_next;
193         return true;
194 }
195
196 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
197                                       struct mlx5e_dma_info *dma_info)
198 {
199         struct mlx5e_page_cache *cache = &rq->page_cache;
200         struct mlx5e_rq_stats *stats = rq->stats;
201
202         if (unlikely(cache->head == cache->tail)) {
203                 stats->cache_empty++;
204                 return false;
205         }
206
207         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
208                 stats->cache_busy++;
209                 return false;
210         }
211
212         *dma_info = cache->page_cache[cache->head];
213         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
214         stats->cache_reuse++;
215
216         dma_sync_single_for_device(rq->pdev, dma_info->addr,
217                                    RQ_PAGE_SIZE(rq),
218                                    DMA_FROM_DEVICE);
219         return true;
220 }
221
222 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
223                                           struct mlx5e_dma_info *dma_info)
224 {
225         if (mlx5e_rx_cache_get(rq, dma_info))
226                 return 0;
227
228         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
229         if (unlikely(!dma_info->page))
230                 return -ENOMEM;
231
232         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
233                                       RQ_PAGE_SIZE(rq), rq->buff.map_dir);
234         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
235                 put_page(dma_info->page);
236                 dma_info->page = NULL;
237                 return -ENOMEM;
238         }
239
240         return 0;
241 }
242
243 static void mlx5e_page_dma_unmap(struct mlx5e_rq *rq,
244                                         struct mlx5e_dma_info *dma_info)
245 {
246         dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
247                        rq->buff.map_dir);
248 }
249
250 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
251                         bool recycle)
252 {
253         if (likely(recycle)) {
254                 if (mlx5e_rx_cache_put(rq, dma_info))
255                         return;
256
257                 mlx5e_page_dma_unmap(rq, dma_info);
258                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
259         } else {
260                 mlx5e_page_dma_unmap(rq, dma_info);
261                 put_page(dma_info->page);
262         }
263 }
264
265 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,
266                                     struct mlx5e_wqe_frag_info *wi)
267 {
268         return rq->wqe.page_reuse && wi->di.page &&
269                 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) &&
270                 !mlx5e_page_is_reserved(wi->di.page);
271 }
272
273 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
274 {
275         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
276
277         /* check if page exists, hence can be reused */
278         if (!wi->di.page) {
279                 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di)))
280                         return -ENOMEM;
281                 wi->offset = 0;
282         }
283
284         wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom);
285         return 0;
286 }
287
288 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
289                                      struct mlx5e_wqe_frag_info *wi)
290 {
291         mlx5e_page_release(rq, &wi->di, true);
292         wi->di.page = NULL;
293 }
294
295 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq,
296                                            struct mlx5e_wqe_frag_info *wi)
297 {
298         if (mlx5e_page_reuse(rq, wi)) {
299                 rq->stats->page_reuse++;
300                 return;
301         }
302
303         mlx5e_free_rx_wqe(rq, wi);
304 }
305
306 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
307 {
308         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
309
310         if (wi->di.page)
311                 mlx5e_free_rx_wqe(rq, wi);
312 }
313
314 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
315                                             struct sk_buff *skb,
316                                             struct mlx5e_dma_info *di,
317                                             u32 frag_offset, u32 len)
318 {
319         unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz));
320
321         dma_sync_single_for_cpu(rq->pdev,
322                                 di->addr + frag_offset,
323                                 len, DMA_FROM_DEVICE);
324         page_ref_inc(di->page);
325         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
326                         di->page, frag_offset, len, truesize);
327 }
328
329 static inline void
330 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
331                             struct sk_buff *skb,
332                             struct mlx5e_dma_info *dma_info,
333                             u32 offset, u32 headlen)
334 {
335         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
336         unsigned int len;
337
338          /* Aligning len to sizeof(long) optimizes memcpy performance */
339         len = ALIGN(headlen_pg, sizeof(long));
340         dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
341                                 DMA_FROM_DEVICE);
342         skb_copy_to_linear_data(skb, page_address(dma_info->page) + offset, len);
343
344         if (unlikely(offset + headlen > PAGE_SIZE)) {
345                 dma_info++;
346                 headlen_pg = len;
347                 len = ALIGN(headlen - headlen_pg, sizeof(long));
348                 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
349                                         DMA_FROM_DEVICE);
350                 skb_copy_to_linear_data_offset(skb, headlen_pg,
351                                                page_address(dma_info->page),
352                                                len);
353         }
354 }
355
356 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
357 {
358         const bool no_xdp_xmit =
359                 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
360         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
361         int i;
362
363         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
364                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
365                         mlx5e_page_release(rq, &dma_info[i], true);
366 }
367
368 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
369 {
370         struct mlx5_wq_ll *wq = &rq->wq;
371         struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
372
373         rq->mpwqe.umr_in_progress = false;
374
375         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
376
377         /* ensure wqes are visible to device before updating doorbell record */
378         dma_wmb();
379
380         mlx5_wq_ll_update_db_record(wq);
381 }
382
383 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
384 {
385         return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
386 }
387
388 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
389                                               struct mlx5_wq_cyc *wq,
390                                               u16 pi, u16 frag_pi)
391 {
392         struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
393         u8 nnops = mlx5_wq_cyc_get_frag_size(wq) - frag_pi;
394
395         edge_wi = wi + nnops;
396
397         /* fill sq frag edge with nops to avoid wqe wrapping two pages */
398         for (; wi < edge_wi; wi++) {
399                 wi->opcode = MLX5_OPCODE_NOP;
400                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
401         }
402 }
403
404 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
405 {
406         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
407         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
408         struct mlx5e_icosq *sq = &rq->channel->icosq;
409         struct mlx5_wq_cyc *wq = &sq->wq;
410         struct mlx5e_umr_wqe *umr_wqe;
411         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
412         u16 pi, frag_pi;
413         int err;
414         int i;
415
416         pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
417         frag_pi = mlx5_wq_cyc_ctr2fragix(wq, sq->pc);
418
419         if (unlikely(frag_pi + MLX5E_UMR_WQEBBS > mlx5_wq_cyc_get_frag_size(wq))) {
420                 mlx5e_fill_icosq_frag_edge(sq, wq, pi, frag_pi);
421                 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
422         }
423
424         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
425         if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
426                 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
427                        offsetof(struct mlx5e_umr_wqe, inline_mtts));
428
429         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
430                 err = mlx5e_page_alloc_mapped(rq, dma_info);
431                 if (unlikely(err))
432                         goto err_unmap;
433                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
434         }
435
436         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
437         wi->consumed_strides = 0;
438
439         rq->mpwqe.umr_in_progress = true;
440
441         umr_wqe->ctrl.opmod_idx_opcode =
442                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
443                             MLX5_OPCODE_UMR);
444         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
445
446         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
447         sq->pc += MLX5E_UMR_WQEBBS;
448         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
449
450         return 0;
451
452 err_unmap:
453         while (--i >= 0) {
454                 dma_info--;
455                 mlx5e_page_release(rq, dma_info, true);
456         }
457         rq->stats->buff_alloc_err++;
458
459         return err;
460 }
461
462 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
463 {
464         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
465
466         mlx5e_free_rx_mpwqe(rq, wi);
467 }
468
469 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
470 {
471         struct mlx5_wq_ll *wq = &rq->wq;
472         int err;
473
474         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
475                 return false;
476
477         if (mlx5_wq_ll_is_full(wq))
478                 return false;
479
480         do {
481                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
482
483                 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head);
484                 if (unlikely(err)) {
485                         rq->stats->buff_alloc_err++;
486                         break;
487                 }
488
489                 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
490         } while (!mlx5_wq_ll_is_full(wq));
491
492         /* ensure wqes are visible to device before updating doorbell record */
493         dma_wmb();
494
495         mlx5_wq_ll_update_db_record(wq);
496
497         return !!err;
498 }
499
500 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
501                                              struct mlx5e_icosq *sq,
502                                              struct mlx5e_rq *rq,
503                                              struct mlx5_cqe64 *cqe)
504 {
505         struct mlx5_wq_cyc *wq = &sq->wq;
506         u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
507         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
508
509         mlx5_cqwq_pop(&cq->wq);
510
511         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
512                 netdev_WARN_ONCE(cq->channel->netdev,
513                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
514                 return;
515         }
516
517         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
518                 mlx5e_post_rx_mpwqe(rq);
519                 return;
520         }
521
522         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
523                 netdev_WARN_ONCE(cq->channel->netdev,
524                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
525 }
526
527 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
528 {
529         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
530         struct mlx5_cqe64 *cqe;
531
532         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
533                 return;
534
535         cqe = mlx5_cqwq_get_cqe(&cq->wq);
536         if (likely(!cqe))
537                 return;
538
539         /* by design, there's only a single cqe */
540         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
541
542         mlx5_cqwq_update_db_record(&cq->wq);
543 }
544
545 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
546 {
547         struct mlx5_wq_ll *wq = &rq->wq;
548
549         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
550                 return false;
551
552         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
553
554         if (mlx5_wq_ll_is_full(wq))
555                 return false;
556
557         if (!rq->mpwqe.umr_in_progress)
558                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
559
560         return false;
561 }
562
563 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
564 {
565         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
566         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
567                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
568
569         tcp->check                      = 0;
570         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
571
572         if (tcp_ack) {
573                 tcp->ack                = 1;
574                 tcp->ack_seq            = cqe->lro_ack_seq_num;
575                 tcp->window             = cqe->lro_tcp_win;
576         }
577 }
578
579 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
580                                  u32 cqe_bcnt)
581 {
582         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
583         struct tcphdr   *tcp;
584         int network_depth = 0;
585         __wsum check;
586         __be16 proto;
587         u16 tot_len;
588         void *ip_p;
589
590         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
591
592         tot_len = cqe_bcnt - network_depth;
593         ip_p = skb->data + network_depth;
594
595         if (proto == htons(ETH_P_IP)) {
596                 struct iphdr *ipv4 = ip_p;
597
598                 tcp = ip_p + sizeof(struct iphdr);
599                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
600
601                 ipv4->ttl               = cqe->lro_min_ttl;
602                 ipv4->tot_len           = cpu_to_be16(tot_len);
603                 ipv4->check             = 0;
604                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
605                                                        ipv4->ihl);
606
607                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
608                 check = csum_partial(tcp, tcp->doff * 4,
609                                      csum_unfold((__force __sum16)cqe->check_sum));
610                 /* Almost done, don't forget the pseudo header */
611                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
612                                                tot_len - sizeof(struct iphdr),
613                                                IPPROTO_TCP, check);
614         } else {
615                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
616                 struct ipv6hdr *ipv6 = ip_p;
617
618                 tcp = ip_p + sizeof(struct ipv6hdr);
619                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
620
621                 ipv6->hop_limit         = cqe->lro_min_ttl;
622                 ipv6->payload_len       = cpu_to_be16(payload_len);
623
624                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
625                 check = csum_partial(tcp, tcp->doff * 4,
626                                      csum_unfold((__force __sum16)cqe->check_sum));
627                 /* Almost done, don't forget the pseudo header */
628                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
629                                              IPPROTO_TCP, check);
630         }
631 }
632
633 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
634                                       struct sk_buff *skb)
635 {
636         u8 cht = cqe->rss_hash_type;
637         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
638                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
639                                             PKT_HASH_TYPE_NONE;
640         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
641 }
642
643 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
644 {
645         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
646
647         ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
648         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
649 }
650
651 static inline void mlx5e_handle_csum(struct net_device *netdev,
652                                      struct mlx5_cqe64 *cqe,
653                                      struct mlx5e_rq *rq,
654                                      struct sk_buff *skb,
655                                      bool   lro)
656 {
657         struct mlx5e_rq_stats *stats = rq->stats;
658         int network_depth = 0;
659
660         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
661                 goto csum_none;
662
663         if (lro) {
664                 skb->ip_summed = CHECKSUM_UNNECESSARY;
665                 stats->csum_unnecessary++;
666                 return;
667         }
668
669         if (likely(is_last_ethertype_ip(skb, &network_depth))) {
670                 skb->ip_summed = CHECKSUM_COMPLETE;
671                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
672                 if (network_depth > ETH_HLEN)
673                         /* CQE csum is calculated from the IP header and does
674                          * not cover VLAN headers (if present). This will add
675                          * the checksum manually.
676                          */
677                         skb->csum = csum_partial(skb->data + ETH_HLEN,
678                                                  network_depth - ETH_HLEN,
679                                                  skb->csum);
680                 stats->csum_complete++;
681                 return;
682         }
683
684         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
685                    (cqe->hds_ip_ext & CQE_L4_OK))) {
686                 skb->ip_summed = CHECKSUM_UNNECESSARY;
687                 if (cqe_is_tunneled(cqe)) {
688                         skb->csum_level = 1;
689                         skb->encapsulation = 1;
690                         stats->csum_unnecessary_inner++;
691                         return;
692                 }
693                 stats->csum_unnecessary++;
694                 return;
695         }
696 csum_none:
697         skb->ip_summed = CHECKSUM_NONE;
698         stats->csum_none++;
699 }
700
701 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
702                                       u32 cqe_bcnt,
703                                       struct mlx5e_rq *rq,
704                                       struct sk_buff *skb)
705 {
706         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
707         struct mlx5e_rq_stats *stats = rq->stats;
708         struct net_device *netdev = rq->netdev;
709
710         skb->mac_len = ETH_HLEN;
711         if (lro_num_seg > 1) {
712                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
713                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
714                 /* Subtract one since we already counted this as one
715                  * "regular" packet in mlx5e_complete_rx_cqe()
716                  */
717                 stats->packets += lro_num_seg - 1;
718                 stats->lro_packets++;
719                 stats->lro_bytes += cqe_bcnt;
720         }
721
722         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
723                 skb_hwtstamps(skb)->hwtstamp =
724                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
725
726         skb_record_rx_queue(skb, rq->ix);
727
728         if (likely(netdev->features & NETIF_F_RXHASH))
729                 mlx5e_skb_set_hash(cqe, skb);
730
731         if (cqe_has_vlan(cqe)) {
732                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
733                                        be16_to_cpu(cqe->vlan_info));
734                 stats->removed_vlan_packets++;
735         }
736
737         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
738
739         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
740         skb->protocol = eth_type_trans(skb, netdev);
741 }
742
743 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
744                                          struct mlx5_cqe64 *cqe,
745                                          u32 cqe_bcnt,
746                                          struct sk_buff *skb)
747 {
748         struct mlx5e_rq_stats *stats = rq->stats;
749
750         stats->packets++;
751         stats->bytes += cqe_bcnt;
752         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
753 }
754
755 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
756 {
757         struct mlx5_wq_cyc *wq = &sq->wq;
758         struct mlx5e_tx_wqe *wqe;
759         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc - 1); /* last pi */
760
761         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
762
763         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
764 }
765
766 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
767                                         struct mlx5e_dma_info *di,
768                                         const struct xdp_buff *xdp)
769 {
770         struct mlx5e_xdpsq       *sq   = &rq->xdpsq;
771         struct mlx5_wq_cyc       *wq   = &sq->wq;
772         u16                       pi   = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
773         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
774
775         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
776         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
777         struct mlx5_wqe_data_seg *dseg;
778
779         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
780         dma_addr_t dma_addr  = di->addr + data_offset;
781         unsigned int dma_len = xdp->data_end - xdp->data;
782
783         struct mlx5e_rq_stats *stats = rq->stats;
784
785         prefetchw(wqe);
786
787         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || rq->hw_mtu < dma_len)) {
788                 stats->xdp_drop++;
789                 return false;
790         }
791
792         if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
793                 if (sq->db.doorbell) {
794                         /* SQ is full, ring doorbell */
795                         mlx5e_xmit_xdp_doorbell(sq);
796                         sq->db.doorbell = false;
797                 }
798                 stats->xdp_tx_full++;
799                 return false;
800         }
801
802         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
803
804         cseg->fm_ce_se = 0;
805
806         dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
807
808         /* copy the inline part if required */
809         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
810                 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
811                 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
812                 dma_len  -= MLX5E_XDP_MIN_INLINE;
813                 dma_addr += MLX5E_XDP_MIN_INLINE;
814                 dseg++;
815         }
816
817         /* write the dma part */
818         dseg->addr       = cpu_to_be64(dma_addr);
819         dseg->byte_count = cpu_to_be32(dma_len);
820
821         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
822
823         /* move page to reference to sq responsibility,
824          * and mark so it's not put back in page-cache.
825          */
826         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
827         sq->db.di[pi] = *di;
828         sq->pc++;
829
830         sq->db.doorbell = true;
831
832         stats->xdp_tx++;
833         return true;
834 }
835
836 /* returns true if packet was consumed by xdp */
837 static inline bool mlx5e_xdp_handle(struct mlx5e_rq *rq,
838                                     struct mlx5e_dma_info *di,
839                                     void *va, u16 *rx_headroom, u32 *len)
840 {
841         struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
842         struct xdp_buff xdp;
843         u32 act;
844         int err;
845
846         if (!prog)
847                 return false;
848
849         xdp.data = va + *rx_headroom;
850         xdp_set_data_meta_invalid(&xdp);
851         xdp.data_end = xdp.data + *len;
852         xdp.data_hard_start = va;
853         xdp.rxq = &rq->xdp_rxq;
854
855         act = bpf_prog_run_xdp(prog, &xdp);
856         switch (act) {
857         case XDP_PASS:
858                 *rx_headroom = xdp.data - xdp.data_hard_start;
859                 *len = xdp.data_end - xdp.data;
860                 return false;
861         case XDP_TX:
862                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
863                         trace_xdp_exception(rq->netdev, prog, act);
864                 return true;
865         case XDP_REDIRECT:
866                 /* When XDP enabled then page-refcnt==1 here */
867                 err = xdp_do_redirect(rq->netdev, &xdp, prog);
868                 if (!err) {
869                         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags);
870                         rq->xdpsq.db.redirect_flush = true;
871                         mlx5e_page_dma_unmap(rq, di);
872                 }
873                 return true;
874         default:
875                 bpf_warn_invalid_xdp_action(act);
876         case XDP_ABORTED:
877                 trace_xdp_exception(rq->netdev, prog, act);
878         case XDP_DROP:
879                 rq->stats->xdp_drop++;
880                 return true;
881         }
882 }
883
884 static inline
885 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
886                                        u32 frag_size, u16 headroom,
887                                        u32 cqe_bcnt)
888 {
889         struct sk_buff *skb = build_skb(va, frag_size);
890
891         if (unlikely(!skb)) {
892                 rq->stats->buff_alloc_err++;
893                 return NULL;
894         }
895
896         skb_reserve(skb, headroom);
897         skb_put(skb, cqe_bcnt);
898
899         return skb;
900 }
901
902 static inline
903 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
904                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
905 {
906         struct mlx5e_dma_info *di = &wi->di;
907         u16 rx_headroom = rq->buff.headroom;
908         struct sk_buff *skb;
909         void *va, *data;
910         bool consumed;
911         u32 frag_size;
912
913         va             = page_address(di->page) + wi->offset;
914         data           = va + rx_headroom;
915         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
916
917         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
918                                       frag_size, DMA_FROM_DEVICE);
919         prefetchw(va); /* xdp_frame data area */
920         prefetch(data);
921         wi->offset += frag_size;
922
923         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
924                 rq->stats->wqe_err++;
925                 return NULL;
926         }
927
928         rcu_read_lock();
929         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
930         rcu_read_unlock();
931         if (consumed)
932                 return NULL; /* page/packet was consumed by XDP */
933
934         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
935         if (unlikely(!skb))
936                 return NULL;
937
938         /* queue up for recycling/reuse */
939         page_ref_inc(di->page);
940
941         return skb;
942 }
943
944 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
945 {
946         struct mlx5e_wqe_frag_info *wi;
947         struct mlx5e_rx_wqe *wqe;
948         __be16 wqe_counter_be;
949         struct sk_buff *skb;
950         u16 wqe_counter;
951         u32 cqe_bcnt;
952
953         wqe_counter_be = cqe->wqe_counter;
954         wqe_counter    = be16_to_cpu(wqe_counter_be);
955         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
956         wi             = &rq->wqe.frag_info[wqe_counter];
957         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
958
959         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
960         if (!skb) {
961                 /* probably for XDP */
962                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
963                         wi->di.page = NULL;
964                         /* do not return page to cache, it will be returned on XDP_TX completion */
965                         goto wq_ll_pop;
966                 }
967                 /* probably an XDP_DROP, save the page-reuse checks */
968                 mlx5e_free_rx_wqe(rq, wi);
969                 goto wq_ll_pop;
970         }
971
972         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
973         napi_gro_receive(rq->cq.napi, skb);
974
975         mlx5e_free_rx_wqe_reuse(rq, wi);
976 wq_ll_pop:
977         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
978                        &wqe->next.next_wqe_index);
979 }
980
981 #ifdef CONFIG_MLX5_ESWITCH
982 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
983 {
984         struct net_device *netdev = rq->netdev;
985         struct mlx5e_priv *priv = netdev_priv(netdev);
986         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
987         struct mlx5_eswitch_rep *rep = rpriv->rep;
988         struct mlx5e_wqe_frag_info *wi;
989         struct mlx5e_rx_wqe *wqe;
990         struct sk_buff *skb;
991         __be16 wqe_counter_be;
992         u16 wqe_counter;
993         u32 cqe_bcnt;
994
995         wqe_counter_be = cqe->wqe_counter;
996         wqe_counter    = be16_to_cpu(wqe_counter_be);
997         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
998         wi             = &rq->wqe.frag_info[wqe_counter];
999         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1000
1001         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1002         if (!skb) {
1003                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1004                         wi->di.page = NULL;
1005                         /* do not return page to cache, it will be returned on XDP_TX completion */
1006                         goto wq_ll_pop;
1007                 }
1008                 /* probably an XDP_DROP, save the page-reuse checks */
1009                 mlx5e_free_rx_wqe(rq, wi);
1010                 goto wq_ll_pop;
1011         }
1012
1013         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1014
1015         if (rep->vlan && skb_vlan_tag_present(skb))
1016                 skb_vlan_pop(skb);
1017
1018         napi_gro_receive(rq->cq.napi, skb);
1019
1020         mlx5e_free_rx_wqe_reuse(rq, wi);
1021 wq_ll_pop:
1022         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1023                        &wqe->next.next_wqe_index);
1024 }
1025 #endif
1026
1027 struct sk_buff *
1028 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1029                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1030 {
1031         u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
1032         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1033         u32 frag_offset    = head_offset + headlen;
1034         u32 byte_cnt       = cqe_bcnt - headlen;
1035         struct mlx5e_dma_info *head_di = di;
1036         struct sk_buff *skb;
1037
1038         skb = napi_alloc_skb(rq->cq.napi,
1039                              ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, sizeof(long)));
1040         if (unlikely(!skb)) {
1041                 rq->stats->buff_alloc_err++;
1042                 return NULL;
1043         }
1044
1045         prefetchw(skb->data);
1046
1047         if (unlikely(frag_offset >= PAGE_SIZE)) {
1048                 di++;
1049                 frag_offset -= PAGE_SIZE;
1050         }
1051
1052         while (byte_cnt) {
1053                 u32 pg_consumed_bytes =
1054                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1055
1056                 mlx5e_add_skb_frag_mpwqe(rq, skb, di, frag_offset,
1057                                          pg_consumed_bytes);
1058                 byte_cnt -= pg_consumed_bytes;
1059                 frag_offset = 0;
1060                 di++;
1061         }
1062         /* copy header */
1063         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1064                                     head_offset, headlen);
1065         /* skb linear part was allocated with headlen and aligned to long */
1066         skb->tail += headlen;
1067         skb->len  += headlen;
1068
1069         return skb;
1070 }
1071
1072 struct sk_buff *
1073 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1074                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1075 {
1076         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1077         u16 rx_headroom = rq->buff.headroom;
1078         u32 cqe_bcnt32 = cqe_bcnt;
1079         struct sk_buff *skb;
1080         void *va, *data;
1081         u32 frag_size;
1082         bool consumed;
1083
1084         va             = page_address(di->page) + head_offset;
1085         data           = va + rx_headroom;
1086         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1087
1088         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1089                                       frag_size, DMA_FROM_DEVICE);
1090         prefetch(data);
1091
1092         rcu_read_lock();
1093         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1094         rcu_read_unlock();
1095         if (consumed) {
1096                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1097                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1098                 return NULL; /* page/packet was consumed by XDP */
1099         }
1100
1101         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1102         if (unlikely(!skb))
1103                 return NULL;
1104
1105         /* queue up for recycling/reuse */
1106         page_ref_inc(di->page);
1107
1108         return skb;
1109 }
1110
1111 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1112 {
1113         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1114         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1115         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1116         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1117         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1118         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1119         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1120         struct mlx5e_rx_wqe *wqe;
1121         struct sk_buff *skb;
1122         u16 cqe_bcnt;
1123
1124         wi->consumed_strides += cstrides;
1125
1126         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1127                 rq->stats->wqe_err++;
1128                 goto mpwrq_cqe_out;
1129         }
1130
1131         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1132                 rq->stats->mpwqe_filler++;
1133                 goto mpwrq_cqe_out;
1134         }
1135
1136         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1137
1138         skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1139                                            page_idx);
1140         if (!skb)
1141                 goto mpwrq_cqe_out;
1142
1143         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1144         napi_gro_receive(rq->cq.napi, skb);
1145
1146 mpwrq_cqe_out:
1147         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1148                 return;
1149
1150         wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
1151         mlx5e_free_rx_mpwqe(rq, wi);
1152         mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1153 }
1154
1155 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1156 {
1157         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1158         struct mlx5e_xdpsq *xdpsq;
1159         struct mlx5_cqe64 *cqe;
1160         int work_done = 0;
1161
1162         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1163                 return 0;
1164
1165         if (cq->decmprs_left)
1166                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1167
1168         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1169         if (!cqe)
1170                 return 0;
1171
1172         xdpsq = &rq->xdpsq;
1173
1174         do {
1175                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1176                         work_done +=
1177                                 mlx5e_decompress_cqes_start(rq, cq,
1178                                                             budget - work_done);
1179                         continue;
1180                 }
1181
1182                 mlx5_cqwq_pop(&cq->wq);
1183
1184                 rq->handle_rx_cqe(rq, cqe);
1185         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1186
1187         if (xdpsq->db.doorbell) {
1188                 mlx5e_xmit_xdp_doorbell(xdpsq);
1189                 xdpsq->db.doorbell = false;
1190         }
1191
1192         if (xdpsq->db.redirect_flush) {
1193                 xdp_do_flush_map();
1194                 xdpsq->db.redirect_flush = false;
1195         }
1196
1197         mlx5_cqwq_update_db_record(&cq->wq);
1198
1199         /* ensure cq space is freed before enabling more cqes */
1200         wmb();
1201
1202         return work_done;
1203 }
1204
1205 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1206 {
1207         struct mlx5e_xdpsq *sq;
1208         struct mlx5_cqe64 *cqe;
1209         struct mlx5e_rq *rq;
1210         u16 sqcc;
1211         int i;
1212
1213         sq = container_of(cq, struct mlx5e_xdpsq, cq);
1214
1215         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
1216                 return false;
1217
1218         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1219         if (!cqe)
1220                 return false;
1221
1222         rq = container_of(sq, struct mlx5e_rq, xdpsq);
1223
1224         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1225          * otherwise a cq overrun may occur
1226          */
1227         sqcc = sq->cc;
1228
1229         i = 0;
1230         do {
1231                 u16 wqe_counter;
1232                 bool last_wqe;
1233
1234                 mlx5_cqwq_pop(&cq->wq);
1235
1236                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1237
1238                 do {
1239                         struct mlx5e_dma_info *di;
1240                         u16 ci;
1241
1242                         last_wqe = (sqcc == wqe_counter);
1243
1244                         ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
1245                         di = &sq->db.di[ci];
1246
1247                         sqcc++;
1248                         /* Recycle RX page */
1249                         mlx5e_page_release(rq, di, true);
1250                 } while (!last_wqe);
1251         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1252
1253         mlx5_cqwq_update_db_record(&cq->wq);
1254
1255         /* ensure cq space is freed before enabling more cqes */
1256         wmb();
1257
1258         sq->cc = sqcc;
1259         return (i == MLX5E_TX_CQ_POLL_BUDGET);
1260 }
1261
1262 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1263 {
1264         struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1265         struct mlx5e_dma_info *di;
1266         u16 ci;
1267
1268         while (sq->cc != sq->pc) {
1269                 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc);
1270                 di = &sq->db.di[ci];
1271                 sq->cc++;
1272
1273                 mlx5e_page_release(rq, di, false);
1274         }
1275 }
1276
1277 #ifdef CONFIG_MLX5_CORE_IPOIB
1278
1279 #define MLX5_IB_GRH_DGID_OFFSET 24
1280 #define MLX5_GID_SIZE           16
1281
1282 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1283                                          struct mlx5_cqe64 *cqe,
1284                                          u32 cqe_bcnt,
1285                                          struct sk_buff *skb)
1286 {
1287         struct mlx5e_rq_stats *stats = rq->stats;
1288         struct hwtstamp_config *tstamp;
1289         struct net_device *netdev;
1290         struct mlx5e_priv *priv;
1291         char *pseudo_header;
1292         u32 qpn;
1293         u8 *dgid;
1294         u8 g;
1295
1296         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1297         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1298
1299         /* No mapping present, cannot process SKB. This might happen if a child
1300          * interface is going down while having unprocessed CQEs on parent RQ
1301          */
1302         if (unlikely(!netdev)) {
1303                 /* TODO: add drop counters support */
1304                 skb->dev = NULL;
1305                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1306                 return;
1307         }
1308
1309         priv = mlx5i_epriv(netdev);
1310         tstamp = &priv->tstamp;
1311
1312         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1313         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1314         if ((!g) || dgid[0] != 0xff)
1315                 skb->pkt_type = PACKET_HOST;
1316         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1317                 skb->pkt_type = PACKET_BROADCAST;
1318         else
1319                 skb->pkt_type = PACKET_MULTICAST;
1320
1321         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1322          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1323          */
1324
1325         skb_pull(skb, MLX5_IB_GRH_BYTES);
1326
1327         skb->protocol = *((__be16 *)(skb->data));
1328
1329         skb->ip_summed = CHECKSUM_COMPLETE;
1330         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1331
1332         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1333                 skb_hwtstamps(skb)->hwtstamp =
1334                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1335
1336         skb_record_rx_queue(skb, rq->ix);
1337
1338         if (likely(netdev->features & NETIF_F_RXHASH))
1339                 mlx5e_skb_set_hash(cqe, skb);
1340
1341         /* 20 bytes of ipoib header and 4 for encap existing */
1342         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1343         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1344         skb_reset_mac_header(skb);
1345         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1346
1347         skb->dev = netdev;
1348
1349         stats->csum_complete++;
1350         stats->packets++;
1351         stats->bytes += cqe_bcnt;
1352 }
1353
1354 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1355 {
1356         struct mlx5e_wqe_frag_info *wi;
1357         struct mlx5e_rx_wqe *wqe;
1358         __be16 wqe_counter_be;
1359         struct sk_buff *skb;
1360         u16 wqe_counter;
1361         u32 cqe_bcnt;
1362
1363         wqe_counter_be = cqe->wqe_counter;
1364         wqe_counter    = be16_to_cpu(wqe_counter_be);
1365         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1366         wi             = &rq->wqe.frag_info[wqe_counter];
1367         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1368
1369         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1370         if (!skb)
1371                 goto wq_free_wqe;
1372
1373         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1374         if (unlikely(!skb->dev)) {
1375                 dev_kfree_skb_any(skb);
1376                 goto wq_free_wqe;
1377         }
1378         napi_gro_receive(rq->cq.napi, skb);
1379
1380 wq_free_wqe:
1381         mlx5e_free_rx_wqe_reuse(rq, wi);
1382         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1383                        &wqe->next.next_wqe_index);
1384 }
1385
1386 #endif /* CONFIG_MLX5_CORE_IPOIB */
1387
1388 #ifdef CONFIG_MLX5_EN_IPSEC
1389
1390 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1391 {
1392         struct mlx5e_wqe_frag_info *wi;
1393         struct mlx5e_rx_wqe *wqe;
1394         __be16 wqe_counter_be;
1395         struct sk_buff *skb;
1396         u16 wqe_counter;
1397         u32 cqe_bcnt;
1398
1399         wqe_counter_be = cqe->wqe_counter;
1400         wqe_counter    = be16_to_cpu(wqe_counter_be);
1401         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1402         wi             = &rq->wqe.frag_info[wqe_counter];
1403         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1404
1405         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1406         if (unlikely(!skb)) {
1407                 /* a DROP, save the page-reuse checks */
1408                 mlx5e_free_rx_wqe(rq, wi);
1409                 goto wq_ll_pop;
1410         }
1411         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1412         if (unlikely(!skb)) {
1413                 mlx5e_free_rx_wqe(rq, wi);
1414                 goto wq_ll_pop;
1415         }
1416
1417         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1418         napi_gro_receive(rq->cq.napi, skb);
1419
1420         mlx5e_free_rx_wqe_reuse(rq, wi);
1421 wq_ll_pop:
1422         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1423                        &wqe->next.next_wqe_index);
1424 }
1425
1426 #endif /* CONFIG_MLX5_EN_IPSEC */