net/mlx5e: Refactor RQ XDP_TX indication
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_rx.c
1 /*
2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/prefetch.h>
34 #include <linux/ip.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/bpf_trace.h>
38 #include <net/busy_poll.h>
39 #include <net/ip6_checksum.h>
40 #include "en.h"
41 #include "en_tc.h"
42 #include "eswitch.h"
43 #include "en_rep.h"
44 #include "ipoib/ipoib.h"
45 #include "en_accel/ipsec_rxtx.h"
46 #include "lib/clock.h"
47
48 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
49 {
50         return config->rx_filter == HWTSTAMP_FILTER_ALL;
51 }
52
53 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
54                                        void *data)
55 {
56         u32 ci = cqcc & cq->wq.fbc.sz_m1;
57
58         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
59 }
60
61 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
62                                          struct mlx5e_cq *cq, u32 cqcc)
63 {
64         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
65         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
66         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
67         rq->stats.cqe_compress_blks++;
68 }
69
70 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
71 {
72         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
73         cq->mini_arr_idx = 0;
74 }
75
76 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
77 {
78         struct mlx5_frag_buf_ctrl *fbc = &cq->wq.fbc;
79         u8 op_own = (cqcc >> fbc->log_sz) & 1;
80         u32 wq_sz = 1 << fbc->log_sz;
81         u32 ci = cqcc & fbc->sz_m1;
82         u32 ci_top = min_t(u32, wq_sz, ci + n);
83
84         for (; ci < ci_top; ci++, n--) {
85                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
86
87                 cqe->op_own = op_own;
88         }
89
90         if (unlikely(ci == wq_sz)) {
91                 op_own = !op_own;
92                 for (ci = 0; ci < n; ci++) {
93                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
94
95                         cqe->op_own = op_own;
96                 }
97         }
98 }
99
100 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
101                                         struct mlx5e_cq *cq, u32 cqcc)
102 {
103         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
104         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
105         cq->title.op_own      &= 0xf0;
106         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
107         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
108
109         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
110                 cq->decmprs_wqe_counter +=
111                         mpwrq_get_cqe_consumed_strides(&cq->title);
112         else
113                 cq->decmprs_wqe_counter =
114                         (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1;
115 }
116
117 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
118                                                 struct mlx5e_cq *cq, u32 cqcc)
119 {
120         mlx5e_decompress_cqe(rq, cq, cqcc);
121         cq->title.rss_hash_type   = 0;
122         cq->title.rss_hash_result = 0;
123 }
124
125 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
126                                              struct mlx5e_cq *cq,
127                                              int update_owner_only,
128                                              int budget_rem)
129 {
130         u32 cqcc = cq->wq.cc + update_owner_only;
131         u32 cqe_count;
132         u32 i;
133
134         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
135
136         for (i = update_owner_only; i < cqe_count;
137              i++, cq->mini_arr_idx++, cqcc++) {
138                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
139                         mlx5e_read_mini_arr_slot(cq, cqcc);
140
141                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
142                 rq->handle_rx_cqe(rq, &cq->title);
143         }
144         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
145         cq->wq.cc = cqcc;
146         cq->decmprs_left -= cqe_count;
147         rq->stats.cqe_compress_pkts += cqe_count;
148
149         return cqe_count;
150 }
151
152 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
153                                               struct mlx5e_cq *cq,
154                                               int budget_rem)
155 {
156         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
157         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
158         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
159         rq->handle_rx_cqe(rq, &cq->title);
160         cq->mini_arr_idx++;
161
162         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
163 }
164
165 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
166
167 static inline bool mlx5e_page_is_reserved(struct page *page)
168 {
169         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
170 }
171
172 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
173                                       struct mlx5e_dma_info *dma_info)
174 {
175         struct mlx5e_page_cache *cache = &rq->page_cache;
176         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
177
178         if (tail_next == cache->head) {
179                 rq->stats.cache_full++;
180                 return false;
181         }
182
183         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
184                 rq->stats.cache_waive++;
185                 return false;
186         }
187
188         cache->page_cache[cache->tail] = *dma_info;
189         cache->tail = tail_next;
190         return true;
191 }
192
193 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
194                                       struct mlx5e_dma_info *dma_info)
195 {
196         struct mlx5e_page_cache *cache = &rq->page_cache;
197
198         if (unlikely(cache->head == cache->tail)) {
199                 rq->stats.cache_empty++;
200                 return false;
201         }
202
203         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
204                 rq->stats.cache_busy++;
205                 return false;
206         }
207
208         *dma_info = cache->page_cache[cache->head];
209         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
210         rq->stats.cache_reuse++;
211
212         dma_sync_single_for_device(rq->pdev, dma_info->addr,
213                                    RQ_PAGE_SIZE(rq),
214                                    DMA_FROM_DEVICE);
215         return true;
216 }
217
218 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
219                                           struct mlx5e_dma_info *dma_info)
220 {
221         if (mlx5e_rx_cache_get(rq, dma_info))
222                 return 0;
223
224         dma_info->page = dev_alloc_pages(rq->buff.page_order);
225         if (unlikely(!dma_info->page))
226                 return -ENOMEM;
227
228         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
229                                       RQ_PAGE_SIZE(rq), rq->buff.map_dir);
230         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
231                 put_page(dma_info->page);
232                 dma_info->page = NULL;
233                 return -ENOMEM;
234         }
235
236         return 0;
237 }
238
239 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
240                         bool recycle)
241 {
242         if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
243                 return;
244
245         dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
246                        rq->buff.map_dir);
247         put_page(dma_info->page);
248 }
249
250 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,
251                                     struct mlx5e_wqe_frag_info *wi)
252 {
253         return rq->wqe.page_reuse && wi->di.page &&
254                 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) &&
255                 !mlx5e_page_is_reserved(wi->di.page);
256 }
257
258 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
259 {
260         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
261
262         /* check if page exists, hence can be reused */
263         if (!wi->di.page) {
264                 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di)))
265                         return -ENOMEM;
266                 wi->offset = 0;
267         }
268
269         wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom);
270         return 0;
271 }
272
273 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
274                                      struct mlx5e_wqe_frag_info *wi)
275 {
276         mlx5e_page_release(rq, &wi->di, true);
277         wi->di.page = NULL;
278 }
279
280 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq,
281                                            struct mlx5e_wqe_frag_info *wi)
282 {
283         if (mlx5e_page_reuse(rq, wi)) {
284                 rq->stats.page_reuse++;
285                 return;
286         }
287
288         mlx5e_free_rx_wqe(rq, wi);
289 }
290
291 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
292 {
293         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
294
295         if (wi->di.page)
296                 mlx5e_free_rx_wqe(rq, wi);
297 }
298
299 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
300 {
301         return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
302 }
303
304 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
305                                             struct sk_buff *skb,
306                                             struct mlx5e_mpw_info *wi,
307                                             u32 page_idx, u32 frag_offset,
308                                             u32 len)
309 {
310         unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz));
311
312         dma_sync_single_for_cpu(rq->pdev,
313                                 wi->umr.dma_info[page_idx].addr + frag_offset,
314                                 len, DMA_FROM_DEVICE);
315         wi->skbs_frags[page_idx]++;
316         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
317                         wi->umr.dma_info[page_idx].page, frag_offset,
318                         len, truesize);
319 }
320
321 static inline void
322 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
323                             struct sk_buff *skb,
324                             struct mlx5e_mpw_info *wi,
325                             u32 page_idx, u32 offset,
326                             u32 headlen)
327 {
328         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
329         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
330         unsigned int len;
331
332          /* Aligning len to sizeof(long) optimizes memcpy performance */
333         len = ALIGN(headlen_pg, sizeof(long));
334         dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
335                                 DMA_FROM_DEVICE);
336         skb_copy_to_linear_data(skb, page_address(dma_info->page) + offset, len);
337
338         if (unlikely(offset + headlen > PAGE_SIZE)) {
339                 dma_info++;
340                 headlen_pg = len;
341                 len = ALIGN(headlen - headlen_pg, sizeof(long));
342                 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
343                                         DMA_FROM_DEVICE);
344                 skb_copy_to_linear_data_offset(skb, headlen_pg,
345                                                page_address(dma_info->page),
346                                                len);
347         }
348 }
349
350 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
351 {
352         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
353         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
354         int i;
355
356         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
357                 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]);
358                 mlx5e_page_release(rq, dma_info, true);
359         }
360 }
361
362 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
363 {
364         struct mlx5_wq_ll *wq = &rq->wq;
365         struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
366
367         rq->mpwqe.umr_in_progress = false;
368
369         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
370
371         /* ensure wqes are visible to device before updating doorbell record */
372         dma_wmb();
373
374         mlx5_wq_ll_update_db_record(wq);
375 }
376
377 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
378 {
379         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
380         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
381         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
382         struct mlx5e_icosq *sq = &rq->channel->icosq;
383         struct mlx5_wq_cyc *wq = &sq->wq;
384         struct mlx5e_umr_wqe *umr_wqe;
385         int cpy = offsetof(struct mlx5e_umr_wqe, inline_mtts);
386         int err;
387         u16 pi;
388         int i;
389
390         /* fill sq edge with nops to avoid wqe wrap around */
391         while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
392                 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
393                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
394         }
395
396         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
397         memcpy(umr_wqe, &wi->umr.wqe, cpy);
398         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
399                 err = mlx5e_page_alloc_mapped(rq, dma_info);
400                 if (unlikely(err))
401                         goto err_unmap;
402                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
403                 page_ref_add(dma_info->page, pg_strides);
404         }
405
406         memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE);
407         wi->consumed_strides = 0;
408
409         rq->mpwqe.umr_in_progress = true;
410
411         umr_wqe->ctrl.opmod_idx_opcode =
412                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
413                             MLX5_OPCODE_UMR);
414
415         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
416         sq->pc += MLX5E_UMR_WQEBBS;
417         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
418
419         return 0;
420
421 err_unmap:
422         while (--i >= 0) {
423                 dma_info--;
424                 page_ref_sub(dma_info->page, pg_strides);
425                 mlx5e_page_release(rq, dma_info, true);
426         }
427         rq->stats.buff_alloc_err++;
428
429         return err;
430 }
431
432 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
433 {
434         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
435
436         mlx5e_free_rx_mpwqe(rq, wi);
437 }
438
439 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
440 {
441         struct mlx5_wq_ll *wq = &rq->wq;
442         int err;
443
444         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
445                 return false;
446
447         if (mlx5_wq_ll_is_full(wq))
448                 return false;
449
450         do {
451                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
452
453                 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head);
454                 if (unlikely(err)) {
455                         rq->stats.buff_alloc_err++;
456                         break;
457                 }
458
459                 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
460         } while (!mlx5_wq_ll_is_full(wq));
461
462         /* ensure wqes are visible to device before updating doorbell record */
463         dma_wmb();
464
465         mlx5_wq_ll_update_db_record(wq);
466
467         return !!err;
468 }
469
470 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
471                                              struct mlx5e_icosq *sq,
472                                              struct mlx5e_rq *rq,
473                                              struct mlx5_cqe64 *cqe)
474 {
475         struct mlx5_wq_cyc *wq = &sq->wq;
476         u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;
477         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
478
479         mlx5_cqwq_pop(&cq->wq);
480
481         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
482                 netdev_WARN_ONCE(cq->channel->netdev,
483                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
484                 return;
485         }
486
487         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
488                 mlx5e_post_rx_mpwqe(rq);
489                 return;
490         }
491
492         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
493                 netdev_WARN_ONCE(cq->channel->netdev,
494                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
495 }
496
497 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
498 {
499         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
500         struct mlx5_cqe64 *cqe;
501
502         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
503                 return;
504
505         cqe = mlx5_cqwq_get_cqe(&cq->wq);
506         if (likely(!cqe))
507                 return;
508
509         /* by design, there's only a single cqe */
510         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
511
512         mlx5_cqwq_update_db_record(&cq->wq);
513 }
514
515 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
516 {
517         struct mlx5_wq_ll *wq = &rq->wq;
518
519         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
520                 return false;
521
522         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
523
524         if (mlx5_wq_ll_is_full(wq))
525                 return false;
526
527         if (!rq->mpwqe.umr_in_progress)
528                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
529
530         return false;
531 }
532
533 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
534 {
535         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
536         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
537                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
538
539         tcp->check                      = 0;
540         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
541
542         if (tcp_ack) {
543                 tcp->ack                = 1;
544                 tcp->ack_seq            = cqe->lro_ack_seq_num;
545                 tcp->window             = cqe->lro_tcp_win;
546         }
547 }
548
549 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
550                                  u32 cqe_bcnt)
551 {
552         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
553         struct tcphdr   *tcp;
554         int network_depth = 0;
555         __wsum check;
556         __be16 proto;
557         u16 tot_len;
558         void *ip_p;
559
560         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
561
562         tot_len = cqe_bcnt - network_depth;
563         ip_p = skb->data + network_depth;
564
565         if (proto == htons(ETH_P_IP)) {
566                 struct iphdr *ipv4 = ip_p;
567
568                 tcp = ip_p + sizeof(struct iphdr);
569                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
570
571                 ipv4->ttl               = cqe->lro_min_ttl;
572                 ipv4->tot_len           = cpu_to_be16(tot_len);
573                 ipv4->check             = 0;
574                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
575                                                        ipv4->ihl);
576
577                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
578                 check = csum_partial(tcp, tcp->doff * 4,
579                                      csum_unfold((__force __sum16)cqe->check_sum));
580                 /* Almost done, don't forget the pseudo header */
581                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
582                                                tot_len - sizeof(struct iphdr),
583                                                IPPROTO_TCP, check);
584         } else {
585                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
586                 struct ipv6hdr *ipv6 = ip_p;
587
588                 tcp = ip_p + sizeof(struct ipv6hdr);
589                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
590
591                 ipv6->hop_limit         = cqe->lro_min_ttl;
592                 ipv6->payload_len       = cpu_to_be16(payload_len);
593
594                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
595                 check = csum_partial(tcp, tcp->doff * 4,
596                                      csum_unfold((__force __sum16)cqe->check_sum));
597                 /* Almost done, don't forget the pseudo header */
598                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
599                                              IPPROTO_TCP, check);
600         }
601 }
602
603 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
604                                       struct sk_buff *skb)
605 {
606         u8 cht = cqe->rss_hash_type;
607         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
608                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
609                                             PKT_HASH_TYPE_NONE;
610         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
611 }
612
613 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
614 {
615         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
616
617         ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
618         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
619 }
620
621 static inline void mlx5e_handle_csum(struct net_device *netdev,
622                                      struct mlx5_cqe64 *cqe,
623                                      struct mlx5e_rq *rq,
624                                      struct sk_buff *skb,
625                                      bool   lro)
626 {
627         int network_depth = 0;
628
629         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
630                 goto csum_none;
631
632         if (lro) {
633                 skb->ip_summed = CHECKSUM_UNNECESSARY;
634                 rq->stats.csum_unnecessary++;
635                 return;
636         }
637
638         if (likely(is_last_ethertype_ip(skb, &network_depth))) {
639                 skb->ip_summed = CHECKSUM_COMPLETE;
640                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
641                 if (network_depth > ETH_HLEN)
642                         /* CQE csum is calculated from the IP header and does
643                          * not cover VLAN headers (if present). This will add
644                          * the checksum manually.
645                          */
646                         skb->csum = csum_partial(skb->data + ETH_HLEN,
647                                                  network_depth - ETH_HLEN,
648                                                  skb->csum);
649                 rq->stats.csum_complete++;
650                 return;
651         }
652
653         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
654                    (cqe->hds_ip_ext & CQE_L4_OK))) {
655                 skb->ip_summed = CHECKSUM_UNNECESSARY;
656                 if (cqe_is_tunneled(cqe)) {
657                         skb->csum_level = 1;
658                         skb->encapsulation = 1;
659                         rq->stats.csum_unnecessary_inner++;
660                         return;
661                 }
662                 rq->stats.csum_unnecessary++;
663                 return;
664         }
665 csum_none:
666         skb->ip_summed = CHECKSUM_NONE;
667         rq->stats.csum_none++;
668 }
669
670 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
671                                       u32 cqe_bcnt,
672                                       struct mlx5e_rq *rq,
673                                       struct sk_buff *skb)
674 {
675         struct net_device *netdev = rq->netdev;
676         int lro_num_seg;
677
678         skb->mac_len = ETH_HLEN;
679         lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
680         if (lro_num_seg > 1) {
681                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
682                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
683                 /* Subtract one since we already counted this as one
684                  * "regular" packet in mlx5e_complete_rx_cqe()
685                  */
686                 rq->stats.packets += lro_num_seg - 1;
687                 rq->stats.lro_packets++;
688                 rq->stats.lro_bytes += cqe_bcnt;
689         }
690
691         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
692                 skb_hwtstamps(skb)->hwtstamp =
693                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
694
695         skb_record_rx_queue(skb, rq->ix);
696
697         if (likely(netdev->features & NETIF_F_RXHASH))
698                 mlx5e_skb_set_hash(cqe, skb);
699
700         if (cqe_has_vlan(cqe)) {
701                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
702                                        be16_to_cpu(cqe->vlan_info));
703                 rq->stats.removed_vlan_packets++;
704         }
705
706         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
707
708         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
709         skb->protocol = eth_type_trans(skb, netdev);
710 }
711
712 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
713                                          struct mlx5_cqe64 *cqe,
714                                          u32 cqe_bcnt,
715                                          struct sk_buff *skb)
716 {
717         rq->stats.packets++;
718         rq->stats.bytes += cqe_bcnt;
719         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
720 }
721
722 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
723 {
724         struct mlx5_wq_cyc *wq = &sq->wq;
725         struct mlx5e_tx_wqe *wqe;
726         u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */
727
728         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
729
730         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
731 }
732
733 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
734                                         struct mlx5e_dma_info *di,
735                                         const struct xdp_buff *xdp)
736 {
737         struct mlx5e_xdpsq       *sq   = &rq->xdpsq;
738         struct mlx5_wq_cyc       *wq   = &sq->wq;
739         u16                       pi   = sq->pc & wq->sz_m1;
740         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
741
742         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
743         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
744         struct mlx5_wqe_data_seg *dseg;
745
746         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
747         dma_addr_t dma_addr  = di->addr + data_offset;
748         unsigned int dma_len = xdp->data_end - xdp->data;
749
750         prefetchw(wqe);
751
752         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || rq->hw_mtu < dma_len)) {
753                 rq->stats.xdp_drop++;
754                 return false;
755         }
756
757         if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
758                 if (sq->db.doorbell) {
759                         /* SQ is full, ring doorbell */
760                         mlx5e_xmit_xdp_doorbell(sq);
761                         sq->db.doorbell = false;
762                 }
763                 rq->stats.xdp_tx_full++;
764                 return false;
765         }
766
767         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
768
769         cseg->fm_ce_se = 0;
770
771         dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
772
773         /* copy the inline part if required */
774         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
775                 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
776                 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
777                 dma_len  -= MLX5E_XDP_MIN_INLINE;
778                 dma_addr += MLX5E_XDP_MIN_INLINE;
779                 dseg++;
780         }
781
782         /* write the dma part */
783         dseg->addr       = cpu_to_be64(dma_addr);
784         dseg->byte_count = cpu_to_be32(dma_len);
785
786         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
787
788         /* move page to reference to sq responsibility,
789          * and mark so it's not put back in page-cache.
790          */
791         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
792         sq->db.di[pi] = *di;
793         sq->pc++;
794
795         sq->db.doorbell = true;
796
797         rq->stats.xdp_tx++;
798         return true;
799 }
800
801 /* returns true if packet was consumed by xdp */
802 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq,
803                                    struct mlx5e_dma_info *di,
804                                    void *va, u16 *rx_headroom, u32 *len)
805 {
806         const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
807         struct xdp_buff xdp;
808         u32 act;
809
810         if (!prog)
811                 return false;
812
813         xdp.data = va + *rx_headroom;
814         xdp_set_data_meta_invalid(&xdp);
815         xdp.data_end = xdp.data + *len;
816         xdp.data_hard_start = va;
817         xdp.rxq = &rq->xdp_rxq;
818
819         act = bpf_prog_run_xdp(prog, &xdp);
820         switch (act) {
821         case XDP_PASS:
822                 *rx_headroom = xdp.data - xdp.data_hard_start;
823                 *len = xdp.data_end - xdp.data;
824                 return false;
825         case XDP_TX:
826                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
827                         trace_xdp_exception(rq->netdev, prog, act);
828                 return true;
829         default:
830                 bpf_warn_invalid_xdp_action(act);
831         case XDP_ABORTED:
832                 trace_xdp_exception(rq->netdev, prog, act);
833         case XDP_DROP:
834                 rq->stats.xdp_drop++;
835                 return true;
836         }
837 }
838
839 static inline
840 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
841                                        u32 frag_size, u16 headroom,
842                                        u32 cqe_bcnt)
843 {
844         struct sk_buff *skb = build_skb(va, frag_size);
845
846         if (unlikely(!skb)) {
847                 rq->stats.buff_alloc_err++;
848                 return NULL;
849         }
850
851         skb_reserve(skb, headroom);
852         skb_put(skb, cqe_bcnt);
853
854         return skb;
855 }
856
857 static inline
858 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
859                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
860 {
861         struct mlx5e_dma_info *di = &wi->di;
862         u16 rx_headroom = rq->buff.headroom;
863         struct sk_buff *skb;
864         void *va, *data;
865         bool consumed;
866         u32 frag_size;
867
868         va             = page_address(di->page) + wi->offset;
869         data           = va + rx_headroom;
870         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
871
872         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
873                                       frag_size, DMA_FROM_DEVICE);
874         prefetch(data);
875         wi->offset += frag_size;
876
877         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
878                 rq->stats.wqe_err++;
879                 return NULL;
880         }
881
882         rcu_read_lock();
883         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
884         rcu_read_unlock();
885         if (consumed)
886                 return NULL; /* page/packet was consumed by XDP */
887
888         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
889         if (unlikely(!skb))
890                 return NULL;
891
892         /* queue up for recycling/reuse */
893         page_ref_inc(di->page);
894
895         return skb;
896 }
897
898 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
899 {
900         struct mlx5e_wqe_frag_info *wi;
901         struct mlx5e_rx_wqe *wqe;
902         __be16 wqe_counter_be;
903         struct sk_buff *skb;
904         u16 wqe_counter;
905         u32 cqe_bcnt;
906
907         wqe_counter_be = cqe->wqe_counter;
908         wqe_counter    = be16_to_cpu(wqe_counter_be);
909         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
910         wi             = &rq->wqe.frag_info[wqe_counter];
911         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
912
913         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
914         if (!skb) {
915                 /* probably for XDP */
916                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
917                         wi->di.page = NULL;
918                         /* do not return page to cache, it will be returned on XDP_TX completion */
919                         goto wq_ll_pop;
920                 }
921                 /* probably an XDP_DROP, save the page-reuse checks */
922                 mlx5e_free_rx_wqe(rq, wi);
923                 goto wq_ll_pop;
924         }
925
926         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
927         napi_gro_receive(rq->cq.napi, skb);
928
929         mlx5e_free_rx_wqe_reuse(rq, wi);
930 wq_ll_pop:
931         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
932                        &wqe->next.next_wqe_index);
933 }
934
935 #ifdef CONFIG_MLX5_ESWITCH
936 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
937 {
938         struct net_device *netdev = rq->netdev;
939         struct mlx5e_priv *priv = netdev_priv(netdev);
940         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
941         struct mlx5_eswitch_rep *rep = rpriv->rep;
942         struct mlx5e_wqe_frag_info *wi;
943         struct mlx5e_rx_wqe *wqe;
944         struct sk_buff *skb;
945         __be16 wqe_counter_be;
946         u16 wqe_counter;
947         u32 cqe_bcnt;
948
949         wqe_counter_be = cqe->wqe_counter;
950         wqe_counter    = be16_to_cpu(wqe_counter_be);
951         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
952         wi             = &rq->wqe.frag_info[wqe_counter];
953         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
954
955         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
956         if (!skb) {
957                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
958                         wi->di.page = NULL;
959                         /* do not return page to cache, it will be returned on XDP_TX completion */
960                         goto wq_ll_pop;
961                 }
962                 /* probably an XDP_DROP, save the page-reuse checks */
963                 mlx5e_free_rx_wqe(rq, wi);
964                 goto wq_ll_pop;
965         }
966
967         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
968
969         if (rep->vlan && skb_vlan_tag_present(skb))
970                 skb_vlan_pop(skb);
971
972         napi_gro_receive(rq->cq.napi, skb);
973
974         mlx5e_free_rx_wqe_reuse(rq, wi);
975 wq_ll_pop:
976         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
977                        &wqe->next.next_wqe_index);
978 }
979 #endif
980
981 struct sk_buff *
982 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
983                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
984 {
985         u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
986         u32 frag_offset    = head_offset + headlen;
987         u16 byte_cnt       = cqe_bcnt - headlen;
988         u32 head_page_idx  = page_idx;
989         struct sk_buff *skb;
990
991         skb = napi_alloc_skb(rq->cq.napi,
992                              ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, sizeof(long)));
993         if (unlikely(!skb)) {
994                 rq->stats.buff_alloc_err++;
995                 return NULL;
996         }
997
998         prefetchw(skb->data);
999
1000         if (unlikely(frag_offset >= PAGE_SIZE)) {
1001                 page_idx++;
1002                 frag_offset -= PAGE_SIZE;
1003         }
1004
1005         while (byte_cnt) {
1006                 u32 pg_consumed_bytes =
1007                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1008
1009                 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
1010                                          pg_consumed_bytes);
1011                 byte_cnt -= pg_consumed_bytes;
1012                 frag_offset = 0;
1013                 page_idx++;
1014         }
1015         /* copy header */
1016         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
1017                                     head_offset, headlen);
1018         /* skb linear part was allocated with headlen and aligned to long */
1019         skb->tail += headlen;
1020         skb->len  += headlen;
1021
1022         return skb;
1023 }
1024
1025 struct sk_buff *
1026 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1027                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1028 {
1029         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1030         u16 rx_headroom = rq->buff.headroom;
1031         struct sk_buff *skb;
1032         void *va, *data;
1033         u32 frag_size;
1034
1035         va             = page_address(di->page) + head_offset;
1036         data           = va + rx_headroom;
1037         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1038
1039         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1040                                       frag_size, DMA_FROM_DEVICE);
1041         prefetch(data);
1042         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1043         if (unlikely(!skb))
1044                 return NULL;
1045
1046         /* queue up for recycling/reuse */
1047         wi->skbs_frags[page_idx]++;
1048
1049         return skb;
1050 }
1051
1052 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1053 {
1054         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1055         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1056         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1057         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1058         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1059         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1060         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1061         struct mlx5e_rx_wqe *wqe;
1062         struct sk_buff *skb;
1063         u16 cqe_bcnt;
1064
1065         wi->consumed_strides += cstrides;
1066
1067         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1068                 rq->stats.wqe_err++;
1069                 goto mpwrq_cqe_out;
1070         }
1071
1072         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1073                 rq->stats.mpwqe_filler++;
1074                 goto mpwrq_cqe_out;
1075         }
1076
1077         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1078
1079         skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1080                                            page_idx);
1081         if (unlikely(!skb))
1082                 goto mpwrq_cqe_out;
1083
1084         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1085         napi_gro_receive(rq->cq.napi, skb);
1086
1087 mpwrq_cqe_out:
1088         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1089                 return;
1090
1091         wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
1092         mlx5e_free_rx_mpwqe(rq, wi);
1093         mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1094 }
1095
1096 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1097 {
1098         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1099         struct mlx5e_xdpsq *xdpsq;
1100         struct mlx5_cqe64 *cqe;
1101         int work_done = 0;
1102
1103         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
1104                 return 0;
1105
1106         if (cq->decmprs_left)
1107                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1108
1109         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1110         if (!cqe)
1111                 return 0;
1112
1113         xdpsq = &rq->xdpsq;
1114
1115         do {
1116                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1117                         work_done +=
1118                                 mlx5e_decompress_cqes_start(rq, cq,
1119                                                             budget - work_done);
1120                         continue;
1121                 }
1122
1123                 mlx5_cqwq_pop(&cq->wq);
1124
1125                 rq->handle_rx_cqe(rq, cqe);
1126         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1127
1128         if (xdpsq->db.doorbell) {
1129                 mlx5e_xmit_xdp_doorbell(xdpsq);
1130                 xdpsq->db.doorbell = false;
1131         }
1132
1133         mlx5_cqwq_update_db_record(&cq->wq);
1134
1135         /* ensure cq space is freed before enabling more cqes */
1136         wmb();
1137
1138         return work_done;
1139 }
1140
1141 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1142 {
1143         struct mlx5e_xdpsq *sq;
1144         struct mlx5_cqe64 *cqe;
1145         struct mlx5e_rq *rq;
1146         u16 sqcc;
1147         int i;
1148
1149         sq = container_of(cq, struct mlx5e_xdpsq, cq);
1150
1151         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
1152                 return false;
1153
1154         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1155         if (!cqe)
1156                 return false;
1157
1158         rq = container_of(sq, struct mlx5e_rq, xdpsq);
1159
1160         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1161          * otherwise a cq overrun may occur
1162          */
1163         sqcc = sq->cc;
1164
1165         i = 0;
1166         do {
1167                 u16 wqe_counter;
1168                 bool last_wqe;
1169
1170                 mlx5_cqwq_pop(&cq->wq);
1171
1172                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1173
1174                 do {
1175                         struct mlx5e_dma_info *di;
1176                         u16 ci;
1177
1178                         last_wqe = (sqcc == wqe_counter);
1179
1180                         ci = sqcc & sq->wq.sz_m1;
1181                         di = &sq->db.di[ci];
1182
1183                         sqcc++;
1184                         /* Recycle RX page */
1185                         mlx5e_page_release(rq, di, true);
1186                 } while (!last_wqe);
1187         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1188
1189         mlx5_cqwq_update_db_record(&cq->wq);
1190
1191         /* ensure cq space is freed before enabling more cqes */
1192         wmb();
1193
1194         sq->cc = sqcc;
1195         return (i == MLX5E_TX_CQ_POLL_BUDGET);
1196 }
1197
1198 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1199 {
1200         struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1201         struct mlx5e_dma_info *di;
1202         u16 ci;
1203
1204         while (sq->cc != sq->pc) {
1205                 ci = sq->cc & sq->wq.sz_m1;
1206                 di = &sq->db.di[ci];
1207                 sq->cc++;
1208
1209                 mlx5e_page_release(rq, di, false);
1210         }
1211 }
1212
1213 #ifdef CONFIG_MLX5_CORE_IPOIB
1214
1215 #define MLX5_IB_GRH_DGID_OFFSET 24
1216 #define MLX5_GID_SIZE           16
1217
1218 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1219                                          struct mlx5_cqe64 *cqe,
1220                                          u32 cqe_bcnt,
1221                                          struct sk_buff *skb)
1222 {
1223         struct hwtstamp_config *tstamp;
1224         struct net_device *netdev;
1225         struct mlx5e_priv *priv;
1226         char *pseudo_header;
1227         u32 qpn;
1228         u8 *dgid;
1229         u8 g;
1230
1231         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1232         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1233
1234         /* No mapping present, cannot process SKB. This might happen if a child
1235          * interface is going down while having unprocessed CQEs on parent RQ
1236          */
1237         if (unlikely(!netdev)) {
1238                 /* TODO: add drop counters support */
1239                 skb->dev = NULL;
1240                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1241                 return;
1242         }
1243
1244         priv = mlx5i_epriv(netdev);
1245         tstamp = &priv->tstamp;
1246
1247         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1248         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1249         if ((!g) || dgid[0] != 0xff)
1250                 skb->pkt_type = PACKET_HOST;
1251         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1252                 skb->pkt_type = PACKET_BROADCAST;
1253         else
1254                 skb->pkt_type = PACKET_MULTICAST;
1255
1256         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1257          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1258          */
1259
1260         skb_pull(skb, MLX5_IB_GRH_BYTES);
1261
1262         skb->protocol = *((__be16 *)(skb->data));
1263
1264         skb->ip_summed = CHECKSUM_COMPLETE;
1265         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1266
1267         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1268                 skb_hwtstamps(skb)->hwtstamp =
1269                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1270
1271         skb_record_rx_queue(skb, rq->ix);
1272
1273         if (likely(netdev->features & NETIF_F_RXHASH))
1274                 mlx5e_skb_set_hash(cqe, skb);
1275
1276         /* 20 bytes of ipoib header and 4 for encap existing */
1277         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1278         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1279         skb_reset_mac_header(skb);
1280         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1281
1282         skb->dev = netdev;
1283
1284         rq->stats.csum_complete++;
1285         rq->stats.packets++;
1286         rq->stats.bytes += cqe_bcnt;
1287 }
1288
1289 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1290 {
1291         struct mlx5e_wqe_frag_info *wi;
1292         struct mlx5e_rx_wqe *wqe;
1293         __be16 wqe_counter_be;
1294         struct sk_buff *skb;
1295         u16 wqe_counter;
1296         u32 cqe_bcnt;
1297
1298         wqe_counter_be = cqe->wqe_counter;
1299         wqe_counter    = be16_to_cpu(wqe_counter_be);
1300         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1301         wi             = &rq->wqe.frag_info[wqe_counter];
1302         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1303
1304         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1305         if (!skb)
1306                 goto wq_free_wqe;
1307
1308         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1309         if (unlikely(!skb->dev)) {
1310                 dev_kfree_skb_any(skb);
1311                 goto wq_free_wqe;
1312         }
1313         napi_gro_receive(rq->cq.napi, skb);
1314
1315 wq_free_wqe:
1316         mlx5e_free_rx_wqe_reuse(rq, wi);
1317         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1318                        &wqe->next.next_wqe_index);
1319 }
1320
1321 #endif /* CONFIG_MLX5_CORE_IPOIB */
1322
1323 #ifdef CONFIG_MLX5_EN_IPSEC
1324
1325 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1326 {
1327         struct mlx5e_wqe_frag_info *wi;
1328         struct mlx5e_rx_wqe *wqe;
1329         __be16 wqe_counter_be;
1330         struct sk_buff *skb;
1331         u16 wqe_counter;
1332         u32 cqe_bcnt;
1333
1334         wqe_counter_be = cqe->wqe_counter;
1335         wqe_counter    = be16_to_cpu(wqe_counter_be);
1336         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1337         wi             = &rq->wqe.frag_info[wqe_counter];
1338         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1339
1340         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1341         if (unlikely(!skb)) {
1342                 /* a DROP, save the page-reuse checks */
1343                 mlx5e_free_rx_wqe(rq, wi);
1344                 goto wq_ll_pop;
1345         }
1346         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1347         if (unlikely(!skb)) {
1348                 mlx5e_free_rx_wqe(rq, wi);
1349                 goto wq_ll_pop;
1350         }
1351
1352         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1353         napi_gro_receive(rq->cq.napi, skb);
1354
1355         mlx5e_free_rx_wqe_reuse(rq, wi);
1356 wq_ll_pop:
1357         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1358                        &wqe->next.next_wqe_index);
1359 }
1360
1361 #endif /* CONFIG_MLX5_EN_IPSEC */