net/mlx5e: Do not recycle RX pages in interface down flow
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_rx.c
1 /*
2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/prefetch.h>
34 #include <linux/ip.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/bpf_trace.h>
38 #include <net/busy_poll.h>
39 #include <net/ip6_checksum.h>
40 #include <net/page_pool.h>
41 #include "en.h"
42 #include "en_tc.h"
43 #include "eswitch.h"
44 #include "en_rep.h"
45 #include "ipoib/ipoib.h"
46 #include "en_accel/ipsec_rxtx.h"
47 #include "en_accel/tls_rxtx.h"
48 #include "lib/clock.h"
49
50 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
51 {
52         return config->rx_filter == HWTSTAMP_FILTER_ALL;
53 }
54
55 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
56                                        void *data)
57 {
58         u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc);
59
60         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
61 }
62
63 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
64                                          struct mlx5e_cq *cq, u32 cqcc)
65 {
66         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
67         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
68         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
69         rq->stats->cqe_compress_blks++;
70 }
71
72 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
73 {
74         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
75         cq->mini_arr_idx = 0;
76 }
77
78 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
79 {
80         struct mlx5_cqwq *wq = &cq->wq;
81
82         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
83         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
84         u32 wq_sz  = mlx5_cqwq_get_size(wq);
85         u32 ci_top = min_t(u32, wq_sz, ci + n);
86
87         for (; ci < ci_top; ci++, n--) {
88                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
89
90                 cqe->op_own = op_own;
91         }
92
93         if (unlikely(ci == wq_sz)) {
94                 op_own = !op_own;
95                 for (ci = 0; ci < n; ci++) {
96                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
97
98                         cqe->op_own = op_own;
99                 }
100         }
101 }
102
103 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
104                                         struct mlx5e_cq *cq, u32 cqcc)
105 {
106         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
107         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
108         cq->title.op_own      &= 0xf0;
109         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
110         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
111
112         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
113                 cq->decmprs_wqe_counter +=
114                         mpwrq_get_cqe_consumed_strides(&cq->title);
115         else
116                 cq->decmprs_wqe_counter =
117                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cq->decmprs_wqe_counter + 1);
118 }
119
120 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
121                                                 struct mlx5e_cq *cq, u32 cqcc)
122 {
123         mlx5e_decompress_cqe(rq, cq, cqcc);
124         cq->title.rss_hash_type   = 0;
125         cq->title.rss_hash_result = 0;
126 }
127
128 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
129                                              struct mlx5e_cq *cq,
130                                              int update_owner_only,
131                                              int budget_rem)
132 {
133         u32 cqcc = cq->wq.cc + update_owner_only;
134         u32 cqe_count;
135         u32 i;
136
137         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
138
139         for (i = update_owner_only; i < cqe_count;
140              i++, cq->mini_arr_idx++, cqcc++) {
141                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
142                         mlx5e_read_mini_arr_slot(cq, cqcc);
143
144                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
145                 rq->handle_rx_cqe(rq, &cq->title);
146         }
147         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
148         cq->wq.cc = cqcc;
149         cq->decmprs_left -= cqe_count;
150         rq->stats->cqe_compress_pkts += cqe_count;
151
152         return cqe_count;
153 }
154
155 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
156                                               struct mlx5e_cq *cq,
157                                               int budget_rem)
158 {
159         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
160         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
161         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
162         rq->handle_rx_cqe(rq, &cq->title);
163         cq->mini_arr_idx++;
164
165         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
166 }
167
168 static inline bool mlx5e_page_is_reserved(struct page *page)
169 {
170         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
171 }
172
173 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
174                                       struct mlx5e_dma_info *dma_info)
175 {
176         struct mlx5e_page_cache *cache = &rq->page_cache;
177         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
178         struct mlx5e_rq_stats *stats = rq->stats;
179
180         if (tail_next == cache->head) {
181                 stats->cache_full++;
182                 return false;
183         }
184
185         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
186                 stats->cache_waive++;
187                 return false;
188         }
189
190         cache->page_cache[cache->tail] = *dma_info;
191         cache->tail = tail_next;
192         return true;
193 }
194
195 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
196                                       struct mlx5e_dma_info *dma_info)
197 {
198         struct mlx5e_page_cache *cache = &rq->page_cache;
199         struct mlx5e_rq_stats *stats = rq->stats;
200
201         if (unlikely(cache->head == cache->tail)) {
202                 stats->cache_empty++;
203                 return false;
204         }
205
206         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
207                 stats->cache_busy++;
208                 return false;
209         }
210
211         *dma_info = cache->page_cache[cache->head];
212         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
213         stats->cache_reuse++;
214
215         dma_sync_single_for_device(rq->pdev, dma_info->addr,
216                                    PAGE_SIZE,
217                                    DMA_FROM_DEVICE);
218         return true;
219 }
220
221 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
222                                           struct mlx5e_dma_info *dma_info)
223 {
224         if (mlx5e_rx_cache_get(rq, dma_info))
225                 return 0;
226
227         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
228         if (unlikely(!dma_info->page))
229                 return -ENOMEM;
230
231         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
232                                       PAGE_SIZE, rq->buff.map_dir);
233         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
234                 put_page(dma_info->page);
235                 dma_info->page = NULL;
236                 return -ENOMEM;
237         }
238
239         return 0;
240 }
241
242 static void mlx5e_page_dma_unmap(struct mlx5e_rq *rq,
243                                         struct mlx5e_dma_info *dma_info)
244 {
245         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
246 }
247
248 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
249                         bool recycle)
250 {
251         if (likely(recycle)) {
252                 if (mlx5e_rx_cache_put(rq, dma_info))
253                         return;
254
255                 mlx5e_page_dma_unmap(rq, dma_info);
256                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
257         } else {
258                 mlx5e_page_dma_unmap(rq, dma_info);
259                 put_page(dma_info->page);
260         }
261 }
262
263 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
264                                     struct mlx5e_wqe_frag_info *frag)
265 {
266         int err = 0;
267
268         if (!frag->offset)
269                 /* On first frag (offset == 0), replenish page (dma_info actually).
270                  * Other frags that point to the same dma_info (with a different
271                  * offset) should just use the new one without replenishing again
272                  * by themselves.
273                  */
274                 err = mlx5e_page_alloc_mapped(rq, frag->di);
275
276         return err;
277 }
278
279 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
280                                      struct mlx5e_wqe_frag_info *frag,
281                                      bool recycle)
282 {
283         if (frag->last_in_page)
284                 mlx5e_page_release(rq, frag->di, recycle);
285 }
286
287 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
288 {
289         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
290 }
291
292 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
293                               u16 ix)
294 {
295         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
296         int err;
297         int i;
298
299         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
300                 err = mlx5e_get_rx_frag(rq, frag);
301                 if (unlikely(err))
302                         goto free_frags;
303
304                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
305                                                 frag->offset + rq->buff.headroom);
306         }
307
308         return 0;
309
310 free_frags:
311         while (--i >= 0)
312                 mlx5e_put_rx_frag(rq, --frag, true);
313
314         return err;
315 }
316
317 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
318                                      struct mlx5e_wqe_frag_info *wi,
319                                      bool recycle)
320 {
321         int i;
322
323         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
324                 mlx5e_put_rx_frag(rq, wi, recycle);
325 }
326
327 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
328 {
329         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
330
331         mlx5e_free_rx_wqe(rq, wi, false);
332 }
333
334 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
335 {
336         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
337         int err;
338         int i;
339
340         for (i = 0; i < wqe_bulk; i++) {
341                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
342
343                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
344                 if (unlikely(err))
345                         goto free_wqes;
346         }
347
348         return 0;
349
350 free_wqes:
351         while (--i >= 0)
352                 mlx5e_dealloc_rx_wqe(rq, ix + i);
353
354         return err;
355 }
356
357 static inline void
358 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
359                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
360                    unsigned int truesize)
361 {
362         dma_sync_single_for_cpu(rq->pdev,
363                                 di->addr + frag_offset,
364                                 len, DMA_FROM_DEVICE);
365         page_ref_inc(di->page);
366         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
367                         di->page, frag_offset, len, truesize);
368 }
369
370 static inline void
371 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
372                       struct mlx5e_dma_info *dma_info,
373                       int offset_from, int offset_to, u32 headlen)
374 {
375         const void *from = page_address(dma_info->page) + offset_from;
376         /* Aligning len to sizeof(long) optimizes memcpy performance */
377         unsigned int len = ALIGN(headlen, sizeof(long));
378
379         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
380                                 DMA_FROM_DEVICE);
381         skb_copy_to_linear_data_offset(skb, offset_to, from, len);
382 }
383
384 static inline void
385 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
386                             struct sk_buff *skb,
387                             struct mlx5e_dma_info *dma_info,
388                             u32 offset, u32 headlen)
389 {
390         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
391
392         mlx5e_copy_skb_header(pdev, skb, dma_info, offset, 0, headlen_pg);
393
394         if (unlikely(offset + headlen > PAGE_SIZE)) {
395                 dma_info++;
396                 mlx5e_copy_skb_header(pdev, skb, dma_info, 0, headlen_pg,
397                                       headlen - headlen_pg);
398         }
399 }
400
401 static void
402 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
403 {
404         const bool no_xdp_xmit =
405                 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
406         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
407         int i;
408
409         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
410                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
411                         mlx5e_page_release(rq, &dma_info[i], recycle);
412 }
413
414 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
415 {
416         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
417         struct mlx5e_rx_wqe_ll *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
418
419         rq->mpwqe.umr_in_progress = false;
420
421         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
422
423         /* ensure wqes are visible to device before updating doorbell record */
424         dma_wmb();
425
426         mlx5_wq_ll_update_db_record(wq);
427 }
428
429 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
430 {
431         return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
432 }
433
434 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
435                                               struct mlx5_wq_cyc *wq,
436                                               u16 pi, u16 frag_pi)
437 {
438         struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
439         u8 nnops = mlx5_wq_cyc_get_frag_size(wq) - frag_pi;
440
441         edge_wi = wi + nnops;
442
443         /* fill sq frag edge with nops to avoid wqe wrapping two pages */
444         for (; wi < edge_wi; wi++) {
445                 wi->opcode = MLX5_OPCODE_NOP;
446                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
447         }
448 }
449
450 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
451 {
452         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
453         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
454         struct mlx5e_icosq *sq = &rq->channel->icosq;
455         struct mlx5_wq_cyc *wq = &sq->wq;
456         struct mlx5e_umr_wqe *umr_wqe;
457         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
458         u16 pi, frag_pi;
459         int err;
460         int i;
461
462         pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
463         frag_pi = mlx5_wq_cyc_ctr2fragix(wq, sq->pc);
464
465         if (unlikely(frag_pi + MLX5E_UMR_WQEBBS > mlx5_wq_cyc_get_frag_size(wq))) {
466                 mlx5e_fill_icosq_frag_edge(sq, wq, pi, frag_pi);
467                 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
468         }
469
470         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
471         if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
472                 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
473                        offsetof(struct mlx5e_umr_wqe, inline_mtts));
474
475         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
476                 err = mlx5e_page_alloc_mapped(rq, dma_info);
477                 if (unlikely(err))
478                         goto err_unmap;
479                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
480         }
481
482         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
483         wi->consumed_strides = 0;
484
485         rq->mpwqe.umr_in_progress = true;
486
487         umr_wqe->ctrl.opmod_idx_opcode =
488                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
489                             MLX5_OPCODE_UMR);
490         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
491
492         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
493         sq->pc += MLX5E_UMR_WQEBBS;
494         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
495
496         return 0;
497
498 err_unmap:
499         while (--i >= 0) {
500                 dma_info--;
501                 mlx5e_page_release(rq, dma_info, true);
502         }
503         rq->stats->buff_alloc_err++;
504
505         return err;
506 }
507
508 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
509 {
510         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
511         /* Don't recycle, this function is called on rq/netdev close */
512         mlx5e_free_rx_mpwqe(rq, wi, false);
513 }
514
515 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
516 {
517         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
518         u8 wqe_bulk;
519         int err;
520
521         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
522                 return false;
523
524         wqe_bulk = rq->wqe.info.wqe_bulk;
525
526         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
527                 return false;
528
529         do {
530                 u16 head = mlx5_wq_cyc_get_head(wq);
531
532                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
533                 if (unlikely(err)) {
534                         rq->stats->buff_alloc_err++;
535                         break;
536                 }
537
538                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
539         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
540
541         /* ensure wqes are visible to device before updating doorbell record */
542         dma_wmb();
543
544         mlx5_wq_cyc_update_db_record(wq);
545
546         return !!err;
547 }
548
549 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
550                                              struct mlx5e_icosq *sq,
551                                              struct mlx5e_rq *rq,
552                                              struct mlx5_cqe64 *cqe)
553 {
554         struct mlx5_wq_cyc *wq = &sq->wq;
555         u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
556         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
557
558         mlx5_cqwq_pop(&cq->wq);
559
560         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
561                 netdev_WARN_ONCE(cq->channel->netdev,
562                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
563                 return;
564         }
565
566         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
567                 mlx5e_post_rx_mpwqe(rq);
568                 return;
569         }
570
571         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
572                 netdev_WARN_ONCE(cq->channel->netdev,
573                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
574 }
575
576 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
577 {
578         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
579         struct mlx5_cqe64 *cqe;
580
581         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
582                 return;
583
584         cqe = mlx5_cqwq_get_cqe(&cq->wq);
585         if (likely(!cqe))
586                 return;
587
588         /* by design, there's only a single cqe */
589         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
590
591         mlx5_cqwq_update_db_record(&cq->wq);
592 }
593
594 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
595 {
596         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
597
598         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
599                 return false;
600
601         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
602
603         if (mlx5_wq_ll_is_full(wq))
604                 return false;
605
606         if (!rq->mpwqe.umr_in_progress)
607                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
608         else
609                 rq->stats->congst_umr += mlx5_wq_ll_missing(wq) > 2;
610
611         return false;
612 }
613
614 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
615 {
616         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
617         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
618                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
619
620         tcp->check                      = 0;
621         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
622
623         if (tcp_ack) {
624                 tcp->ack                = 1;
625                 tcp->ack_seq            = cqe->lro_ack_seq_num;
626                 tcp->window             = cqe->lro_tcp_win;
627         }
628 }
629
630 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
631                                  u32 cqe_bcnt)
632 {
633         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
634         struct tcphdr   *tcp;
635         int network_depth = 0;
636         __wsum check;
637         __be16 proto;
638         u16 tot_len;
639         void *ip_p;
640
641         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
642
643         tot_len = cqe_bcnt - network_depth;
644         ip_p = skb->data + network_depth;
645
646         if (proto == htons(ETH_P_IP)) {
647                 struct iphdr *ipv4 = ip_p;
648
649                 tcp = ip_p + sizeof(struct iphdr);
650                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
651
652                 ipv4->ttl               = cqe->lro_min_ttl;
653                 ipv4->tot_len           = cpu_to_be16(tot_len);
654                 ipv4->check             = 0;
655                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
656                                                        ipv4->ihl);
657
658                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
659                 check = csum_partial(tcp, tcp->doff * 4,
660                                      csum_unfold((__force __sum16)cqe->check_sum));
661                 /* Almost done, don't forget the pseudo header */
662                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
663                                                tot_len - sizeof(struct iphdr),
664                                                IPPROTO_TCP, check);
665         } else {
666                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
667                 struct ipv6hdr *ipv6 = ip_p;
668
669                 tcp = ip_p + sizeof(struct ipv6hdr);
670                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
671
672                 ipv6->hop_limit         = cqe->lro_min_ttl;
673                 ipv6->payload_len       = cpu_to_be16(payload_len);
674
675                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
676                 check = csum_partial(tcp, tcp->doff * 4,
677                                      csum_unfold((__force __sum16)cqe->check_sum));
678                 /* Almost done, don't forget the pseudo header */
679                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
680                                              IPPROTO_TCP, check);
681         }
682 }
683
684 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
685                                       struct sk_buff *skb)
686 {
687         u8 cht = cqe->rss_hash_type;
688         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
689                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
690                                             PKT_HASH_TYPE_NONE;
691         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
692 }
693
694 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
695 {
696         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
697
698         ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
699         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
700 }
701
702 static __be32 mlx5e_get_fcs(struct sk_buff *skb)
703 {
704         int last_frag_sz, bytes_in_prev, nr_frags;
705         u8 *fcs_p1, *fcs_p2;
706         skb_frag_t *last_frag;
707         __be32 fcs_bytes;
708
709         if (!skb_is_nonlinear(skb))
710                 return *(__be32 *)(skb->data + skb->len - ETH_FCS_LEN);
711
712         nr_frags = skb_shinfo(skb)->nr_frags;
713         last_frag = &skb_shinfo(skb)->frags[nr_frags - 1];
714         last_frag_sz = skb_frag_size(last_frag);
715
716         /* If all FCS data is in last frag */
717         if (last_frag_sz >= ETH_FCS_LEN)
718                 return *(__be32 *)(skb_frag_address(last_frag) +
719                                    last_frag_sz - ETH_FCS_LEN);
720
721         fcs_p2 = (u8 *)skb_frag_address(last_frag);
722         bytes_in_prev = ETH_FCS_LEN - last_frag_sz;
723
724         /* Find where the other part of the FCS is - Linear or another frag */
725         if (nr_frags == 1) {
726                 fcs_p1 = skb_tail_pointer(skb);
727         } else {
728                 skb_frag_t *prev_frag = &skb_shinfo(skb)->frags[nr_frags - 2];
729
730                 fcs_p1 = skb_frag_address(prev_frag) +
731                             skb_frag_size(prev_frag);
732         }
733         fcs_p1 -= bytes_in_prev;
734
735         memcpy(&fcs_bytes, fcs_p1, bytes_in_prev);
736         memcpy(((u8 *)&fcs_bytes) + bytes_in_prev, fcs_p2, last_frag_sz);
737
738         return fcs_bytes;
739 }
740
741 static inline void mlx5e_handle_csum(struct net_device *netdev,
742                                      struct mlx5_cqe64 *cqe,
743                                      struct mlx5e_rq *rq,
744                                      struct sk_buff *skb,
745                                      bool   lro)
746 {
747         struct mlx5e_rq_stats *stats = rq->stats;
748         int network_depth = 0;
749
750         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
751                 goto csum_none;
752
753         if (lro) {
754                 skb->ip_summed = CHECKSUM_UNNECESSARY;
755                 stats->csum_unnecessary++;
756                 return;
757         }
758
759         if (likely(is_last_ethertype_ip(skb, &network_depth))) {
760                 skb->ip_summed = CHECKSUM_COMPLETE;
761                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
762                 if (network_depth > ETH_HLEN)
763                         /* CQE csum is calculated from the IP header and does
764                          * not cover VLAN headers (if present). This will add
765                          * the checksum manually.
766                          */
767                         skb->csum = csum_partial(skb->data + ETH_HLEN,
768                                                  network_depth - ETH_HLEN,
769                                                  skb->csum);
770                 if (unlikely(netdev->features & NETIF_F_RXFCS))
771                         skb->csum = csum_add(skb->csum,
772                                              (__force __wsum)mlx5e_get_fcs(skb));
773                 stats->csum_complete++;
774                 return;
775         }
776
777         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
778                    (cqe->hds_ip_ext & CQE_L4_OK))) {
779                 skb->ip_summed = CHECKSUM_UNNECESSARY;
780                 if (cqe_is_tunneled(cqe)) {
781                         skb->csum_level = 1;
782                         skb->encapsulation = 1;
783                         stats->csum_unnecessary_inner++;
784                         return;
785                 }
786                 stats->csum_unnecessary++;
787                 return;
788         }
789 csum_none:
790         skb->ip_summed = CHECKSUM_NONE;
791         stats->csum_none++;
792 }
793
794 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
795                                       u32 cqe_bcnt,
796                                       struct mlx5e_rq *rq,
797                                       struct sk_buff *skb)
798 {
799         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
800         struct mlx5e_rq_stats *stats = rq->stats;
801         struct net_device *netdev = rq->netdev;
802
803         skb->mac_len = ETH_HLEN;
804
805 #ifdef CONFIG_MLX5_EN_TLS
806         mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
807 #endif
808
809         if (lro_num_seg > 1) {
810                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
811                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
812                 /* Subtract one since we already counted this as one
813                  * "regular" packet in mlx5e_complete_rx_cqe()
814                  */
815                 stats->packets += lro_num_seg - 1;
816                 stats->lro_packets++;
817                 stats->lro_bytes += cqe_bcnt;
818         }
819
820         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
821                 skb_hwtstamps(skb)->hwtstamp =
822                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
823
824         skb_record_rx_queue(skb, rq->ix);
825
826         if (likely(netdev->features & NETIF_F_RXHASH))
827                 mlx5e_skb_set_hash(cqe, skb);
828
829         if (cqe_has_vlan(cqe)) {
830                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
831                                        be16_to_cpu(cqe->vlan_info));
832                 stats->removed_vlan_packets++;
833         }
834
835         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
836
837         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
838         skb->protocol = eth_type_trans(skb, netdev);
839 }
840
841 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
842                                          struct mlx5_cqe64 *cqe,
843                                          u32 cqe_bcnt,
844                                          struct sk_buff *skb)
845 {
846         struct mlx5e_rq_stats *stats = rq->stats;
847
848         stats->packets++;
849         stats->bytes += cqe_bcnt;
850         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
851 }
852
853 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
854 {
855         struct mlx5_wq_cyc *wq = &sq->wq;
856         struct mlx5e_tx_wqe *wqe;
857         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc - 1); /* last pi */
858
859         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
860
861         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
862 }
863
864 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
865                                         struct mlx5e_dma_info *di,
866                                         const struct xdp_buff *xdp)
867 {
868         struct mlx5e_xdpsq       *sq   = &rq->xdpsq;
869         struct mlx5_wq_cyc       *wq   = &sq->wq;
870         u16                       pi   = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
871         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
872
873         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
874         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
875         struct mlx5_wqe_data_seg *dseg;
876
877         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
878         dma_addr_t dma_addr  = di->addr + data_offset;
879         unsigned int dma_len = xdp->data_end - xdp->data;
880
881         struct mlx5e_rq_stats *stats = rq->stats;
882
883         prefetchw(wqe);
884
885         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || rq->hw_mtu < dma_len)) {
886                 stats->xdp_drop++;
887                 return false;
888         }
889
890         if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
891                 if (sq->db.doorbell) {
892                         /* SQ is full, ring doorbell */
893                         mlx5e_xmit_xdp_doorbell(sq);
894                         sq->db.doorbell = false;
895                 }
896                 stats->xdp_tx_full++;
897                 return false;
898         }
899
900         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
901
902         cseg->fm_ce_se = 0;
903
904         dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
905
906         /* copy the inline part if required */
907         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
908                 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
909                 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
910                 dma_len  -= MLX5E_XDP_MIN_INLINE;
911                 dma_addr += MLX5E_XDP_MIN_INLINE;
912                 dseg++;
913         }
914
915         /* write the dma part */
916         dseg->addr       = cpu_to_be64(dma_addr);
917         dseg->byte_count = cpu_to_be32(dma_len);
918
919         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
920
921         /* move page to reference to sq responsibility,
922          * and mark so it's not put back in page-cache.
923          */
924         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
925         sq->db.di[pi] = *di;
926         sq->pc++;
927
928         sq->db.doorbell = true;
929
930         stats->xdp_tx++;
931         return true;
932 }
933
934 /* returns true if packet was consumed by xdp */
935 static inline bool mlx5e_xdp_handle(struct mlx5e_rq *rq,
936                                     struct mlx5e_dma_info *di,
937                                     void *va, u16 *rx_headroom, u32 *len)
938 {
939         struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
940         struct xdp_buff xdp;
941         u32 act;
942         int err;
943
944         if (!prog)
945                 return false;
946
947         xdp.data = va + *rx_headroom;
948         xdp_set_data_meta_invalid(&xdp);
949         xdp.data_end = xdp.data + *len;
950         xdp.data_hard_start = va;
951         xdp.rxq = &rq->xdp_rxq;
952
953         act = bpf_prog_run_xdp(prog, &xdp);
954         switch (act) {
955         case XDP_PASS:
956                 *rx_headroom = xdp.data - xdp.data_hard_start;
957                 *len = xdp.data_end - xdp.data;
958                 return false;
959         case XDP_TX:
960                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
961                         trace_xdp_exception(rq->netdev, prog, act);
962                 return true;
963         case XDP_REDIRECT:
964                 /* When XDP enabled then page-refcnt==1 here */
965                 err = xdp_do_redirect(rq->netdev, &xdp, prog);
966                 if (!err) {
967                         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags);
968                         rq->xdpsq.db.redirect_flush = true;
969                         mlx5e_page_dma_unmap(rq, di);
970                 }
971                 return true;
972         default:
973                 bpf_warn_invalid_xdp_action(act);
974         case XDP_ABORTED:
975                 trace_xdp_exception(rq->netdev, prog, act);
976         case XDP_DROP:
977                 rq->stats->xdp_drop++;
978                 return true;
979         }
980 }
981
982 static inline
983 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
984                                        u32 frag_size, u16 headroom,
985                                        u32 cqe_bcnt)
986 {
987         struct sk_buff *skb = build_skb(va, frag_size);
988
989         if (unlikely(!skb)) {
990                 rq->stats->buff_alloc_err++;
991                 return NULL;
992         }
993
994         skb_reserve(skb, headroom);
995         skb_put(skb, cqe_bcnt);
996
997         return skb;
998 }
999
1000 struct sk_buff *
1001 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1002                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1003 {
1004         struct mlx5e_dma_info *di = wi->di;
1005         u16 rx_headroom = rq->buff.headroom;
1006         struct sk_buff *skb;
1007         void *va, *data;
1008         bool consumed;
1009         u32 frag_size;
1010
1011         va             = page_address(di->page) + wi->offset;
1012         data           = va + rx_headroom;
1013         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1014
1015         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1016                                       frag_size, DMA_FROM_DEVICE);
1017         prefetchw(va); /* xdp_frame data area */
1018         prefetch(data);
1019
1020         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1021                 rq->stats->wqe_err++;
1022                 return NULL;
1023         }
1024
1025         rcu_read_lock();
1026         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
1027         rcu_read_unlock();
1028         if (consumed)
1029                 return NULL; /* page/packet was consumed by XDP */
1030
1031         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1032         if (unlikely(!skb))
1033                 return NULL;
1034
1035         /* queue up for recycling/reuse */
1036         page_ref_inc(di->page);
1037
1038         return skb;
1039 }
1040
1041 struct sk_buff *
1042 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1043                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1044 {
1045         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1046         struct mlx5e_wqe_frag_info *head_wi = wi;
1047         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1048         u16 frag_headlen = headlen;
1049         u16 byte_cnt     = cqe_bcnt - headlen;
1050         struct sk_buff *skb;
1051
1052         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1053                 rq->stats->wqe_err++;
1054                 return NULL;
1055         }
1056
1057         /* XDP is not supported in this configuration, as incoming packets
1058          * might spread among multiple pages.
1059          */
1060         skb = napi_alloc_skb(rq->cq.napi,
1061                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1062         if (unlikely(!skb)) {
1063                 rq->stats->buff_alloc_err++;
1064                 return NULL;
1065         }
1066
1067         prefetchw(skb->data);
1068
1069         while (byte_cnt) {
1070                 u16 frag_consumed_bytes =
1071                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1072
1073                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1074                                    frag_consumed_bytes, frag_info->frag_stride);
1075                 byte_cnt -= frag_consumed_bytes;
1076                 frag_headlen = 0;
1077                 frag_info++;
1078                 wi++;
1079         }
1080
1081         /* copy header */
1082         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset,
1083                               0, headlen);
1084         /* skb linear part was allocated with headlen and aligned to long */
1085         skb->tail += headlen;
1086         skb->len  += headlen;
1087
1088         return skb;
1089 }
1090
1091 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1092 {
1093         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1094         struct mlx5e_wqe_frag_info *wi;
1095         struct sk_buff *skb;
1096         u32 cqe_bcnt;
1097         u16 ci;
1098
1099         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1100         wi       = get_frag(rq, ci);
1101         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1102
1103         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1104         if (!skb) {
1105                 /* probably for XDP */
1106                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1107                         /* do not return page to cache,
1108                          * it will be returned on XDP_TX completion.
1109                          */
1110                         goto wq_cyc_pop;
1111                 }
1112                 goto free_wqe;
1113         }
1114
1115         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1116         napi_gro_receive(rq->cq.napi, skb);
1117
1118 free_wqe:
1119         mlx5e_free_rx_wqe(rq, wi, true);
1120 wq_cyc_pop:
1121         mlx5_wq_cyc_pop(wq);
1122 }
1123
1124 #ifdef CONFIG_MLX5_ESWITCH
1125 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1126 {
1127         struct net_device *netdev = rq->netdev;
1128         struct mlx5e_priv *priv = netdev_priv(netdev);
1129         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1130         struct mlx5_eswitch_rep *rep = rpriv->rep;
1131         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1132         struct mlx5e_wqe_frag_info *wi;
1133         struct sk_buff *skb;
1134         u32 cqe_bcnt;
1135         u16 ci;
1136
1137         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1138         wi       = get_frag(rq, ci);
1139         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1140
1141         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1142         if (!skb) {
1143                 /* probably for XDP */
1144                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1145                         /* do not return page to cache,
1146                          * it will be returned on XDP_TX completion.
1147                          */
1148                         goto wq_cyc_pop;
1149                 }
1150                 goto free_wqe;
1151         }
1152
1153         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1154
1155         if (rep->vlan && skb_vlan_tag_present(skb))
1156                 skb_vlan_pop(skb);
1157
1158         napi_gro_receive(rq->cq.napi, skb);
1159
1160 free_wqe:
1161         mlx5e_free_rx_wqe(rq, wi, true);
1162 wq_cyc_pop:
1163         mlx5_wq_cyc_pop(wq);
1164 }
1165 #endif
1166
1167 struct sk_buff *
1168 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1169                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1170 {
1171         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1172         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1173         u32 frag_offset    = head_offset + headlen;
1174         u32 byte_cnt       = cqe_bcnt - headlen;
1175         struct mlx5e_dma_info *head_di = di;
1176         struct sk_buff *skb;
1177
1178         skb = napi_alloc_skb(rq->cq.napi,
1179                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1180         if (unlikely(!skb)) {
1181                 rq->stats->buff_alloc_err++;
1182                 return NULL;
1183         }
1184
1185         prefetchw(skb->data);
1186
1187         if (unlikely(frag_offset >= PAGE_SIZE)) {
1188                 di++;
1189                 frag_offset -= PAGE_SIZE;
1190         }
1191
1192         while (byte_cnt) {
1193                 u32 pg_consumed_bytes =
1194                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1195                 unsigned int truesize =
1196                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1197
1198                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1199                                    pg_consumed_bytes, truesize);
1200                 byte_cnt -= pg_consumed_bytes;
1201                 frag_offset = 0;
1202                 di++;
1203         }
1204         /* copy header */
1205         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1206                                     head_offset, headlen);
1207         /* skb linear part was allocated with headlen and aligned to long */
1208         skb->tail += headlen;
1209         skb->len  += headlen;
1210
1211         return skb;
1212 }
1213
1214 struct sk_buff *
1215 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1216                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1217 {
1218         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1219         u16 rx_headroom = rq->buff.headroom;
1220         u32 cqe_bcnt32 = cqe_bcnt;
1221         struct sk_buff *skb;
1222         void *va, *data;
1223         u32 frag_size;
1224         bool consumed;
1225
1226         va             = page_address(di->page) + head_offset;
1227         data           = va + rx_headroom;
1228         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1229
1230         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1231                                       frag_size, DMA_FROM_DEVICE);
1232         prefetch(data);
1233
1234         rcu_read_lock();
1235         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1236         rcu_read_unlock();
1237         if (consumed) {
1238                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1239                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1240                 return NULL; /* page/packet was consumed by XDP */
1241         }
1242
1243         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1244         if (unlikely(!skb))
1245                 return NULL;
1246
1247         /* queue up for recycling/reuse */
1248         page_ref_inc(di->page);
1249
1250         return skb;
1251 }
1252
1253 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1254 {
1255         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1256         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1257         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1258         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1259         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1260         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1261         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1262         struct mlx5e_rx_wqe_ll *wqe;
1263         struct mlx5_wq_ll *wq;
1264         struct sk_buff *skb;
1265         u16 cqe_bcnt;
1266
1267         wi->consumed_strides += cstrides;
1268
1269         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1270                 rq->stats->wqe_err++;
1271                 goto mpwrq_cqe_out;
1272         }
1273
1274         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1275                 struct mlx5e_rq_stats *stats = rq->stats;
1276
1277                 stats->mpwqe_filler_cqes++;
1278                 stats->mpwqe_filler_strides += cstrides;
1279                 goto mpwrq_cqe_out;
1280         }
1281
1282         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1283
1284         skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1285                                            page_idx);
1286         if (!skb)
1287                 goto mpwrq_cqe_out;
1288
1289         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1290         napi_gro_receive(rq->cq.napi, skb);
1291
1292 mpwrq_cqe_out:
1293         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1294                 return;
1295
1296         wq  = &rq->mpwqe.wq;
1297         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1298         mlx5e_free_rx_mpwqe(rq, wi, true);
1299         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1300 }
1301
1302 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1303 {
1304         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1305         struct mlx5e_xdpsq *xdpsq;
1306         struct mlx5_cqe64 *cqe;
1307         int work_done = 0;
1308
1309         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1310                 return 0;
1311
1312         if (cq->decmprs_left)
1313                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1314
1315         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1316         if (!cqe)
1317                 return 0;
1318
1319         xdpsq = &rq->xdpsq;
1320
1321         do {
1322                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1323                         work_done +=
1324                                 mlx5e_decompress_cqes_start(rq, cq,
1325                                                             budget - work_done);
1326                         continue;
1327                 }
1328
1329                 mlx5_cqwq_pop(&cq->wq);
1330
1331                 rq->handle_rx_cqe(rq, cqe);
1332         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1333
1334         if (xdpsq->db.doorbell) {
1335                 mlx5e_xmit_xdp_doorbell(xdpsq);
1336                 xdpsq->db.doorbell = false;
1337         }
1338
1339         if (xdpsq->db.redirect_flush) {
1340                 xdp_do_flush_map();
1341                 xdpsq->db.redirect_flush = false;
1342         }
1343
1344         mlx5_cqwq_update_db_record(&cq->wq);
1345
1346         /* ensure cq space is freed before enabling more cqes */
1347         wmb();
1348
1349         return work_done;
1350 }
1351
1352 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1353 {
1354         struct mlx5e_xdpsq *sq;
1355         struct mlx5_cqe64 *cqe;
1356         struct mlx5e_rq *rq;
1357         u16 sqcc;
1358         int i;
1359
1360         sq = container_of(cq, struct mlx5e_xdpsq, cq);
1361
1362         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
1363                 return false;
1364
1365         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1366         if (!cqe)
1367                 return false;
1368
1369         rq = container_of(sq, struct mlx5e_rq, xdpsq);
1370
1371         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1372          * otherwise a cq overrun may occur
1373          */
1374         sqcc = sq->cc;
1375
1376         i = 0;
1377         do {
1378                 u16 wqe_counter;
1379                 bool last_wqe;
1380
1381                 mlx5_cqwq_pop(&cq->wq);
1382
1383                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1384
1385                 do {
1386                         struct mlx5e_dma_info *di;
1387                         u16 ci;
1388
1389                         last_wqe = (sqcc == wqe_counter);
1390
1391                         ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
1392                         di = &sq->db.di[ci];
1393
1394                         sqcc++;
1395                         /* Recycle RX page */
1396                         mlx5e_page_release(rq, di, true);
1397                 } while (!last_wqe);
1398         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1399
1400         rq->stats->xdp_tx_cqe += i;
1401
1402         mlx5_cqwq_update_db_record(&cq->wq);
1403
1404         /* ensure cq space is freed before enabling more cqes */
1405         wmb();
1406
1407         sq->cc = sqcc;
1408         return (i == MLX5E_TX_CQ_POLL_BUDGET);
1409 }
1410
1411 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1412 {
1413         struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1414         struct mlx5e_dma_info *di;
1415         u16 ci;
1416
1417         while (sq->cc != sq->pc) {
1418                 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc);
1419                 di = &sq->db.di[ci];
1420                 sq->cc++;
1421
1422                 mlx5e_page_release(rq, di, false);
1423         }
1424 }
1425
1426 #ifdef CONFIG_MLX5_CORE_IPOIB
1427
1428 #define MLX5_IB_GRH_DGID_OFFSET 24
1429 #define MLX5_GID_SIZE           16
1430
1431 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1432                                          struct mlx5_cqe64 *cqe,
1433                                          u32 cqe_bcnt,
1434                                          struct sk_buff *skb)
1435 {
1436         struct mlx5e_rq_stats *stats = rq->stats;
1437         struct hwtstamp_config *tstamp;
1438         struct net_device *netdev;
1439         struct mlx5e_priv *priv;
1440         char *pseudo_header;
1441         u32 qpn;
1442         u8 *dgid;
1443         u8 g;
1444
1445         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1446         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1447
1448         /* No mapping present, cannot process SKB. This might happen if a child
1449          * interface is going down while having unprocessed CQEs on parent RQ
1450          */
1451         if (unlikely(!netdev)) {
1452                 /* TODO: add drop counters support */
1453                 skb->dev = NULL;
1454                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1455                 return;
1456         }
1457
1458         priv = mlx5i_epriv(netdev);
1459         tstamp = &priv->tstamp;
1460
1461         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1462         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1463         if ((!g) || dgid[0] != 0xff)
1464                 skb->pkt_type = PACKET_HOST;
1465         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1466                 skb->pkt_type = PACKET_BROADCAST;
1467         else
1468                 skb->pkt_type = PACKET_MULTICAST;
1469
1470         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1471          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1472          */
1473
1474         skb_pull(skb, MLX5_IB_GRH_BYTES);
1475
1476         skb->protocol = *((__be16 *)(skb->data));
1477
1478         skb->ip_summed = CHECKSUM_COMPLETE;
1479         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1480
1481         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1482                 skb_hwtstamps(skb)->hwtstamp =
1483                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1484
1485         skb_record_rx_queue(skb, rq->ix);
1486
1487         if (likely(netdev->features & NETIF_F_RXHASH))
1488                 mlx5e_skb_set_hash(cqe, skb);
1489
1490         /* 20 bytes of ipoib header and 4 for encap existing */
1491         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1492         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1493         skb_reset_mac_header(skb);
1494         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1495
1496         skb->dev = netdev;
1497
1498         stats->csum_complete++;
1499         stats->packets++;
1500         stats->bytes += cqe_bcnt;
1501 }
1502
1503 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1504 {
1505         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1506         struct mlx5e_wqe_frag_info *wi;
1507         struct sk_buff *skb;
1508         u32 cqe_bcnt;
1509         u16 ci;
1510
1511         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1512         wi       = get_frag(rq, ci);
1513         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1514
1515         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1516         if (!skb)
1517                 goto wq_free_wqe;
1518
1519         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1520         if (unlikely(!skb->dev)) {
1521                 dev_kfree_skb_any(skb);
1522                 goto wq_free_wqe;
1523         }
1524         napi_gro_receive(rq->cq.napi, skb);
1525
1526 wq_free_wqe:
1527         mlx5e_free_rx_wqe(rq, wi, true);
1528         mlx5_wq_cyc_pop(wq);
1529 }
1530
1531 #endif /* CONFIG_MLX5_CORE_IPOIB */
1532
1533 #ifdef CONFIG_MLX5_EN_IPSEC
1534
1535 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1536 {
1537         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1538         struct mlx5e_wqe_frag_info *wi;
1539         struct sk_buff *skb;
1540         u32 cqe_bcnt;
1541         u16 ci;
1542
1543         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1544         wi       = get_frag(rq, ci);
1545         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1546
1547         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1548         if (unlikely(!skb)) {
1549                 /* a DROP, save the page-reuse checks */
1550                 mlx5e_free_rx_wqe(rq, wi, true);
1551                 goto wq_cyc_pop;
1552         }
1553         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1554         if (unlikely(!skb)) {
1555                 mlx5e_free_rx_wqe(rq, wi, true);
1556                 goto wq_cyc_pop;
1557         }
1558
1559         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1560         napi_gro_receive(rq->cq.napi, skb);
1561
1562         mlx5e_free_rx_wqe(rq, wi, true);
1563 wq_cyc_pop:
1564         mlx5_wq_cyc_pop(wq);
1565 }
1566
1567 #endif /* CONFIG_MLX5_EN_IPSEC */