733c5d2c99f2631edf8cc4e42a7b3b70d3761efc
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_rx.c
1 /*
2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/prefetch.h>
34 #include <linux/ip.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/bpf_trace.h>
38 #include <net/busy_poll.h>
39 #include <net/ip6_checksum.h>
40 #include <net/page_pool.h>
41 #include "en.h"
42 #include "en_tc.h"
43 #include "eswitch.h"
44 #include "en_rep.h"
45 #include "ipoib/ipoib.h"
46 #include "en_accel/ipsec_rxtx.h"
47 #include "lib/clock.h"
48
49 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
50 {
51         return config->rx_filter == HWTSTAMP_FILTER_ALL;
52 }
53
54 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
55                                        void *data)
56 {
57         u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc);
58
59         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
60 }
61
62 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
63                                          struct mlx5e_cq *cq, u32 cqcc)
64 {
65         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
66         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
67         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
68         rq->stats->cqe_compress_blks++;
69 }
70
71 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
72 {
73         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
74         cq->mini_arr_idx = 0;
75 }
76
77 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
78 {
79         struct mlx5_cqwq *wq = &cq->wq;
80
81         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
82         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
83         u32 wq_sz  = mlx5_cqwq_get_size(wq);
84         u32 ci_top = min_t(u32, wq_sz, ci + n);
85
86         for (; ci < ci_top; ci++, n--) {
87                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
88
89                 cqe->op_own = op_own;
90         }
91
92         if (unlikely(ci == wq_sz)) {
93                 op_own = !op_own;
94                 for (ci = 0; ci < n; ci++) {
95                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
96
97                         cqe->op_own = op_own;
98                 }
99         }
100 }
101
102 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
103                                         struct mlx5e_cq *cq, u32 cqcc)
104 {
105         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
106         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
107         cq->title.op_own      &= 0xf0;
108         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
109         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
110
111         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
112                 cq->decmprs_wqe_counter +=
113                         mpwrq_get_cqe_consumed_strides(&cq->title);
114         else
115                 cq->decmprs_wqe_counter =
116                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cq->decmprs_wqe_counter + 1);
117 }
118
119 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
120                                                 struct mlx5e_cq *cq, u32 cqcc)
121 {
122         mlx5e_decompress_cqe(rq, cq, cqcc);
123         cq->title.rss_hash_type   = 0;
124         cq->title.rss_hash_result = 0;
125 }
126
127 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
128                                              struct mlx5e_cq *cq,
129                                              int update_owner_only,
130                                              int budget_rem)
131 {
132         u32 cqcc = cq->wq.cc + update_owner_only;
133         u32 cqe_count;
134         u32 i;
135
136         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
137
138         for (i = update_owner_only; i < cqe_count;
139              i++, cq->mini_arr_idx++, cqcc++) {
140                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
141                         mlx5e_read_mini_arr_slot(cq, cqcc);
142
143                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
144                 rq->handle_rx_cqe(rq, &cq->title);
145         }
146         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
147         cq->wq.cc = cqcc;
148         cq->decmprs_left -= cqe_count;
149         rq->stats->cqe_compress_pkts += cqe_count;
150
151         return cqe_count;
152 }
153
154 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
155                                               struct mlx5e_cq *cq,
156                                               int budget_rem)
157 {
158         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
159         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
160         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
161         rq->handle_rx_cqe(rq, &cq->title);
162         cq->mini_arr_idx++;
163
164         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
165 }
166
167 static inline bool mlx5e_page_is_reserved(struct page *page)
168 {
169         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
170 }
171
172 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
173                                       struct mlx5e_dma_info *dma_info)
174 {
175         struct mlx5e_page_cache *cache = &rq->page_cache;
176         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
177         struct mlx5e_rq_stats *stats = rq->stats;
178
179         if (tail_next == cache->head) {
180                 stats->cache_full++;
181                 return false;
182         }
183
184         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
185                 stats->cache_waive++;
186                 return false;
187         }
188
189         cache->page_cache[cache->tail] = *dma_info;
190         cache->tail = tail_next;
191         return true;
192 }
193
194 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
195                                       struct mlx5e_dma_info *dma_info)
196 {
197         struct mlx5e_page_cache *cache = &rq->page_cache;
198         struct mlx5e_rq_stats *stats = rq->stats;
199
200         if (unlikely(cache->head == cache->tail)) {
201                 stats->cache_empty++;
202                 return false;
203         }
204
205         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
206                 stats->cache_busy++;
207                 return false;
208         }
209
210         *dma_info = cache->page_cache[cache->head];
211         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
212         stats->cache_reuse++;
213
214         dma_sync_single_for_device(rq->pdev, dma_info->addr,
215                                    PAGE_SIZE,
216                                    DMA_FROM_DEVICE);
217         return true;
218 }
219
220 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
221                                           struct mlx5e_dma_info *dma_info)
222 {
223         if (mlx5e_rx_cache_get(rq, dma_info))
224                 return 0;
225
226         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
227         if (unlikely(!dma_info->page))
228                 return -ENOMEM;
229
230         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
231                                       PAGE_SIZE, rq->buff.map_dir);
232         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
233                 put_page(dma_info->page);
234                 dma_info->page = NULL;
235                 return -ENOMEM;
236         }
237
238         return 0;
239 }
240
241 static void mlx5e_page_dma_unmap(struct mlx5e_rq *rq,
242                                         struct mlx5e_dma_info *dma_info)
243 {
244         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
245 }
246
247 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
248                         bool recycle)
249 {
250         if (likely(recycle)) {
251                 if (mlx5e_rx_cache_put(rq, dma_info))
252                         return;
253
254                 mlx5e_page_dma_unmap(rq, dma_info);
255                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
256         } else {
257                 mlx5e_page_dma_unmap(rq, dma_info);
258                 put_page(dma_info->page);
259         }
260 }
261
262 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
263                                     struct mlx5e_wqe_frag_info *frag)
264 {
265         int err = 0;
266
267         if (!frag->offset)
268                 /* On first frag (offset == 0), replenish page (dma_info actually).
269                  * Other frags that point to the same dma_info (with a different
270                  * offset) should just use the new one without replenishing again
271                  * by themselves.
272                  */
273                 err = mlx5e_page_alloc_mapped(rq, frag->di);
274
275         return err;
276 }
277
278 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
279                                      struct mlx5e_wqe_frag_info *frag)
280 {
281         if (frag->last_in_page)
282                 mlx5e_page_release(rq, frag->di, true);
283 }
284
285 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
286 {
287         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
288 }
289
290 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
291                               u16 ix)
292 {
293         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
294         int err;
295         int i;
296
297         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
298                 err = mlx5e_get_rx_frag(rq, frag);
299                 if (unlikely(err))
300                         goto free_frags;
301
302                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
303                                                 frag->offset + rq->buff.headroom);
304         }
305
306         return 0;
307
308 free_frags:
309         while (--i >= 0)
310                 mlx5e_put_rx_frag(rq, --frag);
311
312         return err;
313 }
314
315 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
316                                      struct mlx5e_wqe_frag_info *wi)
317 {
318         int i;
319
320         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
321                 mlx5e_put_rx_frag(rq, wi);
322 }
323
324 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
325 {
326         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
327
328         mlx5e_free_rx_wqe(rq, wi);
329 }
330
331 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
332 {
333         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
334         int err;
335         int i;
336
337         for (i = 0; i < wqe_bulk; i++) {
338                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
339
340                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
341                 if (unlikely(err))
342                         goto free_wqes;
343         }
344
345         return 0;
346
347 free_wqes:
348         while (--i >= 0)
349                 mlx5e_dealloc_rx_wqe(rq, ix + i);
350
351         return err;
352 }
353
354 static inline void
355 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
356                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
357                    unsigned int truesize)
358 {
359         dma_sync_single_for_cpu(rq->pdev,
360                                 di->addr + frag_offset,
361                                 len, DMA_FROM_DEVICE);
362         page_ref_inc(di->page);
363         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
364                         di->page, frag_offset, len, truesize);
365 }
366
367 static inline void
368 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
369                       struct mlx5e_dma_info *dma_info,
370                       int offset_from, int offset_to, u32 headlen)
371 {
372         const void *from = page_address(dma_info->page) + offset_from;
373         /* Aligning len to sizeof(long) optimizes memcpy performance */
374         unsigned int len = ALIGN(headlen, sizeof(long));
375
376         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
377                                 DMA_FROM_DEVICE);
378         skb_copy_to_linear_data_offset(skb, offset_to, from, len);
379 }
380
381 static inline void
382 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
383                             struct sk_buff *skb,
384                             struct mlx5e_dma_info *dma_info,
385                             u32 offset, u32 headlen)
386 {
387         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
388
389         mlx5e_copy_skb_header(pdev, skb, dma_info, offset, 0, headlen_pg);
390
391         if (unlikely(offset + headlen > PAGE_SIZE)) {
392                 dma_info++;
393                 mlx5e_copy_skb_header(pdev, skb, dma_info, 0, headlen_pg,
394                                       headlen - headlen_pg);
395         }
396 }
397
398 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
399 {
400         const bool no_xdp_xmit =
401                 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
402         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
403         int i;
404
405         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
406                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
407                         mlx5e_page_release(rq, &dma_info[i], true);
408 }
409
410 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
411 {
412         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
413         struct mlx5e_rx_wqe_ll *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
414
415         rq->mpwqe.umr_in_progress = false;
416
417         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
418
419         /* ensure wqes are visible to device before updating doorbell record */
420         dma_wmb();
421
422         mlx5_wq_ll_update_db_record(wq);
423 }
424
425 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
426 {
427         return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
428 }
429
430 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
431                                               struct mlx5_wq_cyc *wq,
432                                               u16 pi, u16 frag_pi)
433 {
434         struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
435         u8 nnops = mlx5_wq_cyc_get_frag_size(wq) - frag_pi;
436
437         edge_wi = wi + nnops;
438
439         /* fill sq frag edge with nops to avoid wqe wrapping two pages */
440         for (; wi < edge_wi; wi++) {
441                 wi->opcode = MLX5_OPCODE_NOP;
442                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
443         }
444 }
445
446 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
447 {
448         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
449         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
450         struct mlx5e_icosq *sq = &rq->channel->icosq;
451         struct mlx5_wq_cyc *wq = &sq->wq;
452         struct mlx5e_umr_wqe *umr_wqe;
453         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
454         u16 pi, frag_pi;
455         int err;
456         int i;
457
458         pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
459         frag_pi = mlx5_wq_cyc_ctr2fragix(wq, sq->pc);
460
461         if (unlikely(frag_pi + MLX5E_UMR_WQEBBS > mlx5_wq_cyc_get_frag_size(wq))) {
462                 mlx5e_fill_icosq_frag_edge(sq, wq, pi, frag_pi);
463                 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
464         }
465
466         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
467         if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
468                 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
469                        offsetof(struct mlx5e_umr_wqe, inline_mtts));
470
471         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
472                 err = mlx5e_page_alloc_mapped(rq, dma_info);
473                 if (unlikely(err))
474                         goto err_unmap;
475                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
476         }
477
478         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
479         wi->consumed_strides = 0;
480
481         rq->mpwqe.umr_in_progress = true;
482
483         umr_wqe->ctrl.opmod_idx_opcode =
484                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
485                             MLX5_OPCODE_UMR);
486         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
487
488         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
489         sq->pc += MLX5E_UMR_WQEBBS;
490         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
491
492         return 0;
493
494 err_unmap:
495         while (--i >= 0) {
496                 dma_info--;
497                 mlx5e_page_release(rq, dma_info, true);
498         }
499         rq->stats->buff_alloc_err++;
500
501         return err;
502 }
503
504 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
505 {
506         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
507
508         mlx5e_free_rx_mpwqe(rq, wi);
509 }
510
511 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
512 {
513         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
514         u8 wqe_bulk;
515         int err;
516
517         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
518                 return false;
519
520         wqe_bulk = rq->wqe.info.wqe_bulk;
521
522         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
523                 return false;
524
525         do {
526                 u16 head = mlx5_wq_cyc_get_head(wq);
527
528                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
529                 if (unlikely(err)) {
530                         rq->stats->buff_alloc_err++;
531                         break;
532                 }
533
534                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
535         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
536
537         /* ensure wqes are visible to device before updating doorbell record */
538         dma_wmb();
539
540         mlx5_wq_cyc_update_db_record(wq);
541
542         return !!err;
543 }
544
545 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
546                                              struct mlx5e_icosq *sq,
547                                              struct mlx5e_rq *rq,
548                                              struct mlx5_cqe64 *cqe)
549 {
550         struct mlx5_wq_cyc *wq = &sq->wq;
551         u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
552         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
553
554         mlx5_cqwq_pop(&cq->wq);
555
556         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
557                 netdev_WARN_ONCE(cq->channel->netdev,
558                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
559                 return;
560         }
561
562         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
563                 mlx5e_post_rx_mpwqe(rq);
564                 return;
565         }
566
567         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
568                 netdev_WARN_ONCE(cq->channel->netdev,
569                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
570 }
571
572 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
573 {
574         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
575         struct mlx5_cqe64 *cqe;
576
577         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
578                 return;
579
580         cqe = mlx5_cqwq_get_cqe(&cq->wq);
581         if (likely(!cqe))
582                 return;
583
584         /* by design, there's only a single cqe */
585         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
586
587         mlx5_cqwq_update_db_record(&cq->wq);
588 }
589
590 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
591 {
592         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
593
594         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
595                 return false;
596
597         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
598
599         if (mlx5_wq_ll_is_full(wq))
600                 return false;
601
602         if (!rq->mpwqe.umr_in_progress)
603                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
604
605         return false;
606 }
607
608 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
609 {
610         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
611         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
612                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
613
614         tcp->check                      = 0;
615         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
616
617         if (tcp_ack) {
618                 tcp->ack                = 1;
619                 tcp->ack_seq            = cqe->lro_ack_seq_num;
620                 tcp->window             = cqe->lro_tcp_win;
621         }
622 }
623
624 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
625                                  u32 cqe_bcnt)
626 {
627         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
628         struct tcphdr   *tcp;
629         int network_depth = 0;
630         __wsum check;
631         __be16 proto;
632         u16 tot_len;
633         void *ip_p;
634
635         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
636
637         tot_len = cqe_bcnt - network_depth;
638         ip_p = skb->data + network_depth;
639
640         if (proto == htons(ETH_P_IP)) {
641                 struct iphdr *ipv4 = ip_p;
642
643                 tcp = ip_p + sizeof(struct iphdr);
644                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
645
646                 ipv4->ttl               = cqe->lro_min_ttl;
647                 ipv4->tot_len           = cpu_to_be16(tot_len);
648                 ipv4->check             = 0;
649                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
650                                                        ipv4->ihl);
651
652                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
653                 check = csum_partial(tcp, tcp->doff * 4,
654                                      csum_unfold((__force __sum16)cqe->check_sum));
655                 /* Almost done, don't forget the pseudo header */
656                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
657                                                tot_len - sizeof(struct iphdr),
658                                                IPPROTO_TCP, check);
659         } else {
660                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
661                 struct ipv6hdr *ipv6 = ip_p;
662
663                 tcp = ip_p + sizeof(struct ipv6hdr);
664                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
665
666                 ipv6->hop_limit         = cqe->lro_min_ttl;
667                 ipv6->payload_len       = cpu_to_be16(payload_len);
668
669                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
670                 check = csum_partial(tcp, tcp->doff * 4,
671                                      csum_unfold((__force __sum16)cqe->check_sum));
672                 /* Almost done, don't forget the pseudo header */
673                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
674                                              IPPROTO_TCP, check);
675         }
676 }
677
678 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
679                                       struct sk_buff *skb)
680 {
681         u8 cht = cqe->rss_hash_type;
682         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
683                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
684                                             PKT_HASH_TYPE_NONE;
685         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
686 }
687
688 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
689 {
690         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
691
692         ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
693         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
694 }
695
696 static __be32 mlx5e_get_fcs(struct sk_buff *skb)
697 {
698         int last_frag_sz, bytes_in_prev, nr_frags;
699         u8 *fcs_p1, *fcs_p2;
700         skb_frag_t *last_frag;
701         __be32 fcs_bytes;
702
703         if (!skb_is_nonlinear(skb))
704                 return *(__be32 *)(skb->data + skb->len - ETH_FCS_LEN);
705
706         nr_frags = skb_shinfo(skb)->nr_frags;
707         last_frag = &skb_shinfo(skb)->frags[nr_frags - 1];
708         last_frag_sz = skb_frag_size(last_frag);
709
710         /* If all FCS data is in last frag */
711         if (last_frag_sz >= ETH_FCS_LEN)
712                 return *(__be32 *)(skb_frag_address(last_frag) +
713                                    last_frag_sz - ETH_FCS_LEN);
714
715         fcs_p2 = (u8 *)skb_frag_address(last_frag);
716         bytes_in_prev = ETH_FCS_LEN - last_frag_sz;
717
718         /* Find where the other part of the FCS is - Linear or another frag */
719         if (nr_frags == 1) {
720                 fcs_p1 = skb_tail_pointer(skb);
721         } else {
722                 skb_frag_t *prev_frag = &skb_shinfo(skb)->frags[nr_frags - 2];
723
724                 fcs_p1 = skb_frag_address(prev_frag) +
725                             skb_frag_size(prev_frag);
726         }
727         fcs_p1 -= bytes_in_prev;
728
729         memcpy(&fcs_bytes, fcs_p1, bytes_in_prev);
730         memcpy(((u8 *)&fcs_bytes) + bytes_in_prev, fcs_p2, last_frag_sz);
731
732         return fcs_bytes;
733 }
734
735 static inline void mlx5e_handle_csum(struct net_device *netdev,
736                                      struct mlx5_cqe64 *cqe,
737                                      struct mlx5e_rq *rq,
738                                      struct sk_buff *skb,
739                                      bool   lro)
740 {
741         struct mlx5e_rq_stats *stats = rq->stats;
742         int network_depth = 0;
743
744         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
745                 goto csum_none;
746
747         if (lro) {
748                 skb->ip_summed = CHECKSUM_UNNECESSARY;
749                 stats->csum_unnecessary++;
750                 return;
751         }
752
753         if (likely(is_last_ethertype_ip(skb, &network_depth))) {
754                 skb->ip_summed = CHECKSUM_COMPLETE;
755                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
756                 if (network_depth > ETH_HLEN)
757                         /* CQE csum is calculated from the IP header and does
758                          * not cover VLAN headers (if present). This will add
759                          * the checksum manually.
760                          */
761                         skb->csum = csum_partial(skb->data + ETH_HLEN,
762                                                  network_depth - ETH_HLEN,
763                                                  skb->csum);
764                 if (unlikely(netdev->features & NETIF_F_RXFCS))
765                         skb->csum = csum_add(skb->csum,
766                                              (__force __wsum)mlx5e_get_fcs(skb));
767                 stats->csum_complete++;
768                 return;
769         }
770
771         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
772                    (cqe->hds_ip_ext & CQE_L4_OK))) {
773                 skb->ip_summed = CHECKSUM_UNNECESSARY;
774                 if (cqe_is_tunneled(cqe)) {
775                         skb->csum_level = 1;
776                         skb->encapsulation = 1;
777                         stats->csum_unnecessary_inner++;
778                         return;
779                 }
780                 stats->csum_unnecessary++;
781                 return;
782         }
783 csum_none:
784         skb->ip_summed = CHECKSUM_NONE;
785         stats->csum_none++;
786 }
787
788 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
789                                       u32 cqe_bcnt,
790                                       struct mlx5e_rq *rq,
791                                       struct sk_buff *skb)
792 {
793         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
794         struct mlx5e_rq_stats *stats = rq->stats;
795         struct net_device *netdev = rq->netdev;
796
797         skb->mac_len = ETH_HLEN;
798         if (lro_num_seg > 1) {
799                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
800                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
801                 /* Subtract one since we already counted this as one
802                  * "regular" packet in mlx5e_complete_rx_cqe()
803                  */
804                 stats->packets += lro_num_seg - 1;
805                 stats->lro_packets++;
806                 stats->lro_bytes += cqe_bcnt;
807         }
808
809         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
810                 skb_hwtstamps(skb)->hwtstamp =
811                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
812
813         skb_record_rx_queue(skb, rq->ix);
814
815         if (likely(netdev->features & NETIF_F_RXHASH))
816                 mlx5e_skb_set_hash(cqe, skb);
817
818         if (cqe_has_vlan(cqe)) {
819                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
820                                        be16_to_cpu(cqe->vlan_info));
821                 stats->removed_vlan_packets++;
822         }
823
824         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
825
826         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
827         skb->protocol = eth_type_trans(skb, netdev);
828 }
829
830 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
831                                          struct mlx5_cqe64 *cqe,
832                                          u32 cqe_bcnt,
833                                          struct sk_buff *skb)
834 {
835         struct mlx5e_rq_stats *stats = rq->stats;
836
837         stats->packets++;
838         stats->bytes += cqe_bcnt;
839         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
840 }
841
842 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
843 {
844         struct mlx5_wq_cyc *wq = &sq->wq;
845         struct mlx5e_tx_wqe *wqe;
846         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc - 1); /* last pi */
847
848         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
849
850         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
851 }
852
853 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
854                                         struct mlx5e_dma_info *di,
855                                         const struct xdp_buff *xdp)
856 {
857         struct mlx5e_xdpsq       *sq   = &rq->xdpsq;
858         struct mlx5_wq_cyc       *wq   = &sq->wq;
859         u16                       pi   = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
860         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
861
862         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
863         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
864         struct mlx5_wqe_data_seg *dseg;
865
866         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
867         dma_addr_t dma_addr  = di->addr + data_offset;
868         unsigned int dma_len = xdp->data_end - xdp->data;
869
870         struct mlx5e_rq_stats *stats = rq->stats;
871
872         prefetchw(wqe);
873
874         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || rq->hw_mtu < dma_len)) {
875                 stats->xdp_drop++;
876                 return false;
877         }
878
879         if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
880                 if (sq->db.doorbell) {
881                         /* SQ is full, ring doorbell */
882                         mlx5e_xmit_xdp_doorbell(sq);
883                         sq->db.doorbell = false;
884                 }
885                 stats->xdp_tx_full++;
886                 return false;
887         }
888
889         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
890
891         cseg->fm_ce_se = 0;
892
893         dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
894
895         /* copy the inline part if required */
896         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
897                 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
898                 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
899                 dma_len  -= MLX5E_XDP_MIN_INLINE;
900                 dma_addr += MLX5E_XDP_MIN_INLINE;
901                 dseg++;
902         }
903
904         /* write the dma part */
905         dseg->addr       = cpu_to_be64(dma_addr);
906         dseg->byte_count = cpu_to_be32(dma_len);
907
908         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
909
910         /* move page to reference to sq responsibility,
911          * and mark so it's not put back in page-cache.
912          */
913         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
914         sq->db.di[pi] = *di;
915         sq->pc++;
916
917         sq->db.doorbell = true;
918
919         stats->xdp_tx++;
920         return true;
921 }
922
923 /* returns true if packet was consumed by xdp */
924 static inline bool mlx5e_xdp_handle(struct mlx5e_rq *rq,
925                                     struct mlx5e_dma_info *di,
926                                     void *va, u16 *rx_headroom, u32 *len)
927 {
928         struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
929         struct xdp_buff xdp;
930         u32 act;
931         int err;
932
933         if (!prog)
934                 return false;
935
936         xdp.data = va + *rx_headroom;
937         xdp_set_data_meta_invalid(&xdp);
938         xdp.data_end = xdp.data + *len;
939         xdp.data_hard_start = va;
940         xdp.rxq = &rq->xdp_rxq;
941
942         act = bpf_prog_run_xdp(prog, &xdp);
943         switch (act) {
944         case XDP_PASS:
945                 *rx_headroom = xdp.data - xdp.data_hard_start;
946                 *len = xdp.data_end - xdp.data;
947                 return false;
948         case XDP_TX:
949                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
950                         trace_xdp_exception(rq->netdev, prog, act);
951                 return true;
952         case XDP_REDIRECT:
953                 /* When XDP enabled then page-refcnt==1 here */
954                 err = xdp_do_redirect(rq->netdev, &xdp, prog);
955                 if (!err) {
956                         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags);
957                         rq->xdpsq.db.redirect_flush = true;
958                         mlx5e_page_dma_unmap(rq, di);
959                 }
960                 return true;
961         default:
962                 bpf_warn_invalid_xdp_action(act);
963         case XDP_ABORTED:
964                 trace_xdp_exception(rq->netdev, prog, act);
965         case XDP_DROP:
966                 rq->stats->xdp_drop++;
967                 return true;
968         }
969 }
970
971 static inline
972 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
973                                        u32 frag_size, u16 headroom,
974                                        u32 cqe_bcnt)
975 {
976         struct sk_buff *skb = build_skb(va, frag_size);
977
978         if (unlikely(!skb)) {
979                 rq->stats->buff_alloc_err++;
980                 return NULL;
981         }
982
983         skb_reserve(skb, headroom);
984         skb_put(skb, cqe_bcnt);
985
986         return skb;
987 }
988
989 struct sk_buff *
990 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
991                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
992 {
993         struct mlx5e_dma_info *di = wi->di;
994         u16 rx_headroom = rq->buff.headroom;
995         struct sk_buff *skb;
996         void *va, *data;
997         bool consumed;
998         u32 frag_size;
999
1000         va             = page_address(di->page) + wi->offset;
1001         data           = va + rx_headroom;
1002         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1003
1004         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1005                                       frag_size, DMA_FROM_DEVICE);
1006         prefetchw(va); /* xdp_frame data area */
1007         prefetch(data);
1008
1009         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1010                 rq->stats->wqe_err++;
1011                 return NULL;
1012         }
1013
1014         rcu_read_lock();
1015         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
1016         rcu_read_unlock();
1017         if (consumed)
1018                 return NULL; /* page/packet was consumed by XDP */
1019
1020         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1021         if (unlikely(!skb))
1022                 return NULL;
1023
1024         /* queue up for recycling/reuse */
1025         page_ref_inc(di->page);
1026
1027         return skb;
1028 }
1029
1030 struct sk_buff *
1031 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1032                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1033 {
1034         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1035         struct mlx5e_wqe_frag_info *head_wi = wi;
1036         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1037         u16 frag_headlen = headlen;
1038         u16 byte_cnt     = cqe_bcnt - headlen;
1039         struct sk_buff *skb;
1040
1041         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1042                 rq->stats->wqe_err++;
1043                 return NULL;
1044         }
1045
1046         /* XDP is not supported in this configuration, as incoming packets
1047          * might spread among multiple pages.
1048          */
1049         skb = napi_alloc_skb(rq->cq.napi,
1050                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1051         if (unlikely(!skb)) {
1052                 rq->stats->buff_alloc_err++;
1053                 return NULL;
1054         }
1055
1056         prefetchw(skb->data);
1057
1058         while (byte_cnt) {
1059                 u16 frag_consumed_bytes =
1060                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1061
1062                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1063                                    frag_consumed_bytes, frag_info->frag_stride);
1064                 byte_cnt -= frag_consumed_bytes;
1065                 frag_headlen = 0;
1066                 frag_info++;
1067                 wi++;
1068         }
1069
1070         /* copy header */
1071         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset,
1072                               0, headlen);
1073         /* skb linear part was allocated with headlen and aligned to long */
1074         skb->tail += headlen;
1075         skb->len  += headlen;
1076
1077         return skb;
1078 }
1079
1080 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1081 {
1082         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1083         struct mlx5e_wqe_frag_info *wi;
1084         struct sk_buff *skb;
1085         u32 cqe_bcnt;
1086         u16 ci;
1087
1088         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1089         wi       = get_frag(rq, ci);
1090         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1091
1092         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1093         if (!skb) {
1094                 /* probably for XDP */
1095                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1096                         /* do not return page to cache,
1097                          * it will be returned on XDP_TX completion.
1098                          */
1099                         goto wq_cyc_pop;
1100                 }
1101                 goto free_wqe;
1102         }
1103
1104         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1105         napi_gro_receive(rq->cq.napi, skb);
1106
1107 free_wqe:
1108         mlx5e_free_rx_wqe(rq, wi);
1109 wq_cyc_pop:
1110         mlx5_wq_cyc_pop(wq);
1111 }
1112
1113 #ifdef CONFIG_MLX5_ESWITCH
1114 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1115 {
1116         struct net_device *netdev = rq->netdev;
1117         struct mlx5e_priv *priv = netdev_priv(netdev);
1118         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1119         struct mlx5_eswitch_rep *rep = rpriv->rep;
1120         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1121         struct mlx5e_wqe_frag_info *wi;
1122         struct sk_buff *skb;
1123         u32 cqe_bcnt;
1124         u16 ci;
1125
1126         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1127         wi       = get_frag(rq, ci);
1128         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1129
1130         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1131         if (!skb) {
1132                 /* probably for XDP */
1133                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1134                         /* do not return page to cache,
1135                          * it will be returned on XDP_TX completion.
1136                          */
1137                         goto wq_cyc_pop;
1138                 }
1139                 goto free_wqe;
1140         }
1141
1142         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1143
1144         if (rep->vlan && skb_vlan_tag_present(skb))
1145                 skb_vlan_pop(skb);
1146
1147         napi_gro_receive(rq->cq.napi, skb);
1148
1149 free_wqe:
1150         mlx5e_free_rx_wqe(rq, wi);
1151 wq_cyc_pop:
1152         mlx5_wq_cyc_pop(wq);
1153 }
1154 #endif
1155
1156 struct sk_buff *
1157 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1158                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1159 {
1160         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1161         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1162         u32 frag_offset    = head_offset + headlen;
1163         u32 byte_cnt       = cqe_bcnt - headlen;
1164         struct mlx5e_dma_info *head_di = di;
1165         struct sk_buff *skb;
1166
1167         skb = napi_alloc_skb(rq->cq.napi,
1168                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1169         if (unlikely(!skb)) {
1170                 rq->stats->buff_alloc_err++;
1171                 return NULL;
1172         }
1173
1174         prefetchw(skb->data);
1175
1176         if (unlikely(frag_offset >= PAGE_SIZE)) {
1177                 di++;
1178                 frag_offset -= PAGE_SIZE;
1179         }
1180
1181         while (byte_cnt) {
1182                 u32 pg_consumed_bytes =
1183                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1184                 unsigned int truesize =
1185                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1186
1187                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1188                                    pg_consumed_bytes, truesize);
1189                 byte_cnt -= pg_consumed_bytes;
1190                 frag_offset = 0;
1191                 di++;
1192         }
1193         /* copy header */
1194         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1195                                     head_offset, headlen);
1196         /* skb linear part was allocated with headlen and aligned to long */
1197         skb->tail += headlen;
1198         skb->len  += headlen;
1199
1200         return skb;
1201 }
1202
1203 struct sk_buff *
1204 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1205                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1206 {
1207         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1208         u16 rx_headroom = rq->buff.headroom;
1209         u32 cqe_bcnt32 = cqe_bcnt;
1210         struct sk_buff *skb;
1211         void *va, *data;
1212         u32 frag_size;
1213         bool consumed;
1214
1215         va             = page_address(di->page) + head_offset;
1216         data           = va + rx_headroom;
1217         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1218
1219         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1220                                       frag_size, DMA_FROM_DEVICE);
1221         prefetch(data);
1222
1223         rcu_read_lock();
1224         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1225         rcu_read_unlock();
1226         if (consumed) {
1227                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1228                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1229                 return NULL; /* page/packet was consumed by XDP */
1230         }
1231
1232         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1233         if (unlikely(!skb))
1234                 return NULL;
1235
1236         /* queue up for recycling/reuse */
1237         page_ref_inc(di->page);
1238
1239         return skb;
1240 }
1241
1242 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1243 {
1244         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1245         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1246         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1247         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1248         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1249         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1250         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1251         struct mlx5e_rx_wqe_ll *wqe;
1252         struct mlx5_wq_ll *wq;
1253         struct sk_buff *skb;
1254         u16 cqe_bcnt;
1255
1256         wi->consumed_strides += cstrides;
1257
1258         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1259                 rq->stats->wqe_err++;
1260                 goto mpwrq_cqe_out;
1261         }
1262
1263         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1264                 rq->stats->mpwqe_filler++;
1265                 goto mpwrq_cqe_out;
1266         }
1267
1268         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1269
1270         skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1271                                            page_idx);
1272         if (!skb)
1273                 goto mpwrq_cqe_out;
1274
1275         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1276         napi_gro_receive(rq->cq.napi, skb);
1277
1278 mpwrq_cqe_out:
1279         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1280                 return;
1281
1282         wq  = &rq->mpwqe.wq;
1283         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1284         mlx5e_free_rx_mpwqe(rq, wi);
1285         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1286 }
1287
1288 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1289 {
1290         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1291         struct mlx5e_xdpsq *xdpsq;
1292         struct mlx5_cqe64 *cqe;
1293         int work_done = 0;
1294
1295         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1296                 return 0;
1297
1298         if (cq->decmprs_left)
1299                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1300
1301         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1302         if (!cqe)
1303                 return 0;
1304
1305         xdpsq = &rq->xdpsq;
1306
1307         do {
1308                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1309                         work_done +=
1310                                 mlx5e_decompress_cqes_start(rq, cq,
1311                                                             budget - work_done);
1312                         continue;
1313                 }
1314
1315                 mlx5_cqwq_pop(&cq->wq);
1316
1317                 rq->handle_rx_cqe(rq, cqe);
1318         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1319
1320         if (xdpsq->db.doorbell) {
1321                 mlx5e_xmit_xdp_doorbell(xdpsq);
1322                 xdpsq->db.doorbell = false;
1323         }
1324
1325         if (xdpsq->db.redirect_flush) {
1326                 xdp_do_flush_map();
1327                 xdpsq->db.redirect_flush = false;
1328         }
1329
1330         mlx5_cqwq_update_db_record(&cq->wq);
1331
1332         /* ensure cq space is freed before enabling more cqes */
1333         wmb();
1334
1335         return work_done;
1336 }
1337
1338 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1339 {
1340         struct mlx5e_xdpsq *sq;
1341         struct mlx5_cqe64 *cqe;
1342         struct mlx5e_rq *rq;
1343         u16 sqcc;
1344         int i;
1345
1346         sq = container_of(cq, struct mlx5e_xdpsq, cq);
1347
1348         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
1349                 return false;
1350
1351         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1352         if (!cqe)
1353                 return false;
1354
1355         rq = container_of(sq, struct mlx5e_rq, xdpsq);
1356
1357         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1358          * otherwise a cq overrun may occur
1359          */
1360         sqcc = sq->cc;
1361
1362         i = 0;
1363         do {
1364                 u16 wqe_counter;
1365                 bool last_wqe;
1366
1367                 mlx5_cqwq_pop(&cq->wq);
1368
1369                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1370
1371                 do {
1372                         struct mlx5e_dma_info *di;
1373                         u16 ci;
1374
1375                         last_wqe = (sqcc == wqe_counter);
1376
1377                         ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
1378                         di = &sq->db.di[ci];
1379
1380                         sqcc++;
1381                         /* Recycle RX page */
1382                         mlx5e_page_release(rq, di, true);
1383                 } while (!last_wqe);
1384         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1385
1386         rq->stats->xdp_tx_cqe += i;
1387
1388         mlx5_cqwq_update_db_record(&cq->wq);
1389
1390         /* ensure cq space is freed before enabling more cqes */
1391         wmb();
1392
1393         sq->cc = sqcc;
1394         return (i == MLX5E_TX_CQ_POLL_BUDGET);
1395 }
1396
1397 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1398 {
1399         struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1400         struct mlx5e_dma_info *di;
1401         u16 ci;
1402
1403         while (sq->cc != sq->pc) {
1404                 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc);
1405                 di = &sq->db.di[ci];
1406                 sq->cc++;
1407
1408                 mlx5e_page_release(rq, di, false);
1409         }
1410 }
1411
1412 #ifdef CONFIG_MLX5_CORE_IPOIB
1413
1414 #define MLX5_IB_GRH_DGID_OFFSET 24
1415 #define MLX5_GID_SIZE           16
1416
1417 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1418                                          struct mlx5_cqe64 *cqe,
1419                                          u32 cqe_bcnt,
1420                                          struct sk_buff *skb)
1421 {
1422         struct mlx5e_rq_stats *stats = rq->stats;
1423         struct hwtstamp_config *tstamp;
1424         struct net_device *netdev;
1425         struct mlx5e_priv *priv;
1426         char *pseudo_header;
1427         u32 qpn;
1428         u8 *dgid;
1429         u8 g;
1430
1431         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1432         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1433
1434         /* No mapping present, cannot process SKB. This might happen if a child
1435          * interface is going down while having unprocessed CQEs on parent RQ
1436          */
1437         if (unlikely(!netdev)) {
1438                 /* TODO: add drop counters support */
1439                 skb->dev = NULL;
1440                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1441                 return;
1442         }
1443
1444         priv = mlx5i_epriv(netdev);
1445         tstamp = &priv->tstamp;
1446
1447         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1448         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1449         if ((!g) || dgid[0] != 0xff)
1450                 skb->pkt_type = PACKET_HOST;
1451         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1452                 skb->pkt_type = PACKET_BROADCAST;
1453         else
1454                 skb->pkt_type = PACKET_MULTICAST;
1455
1456         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1457          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1458          */
1459
1460         skb_pull(skb, MLX5_IB_GRH_BYTES);
1461
1462         skb->protocol = *((__be16 *)(skb->data));
1463
1464         skb->ip_summed = CHECKSUM_COMPLETE;
1465         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1466
1467         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1468                 skb_hwtstamps(skb)->hwtstamp =
1469                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1470
1471         skb_record_rx_queue(skb, rq->ix);
1472
1473         if (likely(netdev->features & NETIF_F_RXHASH))
1474                 mlx5e_skb_set_hash(cqe, skb);
1475
1476         /* 20 bytes of ipoib header and 4 for encap existing */
1477         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1478         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1479         skb_reset_mac_header(skb);
1480         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1481
1482         skb->dev = netdev;
1483
1484         stats->csum_complete++;
1485         stats->packets++;
1486         stats->bytes += cqe_bcnt;
1487 }
1488
1489 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1490 {
1491         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1492         struct mlx5e_wqe_frag_info *wi;
1493         struct sk_buff *skb;
1494         u32 cqe_bcnt;
1495         u16 ci;
1496
1497         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1498         wi       = get_frag(rq, ci);
1499         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1500
1501         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1502         if (!skb)
1503                 goto wq_free_wqe;
1504
1505         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1506         if (unlikely(!skb->dev)) {
1507                 dev_kfree_skb_any(skb);
1508                 goto wq_free_wqe;
1509         }
1510         napi_gro_receive(rq->cq.napi, skb);
1511
1512 wq_free_wqe:
1513         mlx5e_free_rx_wqe(rq, wi);
1514         mlx5_wq_cyc_pop(wq);
1515 }
1516
1517 #endif /* CONFIG_MLX5_CORE_IPOIB */
1518
1519 #ifdef CONFIG_MLX5_EN_IPSEC
1520
1521 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1522 {
1523         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1524         struct mlx5e_wqe_frag_info *wi;
1525         struct sk_buff *skb;
1526         u32 cqe_bcnt;
1527         u16 ci;
1528
1529         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1530         wi       = get_frag(rq, ci);
1531         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1532
1533         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1534         if (unlikely(!skb)) {
1535                 /* a DROP, save the page-reuse checks */
1536                 mlx5e_free_rx_wqe(rq, wi);
1537                 goto wq_cyc_pop;
1538         }
1539         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1540         if (unlikely(!skb)) {
1541                 mlx5e_free_rx_wqe(rq, wi);
1542                 goto wq_cyc_pop;
1543         }
1544
1545         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1546         napi_gro_receive(rq->cq.napi, skb);
1547
1548         mlx5e_free_rx_wqe(rq, wi);
1549 wq_cyc_pop:
1550         mlx5_wq_cyc_pop(wq);
1551 }
1552
1553 #endif /* CONFIG_MLX5_EN_IPSEC */