net/mlx5e: Add a counter for congested UMRs
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_rx.c
1 /*
2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/prefetch.h>
34 #include <linux/ip.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/bpf_trace.h>
38 #include <net/busy_poll.h>
39 #include <net/ip6_checksum.h>
40 #include <net/page_pool.h>
41 #include "en.h"
42 #include "en_tc.h"
43 #include "eswitch.h"
44 #include "en_rep.h"
45 #include "ipoib/ipoib.h"
46 #include "en_accel/ipsec_rxtx.h"
47 #include "lib/clock.h"
48
49 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
50 {
51         return config->rx_filter == HWTSTAMP_FILTER_ALL;
52 }
53
54 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
55                                        void *data)
56 {
57         u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc);
58
59         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
60 }
61
62 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
63                                          struct mlx5e_cq *cq, u32 cqcc)
64 {
65         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
66         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
67         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
68         rq->stats->cqe_compress_blks++;
69 }
70
71 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
72 {
73         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
74         cq->mini_arr_idx = 0;
75 }
76
77 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
78 {
79         struct mlx5_cqwq *wq = &cq->wq;
80
81         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
82         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
83         u32 wq_sz  = mlx5_cqwq_get_size(wq);
84         u32 ci_top = min_t(u32, wq_sz, ci + n);
85
86         for (; ci < ci_top; ci++, n--) {
87                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
88
89                 cqe->op_own = op_own;
90         }
91
92         if (unlikely(ci == wq_sz)) {
93                 op_own = !op_own;
94                 for (ci = 0; ci < n; ci++) {
95                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
96
97                         cqe->op_own = op_own;
98                 }
99         }
100 }
101
102 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
103                                         struct mlx5e_cq *cq, u32 cqcc)
104 {
105         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
106         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
107         cq->title.op_own      &= 0xf0;
108         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
109         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
110
111         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
112                 cq->decmprs_wqe_counter +=
113                         mpwrq_get_cqe_consumed_strides(&cq->title);
114         else
115                 cq->decmprs_wqe_counter =
116                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cq->decmprs_wqe_counter + 1);
117 }
118
119 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
120                                                 struct mlx5e_cq *cq, u32 cqcc)
121 {
122         mlx5e_decompress_cqe(rq, cq, cqcc);
123         cq->title.rss_hash_type   = 0;
124         cq->title.rss_hash_result = 0;
125 }
126
127 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
128                                              struct mlx5e_cq *cq,
129                                              int update_owner_only,
130                                              int budget_rem)
131 {
132         u32 cqcc = cq->wq.cc + update_owner_only;
133         u32 cqe_count;
134         u32 i;
135
136         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
137
138         for (i = update_owner_only; i < cqe_count;
139              i++, cq->mini_arr_idx++, cqcc++) {
140                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
141                         mlx5e_read_mini_arr_slot(cq, cqcc);
142
143                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
144                 rq->handle_rx_cqe(rq, &cq->title);
145         }
146         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
147         cq->wq.cc = cqcc;
148         cq->decmprs_left -= cqe_count;
149         rq->stats->cqe_compress_pkts += cqe_count;
150
151         return cqe_count;
152 }
153
154 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
155                                               struct mlx5e_cq *cq,
156                                               int budget_rem)
157 {
158         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
159         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
160         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
161         rq->handle_rx_cqe(rq, &cq->title);
162         cq->mini_arr_idx++;
163
164         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
165 }
166
167 static inline bool mlx5e_page_is_reserved(struct page *page)
168 {
169         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
170 }
171
172 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
173                                       struct mlx5e_dma_info *dma_info)
174 {
175         struct mlx5e_page_cache *cache = &rq->page_cache;
176         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
177         struct mlx5e_rq_stats *stats = rq->stats;
178
179         if (tail_next == cache->head) {
180                 stats->cache_full++;
181                 return false;
182         }
183
184         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
185                 stats->cache_waive++;
186                 return false;
187         }
188
189         cache->page_cache[cache->tail] = *dma_info;
190         cache->tail = tail_next;
191         return true;
192 }
193
194 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
195                                       struct mlx5e_dma_info *dma_info)
196 {
197         struct mlx5e_page_cache *cache = &rq->page_cache;
198         struct mlx5e_rq_stats *stats = rq->stats;
199
200         if (unlikely(cache->head == cache->tail)) {
201                 stats->cache_empty++;
202                 return false;
203         }
204
205         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
206                 stats->cache_busy++;
207                 return false;
208         }
209
210         *dma_info = cache->page_cache[cache->head];
211         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
212         stats->cache_reuse++;
213
214         dma_sync_single_for_device(rq->pdev, dma_info->addr,
215                                    PAGE_SIZE,
216                                    DMA_FROM_DEVICE);
217         return true;
218 }
219
220 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
221                                           struct mlx5e_dma_info *dma_info)
222 {
223         if (mlx5e_rx_cache_get(rq, dma_info))
224                 return 0;
225
226         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
227         if (unlikely(!dma_info->page))
228                 return -ENOMEM;
229
230         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
231                                       PAGE_SIZE, rq->buff.map_dir);
232         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
233                 put_page(dma_info->page);
234                 dma_info->page = NULL;
235                 return -ENOMEM;
236         }
237
238         return 0;
239 }
240
241 static void mlx5e_page_dma_unmap(struct mlx5e_rq *rq,
242                                         struct mlx5e_dma_info *dma_info)
243 {
244         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
245 }
246
247 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
248                         bool recycle)
249 {
250         if (likely(recycle)) {
251                 if (mlx5e_rx_cache_put(rq, dma_info))
252                         return;
253
254                 mlx5e_page_dma_unmap(rq, dma_info);
255                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
256         } else {
257                 mlx5e_page_dma_unmap(rq, dma_info);
258                 put_page(dma_info->page);
259         }
260 }
261
262 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
263                                     struct mlx5e_wqe_frag_info *frag)
264 {
265         int err = 0;
266
267         if (!frag->offset)
268                 /* On first frag (offset == 0), replenish page (dma_info actually).
269                  * Other frags that point to the same dma_info (with a different
270                  * offset) should just use the new one without replenishing again
271                  * by themselves.
272                  */
273                 err = mlx5e_page_alloc_mapped(rq, frag->di);
274
275         return err;
276 }
277
278 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
279                                      struct mlx5e_wqe_frag_info *frag)
280 {
281         if (frag->last_in_page)
282                 mlx5e_page_release(rq, frag->di, true);
283 }
284
285 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
286 {
287         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
288 }
289
290 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
291                               u16 ix)
292 {
293         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
294         int err;
295         int i;
296
297         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
298                 err = mlx5e_get_rx_frag(rq, frag);
299                 if (unlikely(err))
300                         goto free_frags;
301
302                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
303                                                 frag->offset + rq->buff.headroom);
304         }
305
306         return 0;
307
308 free_frags:
309         while (--i >= 0)
310                 mlx5e_put_rx_frag(rq, --frag);
311
312         return err;
313 }
314
315 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
316                                      struct mlx5e_wqe_frag_info *wi)
317 {
318         int i;
319
320         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
321                 mlx5e_put_rx_frag(rq, wi);
322 }
323
324 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
325 {
326         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
327
328         mlx5e_free_rx_wqe(rq, wi);
329 }
330
331 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
332 {
333         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
334         int err;
335         int i;
336
337         for (i = 0; i < wqe_bulk; i++) {
338                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
339
340                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
341                 if (unlikely(err))
342                         goto free_wqes;
343         }
344
345         return 0;
346
347 free_wqes:
348         while (--i >= 0)
349                 mlx5e_dealloc_rx_wqe(rq, ix + i);
350
351         return err;
352 }
353
354 static inline void
355 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
356                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
357                    unsigned int truesize)
358 {
359         dma_sync_single_for_cpu(rq->pdev,
360                                 di->addr + frag_offset,
361                                 len, DMA_FROM_DEVICE);
362         page_ref_inc(di->page);
363         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
364                         di->page, frag_offset, len, truesize);
365 }
366
367 static inline void
368 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
369                       struct mlx5e_dma_info *dma_info,
370                       int offset_from, int offset_to, u32 headlen)
371 {
372         const void *from = page_address(dma_info->page) + offset_from;
373         /* Aligning len to sizeof(long) optimizes memcpy performance */
374         unsigned int len = ALIGN(headlen, sizeof(long));
375
376         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
377                                 DMA_FROM_DEVICE);
378         skb_copy_to_linear_data_offset(skb, offset_to, from, len);
379 }
380
381 static inline void
382 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
383                             struct sk_buff *skb,
384                             struct mlx5e_dma_info *dma_info,
385                             u32 offset, u32 headlen)
386 {
387         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
388
389         mlx5e_copy_skb_header(pdev, skb, dma_info, offset, 0, headlen_pg);
390
391         if (unlikely(offset + headlen > PAGE_SIZE)) {
392                 dma_info++;
393                 mlx5e_copy_skb_header(pdev, skb, dma_info, 0, headlen_pg,
394                                       headlen - headlen_pg);
395         }
396 }
397
398 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
399 {
400         const bool no_xdp_xmit =
401                 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
402         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
403         int i;
404
405         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
406                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
407                         mlx5e_page_release(rq, &dma_info[i], true);
408 }
409
410 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
411 {
412         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
413         struct mlx5e_rx_wqe_ll *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
414
415         rq->mpwqe.umr_in_progress = false;
416
417         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
418
419         /* ensure wqes are visible to device before updating doorbell record */
420         dma_wmb();
421
422         mlx5_wq_ll_update_db_record(wq);
423 }
424
425 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
426 {
427         return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
428 }
429
430 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
431                                               struct mlx5_wq_cyc *wq,
432                                               u16 pi, u16 frag_pi)
433 {
434         struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
435         u8 nnops = mlx5_wq_cyc_get_frag_size(wq) - frag_pi;
436
437         edge_wi = wi + nnops;
438
439         /* fill sq frag edge with nops to avoid wqe wrapping two pages */
440         for (; wi < edge_wi; wi++) {
441                 wi->opcode = MLX5_OPCODE_NOP;
442                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
443         }
444 }
445
446 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
447 {
448         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
449         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
450         struct mlx5e_icosq *sq = &rq->channel->icosq;
451         struct mlx5_wq_cyc *wq = &sq->wq;
452         struct mlx5e_umr_wqe *umr_wqe;
453         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
454         u16 pi, frag_pi;
455         int err;
456         int i;
457
458         pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
459         frag_pi = mlx5_wq_cyc_ctr2fragix(wq, sq->pc);
460
461         if (unlikely(frag_pi + MLX5E_UMR_WQEBBS > mlx5_wq_cyc_get_frag_size(wq))) {
462                 mlx5e_fill_icosq_frag_edge(sq, wq, pi, frag_pi);
463                 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
464         }
465
466         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
467         if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
468                 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
469                        offsetof(struct mlx5e_umr_wqe, inline_mtts));
470
471         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
472                 err = mlx5e_page_alloc_mapped(rq, dma_info);
473                 if (unlikely(err))
474                         goto err_unmap;
475                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
476         }
477
478         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
479         wi->consumed_strides = 0;
480
481         rq->mpwqe.umr_in_progress = true;
482
483         umr_wqe->ctrl.opmod_idx_opcode =
484                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
485                             MLX5_OPCODE_UMR);
486         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
487
488         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
489         sq->pc += MLX5E_UMR_WQEBBS;
490         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
491
492         return 0;
493
494 err_unmap:
495         while (--i >= 0) {
496                 dma_info--;
497                 mlx5e_page_release(rq, dma_info, true);
498         }
499         rq->stats->buff_alloc_err++;
500
501         return err;
502 }
503
504 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
505 {
506         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
507
508         mlx5e_free_rx_mpwqe(rq, wi);
509 }
510
511 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
512 {
513         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
514         u8 wqe_bulk;
515         int err;
516
517         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
518                 return false;
519
520         wqe_bulk = rq->wqe.info.wqe_bulk;
521
522         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
523                 return false;
524
525         do {
526                 u16 head = mlx5_wq_cyc_get_head(wq);
527
528                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
529                 if (unlikely(err)) {
530                         rq->stats->buff_alloc_err++;
531                         break;
532                 }
533
534                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
535         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
536
537         /* ensure wqes are visible to device before updating doorbell record */
538         dma_wmb();
539
540         mlx5_wq_cyc_update_db_record(wq);
541
542         return !!err;
543 }
544
545 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
546                                              struct mlx5e_icosq *sq,
547                                              struct mlx5e_rq *rq,
548                                              struct mlx5_cqe64 *cqe)
549 {
550         struct mlx5_wq_cyc *wq = &sq->wq;
551         u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
552         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
553
554         mlx5_cqwq_pop(&cq->wq);
555
556         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
557                 netdev_WARN_ONCE(cq->channel->netdev,
558                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
559                 return;
560         }
561
562         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
563                 mlx5e_post_rx_mpwqe(rq);
564                 return;
565         }
566
567         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
568                 netdev_WARN_ONCE(cq->channel->netdev,
569                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
570 }
571
572 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
573 {
574         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
575         struct mlx5_cqe64 *cqe;
576
577         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
578                 return;
579
580         cqe = mlx5_cqwq_get_cqe(&cq->wq);
581         if (likely(!cqe))
582                 return;
583
584         /* by design, there's only a single cqe */
585         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
586
587         mlx5_cqwq_update_db_record(&cq->wq);
588 }
589
590 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
591 {
592         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
593
594         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
595                 return false;
596
597         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
598
599         if (mlx5_wq_ll_is_full(wq))
600                 return false;
601
602         if (!rq->mpwqe.umr_in_progress)
603                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
604         else
605                 rq->stats->congst_umr += mlx5_wq_ll_missing(wq) > 2;
606
607         return false;
608 }
609
610 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
611 {
612         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
613         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
614                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
615
616         tcp->check                      = 0;
617         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
618
619         if (tcp_ack) {
620                 tcp->ack                = 1;
621                 tcp->ack_seq            = cqe->lro_ack_seq_num;
622                 tcp->window             = cqe->lro_tcp_win;
623         }
624 }
625
626 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
627                                  u32 cqe_bcnt)
628 {
629         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
630         struct tcphdr   *tcp;
631         int network_depth = 0;
632         __wsum check;
633         __be16 proto;
634         u16 tot_len;
635         void *ip_p;
636
637         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
638
639         tot_len = cqe_bcnt - network_depth;
640         ip_p = skb->data + network_depth;
641
642         if (proto == htons(ETH_P_IP)) {
643                 struct iphdr *ipv4 = ip_p;
644
645                 tcp = ip_p + sizeof(struct iphdr);
646                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
647
648                 ipv4->ttl               = cqe->lro_min_ttl;
649                 ipv4->tot_len           = cpu_to_be16(tot_len);
650                 ipv4->check             = 0;
651                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
652                                                        ipv4->ihl);
653
654                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
655                 check = csum_partial(tcp, tcp->doff * 4,
656                                      csum_unfold((__force __sum16)cqe->check_sum));
657                 /* Almost done, don't forget the pseudo header */
658                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
659                                                tot_len - sizeof(struct iphdr),
660                                                IPPROTO_TCP, check);
661         } else {
662                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
663                 struct ipv6hdr *ipv6 = ip_p;
664
665                 tcp = ip_p + sizeof(struct ipv6hdr);
666                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
667
668                 ipv6->hop_limit         = cqe->lro_min_ttl;
669                 ipv6->payload_len       = cpu_to_be16(payload_len);
670
671                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
672                 check = csum_partial(tcp, tcp->doff * 4,
673                                      csum_unfold((__force __sum16)cqe->check_sum));
674                 /* Almost done, don't forget the pseudo header */
675                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
676                                              IPPROTO_TCP, check);
677         }
678 }
679
680 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
681                                       struct sk_buff *skb)
682 {
683         u8 cht = cqe->rss_hash_type;
684         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
685                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
686                                             PKT_HASH_TYPE_NONE;
687         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
688 }
689
690 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
691 {
692         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
693
694         ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
695         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
696 }
697
698 static __be32 mlx5e_get_fcs(struct sk_buff *skb)
699 {
700         int last_frag_sz, bytes_in_prev, nr_frags;
701         u8 *fcs_p1, *fcs_p2;
702         skb_frag_t *last_frag;
703         __be32 fcs_bytes;
704
705         if (!skb_is_nonlinear(skb))
706                 return *(__be32 *)(skb->data + skb->len - ETH_FCS_LEN);
707
708         nr_frags = skb_shinfo(skb)->nr_frags;
709         last_frag = &skb_shinfo(skb)->frags[nr_frags - 1];
710         last_frag_sz = skb_frag_size(last_frag);
711
712         /* If all FCS data is in last frag */
713         if (last_frag_sz >= ETH_FCS_LEN)
714                 return *(__be32 *)(skb_frag_address(last_frag) +
715                                    last_frag_sz - ETH_FCS_LEN);
716
717         fcs_p2 = (u8 *)skb_frag_address(last_frag);
718         bytes_in_prev = ETH_FCS_LEN - last_frag_sz;
719
720         /* Find where the other part of the FCS is - Linear or another frag */
721         if (nr_frags == 1) {
722                 fcs_p1 = skb_tail_pointer(skb);
723         } else {
724                 skb_frag_t *prev_frag = &skb_shinfo(skb)->frags[nr_frags - 2];
725
726                 fcs_p1 = skb_frag_address(prev_frag) +
727                             skb_frag_size(prev_frag);
728         }
729         fcs_p1 -= bytes_in_prev;
730
731         memcpy(&fcs_bytes, fcs_p1, bytes_in_prev);
732         memcpy(((u8 *)&fcs_bytes) + bytes_in_prev, fcs_p2, last_frag_sz);
733
734         return fcs_bytes;
735 }
736
737 static inline void mlx5e_handle_csum(struct net_device *netdev,
738                                      struct mlx5_cqe64 *cqe,
739                                      struct mlx5e_rq *rq,
740                                      struct sk_buff *skb,
741                                      bool   lro)
742 {
743         struct mlx5e_rq_stats *stats = rq->stats;
744         int network_depth = 0;
745
746         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
747                 goto csum_none;
748
749         if (lro) {
750                 skb->ip_summed = CHECKSUM_UNNECESSARY;
751                 stats->csum_unnecessary++;
752                 return;
753         }
754
755         if (likely(is_last_ethertype_ip(skb, &network_depth))) {
756                 skb->ip_summed = CHECKSUM_COMPLETE;
757                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
758                 if (network_depth > ETH_HLEN)
759                         /* CQE csum is calculated from the IP header and does
760                          * not cover VLAN headers (if present). This will add
761                          * the checksum manually.
762                          */
763                         skb->csum = csum_partial(skb->data + ETH_HLEN,
764                                                  network_depth - ETH_HLEN,
765                                                  skb->csum);
766                 if (unlikely(netdev->features & NETIF_F_RXFCS))
767                         skb->csum = csum_add(skb->csum,
768                                              (__force __wsum)mlx5e_get_fcs(skb));
769                 stats->csum_complete++;
770                 return;
771         }
772
773         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
774                    (cqe->hds_ip_ext & CQE_L4_OK))) {
775                 skb->ip_summed = CHECKSUM_UNNECESSARY;
776                 if (cqe_is_tunneled(cqe)) {
777                         skb->csum_level = 1;
778                         skb->encapsulation = 1;
779                         stats->csum_unnecessary_inner++;
780                         return;
781                 }
782                 stats->csum_unnecessary++;
783                 return;
784         }
785 csum_none:
786         skb->ip_summed = CHECKSUM_NONE;
787         stats->csum_none++;
788 }
789
790 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
791                                       u32 cqe_bcnt,
792                                       struct mlx5e_rq *rq,
793                                       struct sk_buff *skb)
794 {
795         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
796         struct mlx5e_rq_stats *stats = rq->stats;
797         struct net_device *netdev = rq->netdev;
798
799         skb->mac_len = ETH_HLEN;
800         if (lro_num_seg > 1) {
801                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
802                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
803                 /* Subtract one since we already counted this as one
804                  * "regular" packet in mlx5e_complete_rx_cqe()
805                  */
806                 stats->packets += lro_num_seg - 1;
807                 stats->lro_packets++;
808                 stats->lro_bytes += cqe_bcnt;
809         }
810
811         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
812                 skb_hwtstamps(skb)->hwtstamp =
813                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
814
815         skb_record_rx_queue(skb, rq->ix);
816
817         if (likely(netdev->features & NETIF_F_RXHASH))
818                 mlx5e_skb_set_hash(cqe, skb);
819
820         if (cqe_has_vlan(cqe)) {
821                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
822                                        be16_to_cpu(cqe->vlan_info));
823                 stats->removed_vlan_packets++;
824         }
825
826         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
827
828         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
829         skb->protocol = eth_type_trans(skb, netdev);
830 }
831
832 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
833                                          struct mlx5_cqe64 *cqe,
834                                          u32 cqe_bcnt,
835                                          struct sk_buff *skb)
836 {
837         struct mlx5e_rq_stats *stats = rq->stats;
838
839         stats->packets++;
840         stats->bytes += cqe_bcnt;
841         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
842 }
843
844 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
845 {
846         struct mlx5_wq_cyc *wq = &sq->wq;
847         struct mlx5e_tx_wqe *wqe;
848         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc - 1); /* last pi */
849
850         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
851
852         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
853 }
854
855 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
856                                         struct mlx5e_dma_info *di,
857                                         const struct xdp_buff *xdp)
858 {
859         struct mlx5e_xdpsq       *sq   = &rq->xdpsq;
860         struct mlx5_wq_cyc       *wq   = &sq->wq;
861         u16                       pi   = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
862         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
863
864         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
865         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
866         struct mlx5_wqe_data_seg *dseg;
867
868         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
869         dma_addr_t dma_addr  = di->addr + data_offset;
870         unsigned int dma_len = xdp->data_end - xdp->data;
871
872         struct mlx5e_rq_stats *stats = rq->stats;
873
874         prefetchw(wqe);
875
876         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || rq->hw_mtu < dma_len)) {
877                 stats->xdp_drop++;
878                 return false;
879         }
880
881         if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
882                 if (sq->db.doorbell) {
883                         /* SQ is full, ring doorbell */
884                         mlx5e_xmit_xdp_doorbell(sq);
885                         sq->db.doorbell = false;
886                 }
887                 stats->xdp_tx_full++;
888                 return false;
889         }
890
891         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
892
893         cseg->fm_ce_se = 0;
894
895         dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
896
897         /* copy the inline part if required */
898         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
899                 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
900                 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
901                 dma_len  -= MLX5E_XDP_MIN_INLINE;
902                 dma_addr += MLX5E_XDP_MIN_INLINE;
903                 dseg++;
904         }
905
906         /* write the dma part */
907         dseg->addr       = cpu_to_be64(dma_addr);
908         dseg->byte_count = cpu_to_be32(dma_len);
909
910         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
911
912         /* move page to reference to sq responsibility,
913          * and mark so it's not put back in page-cache.
914          */
915         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
916         sq->db.di[pi] = *di;
917         sq->pc++;
918
919         sq->db.doorbell = true;
920
921         stats->xdp_tx++;
922         return true;
923 }
924
925 /* returns true if packet was consumed by xdp */
926 static inline bool mlx5e_xdp_handle(struct mlx5e_rq *rq,
927                                     struct mlx5e_dma_info *di,
928                                     void *va, u16 *rx_headroom, u32 *len)
929 {
930         struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
931         struct xdp_buff xdp;
932         u32 act;
933         int err;
934
935         if (!prog)
936                 return false;
937
938         xdp.data = va + *rx_headroom;
939         xdp_set_data_meta_invalid(&xdp);
940         xdp.data_end = xdp.data + *len;
941         xdp.data_hard_start = va;
942         xdp.rxq = &rq->xdp_rxq;
943
944         act = bpf_prog_run_xdp(prog, &xdp);
945         switch (act) {
946         case XDP_PASS:
947                 *rx_headroom = xdp.data - xdp.data_hard_start;
948                 *len = xdp.data_end - xdp.data;
949                 return false;
950         case XDP_TX:
951                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
952                         trace_xdp_exception(rq->netdev, prog, act);
953                 return true;
954         case XDP_REDIRECT:
955                 /* When XDP enabled then page-refcnt==1 here */
956                 err = xdp_do_redirect(rq->netdev, &xdp, prog);
957                 if (!err) {
958                         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags);
959                         rq->xdpsq.db.redirect_flush = true;
960                         mlx5e_page_dma_unmap(rq, di);
961                 }
962                 return true;
963         default:
964                 bpf_warn_invalid_xdp_action(act);
965         case XDP_ABORTED:
966                 trace_xdp_exception(rq->netdev, prog, act);
967         case XDP_DROP:
968                 rq->stats->xdp_drop++;
969                 return true;
970         }
971 }
972
973 static inline
974 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
975                                        u32 frag_size, u16 headroom,
976                                        u32 cqe_bcnt)
977 {
978         struct sk_buff *skb = build_skb(va, frag_size);
979
980         if (unlikely(!skb)) {
981                 rq->stats->buff_alloc_err++;
982                 return NULL;
983         }
984
985         skb_reserve(skb, headroom);
986         skb_put(skb, cqe_bcnt);
987
988         return skb;
989 }
990
991 struct sk_buff *
992 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
993                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
994 {
995         struct mlx5e_dma_info *di = wi->di;
996         u16 rx_headroom = rq->buff.headroom;
997         struct sk_buff *skb;
998         void *va, *data;
999         bool consumed;
1000         u32 frag_size;
1001
1002         va             = page_address(di->page) + wi->offset;
1003         data           = va + rx_headroom;
1004         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1005
1006         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1007                                       frag_size, DMA_FROM_DEVICE);
1008         prefetchw(va); /* xdp_frame data area */
1009         prefetch(data);
1010
1011         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1012                 rq->stats->wqe_err++;
1013                 return NULL;
1014         }
1015
1016         rcu_read_lock();
1017         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
1018         rcu_read_unlock();
1019         if (consumed)
1020                 return NULL; /* page/packet was consumed by XDP */
1021
1022         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1023         if (unlikely(!skb))
1024                 return NULL;
1025
1026         /* queue up for recycling/reuse */
1027         page_ref_inc(di->page);
1028
1029         return skb;
1030 }
1031
1032 struct sk_buff *
1033 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1034                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1035 {
1036         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1037         struct mlx5e_wqe_frag_info *head_wi = wi;
1038         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1039         u16 frag_headlen = headlen;
1040         u16 byte_cnt     = cqe_bcnt - headlen;
1041         struct sk_buff *skb;
1042
1043         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1044                 rq->stats->wqe_err++;
1045                 return NULL;
1046         }
1047
1048         /* XDP is not supported in this configuration, as incoming packets
1049          * might spread among multiple pages.
1050          */
1051         skb = napi_alloc_skb(rq->cq.napi,
1052                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1053         if (unlikely(!skb)) {
1054                 rq->stats->buff_alloc_err++;
1055                 return NULL;
1056         }
1057
1058         prefetchw(skb->data);
1059
1060         while (byte_cnt) {
1061                 u16 frag_consumed_bytes =
1062                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1063
1064                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1065                                    frag_consumed_bytes, frag_info->frag_stride);
1066                 byte_cnt -= frag_consumed_bytes;
1067                 frag_headlen = 0;
1068                 frag_info++;
1069                 wi++;
1070         }
1071
1072         /* copy header */
1073         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset,
1074                               0, headlen);
1075         /* skb linear part was allocated with headlen and aligned to long */
1076         skb->tail += headlen;
1077         skb->len  += headlen;
1078
1079         return skb;
1080 }
1081
1082 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1083 {
1084         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1085         struct mlx5e_wqe_frag_info *wi;
1086         struct sk_buff *skb;
1087         u32 cqe_bcnt;
1088         u16 ci;
1089
1090         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1091         wi       = get_frag(rq, ci);
1092         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1093
1094         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1095         if (!skb) {
1096                 /* probably for XDP */
1097                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1098                         /* do not return page to cache,
1099                          * it will be returned on XDP_TX completion.
1100                          */
1101                         goto wq_cyc_pop;
1102                 }
1103                 goto free_wqe;
1104         }
1105
1106         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1107         napi_gro_receive(rq->cq.napi, skb);
1108
1109 free_wqe:
1110         mlx5e_free_rx_wqe(rq, wi);
1111 wq_cyc_pop:
1112         mlx5_wq_cyc_pop(wq);
1113 }
1114
1115 #ifdef CONFIG_MLX5_ESWITCH
1116 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1117 {
1118         struct net_device *netdev = rq->netdev;
1119         struct mlx5e_priv *priv = netdev_priv(netdev);
1120         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1121         struct mlx5_eswitch_rep *rep = rpriv->rep;
1122         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1123         struct mlx5e_wqe_frag_info *wi;
1124         struct sk_buff *skb;
1125         u32 cqe_bcnt;
1126         u16 ci;
1127
1128         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1129         wi       = get_frag(rq, ci);
1130         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1131
1132         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1133         if (!skb) {
1134                 /* probably for XDP */
1135                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1136                         /* do not return page to cache,
1137                          * it will be returned on XDP_TX completion.
1138                          */
1139                         goto wq_cyc_pop;
1140                 }
1141                 goto free_wqe;
1142         }
1143
1144         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1145
1146         if (rep->vlan && skb_vlan_tag_present(skb))
1147                 skb_vlan_pop(skb);
1148
1149         napi_gro_receive(rq->cq.napi, skb);
1150
1151 free_wqe:
1152         mlx5e_free_rx_wqe(rq, wi);
1153 wq_cyc_pop:
1154         mlx5_wq_cyc_pop(wq);
1155 }
1156 #endif
1157
1158 struct sk_buff *
1159 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1160                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1161 {
1162         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1163         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1164         u32 frag_offset    = head_offset + headlen;
1165         u32 byte_cnt       = cqe_bcnt - headlen;
1166         struct mlx5e_dma_info *head_di = di;
1167         struct sk_buff *skb;
1168
1169         skb = napi_alloc_skb(rq->cq.napi,
1170                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1171         if (unlikely(!skb)) {
1172                 rq->stats->buff_alloc_err++;
1173                 return NULL;
1174         }
1175
1176         prefetchw(skb->data);
1177
1178         if (unlikely(frag_offset >= PAGE_SIZE)) {
1179                 di++;
1180                 frag_offset -= PAGE_SIZE;
1181         }
1182
1183         while (byte_cnt) {
1184                 u32 pg_consumed_bytes =
1185                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1186                 unsigned int truesize =
1187                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1188
1189                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1190                                    pg_consumed_bytes, truesize);
1191                 byte_cnt -= pg_consumed_bytes;
1192                 frag_offset = 0;
1193                 di++;
1194         }
1195         /* copy header */
1196         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1197                                     head_offset, headlen);
1198         /* skb linear part was allocated with headlen and aligned to long */
1199         skb->tail += headlen;
1200         skb->len  += headlen;
1201
1202         return skb;
1203 }
1204
1205 struct sk_buff *
1206 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1207                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1208 {
1209         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1210         u16 rx_headroom = rq->buff.headroom;
1211         u32 cqe_bcnt32 = cqe_bcnt;
1212         struct sk_buff *skb;
1213         void *va, *data;
1214         u32 frag_size;
1215         bool consumed;
1216
1217         va             = page_address(di->page) + head_offset;
1218         data           = va + rx_headroom;
1219         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1220
1221         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1222                                       frag_size, DMA_FROM_DEVICE);
1223         prefetch(data);
1224
1225         rcu_read_lock();
1226         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1227         rcu_read_unlock();
1228         if (consumed) {
1229                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1230                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1231                 return NULL; /* page/packet was consumed by XDP */
1232         }
1233
1234         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1235         if (unlikely(!skb))
1236                 return NULL;
1237
1238         /* queue up for recycling/reuse */
1239         page_ref_inc(di->page);
1240
1241         return skb;
1242 }
1243
1244 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1245 {
1246         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1247         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1248         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1249         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1250         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1251         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1252         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1253         struct mlx5e_rx_wqe_ll *wqe;
1254         struct mlx5_wq_ll *wq;
1255         struct sk_buff *skb;
1256         u16 cqe_bcnt;
1257
1258         wi->consumed_strides += cstrides;
1259
1260         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1261                 rq->stats->wqe_err++;
1262                 goto mpwrq_cqe_out;
1263         }
1264
1265         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1266                 rq->stats->mpwqe_filler++;
1267                 goto mpwrq_cqe_out;
1268         }
1269
1270         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1271
1272         skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1273                                            page_idx);
1274         if (!skb)
1275                 goto mpwrq_cqe_out;
1276
1277         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1278         napi_gro_receive(rq->cq.napi, skb);
1279
1280 mpwrq_cqe_out:
1281         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1282                 return;
1283
1284         wq  = &rq->mpwqe.wq;
1285         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1286         mlx5e_free_rx_mpwqe(rq, wi);
1287         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1288 }
1289
1290 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1291 {
1292         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1293         struct mlx5e_xdpsq *xdpsq;
1294         struct mlx5_cqe64 *cqe;
1295         int work_done = 0;
1296
1297         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1298                 return 0;
1299
1300         if (cq->decmprs_left)
1301                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1302
1303         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1304         if (!cqe)
1305                 return 0;
1306
1307         xdpsq = &rq->xdpsq;
1308
1309         do {
1310                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1311                         work_done +=
1312                                 mlx5e_decompress_cqes_start(rq, cq,
1313                                                             budget - work_done);
1314                         continue;
1315                 }
1316
1317                 mlx5_cqwq_pop(&cq->wq);
1318
1319                 rq->handle_rx_cqe(rq, cqe);
1320         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1321
1322         if (xdpsq->db.doorbell) {
1323                 mlx5e_xmit_xdp_doorbell(xdpsq);
1324                 xdpsq->db.doorbell = false;
1325         }
1326
1327         if (xdpsq->db.redirect_flush) {
1328                 xdp_do_flush_map();
1329                 xdpsq->db.redirect_flush = false;
1330         }
1331
1332         mlx5_cqwq_update_db_record(&cq->wq);
1333
1334         /* ensure cq space is freed before enabling more cqes */
1335         wmb();
1336
1337         return work_done;
1338 }
1339
1340 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1341 {
1342         struct mlx5e_xdpsq *sq;
1343         struct mlx5_cqe64 *cqe;
1344         struct mlx5e_rq *rq;
1345         u16 sqcc;
1346         int i;
1347
1348         sq = container_of(cq, struct mlx5e_xdpsq, cq);
1349
1350         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
1351                 return false;
1352
1353         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1354         if (!cqe)
1355                 return false;
1356
1357         rq = container_of(sq, struct mlx5e_rq, xdpsq);
1358
1359         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1360          * otherwise a cq overrun may occur
1361          */
1362         sqcc = sq->cc;
1363
1364         i = 0;
1365         do {
1366                 u16 wqe_counter;
1367                 bool last_wqe;
1368
1369                 mlx5_cqwq_pop(&cq->wq);
1370
1371                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1372
1373                 do {
1374                         struct mlx5e_dma_info *di;
1375                         u16 ci;
1376
1377                         last_wqe = (sqcc == wqe_counter);
1378
1379                         ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
1380                         di = &sq->db.di[ci];
1381
1382                         sqcc++;
1383                         /* Recycle RX page */
1384                         mlx5e_page_release(rq, di, true);
1385                 } while (!last_wqe);
1386         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1387
1388         rq->stats->xdp_tx_cqe += i;
1389
1390         mlx5_cqwq_update_db_record(&cq->wq);
1391
1392         /* ensure cq space is freed before enabling more cqes */
1393         wmb();
1394
1395         sq->cc = sqcc;
1396         return (i == MLX5E_TX_CQ_POLL_BUDGET);
1397 }
1398
1399 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1400 {
1401         struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1402         struct mlx5e_dma_info *di;
1403         u16 ci;
1404
1405         while (sq->cc != sq->pc) {
1406                 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc);
1407                 di = &sq->db.di[ci];
1408                 sq->cc++;
1409
1410                 mlx5e_page_release(rq, di, false);
1411         }
1412 }
1413
1414 #ifdef CONFIG_MLX5_CORE_IPOIB
1415
1416 #define MLX5_IB_GRH_DGID_OFFSET 24
1417 #define MLX5_GID_SIZE           16
1418
1419 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1420                                          struct mlx5_cqe64 *cqe,
1421                                          u32 cqe_bcnt,
1422                                          struct sk_buff *skb)
1423 {
1424         struct mlx5e_rq_stats *stats = rq->stats;
1425         struct hwtstamp_config *tstamp;
1426         struct net_device *netdev;
1427         struct mlx5e_priv *priv;
1428         char *pseudo_header;
1429         u32 qpn;
1430         u8 *dgid;
1431         u8 g;
1432
1433         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1434         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1435
1436         /* No mapping present, cannot process SKB. This might happen if a child
1437          * interface is going down while having unprocessed CQEs on parent RQ
1438          */
1439         if (unlikely(!netdev)) {
1440                 /* TODO: add drop counters support */
1441                 skb->dev = NULL;
1442                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1443                 return;
1444         }
1445
1446         priv = mlx5i_epriv(netdev);
1447         tstamp = &priv->tstamp;
1448
1449         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1450         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1451         if ((!g) || dgid[0] != 0xff)
1452                 skb->pkt_type = PACKET_HOST;
1453         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1454                 skb->pkt_type = PACKET_BROADCAST;
1455         else
1456                 skb->pkt_type = PACKET_MULTICAST;
1457
1458         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1459          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1460          */
1461
1462         skb_pull(skb, MLX5_IB_GRH_BYTES);
1463
1464         skb->protocol = *((__be16 *)(skb->data));
1465
1466         skb->ip_summed = CHECKSUM_COMPLETE;
1467         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1468
1469         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1470                 skb_hwtstamps(skb)->hwtstamp =
1471                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1472
1473         skb_record_rx_queue(skb, rq->ix);
1474
1475         if (likely(netdev->features & NETIF_F_RXHASH))
1476                 mlx5e_skb_set_hash(cqe, skb);
1477
1478         /* 20 bytes of ipoib header and 4 for encap existing */
1479         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1480         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1481         skb_reset_mac_header(skb);
1482         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1483
1484         skb->dev = netdev;
1485
1486         stats->csum_complete++;
1487         stats->packets++;
1488         stats->bytes += cqe_bcnt;
1489 }
1490
1491 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1492 {
1493         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1494         struct mlx5e_wqe_frag_info *wi;
1495         struct sk_buff *skb;
1496         u32 cqe_bcnt;
1497         u16 ci;
1498
1499         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1500         wi       = get_frag(rq, ci);
1501         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1502
1503         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1504         if (!skb)
1505                 goto wq_free_wqe;
1506
1507         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1508         if (unlikely(!skb->dev)) {
1509                 dev_kfree_skb_any(skb);
1510                 goto wq_free_wqe;
1511         }
1512         napi_gro_receive(rq->cq.napi, skb);
1513
1514 wq_free_wqe:
1515         mlx5e_free_rx_wqe(rq, wi);
1516         mlx5_wq_cyc_pop(wq);
1517 }
1518
1519 #endif /* CONFIG_MLX5_CORE_IPOIB */
1520
1521 #ifdef CONFIG_MLX5_EN_IPSEC
1522
1523 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1524 {
1525         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1526         struct mlx5e_wqe_frag_info *wi;
1527         struct sk_buff *skb;
1528         u32 cqe_bcnt;
1529         u16 ci;
1530
1531         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1532         wi       = get_frag(rq, ci);
1533         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1534
1535         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1536         if (unlikely(!skb)) {
1537                 /* a DROP, save the page-reuse checks */
1538                 mlx5e_free_rx_wqe(rq, wi);
1539                 goto wq_cyc_pop;
1540         }
1541         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1542         if (unlikely(!skb)) {
1543                 mlx5e_free_rx_wqe(rq, wi);
1544                 goto wq_cyc_pop;
1545         }
1546
1547         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1548         napi_gro_receive(rq->cq.napi, skb);
1549
1550         mlx5e_free_rx_wqe(rq, wi);
1551 wq_cyc_pop:
1552         mlx5_wq_cyc_pop(wq);
1553 }
1554
1555 #endif /* CONFIG_MLX5_EN_IPSEC */