2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/prefetch.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/bpf_trace.h>
38 #include <net/busy_poll.h>
39 #include <net/ip6_checksum.h>
44 #include "ipoib/ipoib.h"
45 #include "en_accel/ipsec_rxtx.h"
46 #include "lib/clock.h"
48 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
50 return config->rx_filter == HWTSTAMP_FILTER_ALL;
53 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
56 u32 ci = cqcc & cq->wq.fbc.sz_m1;
58 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
61 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
62 struct mlx5e_cq *cq, u32 cqcc)
64 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
65 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
66 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
67 rq->stats.cqe_compress_blks++;
70 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
72 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
76 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
78 struct mlx5_frag_buf_ctrl *fbc = &cq->wq.fbc;
79 u8 op_own = (cqcc >> fbc->log_sz) & 1;
80 u32 wq_sz = 1 << fbc->log_sz;
81 u32 ci = cqcc & fbc->sz_m1;
82 u32 ci_top = min_t(u32, wq_sz, ci + n);
84 for (; ci < ci_top; ci++, n--) {
85 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
90 if (unlikely(ci == wq_sz)) {
92 for (ci = 0; ci < n; ci++) {
93 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
100 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
101 struct mlx5e_cq *cq, u32 cqcc)
103 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
104 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
105 cq->title.op_own &= 0xf0;
106 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
107 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
109 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
110 cq->decmprs_wqe_counter +=
111 mpwrq_get_cqe_consumed_strides(&cq->title);
113 cq->decmprs_wqe_counter =
114 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1;
117 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
118 struct mlx5e_cq *cq, u32 cqcc)
120 mlx5e_decompress_cqe(rq, cq, cqcc);
121 cq->title.rss_hash_type = 0;
122 cq->title.rss_hash_result = 0;
125 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
127 int update_owner_only,
130 u32 cqcc = cq->wq.cc + update_owner_only;
134 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
136 for (i = update_owner_only; i < cqe_count;
137 i++, cq->mini_arr_idx++, cqcc++) {
138 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
139 mlx5e_read_mini_arr_slot(cq, cqcc);
141 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
142 rq->handle_rx_cqe(rq, &cq->title);
144 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
146 cq->decmprs_left -= cqe_count;
147 rq->stats.cqe_compress_pkts += cqe_count;
152 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
156 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
157 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
158 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
159 rq->handle_rx_cqe(rq, &cq->title);
162 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
165 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
167 static inline bool mlx5e_page_is_reserved(struct page *page)
169 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
172 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
173 struct mlx5e_dma_info *dma_info)
175 struct mlx5e_page_cache *cache = &rq->page_cache;
176 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
178 if (tail_next == cache->head) {
179 rq->stats.cache_full++;
183 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
184 rq->stats.cache_waive++;
188 cache->page_cache[cache->tail] = *dma_info;
189 cache->tail = tail_next;
193 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
194 struct mlx5e_dma_info *dma_info)
196 struct mlx5e_page_cache *cache = &rq->page_cache;
198 if (unlikely(cache->head == cache->tail)) {
199 rq->stats.cache_empty++;
203 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
204 rq->stats.cache_busy++;
208 *dma_info = cache->page_cache[cache->head];
209 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
210 rq->stats.cache_reuse++;
212 dma_sync_single_for_device(rq->pdev, dma_info->addr,
218 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
219 struct mlx5e_dma_info *dma_info)
221 if (mlx5e_rx_cache_get(rq, dma_info))
224 dma_info->page = dev_alloc_pages(rq->buff.page_order);
225 if (unlikely(!dma_info->page))
228 dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
229 RQ_PAGE_SIZE(rq), rq->buff.map_dir);
230 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
231 put_page(dma_info->page);
232 dma_info->page = NULL;
239 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
242 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
245 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
247 put_page(dma_info->page);
250 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,
251 struct mlx5e_wqe_frag_info *wi)
253 return rq->wqe.page_reuse && wi->di.page &&
254 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) &&
255 !mlx5e_page_is_reserved(wi->di.page);
258 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
260 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
262 /* check if page exists, hence can be reused */
264 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di)))
269 wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom);
273 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
274 struct mlx5e_wqe_frag_info *wi)
276 mlx5e_page_release(rq, &wi->di, true);
280 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq,
281 struct mlx5e_wqe_frag_info *wi)
283 if (mlx5e_page_reuse(rq, wi)) {
284 rq->stats.page_reuse++;
288 mlx5e_free_rx_wqe(rq, wi);
291 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
293 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
296 mlx5e_free_rx_wqe(rq, wi);
299 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
301 struct mlx5e_dma_info *di,
302 u32 frag_offset, u32 len)
304 unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz));
306 dma_sync_single_for_cpu(rq->pdev,
307 di->addr + frag_offset,
308 len, DMA_FROM_DEVICE);
309 page_ref_inc(di->page);
310 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
311 di->page, frag_offset, len, truesize);
315 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
317 struct mlx5e_dma_info *dma_info,
318 u32 offset, u32 headlen)
320 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
323 /* Aligning len to sizeof(long) optimizes memcpy performance */
324 len = ALIGN(headlen_pg, sizeof(long));
325 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
327 skb_copy_to_linear_data(skb, page_address(dma_info->page) + offset, len);
329 if (unlikely(offset + headlen > PAGE_SIZE)) {
332 len = ALIGN(headlen - headlen_pg, sizeof(long));
333 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
335 skb_copy_to_linear_data_offset(skb, headlen_pg,
336 page_address(dma_info->page),
341 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
343 const bool no_xdp_xmit =
344 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
345 struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
348 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
349 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
350 mlx5e_page_release(rq, &dma_info[i], true);
353 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
355 struct mlx5_wq_ll *wq = &rq->wq;
356 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
358 rq->mpwqe.umr_in_progress = false;
360 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
362 /* ensure wqes are visible to device before updating doorbell record */
365 mlx5_wq_ll_update_db_record(wq);
368 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
370 return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
373 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
375 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
376 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
377 struct mlx5e_icosq *sq = &rq->channel->icosq;
378 struct mlx5_wq_cyc *wq = &sq->wq;
379 struct mlx5e_umr_wqe *umr_wqe;
380 u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
385 /* fill sq edge with nops to avoid wqe wrap around */
386 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
387 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
388 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
391 umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
392 if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
393 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
394 offsetof(struct mlx5e_umr_wqe, inline_mtts));
396 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
397 err = mlx5e_page_alloc_mapped(rq, dma_info);
400 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
403 bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
404 wi->consumed_strides = 0;
406 rq->mpwqe.umr_in_progress = true;
408 umr_wqe->ctrl.opmod_idx_opcode =
409 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
411 umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
413 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
414 sq->pc += MLX5E_UMR_WQEBBS;
415 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
422 mlx5e_page_release(rq, dma_info, true);
424 rq->stats.buff_alloc_err++;
429 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
431 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
433 mlx5e_free_rx_mpwqe(rq, wi);
436 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
438 struct mlx5_wq_ll *wq = &rq->wq;
441 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
444 if (mlx5_wq_ll_is_full(wq))
448 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
450 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head);
452 rq->stats.buff_alloc_err++;
456 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
457 } while (!mlx5_wq_ll_is_full(wq));
459 /* ensure wqes are visible to device before updating doorbell record */
462 mlx5_wq_ll_update_db_record(wq);
467 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
468 struct mlx5e_icosq *sq,
470 struct mlx5_cqe64 *cqe)
472 struct mlx5_wq_cyc *wq = &sq->wq;
473 u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;
474 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
476 mlx5_cqwq_pop(&cq->wq);
478 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
479 netdev_WARN_ONCE(cq->channel->netdev,
480 "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
484 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
485 mlx5e_post_rx_mpwqe(rq);
489 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
490 netdev_WARN_ONCE(cq->channel->netdev,
491 "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
494 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
496 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
497 struct mlx5_cqe64 *cqe;
499 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
502 cqe = mlx5_cqwq_get_cqe(&cq->wq);
506 /* by design, there's only a single cqe */
507 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
509 mlx5_cqwq_update_db_record(&cq->wq);
512 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
514 struct mlx5_wq_ll *wq = &rq->wq;
516 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
519 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
521 if (mlx5_wq_ll_is_full(wq))
524 if (!rq->mpwqe.umr_in_progress)
525 mlx5e_alloc_rx_mpwqe(rq, wq->head);
530 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
532 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
533 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
534 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
537 tcp->psh = get_cqe_lro_tcppsh(cqe);
541 tcp->ack_seq = cqe->lro_ack_seq_num;
542 tcp->window = cqe->lro_tcp_win;
546 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
549 struct ethhdr *eth = (struct ethhdr *)(skb->data);
551 int network_depth = 0;
557 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
559 tot_len = cqe_bcnt - network_depth;
560 ip_p = skb->data + network_depth;
562 if (proto == htons(ETH_P_IP)) {
563 struct iphdr *ipv4 = ip_p;
565 tcp = ip_p + sizeof(struct iphdr);
566 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
568 ipv4->ttl = cqe->lro_min_ttl;
569 ipv4->tot_len = cpu_to_be16(tot_len);
571 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
574 mlx5e_lro_update_tcp_hdr(cqe, tcp);
575 check = csum_partial(tcp, tcp->doff * 4,
576 csum_unfold((__force __sum16)cqe->check_sum));
577 /* Almost done, don't forget the pseudo header */
578 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
579 tot_len - sizeof(struct iphdr),
582 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
583 struct ipv6hdr *ipv6 = ip_p;
585 tcp = ip_p + sizeof(struct ipv6hdr);
586 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
588 ipv6->hop_limit = cqe->lro_min_ttl;
589 ipv6->payload_len = cpu_to_be16(payload_len);
591 mlx5e_lro_update_tcp_hdr(cqe, tcp);
592 check = csum_partial(tcp, tcp->doff * 4,
593 csum_unfold((__force __sum16)cqe->check_sum));
594 /* Almost done, don't forget the pseudo header */
595 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
600 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
603 u8 cht = cqe->rss_hash_type;
604 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
605 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
607 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
610 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
612 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
614 ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
615 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
618 static __be32 mlx5e_get_fcs(struct sk_buff *skb)
620 int last_frag_sz, bytes_in_prev, nr_frags;
622 skb_frag_t *last_frag;
625 if (!skb_is_nonlinear(skb))
626 return *(__be32 *)(skb->data + skb->len - ETH_FCS_LEN);
628 nr_frags = skb_shinfo(skb)->nr_frags;
629 last_frag = &skb_shinfo(skb)->frags[nr_frags - 1];
630 last_frag_sz = skb_frag_size(last_frag);
632 /* If all FCS data is in last frag */
633 if (last_frag_sz >= ETH_FCS_LEN)
634 return *(__be32 *)(skb_frag_address(last_frag) +
635 last_frag_sz - ETH_FCS_LEN);
637 fcs_p2 = (u8 *)skb_frag_address(last_frag);
638 bytes_in_prev = ETH_FCS_LEN - last_frag_sz;
640 /* Find where the other part of the FCS is - Linear or another frag */
642 fcs_p1 = skb_tail_pointer(skb);
644 skb_frag_t *prev_frag = &skb_shinfo(skb)->frags[nr_frags - 2];
646 fcs_p1 = skb_frag_address(prev_frag) +
647 skb_frag_size(prev_frag);
649 fcs_p1 -= bytes_in_prev;
651 memcpy(&fcs_bytes, fcs_p1, bytes_in_prev);
652 memcpy(((u8 *)&fcs_bytes) + bytes_in_prev, fcs_p2, last_frag_sz);
657 static inline void mlx5e_handle_csum(struct net_device *netdev,
658 struct mlx5_cqe64 *cqe,
663 int network_depth = 0;
665 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
669 skb->ip_summed = CHECKSUM_UNNECESSARY;
670 rq->stats.csum_unnecessary++;
674 if (likely(is_last_ethertype_ip(skb, &network_depth))) {
675 skb->ip_summed = CHECKSUM_COMPLETE;
676 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
677 if (network_depth > ETH_HLEN)
678 /* CQE csum is calculated from the IP header and does
679 * not cover VLAN headers (if present). This will add
680 * the checksum manually.
682 skb->csum = csum_partial(skb->data + ETH_HLEN,
683 network_depth - ETH_HLEN,
685 if (unlikely(netdev->features & NETIF_F_RXFCS))
686 skb->csum = csum_add(skb->csum,
687 (__force __wsum)mlx5e_get_fcs(skb));
688 rq->stats.csum_complete++;
692 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
693 (cqe->hds_ip_ext & CQE_L4_OK))) {
694 skb->ip_summed = CHECKSUM_UNNECESSARY;
695 if (cqe_is_tunneled(cqe)) {
697 skb->encapsulation = 1;
698 rq->stats.csum_unnecessary_inner++;
701 rq->stats.csum_unnecessary++;
705 skb->ip_summed = CHECKSUM_NONE;
706 rq->stats.csum_none++;
709 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
714 struct net_device *netdev = rq->netdev;
717 skb->mac_len = ETH_HLEN;
718 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
719 if (lro_num_seg > 1) {
720 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
721 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
722 /* Subtract one since we already counted this as one
723 * "regular" packet in mlx5e_complete_rx_cqe()
725 rq->stats.packets += lro_num_seg - 1;
726 rq->stats.lro_packets++;
727 rq->stats.lro_bytes += cqe_bcnt;
730 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
731 skb_hwtstamps(skb)->hwtstamp =
732 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
734 skb_record_rx_queue(skb, rq->ix);
736 if (likely(netdev->features & NETIF_F_RXHASH))
737 mlx5e_skb_set_hash(cqe, skb);
739 if (cqe_has_vlan(cqe)) {
740 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
741 be16_to_cpu(cqe->vlan_info));
742 rq->stats.removed_vlan_packets++;
745 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
747 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
748 skb->protocol = eth_type_trans(skb, netdev);
751 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
752 struct mlx5_cqe64 *cqe,
757 rq->stats.bytes += cqe_bcnt;
758 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
761 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
763 struct mlx5_wq_cyc *wq = &sq->wq;
764 struct mlx5e_tx_wqe *wqe;
765 u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */
767 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
769 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
772 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
773 struct mlx5e_dma_info *di,
774 const struct xdp_buff *xdp)
776 struct mlx5e_xdpsq *sq = &rq->xdpsq;
777 struct mlx5_wq_cyc *wq = &sq->wq;
778 u16 pi = sq->pc & wq->sz_m1;
779 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
781 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
782 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
783 struct mlx5_wqe_data_seg *dseg;
785 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
786 dma_addr_t dma_addr = di->addr + data_offset;
787 unsigned int dma_len = xdp->data_end - xdp->data;
791 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || rq->hw_mtu < dma_len)) {
792 rq->stats.xdp_drop++;
796 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
797 if (sq->db.doorbell) {
798 /* SQ is full, ring doorbell */
799 mlx5e_xmit_xdp_doorbell(sq);
800 sq->db.doorbell = false;
802 rq->stats.xdp_tx_full++;
806 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
810 dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
812 /* copy the inline part if required */
813 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
814 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
815 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
816 dma_len -= MLX5E_XDP_MIN_INLINE;
817 dma_addr += MLX5E_XDP_MIN_INLINE;
821 /* write the dma part */
822 dseg->addr = cpu_to_be64(dma_addr);
823 dseg->byte_count = cpu_to_be32(dma_len);
825 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
827 /* move page to reference to sq responsibility,
828 * and mark so it's not put back in page-cache.
830 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
834 sq->db.doorbell = true;
840 /* returns true if packet was consumed by xdp */
841 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq,
842 struct mlx5e_dma_info *di,
843 void *va, u16 *rx_headroom, u32 *len)
845 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
852 xdp.data = va + *rx_headroom;
853 xdp_set_data_meta_invalid(&xdp);
854 xdp.data_end = xdp.data + *len;
855 xdp.data_hard_start = va;
856 xdp.rxq = &rq->xdp_rxq;
858 act = bpf_prog_run_xdp(prog, &xdp);
861 *rx_headroom = xdp.data - xdp.data_hard_start;
862 *len = xdp.data_end - xdp.data;
865 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
866 trace_xdp_exception(rq->netdev, prog, act);
869 bpf_warn_invalid_xdp_action(act);
871 trace_xdp_exception(rq->netdev, prog, act);
873 rq->stats.xdp_drop++;
879 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
880 u32 frag_size, u16 headroom,
883 struct sk_buff *skb = build_skb(va, frag_size);
885 if (unlikely(!skb)) {
886 rq->stats.buff_alloc_err++;
890 skb_reserve(skb, headroom);
891 skb_put(skb, cqe_bcnt);
897 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
898 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
900 struct mlx5e_dma_info *di = &wi->di;
901 u16 rx_headroom = rq->buff.headroom;
907 va = page_address(di->page) + wi->offset;
908 data = va + rx_headroom;
909 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
911 dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
912 frag_size, DMA_FROM_DEVICE);
914 wi->offset += frag_size;
916 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
922 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
925 return NULL; /* page/packet was consumed by XDP */
927 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
931 /* queue up for recycling/reuse */
932 page_ref_inc(di->page);
937 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
939 struct mlx5e_wqe_frag_info *wi;
940 struct mlx5e_rx_wqe *wqe;
941 __be16 wqe_counter_be;
946 wqe_counter_be = cqe->wqe_counter;
947 wqe_counter = be16_to_cpu(wqe_counter_be);
948 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
949 wi = &rq->wqe.frag_info[wqe_counter];
950 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
952 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
954 /* probably for XDP */
955 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
957 /* do not return page to cache, it will be returned on XDP_TX completion */
960 /* probably an XDP_DROP, save the page-reuse checks */
961 mlx5e_free_rx_wqe(rq, wi);
965 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
966 napi_gro_receive(rq->cq.napi, skb);
968 mlx5e_free_rx_wqe_reuse(rq, wi);
970 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
971 &wqe->next.next_wqe_index);
974 #ifdef CONFIG_MLX5_ESWITCH
975 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
977 struct net_device *netdev = rq->netdev;
978 struct mlx5e_priv *priv = netdev_priv(netdev);
979 struct mlx5e_rep_priv *rpriv = priv->ppriv;
980 struct mlx5_eswitch_rep *rep = rpriv->rep;
981 struct mlx5e_wqe_frag_info *wi;
982 struct mlx5e_rx_wqe *wqe;
984 __be16 wqe_counter_be;
988 wqe_counter_be = cqe->wqe_counter;
989 wqe_counter = be16_to_cpu(wqe_counter_be);
990 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
991 wi = &rq->wqe.frag_info[wqe_counter];
992 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
994 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
996 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
998 /* do not return page to cache, it will be returned on XDP_TX completion */
1001 /* probably an XDP_DROP, save the page-reuse checks */
1002 mlx5e_free_rx_wqe(rq, wi);
1006 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1008 if (rep->vlan && skb_vlan_tag_present(skb))
1011 napi_gro_receive(rq->cq.napi, skb);
1013 mlx5e_free_rx_wqe_reuse(rq, wi);
1015 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1016 &wqe->next.next_wqe_index);
1021 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1022 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1024 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
1025 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1026 u32 frag_offset = head_offset + headlen;
1027 u32 byte_cnt = cqe_bcnt - headlen;
1028 struct mlx5e_dma_info *head_di = di;
1029 struct sk_buff *skb;
1031 skb = napi_alloc_skb(rq->cq.napi,
1032 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, sizeof(long)));
1033 if (unlikely(!skb)) {
1034 rq->stats.buff_alloc_err++;
1038 prefetchw(skb->data);
1040 if (unlikely(frag_offset >= PAGE_SIZE)) {
1042 frag_offset -= PAGE_SIZE;
1046 u32 pg_consumed_bytes =
1047 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1049 mlx5e_add_skb_frag_mpwqe(rq, skb, di, frag_offset,
1051 byte_cnt -= pg_consumed_bytes;
1056 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1057 head_offset, headlen);
1058 /* skb linear part was allocated with headlen and aligned to long */
1059 skb->tail += headlen;
1060 skb->len += headlen;
1066 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1067 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1069 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1070 u16 rx_headroom = rq->buff.headroom;
1071 u32 cqe_bcnt32 = cqe_bcnt;
1072 struct sk_buff *skb;
1077 va = page_address(di->page) + head_offset;
1078 data = va + rx_headroom;
1079 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1081 dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1082 frag_size, DMA_FROM_DEVICE);
1086 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1089 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1090 __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1091 return NULL; /* page/packet was consumed by XDP */
1094 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1098 /* queue up for recycling/reuse */
1099 page_ref_inc(di->page);
1104 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1106 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
1107 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
1108 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1109 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
1110 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz;
1111 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
1112 u32 page_idx = wqe_offset >> PAGE_SHIFT;
1113 struct mlx5e_rx_wqe *wqe;
1114 struct sk_buff *skb;
1117 wi->consumed_strides += cstrides;
1119 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1120 rq->stats.wqe_err++;
1124 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1125 rq->stats.mpwqe_filler++;
1129 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1131 skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1136 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1137 napi_gro_receive(rq->cq.napi, skb);
1140 if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1143 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
1144 mlx5e_free_rx_mpwqe(rq, wi);
1145 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1148 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1150 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1151 struct mlx5e_xdpsq *xdpsq;
1152 struct mlx5_cqe64 *cqe;
1155 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
1158 if (cq->decmprs_left)
1159 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1161 cqe = mlx5_cqwq_get_cqe(&cq->wq);
1168 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1170 mlx5e_decompress_cqes_start(rq, cq,
1171 budget - work_done);
1175 mlx5_cqwq_pop(&cq->wq);
1177 rq->handle_rx_cqe(rq, cqe);
1178 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1180 if (xdpsq->db.doorbell) {
1181 mlx5e_xmit_xdp_doorbell(xdpsq);
1182 xdpsq->db.doorbell = false;
1185 mlx5_cqwq_update_db_record(&cq->wq);
1187 /* ensure cq space is freed before enabling more cqes */
1193 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1195 struct mlx5e_xdpsq *sq;
1196 struct mlx5_cqe64 *cqe;
1197 struct mlx5e_rq *rq;
1201 sq = container_of(cq, struct mlx5e_xdpsq, cq);
1203 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
1206 cqe = mlx5_cqwq_get_cqe(&cq->wq);
1210 rq = container_of(sq, struct mlx5e_rq, xdpsq);
1212 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1213 * otherwise a cq overrun may occur
1222 mlx5_cqwq_pop(&cq->wq);
1224 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1227 struct mlx5e_dma_info *di;
1230 last_wqe = (sqcc == wqe_counter);
1232 ci = sqcc & sq->wq.sz_m1;
1233 di = &sq->db.di[ci];
1236 /* Recycle RX page */
1237 mlx5e_page_release(rq, di, true);
1238 } while (!last_wqe);
1239 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1241 mlx5_cqwq_update_db_record(&cq->wq);
1243 /* ensure cq space is freed before enabling more cqes */
1247 return (i == MLX5E_TX_CQ_POLL_BUDGET);
1250 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1252 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1253 struct mlx5e_dma_info *di;
1256 while (sq->cc != sq->pc) {
1257 ci = sq->cc & sq->wq.sz_m1;
1258 di = &sq->db.di[ci];
1261 mlx5e_page_release(rq, di, false);
1265 #ifdef CONFIG_MLX5_CORE_IPOIB
1267 #define MLX5_IB_GRH_DGID_OFFSET 24
1268 #define MLX5_GID_SIZE 16
1270 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1271 struct mlx5_cqe64 *cqe,
1273 struct sk_buff *skb)
1275 struct hwtstamp_config *tstamp;
1276 struct net_device *netdev;
1277 struct mlx5e_priv *priv;
1278 char *pseudo_header;
1283 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1284 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1286 /* No mapping present, cannot process SKB. This might happen if a child
1287 * interface is going down while having unprocessed CQEs on parent RQ
1289 if (unlikely(!netdev)) {
1290 /* TODO: add drop counters support */
1292 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1296 priv = mlx5i_epriv(netdev);
1297 tstamp = &priv->tstamp;
1299 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1300 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1301 if ((!g) || dgid[0] != 0xff)
1302 skb->pkt_type = PACKET_HOST;
1303 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1304 skb->pkt_type = PACKET_BROADCAST;
1306 skb->pkt_type = PACKET_MULTICAST;
1308 /* TODO: IB/ipoib: Allow mcast packets from other VFs
1309 * 68996a6e760e5c74654723eeb57bf65628ae87f4
1312 skb_pull(skb, MLX5_IB_GRH_BYTES);
1314 skb->protocol = *((__be16 *)(skb->data));
1316 skb->ip_summed = CHECKSUM_COMPLETE;
1317 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1319 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1320 skb_hwtstamps(skb)->hwtstamp =
1321 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1323 skb_record_rx_queue(skb, rq->ix);
1325 if (likely(netdev->features & NETIF_F_RXHASH))
1326 mlx5e_skb_set_hash(cqe, skb);
1328 /* 20 bytes of ipoib header and 4 for encap existing */
1329 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1330 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1331 skb_reset_mac_header(skb);
1332 skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1336 rq->stats.csum_complete++;
1337 rq->stats.packets++;
1338 rq->stats.bytes += cqe_bcnt;
1341 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1343 struct mlx5e_wqe_frag_info *wi;
1344 struct mlx5e_rx_wqe *wqe;
1345 __be16 wqe_counter_be;
1346 struct sk_buff *skb;
1350 wqe_counter_be = cqe->wqe_counter;
1351 wqe_counter = be16_to_cpu(wqe_counter_be);
1352 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1353 wi = &rq->wqe.frag_info[wqe_counter];
1354 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1356 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1360 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1361 if (unlikely(!skb->dev)) {
1362 dev_kfree_skb_any(skb);
1365 napi_gro_receive(rq->cq.napi, skb);
1368 mlx5e_free_rx_wqe_reuse(rq, wi);
1369 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1370 &wqe->next.next_wqe_index);
1373 #endif /* CONFIG_MLX5_CORE_IPOIB */
1375 #ifdef CONFIG_MLX5_EN_IPSEC
1377 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1379 struct mlx5e_wqe_frag_info *wi;
1380 struct mlx5e_rx_wqe *wqe;
1381 __be16 wqe_counter_be;
1382 struct sk_buff *skb;
1386 wqe_counter_be = cqe->wqe_counter;
1387 wqe_counter = be16_to_cpu(wqe_counter_be);
1388 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1389 wi = &rq->wqe.frag_info[wqe_counter];
1390 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1392 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1393 if (unlikely(!skb)) {
1394 /* a DROP, save the page-reuse checks */
1395 mlx5e_free_rx_wqe(rq, wi);
1398 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1399 if (unlikely(!skb)) {
1400 mlx5e_free_rx_wqe(rq, wi);
1404 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1405 napi_gro_receive(rq->cq.napi, skb);
1407 mlx5e_free_rx_wqe_reuse(rq, wi);
1409 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1410 &wqe->next.next_wqe_index);
1413 #endif /* CONFIG_MLX5_EN_IPSEC */