net/mlx5e: RX, Prefetch the xdp_frame data area
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_rx.c
1 /*
2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/prefetch.h>
34 #include <linux/ip.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <net/busy_poll.h>
38 #include <net/ip6_checksum.h>
39 #include <net/page_pool.h>
40 #include "en.h"
41 #include "en_tc.h"
42 #include "eswitch.h"
43 #include "en_rep.h"
44 #include "ipoib/ipoib.h"
45 #include "en_accel/ipsec_rxtx.h"
46 #include "en_accel/tls_rxtx.h"
47 #include "lib/clock.h"
48 #include "en/xdp.h"
49
50 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
51 {
52         return config->rx_filter == HWTSTAMP_FILTER_ALL;
53 }
54
55 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
56                                        void *data)
57 {
58         u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc);
59
60         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
61 }
62
63 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
64                                          struct mlx5e_cq *cq, u32 cqcc)
65 {
66         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
67         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
68         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
69         rq->stats->cqe_compress_blks++;
70 }
71
72 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
73 {
74         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
75         cq->mini_arr_idx = 0;
76 }
77
78 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
79 {
80         struct mlx5_cqwq *wq = &cq->wq;
81
82         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
83         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
84         u32 wq_sz  = mlx5_cqwq_get_size(wq);
85         u32 ci_top = min_t(u32, wq_sz, ci + n);
86
87         for (; ci < ci_top; ci++, n--) {
88                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
89
90                 cqe->op_own = op_own;
91         }
92
93         if (unlikely(ci == wq_sz)) {
94                 op_own = !op_own;
95                 for (ci = 0; ci < n; ci++) {
96                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
97
98                         cqe->op_own = op_own;
99                 }
100         }
101 }
102
103 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
104                                         struct mlx5e_cq *cq, u32 cqcc)
105 {
106         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
107         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
108         cq->title.op_own      &= 0xf0;
109         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
110         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
111
112         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
113                 cq->decmprs_wqe_counter +=
114                         mpwrq_get_cqe_consumed_strides(&cq->title);
115         else
116                 cq->decmprs_wqe_counter =
117                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cq->decmprs_wqe_counter + 1);
118 }
119
120 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
121                                                 struct mlx5e_cq *cq, u32 cqcc)
122 {
123         mlx5e_decompress_cqe(rq, cq, cqcc);
124         cq->title.rss_hash_type   = 0;
125         cq->title.rss_hash_result = 0;
126 }
127
128 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
129                                              struct mlx5e_cq *cq,
130                                              int update_owner_only,
131                                              int budget_rem)
132 {
133         u32 cqcc = cq->wq.cc + update_owner_only;
134         u32 cqe_count;
135         u32 i;
136
137         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
138
139         for (i = update_owner_only; i < cqe_count;
140              i++, cq->mini_arr_idx++, cqcc++) {
141                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
142                         mlx5e_read_mini_arr_slot(cq, cqcc);
143
144                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
145                 rq->handle_rx_cqe(rq, &cq->title);
146         }
147         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
148         cq->wq.cc = cqcc;
149         cq->decmprs_left -= cqe_count;
150         rq->stats->cqe_compress_pkts += cqe_count;
151
152         return cqe_count;
153 }
154
155 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
156                                               struct mlx5e_cq *cq,
157                                               int budget_rem)
158 {
159         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
160         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
161         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
162         rq->handle_rx_cqe(rq, &cq->title);
163         cq->mini_arr_idx++;
164
165         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
166 }
167
168 static inline bool mlx5e_page_is_reserved(struct page *page)
169 {
170         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
171 }
172
173 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
174                                       struct mlx5e_dma_info *dma_info)
175 {
176         struct mlx5e_page_cache *cache = &rq->page_cache;
177         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
178         struct mlx5e_rq_stats *stats = rq->stats;
179
180         if (tail_next == cache->head) {
181                 stats->cache_full++;
182                 return false;
183         }
184
185         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
186                 stats->cache_waive++;
187                 return false;
188         }
189
190         cache->page_cache[cache->tail] = *dma_info;
191         cache->tail = tail_next;
192         return true;
193 }
194
195 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
196                                       struct mlx5e_dma_info *dma_info)
197 {
198         struct mlx5e_page_cache *cache = &rq->page_cache;
199         struct mlx5e_rq_stats *stats = rq->stats;
200
201         if (unlikely(cache->head == cache->tail)) {
202                 stats->cache_empty++;
203                 return false;
204         }
205
206         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
207                 stats->cache_busy++;
208                 return false;
209         }
210
211         *dma_info = cache->page_cache[cache->head];
212         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
213         stats->cache_reuse++;
214
215         dma_sync_single_for_device(rq->pdev, dma_info->addr,
216                                    PAGE_SIZE,
217                                    DMA_FROM_DEVICE);
218         return true;
219 }
220
221 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
222                                           struct mlx5e_dma_info *dma_info)
223 {
224         if (mlx5e_rx_cache_get(rq, dma_info))
225                 return 0;
226
227         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
228         if (unlikely(!dma_info->page))
229                 return -ENOMEM;
230
231         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
232                                       PAGE_SIZE, rq->buff.map_dir);
233         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
234                 put_page(dma_info->page);
235                 dma_info->page = NULL;
236                 return -ENOMEM;
237         }
238
239         return 0;
240 }
241
242 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
243 {
244         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
245 }
246
247 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
248                         bool recycle)
249 {
250         if (likely(recycle)) {
251                 if (mlx5e_rx_cache_put(rq, dma_info))
252                         return;
253
254                 mlx5e_page_dma_unmap(rq, dma_info);
255                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
256         } else {
257                 mlx5e_page_dma_unmap(rq, dma_info);
258                 put_page(dma_info->page);
259         }
260 }
261
262 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
263                                     struct mlx5e_wqe_frag_info *frag)
264 {
265         int err = 0;
266
267         if (!frag->offset)
268                 /* On first frag (offset == 0), replenish page (dma_info actually).
269                  * Other frags that point to the same dma_info (with a different
270                  * offset) should just use the new one without replenishing again
271                  * by themselves.
272                  */
273                 err = mlx5e_page_alloc_mapped(rq, frag->di);
274
275         return err;
276 }
277
278 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
279                                      struct mlx5e_wqe_frag_info *frag,
280                                      bool recycle)
281 {
282         if (frag->last_in_page)
283                 mlx5e_page_release(rq, frag->di, recycle);
284 }
285
286 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
287 {
288         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
289 }
290
291 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
292                               u16 ix)
293 {
294         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
295         int err;
296         int i;
297
298         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
299                 err = mlx5e_get_rx_frag(rq, frag);
300                 if (unlikely(err))
301                         goto free_frags;
302
303                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
304                                                 frag->offset + rq->buff.headroom);
305         }
306
307         return 0;
308
309 free_frags:
310         while (--i >= 0)
311                 mlx5e_put_rx_frag(rq, --frag, true);
312
313         return err;
314 }
315
316 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
317                                      struct mlx5e_wqe_frag_info *wi,
318                                      bool recycle)
319 {
320         int i;
321
322         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
323                 mlx5e_put_rx_frag(rq, wi, recycle);
324 }
325
326 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
327 {
328         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
329
330         mlx5e_free_rx_wqe(rq, wi, false);
331 }
332
333 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
334 {
335         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
336         int err;
337         int i;
338
339         for (i = 0; i < wqe_bulk; i++) {
340                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
341
342                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
343                 if (unlikely(err))
344                         goto free_wqes;
345         }
346
347         return 0;
348
349 free_wqes:
350         while (--i >= 0)
351                 mlx5e_dealloc_rx_wqe(rq, ix + i);
352
353         return err;
354 }
355
356 static inline void
357 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
358                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
359                    unsigned int truesize)
360 {
361         dma_sync_single_for_cpu(rq->pdev,
362                                 di->addr + frag_offset,
363                                 len, DMA_FROM_DEVICE);
364         page_ref_inc(di->page);
365         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
366                         di->page, frag_offset, len, truesize);
367 }
368
369 static inline void
370 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
371                       struct mlx5e_dma_info *dma_info,
372                       int offset_from, int offset_to, u32 headlen)
373 {
374         const void *from = page_address(dma_info->page) + offset_from;
375         /* Aligning len to sizeof(long) optimizes memcpy performance */
376         unsigned int len = ALIGN(headlen, sizeof(long));
377
378         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
379                                 DMA_FROM_DEVICE);
380         skb_copy_to_linear_data_offset(skb, offset_to, from, len);
381 }
382
383 static inline void
384 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
385                             struct sk_buff *skb,
386                             struct mlx5e_dma_info *dma_info,
387                             u32 offset, u32 headlen)
388 {
389         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
390
391         mlx5e_copy_skb_header(pdev, skb, dma_info, offset, 0, headlen_pg);
392
393         if (unlikely(offset + headlen > PAGE_SIZE)) {
394                 dma_info++;
395                 mlx5e_copy_skb_header(pdev, skb, dma_info, 0, headlen_pg,
396                                       headlen - headlen_pg);
397         }
398 }
399
400 static void
401 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
402 {
403         const bool no_xdp_xmit =
404                 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
405         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
406         int i;
407
408         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
409                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
410                         mlx5e_page_release(rq, &dma_info[i], recycle);
411 }
412
413 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
414 {
415         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
416         struct mlx5e_rx_wqe_ll *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
417
418         rq->mpwqe.umr_in_progress = false;
419
420         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
421
422         /* ensure wqes are visible to device before updating doorbell record */
423         dma_wmb();
424
425         mlx5_wq_ll_update_db_record(wq);
426 }
427
428 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
429 {
430         return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
431 }
432
433 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
434                                               struct mlx5_wq_cyc *wq,
435                                               u16 pi, u16 frag_pi)
436 {
437         struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
438         u8 nnops = mlx5_wq_cyc_get_frag_size(wq) - frag_pi;
439
440         edge_wi = wi + nnops;
441
442         /* fill sq frag edge with nops to avoid wqe wrapping two pages */
443         for (; wi < edge_wi; wi++) {
444                 wi->opcode = MLX5_OPCODE_NOP;
445                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
446         }
447 }
448
449 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
450 {
451         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
452         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
453         struct mlx5e_icosq *sq = &rq->channel->icosq;
454         struct mlx5_wq_cyc *wq = &sq->wq;
455         struct mlx5e_umr_wqe *umr_wqe;
456         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
457         u16 pi, frag_pi;
458         int err;
459         int i;
460
461         pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
462         frag_pi = mlx5_wq_cyc_ctr2fragix(wq, sq->pc);
463
464         if (unlikely(frag_pi + MLX5E_UMR_WQEBBS > mlx5_wq_cyc_get_frag_size(wq))) {
465                 mlx5e_fill_icosq_frag_edge(sq, wq, pi, frag_pi);
466                 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
467         }
468
469         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
470         if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
471                 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
472                        offsetof(struct mlx5e_umr_wqe, inline_mtts));
473
474         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
475                 err = mlx5e_page_alloc_mapped(rq, dma_info);
476                 if (unlikely(err))
477                         goto err_unmap;
478                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
479         }
480
481         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
482         wi->consumed_strides = 0;
483
484         rq->mpwqe.umr_in_progress = true;
485
486         umr_wqe->ctrl.opmod_idx_opcode =
487                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
488                             MLX5_OPCODE_UMR);
489         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
490
491         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
492         sq->pc += MLX5E_UMR_WQEBBS;
493         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
494
495         return 0;
496
497 err_unmap:
498         while (--i >= 0) {
499                 dma_info--;
500                 mlx5e_page_release(rq, dma_info, true);
501         }
502         rq->stats->buff_alloc_err++;
503
504         return err;
505 }
506
507 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
508 {
509         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
510         /* Don't recycle, this function is called on rq/netdev close */
511         mlx5e_free_rx_mpwqe(rq, wi, false);
512 }
513
514 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
515 {
516         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
517         u8 wqe_bulk;
518         int err;
519
520         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
521                 return false;
522
523         wqe_bulk = rq->wqe.info.wqe_bulk;
524
525         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
526                 return false;
527
528         do {
529                 u16 head = mlx5_wq_cyc_get_head(wq);
530
531                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
532                 if (unlikely(err)) {
533                         rq->stats->buff_alloc_err++;
534                         break;
535                 }
536
537                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
538         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
539
540         /* ensure wqes are visible to device before updating doorbell record */
541         dma_wmb();
542
543         mlx5_wq_cyc_update_db_record(wq);
544
545         return !!err;
546 }
547
548 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
549                                              struct mlx5e_icosq *sq,
550                                              struct mlx5e_rq *rq,
551                                              struct mlx5_cqe64 *cqe)
552 {
553         struct mlx5_wq_cyc *wq = &sq->wq;
554         u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
555         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
556
557         mlx5_cqwq_pop(&cq->wq);
558
559         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
560                 netdev_WARN_ONCE(cq->channel->netdev,
561                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
562                 return;
563         }
564
565         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
566                 mlx5e_post_rx_mpwqe(rq);
567                 return;
568         }
569
570         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
571                 netdev_WARN_ONCE(cq->channel->netdev,
572                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
573 }
574
575 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
576 {
577         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
578         struct mlx5_cqe64 *cqe;
579
580         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
581                 return;
582
583         cqe = mlx5_cqwq_get_cqe(&cq->wq);
584         if (likely(!cqe))
585                 return;
586
587         /* by design, there's only a single cqe */
588         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
589
590         mlx5_cqwq_update_db_record(&cq->wq);
591 }
592
593 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
594 {
595         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
596
597         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
598                 return false;
599
600         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
601
602         if (mlx5_wq_ll_is_full(wq))
603                 return false;
604
605         if (!rq->mpwqe.umr_in_progress)
606                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
607         else
608                 rq->stats->congst_umr += mlx5_wq_ll_missing(wq) > 2;
609
610         return false;
611 }
612
613 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
614 {
615         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
616         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
617                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
618
619         tcp->check                      = 0;
620         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
621
622         if (tcp_ack) {
623                 tcp->ack                = 1;
624                 tcp->ack_seq            = cqe->lro_ack_seq_num;
625                 tcp->window             = cqe->lro_tcp_win;
626         }
627 }
628
629 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
630                                  u32 cqe_bcnt)
631 {
632         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
633         struct tcphdr   *tcp;
634         int network_depth = 0;
635         __wsum check;
636         __be16 proto;
637         u16 tot_len;
638         void *ip_p;
639
640         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
641
642         tot_len = cqe_bcnt - network_depth;
643         ip_p = skb->data + network_depth;
644
645         if (proto == htons(ETH_P_IP)) {
646                 struct iphdr *ipv4 = ip_p;
647
648                 tcp = ip_p + sizeof(struct iphdr);
649                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
650
651                 ipv4->ttl               = cqe->lro_min_ttl;
652                 ipv4->tot_len           = cpu_to_be16(tot_len);
653                 ipv4->check             = 0;
654                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
655                                                        ipv4->ihl);
656
657                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
658                 check = csum_partial(tcp, tcp->doff * 4,
659                                      csum_unfold((__force __sum16)cqe->check_sum));
660                 /* Almost done, don't forget the pseudo header */
661                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
662                                                tot_len - sizeof(struct iphdr),
663                                                IPPROTO_TCP, check);
664         } else {
665                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
666                 struct ipv6hdr *ipv6 = ip_p;
667
668                 tcp = ip_p + sizeof(struct ipv6hdr);
669                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
670
671                 ipv6->hop_limit         = cqe->lro_min_ttl;
672                 ipv6->payload_len       = cpu_to_be16(payload_len);
673
674                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
675                 check = csum_partial(tcp, tcp->doff * 4,
676                                      csum_unfold((__force __sum16)cqe->check_sum));
677                 /* Almost done, don't forget the pseudo header */
678                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
679                                              IPPROTO_TCP, check);
680         }
681 }
682
683 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
684                                       struct sk_buff *skb)
685 {
686         u8 cht = cqe->rss_hash_type;
687         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
688                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
689                                             PKT_HASH_TYPE_NONE;
690         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
691 }
692
693 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
694 {
695         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
696
697         ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
698         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
699 }
700
701 static __be32 mlx5e_get_fcs(struct sk_buff *skb)
702 {
703         int last_frag_sz, bytes_in_prev, nr_frags;
704         u8 *fcs_p1, *fcs_p2;
705         skb_frag_t *last_frag;
706         __be32 fcs_bytes;
707
708         if (!skb_is_nonlinear(skb))
709                 return *(__be32 *)(skb->data + skb->len - ETH_FCS_LEN);
710
711         nr_frags = skb_shinfo(skb)->nr_frags;
712         last_frag = &skb_shinfo(skb)->frags[nr_frags - 1];
713         last_frag_sz = skb_frag_size(last_frag);
714
715         /* If all FCS data is in last frag */
716         if (last_frag_sz >= ETH_FCS_LEN)
717                 return *(__be32 *)(skb_frag_address(last_frag) +
718                                    last_frag_sz - ETH_FCS_LEN);
719
720         fcs_p2 = (u8 *)skb_frag_address(last_frag);
721         bytes_in_prev = ETH_FCS_LEN - last_frag_sz;
722
723         /* Find where the other part of the FCS is - Linear or another frag */
724         if (nr_frags == 1) {
725                 fcs_p1 = skb_tail_pointer(skb);
726         } else {
727                 skb_frag_t *prev_frag = &skb_shinfo(skb)->frags[nr_frags - 2];
728
729                 fcs_p1 = skb_frag_address(prev_frag) +
730                             skb_frag_size(prev_frag);
731         }
732         fcs_p1 -= bytes_in_prev;
733
734         memcpy(&fcs_bytes, fcs_p1, bytes_in_prev);
735         memcpy(((u8 *)&fcs_bytes) + bytes_in_prev, fcs_p2, last_frag_sz);
736
737         return fcs_bytes;
738 }
739
740 static inline void mlx5e_handle_csum(struct net_device *netdev,
741                                      struct mlx5_cqe64 *cqe,
742                                      struct mlx5e_rq *rq,
743                                      struct sk_buff *skb,
744                                      bool   lro)
745 {
746         struct mlx5e_rq_stats *stats = rq->stats;
747         int network_depth = 0;
748
749         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
750                 goto csum_none;
751
752         if (lro) {
753                 skb->ip_summed = CHECKSUM_UNNECESSARY;
754                 stats->csum_unnecessary++;
755                 return;
756         }
757
758         if (likely(is_last_ethertype_ip(skb, &network_depth))) {
759                 skb->ip_summed = CHECKSUM_COMPLETE;
760                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
761                 if (network_depth > ETH_HLEN)
762                         /* CQE csum is calculated from the IP header and does
763                          * not cover VLAN headers (if present). This will add
764                          * the checksum manually.
765                          */
766                         skb->csum = csum_partial(skb->data + ETH_HLEN,
767                                                  network_depth - ETH_HLEN,
768                                                  skb->csum);
769                 if (unlikely(netdev->features & NETIF_F_RXFCS))
770                         skb->csum = csum_add(skb->csum,
771                                              (__force __wsum)mlx5e_get_fcs(skb));
772                 stats->csum_complete++;
773                 return;
774         }
775
776         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
777                    (cqe->hds_ip_ext & CQE_L4_OK))) {
778                 skb->ip_summed = CHECKSUM_UNNECESSARY;
779                 if (cqe_is_tunneled(cqe)) {
780                         skb->csum_level = 1;
781                         skb->encapsulation = 1;
782                         stats->csum_unnecessary_inner++;
783                         return;
784                 }
785                 stats->csum_unnecessary++;
786                 return;
787         }
788 csum_none:
789         skb->ip_summed = CHECKSUM_NONE;
790         stats->csum_none++;
791 }
792
793 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
794                                       u32 cqe_bcnt,
795                                       struct mlx5e_rq *rq,
796                                       struct sk_buff *skb)
797 {
798         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
799         struct mlx5e_rq_stats *stats = rq->stats;
800         struct net_device *netdev = rq->netdev;
801
802         skb->mac_len = ETH_HLEN;
803
804 #ifdef CONFIG_MLX5_EN_TLS
805         mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
806 #endif
807
808         if (lro_num_seg > 1) {
809                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
810                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
811                 /* Subtract one since we already counted this as one
812                  * "regular" packet in mlx5e_complete_rx_cqe()
813                  */
814                 stats->packets += lro_num_seg - 1;
815                 stats->lro_packets++;
816                 stats->lro_bytes += cqe_bcnt;
817         }
818
819         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
820                 skb_hwtstamps(skb)->hwtstamp =
821                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
822
823         skb_record_rx_queue(skb, rq->ix);
824
825         if (likely(netdev->features & NETIF_F_RXHASH))
826                 mlx5e_skb_set_hash(cqe, skb);
827
828         if (cqe_has_vlan(cqe)) {
829                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
830                                        be16_to_cpu(cqe->vlan_info));
831                 stats->removed_vlan_packets++;
832         }
833
834         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
835
836         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
837         skb->protocol = eth_type_trans(skb, netdev);
838 }
839
840 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
841                                          struct mlx5_cqe64 *cqe,
842                                          u32 cqe_bcnt,
843                                          struct sk_buff *skb)
844 {
845         struct mlx5e_rq_stats *stats = rq->stats;
846
847         stats->packets++;
848         stats->bytes += cqe_bcnt;
849         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
850 }
851
852 static inline
853 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
854                                        u32 frag_size, u16 headroom,
855                                        u32 cqe_bcnt)
856 {
857         struct sk_buff *skb = build_skb(va, frag_size);
858
859         if (unlikely(!skb)) {
860                 rq->stats->buff_alloc_err++;
861                 return NULL;
862         }
863
864         skb_reserve(skb, headroom);
865         skb_put(skb, cqe_bcnt);
866
867         return skb;
868 }
869
870 struct sk_buff *
871 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
872                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
873 {
874         struct mlx5e_dma_info *di = wi->di;
875         u16 rx_headroom = rq->buff.headroom;
876         struct sk_buff *skb;
877         void *va, *data;
878         bool consumed;
879         u32 frag_size;
880
881         va             = page_address(di->page) + wi->offset;
882         data           = va + rx_headroom;
883         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
884
885         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
886                                       frag_size, DMA_FROM_DEVICE);
887         prefetchw(va); /* xdp_frame data area */
888         prefetch(data);
889
890         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
891                 rq->stats->wqe_err++;
892                 return NULL;
893         }
894
895         rcu_read_lock();
896         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
897         rcu_read_unlock();
898         if (consumed)
899                 return NULL; /* page/packet was consumed by XDP */
900
901         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
902         if (unlikely(!skb))
903                 return NULL;
904
905         /* queue up for recycling/reuse */
906         page_ref_inc(di->page);
907
908         return skb;
909 }
910
911 struct sk_buff *
912 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
913                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
914 {
915         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
916         struct mlx5e_wqe_frag_info *head_wi = wi;
917         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
918         u16 frag_headlen = headlen;
919         u16 byte_cnt     = cqe_bcnt - headlen;
920         struct sk_buff *skb;
921
922         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
923                 rq->stats->wqe_err++;
924                 return NULL;
925         }
926
927         /* XDP is not supported in this configuration, as incoming packets
928          * might spread among multiple pages.
929          */
930         skb = napi_alloc_skb(rq->cq.napi,
931                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
932         if (unlikely(!skb)) {
933                 rq->stats->buff_alloc_err++;
934                 return NULL;
935         }
936
937         prefetchw(skb->data);
938
939         while (byte_cnt) {
940                 u16 frag_consumed_bytes =
941                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
942
943                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
944                                    frag_consumed_bytes, frag_info->frag_stride);
945                 byte_cnt -= frag_consumed_bytes;
946                 frag_headlen = 0;
947                 frag_info++;
948                 wi++;
949         }
950
951         /* copy header */
952         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset,
953                               0, headlen);
954         /* skb linear part was allocated with headlen and aligned to long */
955         skb->tail += headlen;
956         skb->len  += headlen;
957
958         return skb;
959 }
960
961 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
962 {
963         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
964         struct mlx5e_wqe_frag_info *wi;
965         struct sk_buff *skb;
966         u32 cqe_bcnt;
967         u16 ci;
968
969         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
970         wi       = get_frag(rq, ci);
971         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
972
973         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
974         if (!skb) {
975                 /* probably for XDP */
976                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
977                         /* do not return page to cache,
978                          * it will be returned on XDP_TX completion.
979                          */
980                         goto wq_cyc_pop;
981                 }
982                 goto free_wqe;
983         }
984
985         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
986         napi_gro_receive(rq->cq.napi, skb);
987
988 free_wqe:
989         mlx5e_free_rx_wqe(rq, wi, true);
990 wq_cyc_pop:
991         mlx5_wq_cyc_pop(wq);
992 }
993
994 #ifdef CONFIG_MLX5_ESWITCH
995 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
996 {
997         struct net_device *netdev = rq->netdev;
998         struct mlx5e_priv *priv = netdev_priv(netdev);
999         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1000         struct mlx5_eswitch_rep *rep = rpriv->rep;
1001         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1002         struct mlx5e_wqe_frag_info *wi;
1003         struct sk_buff *skb;
1004         u32 cqe_bcnt;
1005         u16 ci;
1006
1007         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1008         wi       = get_frag(rq, ci);
1009         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1010
1011         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1012         if (!skb) {
1013                 /* probably for XDP */
1014                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1015                         /* do not return page to cache,
1016                          * it will be returned on XDP_TX completion.
1017                          */
1018                         goto wq_cyc_pop;
1019                 }
1020                 goto free_wqe;
1021         }
1022
1023         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1024
1025         if (rep->vlan && skb_vlan_tag_present(skb))
1026                 skb_vlan_pop(skb);
1027
1028         napi_gro_receive(rq->cq.napi, skb);
1029
1030 free_wqe:
1031         mlx5e_free_rx_wqe(rq, wi, true);
1032 wq_cyc_pop:
1033         mlx5_wq_cyc_pop(wq);
1034 }
1035 #endif
1036
1037 struct sk_buff *
1038 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1039                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1040 {
1041         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1042         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1043         u32 frag_offset    = head_offset + headlen;
1044         u32 byte_cnt       = cqe_bcnt - headlen;
1045         struct mlx5e_dma_info *head_di = di;
1046         struct sk_buff *skb;
1047
1048         skb = napi_alloc_skb(rq->cq.napi,
1049                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1050         if (unlikely(!skb)) {
1051                 rq->stats->buff_alloc_err++;
1052                 return NULL;
1053         }
1054
1055         prefetchw(skb->data);
1056
1057         if (unlikely(frag_offset >= PAGE_SIZE)) {
1058                 di++;
1059                 frag_offset -= PAGE_SIZE;
1060         }
1061
1062         while (byte_cnt) {
1063                 u32 pg_consumed_bytes =
1064                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1065                 unsigned int truesize =
1066                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1067
1068                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1069                                    pg_consumed_bytes, truesize);
1070                 byte_cnt -= pg_consumed_bytes;
1071                 frag_offset = 0;
1072                 di++;
1073         }
1074         /* copy header */
1075         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1076                                     head_offset, headlen);
1077         /* skb linear part was allocated with headlen and aligned to long */
1078         skb->tail += headlen;
1079         skb->len  += headlen;
1080
1081         return skb;
1082 }
1083
1084 struct sk_buff *
1085 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1086                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1087 {
1088         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1089         u16 rx_headroom = rq->buff.headroom;
1090         u32 cqe_bcnt32 = cqe_bcnt;
1091         struct sk_buff *skb;
1092         void *va, *data;
1093         u32 frag_size;
1094         bool consumed;
1095
1096         va             = page_address(di->page) + head_offset;
1097         data           = va + rx_headroom;
1098         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1099
1100         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1101                                       frag_size, DMA_FROM_DEVICE);
1102         prefetchw(va); /* xdp_frame data area */
1103         prefetch(data);
1104
1105         rcu_read_lock();
1106         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1107         rcu_read_unlock();
1108         if (consumed) {
1109                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1110                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1111                 return NULL; /* page/packet was consumed by XDP */
1112         }
1113
1114         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1115         if (unlikely(!skb))
1116                 return NULL;
1117
1118         /* queue up for recycling/reuse */
1119         page_ref_inc(di->page);
1120
1121         return skb;
1122 }
1123
1124 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1125 {
1126         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1127         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1128         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1129         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1130         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1131         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1132         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1133         struct mlx5e_rx_wqe_ll *wqe;
1134         struct mlx5_wq_ll *wq;
1135         struct sk_buff *skb;
1136         u16 cqe_bcnt;
1137
1138         wi->consumed_strides += cstrides;
1139
1140         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1141                 rq->stats->wqe_err++;
1142                 goto mpwrq_cqe_out;
1143         }
1144
1145         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1146                 struct mlx5e_rq_stats *stats = rq->stats;
1147
1148                 stats->mpwqe_filler_cqes++;
1149                 stats->mpwqe_filler_strides += cstrides;
1150                 goto mpwrq_cqe_out;
1151         }
1152
1153         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1154
1155         skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1156                                            page_idx);
1157         if (!skb)
1158                 goto mpwrq_cqe_out;
1159
1160         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1161         napi_gro_receive(rq->cq.napi, skb);
1162
1163 mpwrq_cqe_out:
1164         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1165                 return;
1166
1167         wq  = &rq->mpwqe.wq;
1168         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1169         mlx5e_free_rx_mpwqe(rq, wi, true);
1170         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1171 }
1172
1173 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1174 {
1175         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1176         struct mlx5e_xdpsq *xdpsq;
1177         struct mlx5_cqe64 *cqe;
1178         int work_done = 0;
1179
1180         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1181                 return 0;
1182
1183         if (cq->decmprs_left)
1184                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1185
1186         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1187         if (!cqe)
1188                 return 0;
1189
1190         xdpsq = &rq->xdpsq;
1191
1192         do {
1193                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1194                         work_done +=
1195                                 mlx5e_decompress_cqes_start(rq, cq,
1196                                                             budget - work_done);
1197                         continue;
1198                 }
1199
1200                 mlx5_cqwq_pop(&cq->wq);
1201
1202                 rq->handle_rx_cqe(rq, cqe);
1203         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1204
1205         if (xdpsq->doorbell) {
1206                 mlx5e_xmit_xdp_doorbell(xdpsq);
1207                 xdpsq->doorbell = false;
1208         }
1209
1210         if (xdpsq->redirect_flush) {
1211                 xdp_do_flush_map();
1212                 xdpsq->redirect_flush = false;
1213         }
1214
1215         mlx5_cqwq_update_db_record(&cq->wq);
1216
1217         /* ensure cq space is freed before enabling more cqes */
1218         wmb();
1219
1220         return work_done;
1221 }
1222
1223 #ifdef CONFIG_MLX5_CORE_IPOIB
1224
1225 #define MLX5_IB_GRH_DGID_OFFSET 24
1226 #define MLX5_GID_SIZE           16
1227
1228 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1229                                          struct mlx5_cqe64 *cqe,
1230                                          u32 cqe_bcnt,
1231                                          struct sk_buff *skb)
1232 {
1233         struct mlx5e_rq_stats *stats = rq->stats;
1234         struct hwtstamp_config *tstamp;
1235         struct net_device *netdev;
1236         struct mlx5e_priv *priv;
1237         char *pseudo_header;
1238         u32 qpn;
1239         u8 *dgid;
1240         u8 g;
1241
1242         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1243         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1244
1245         /* No mapping present, cannot process SKB. This might happen if a child
1246          * interface is going down while having unprocessed CQEs on parent RQ
1247          */
1248         if (unlikely(!netdev)) {
1249                 /* TODO: add drop counters support */
1250                 skb->dev = NULL;
1251                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1252                 return;
1253         }
1254
1255         priv = mlx5i_epriv(netdev);
1256         tstamp = &priv->tstamp;
1257
1258         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1259         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1260         if ((!g) || dgid[0] != 0xff)
1261                 skb->pkt_type = PACKET_HOST;
1262         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1263                 skb->pkt_type = PACKET_BROADCAST;
1264         else
1265                 skb->pkt_type = PACKET_MULTICAST;
1266
1267         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1268          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1269          */
1270
1271         skb_pull(skb, MLX5_IB_GRH_BYTES);
1272
1273         skb->protocol = *((__be16 *)(skb->data));
1274
1275         skb->ip_summed = CHECKSUM_COMPLETE;
1276         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1277
1278         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1279                 skb_hwtstamps(skb)->hwtstamp =
1280                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1281
1282         skb_record_rx_queue(skb, rq->ix);
1283
1284         if (likely(netdev->features & NETIF_F_RXHASH))
1285                 mlx5e_skb_set_hash(cqe, skb);
1286
1287         /* 20 bytes of ipoib header and 4 for encap existing */
1288         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1289         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1290         skb_reset_mac_header(skb);
1291         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1292
1293         skb->dev = netdev;
1294
1295         stats->csum_complete++;
1296         stats->packets++;
1297         stats->bytes += cqe_bcnt;
1298 }
1299
1300 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1301 {
1302         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1303         struct mlx5e_wqe_frag_info *wi;
1304         struct sk_buff *skb;
1305         u32 cqe_bcnt;
1306         u16 ci;
1307
1308         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1309         wi       = get_frag(rq, ci);
1310         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1311
1312         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1313         if (!skb)
1314                 goto wq_free_wqe;
1315
1316         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1317         if (unlikely(!skb->dev)) {
1318                 dev_kfree_skb_any(skb);
1319                 goto wq_free_wqe;
1320         }
1321         napi_gro_receive(rq->cq.napi, skb);
1322
1323 wq_free_wqe:
1324         mlx5e_free_rx_wqe(rq, wi, true);
1325         mlx5_wq_cyc_pop(wq);
1326 }
1327
1328 #endif /* CONFIG_MLX5_CORE_IPOIB */
1329
1330 #ifdef CONFIG_MLX5_EN_IPSEC
1331
1332 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1333 {
1334         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1335         struct mlx5e_wqe_frag_info *wi;
1336         struct sk_buff *skb;
1337         u32 cqe_bcnt;
1338         u16 ci;
1339
1340         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1341         wi       = get_frag(rq, ci);
1342         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1343
1344         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1345         if (unlikely(!skb)) {
1346                 /* a DROP, save the page-reuse checks */
1347                 mlx5e_free_rx_wqe(rq, wi, true);
1348                 goto wq_cyc_pop;
1349         }
1350         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1351         if (unlikely(!skb)) {
1352                 mlx5e_free_rx_wqe(rq, wi, true);
1353                 goto wq_cyc_pop;
1354         }
1355
1356         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1357         napi_gro_receive(rq->cq.napi, skb);
1358
1359         mlx5e_free_rx_wqe(rq, wi, true);
1360 wq_cyc_pop:
1361         mlx5_wq_cyc_pop(wq);
1362 }
1363
1364 #endif /* CONFIG_MLX5_EN_IPSEC */