drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include <net/page_pool.h>
  39 #include "eswitch.h"
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "en_rep.h"
  43 #include "en_accel/ipsec.h"
  44 #include "en_accel/ipsec_rxtx.h"
  45 #include "en_accel/tls.h"
  46 #include "accel/ipsec.h"
  47 #include "accel/tls.h"
  48 #include "vxlan.h"
  49 #include "en/port.h"
  50
  51 struct mlx5e_rq_param {
  52         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  53         struct mlx5_wq_param    wq;
  54         struct mlx5e_rq_frags_info frags_info;
  55 };
  56
  57 struct mlx5e_sq_param {
  58         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  59         struct mlx5_wq_param       wq;
  60 };
  61
  62 struct mlx5e_cq_param {
  63         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  64         struct mlx5_wq_param       wq;
  65         u16                        eq_ix;
  66         u8                         cq_period_mode;
  67 };
  68
  69 struct mlx5e_channel_param {
  70         struct mlx5e_rq_param      rq;
  71         struct mlx5e_sq_param      sq;
  72         struct mlx5e_sq_param      xdp_sq;
  73         struct mlx5e_sq_param      icosq;
  74         struct mlx5e_cq_param      rx_cq;
  75         struct mlx5e_cq_param      tx_cq;
  76         struct mlx5e_cq_param      icosq_cq;
  77 };
  78
  79 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  80 {
  81         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  82                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  83                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  84         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  85         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  86
  87         if (!striding_rq_umr)
  88                 return false;
  89         if (!inline_umr) {
  90                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  91                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  92                 return false;
  93         }
  94         return true;
  95 }
  96
  97 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
  98 {
  99         if (!params->xdp_prog) {
 100                 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 101                 u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN;
 102
 103                 return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu);
 104         }
 105
 106         return PAGE_SIZE;
 107 }
 108
 109 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 110 {
 111         u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 112
 113         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 114 }
 115
 116 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
 117                                    struct mlx5e_params *params)
 118 {
 119         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 120
 121         return !params->lro_en && frag_sz <= PAGE_SIZE;
 122 }
 123
 124 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 125                                          struct mlx5e_params *params)
 126 {
 127         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 128         s8 signed_log_num_strides_param;
 129         u8 log_num_strides;
 130
 131         if (!mlx5e_rx_is_linear_skb(mdev, params))
 132                 return false;
 133
 134         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 135                 return true;
 136
 137         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 138         signed_log_num_strides_param =
 139                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 140
 141         return signed_log_num_strides_param >= 0;
 142 }
 143
 144 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 145 {
 146         if (params->log_rq_mtu_frames <
 147             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 148                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 149
 150         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 151 }
 152
 153 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 154                                           struct mlx5e_params *params)
 155 {
 156         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 157                 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
 158
 159         return MLX5E_MPWQE_STRIDE_SZ(mdev,
 160                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 161 }
 162
 163 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 164                                           struct mlx5e_params *params)
 165 {
 166         return MLX5_MPWRQ_LOG_WQE_SZ -
 167                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 168 }
 169
 170 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 171                                  struct mlx5e_params *params)
 172 {
 173         u16 linear_rq_headroom = params->xdp_prog ?
 174                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 175         bool is_linear_skb;
 176
 177         linear_rq_headroom += NET_IP_ALIGN;
 178
 179         is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
 180                 mlx5e_rx_is_linear_skb(mdev, params) :
 181                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
 182
 183         return is_linear_skb ? linear_rq_headroom : 0;
 184 }
 185
 186 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 187                                struct mlx5e_params *params)
 188 {
 189         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 190         params->log_rq_mtu_frames = is_kdump_kernel() ?
 191                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 192                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 193
 194         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 195                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 196                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 197                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 198                        BIT(params->log_rq_mtu_frames),
 199                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 200                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 201 }
 202
 203 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 204                                 struct mlx5e_params *params)
 205 {
 206         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 207                 !MLX5_IPSEC_DEV(mdev) &&
 208                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 209 }
 210
 211 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 212 {
 213         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 214                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 215                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 216                 MLX5_WQ_TYPE_CYCLIC;
 217 }
 218
 219 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 220 {
 221         struct mlx5_core_dev *mdev = priv->mdev;
 222         u8 port_state;
 223
 224         port_state = mlx5_query_vport_state(mdev,
 225                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
 226                                             0);
 227
 228         if (port_state == VPORT_STATE_UP) {
 229                 netdev_info(priv->netdev, "Link up\n");
 230                 netif_carrier_on(priv->netdev);
 231         } else {
 232                 netdev_info(priv->netdev, "Link down\n");
 233                 netif_carrier_off(priv->netdev);
 234         }
 235 }
 236
 237 static void mlx5e_update_carrier_work(struct work_struct *work)
 238 {
 239         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 240                                                update_carrier_work);
 241
 242         mutex_lock(&priv->state_lock);
 243         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 244                 if (priv->profile->update_carrier)
 245                         priv->profile->update_carrier(priv);
 246         mutex_unlock(&priv->state_lock);
 247 }
 248
 249 void mlx5e_update_stats(struct mlx5e_priv *priv)
 250 {
 251         int i;
 252
 253         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 254                 if (mlx5e_stats_grps[i].update_stats)
 255                         mlx5e_stats_grps[i].update_stats(priv);
 256 }
 257
 258 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 259 {
 260         int i;
 261
 262         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 263                 if (mlx5e_stats_grps[i].update_stats_mask &
 264                     MLX5E_NDO_UPDATE_STATS)
 265                         mlx5e_stats_grps[i].update_stats(priv);
 266 }
 267
 268 void mlx5e_update_stats_work(struct work_struct *work)
 269 {
 270         struct delayed_work *dwork = to_delayed_work(work);
 271         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 272                                                update_stats_work);
 273
 274         mutex_lock(&priv->state_lock);
 275         priv->profile->update_stats(priv);
 276         mutex_unlock(&priv->state_lock);
 277 }
 278
 279 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 280                               enum mlx5_dev_event event, unsigned long param)
 281 {
 282         struct mlx5e_priv *priv = vpriv;
 283
 284         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 285                 return;
 286
 287         switch (event) {
 288         case MLX5_DEV_EVENT_PORT_UP:
 289         case MLX5_DEV_EVENT_PORT_DOWN:
 290                 queue_work(priv->wq, &priv->update_carrier_work);
 291                 break;
 292         default:
 293                 break;
 294         }
 295 }
 296
 297 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 298 {
 299         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 300 }
 301
 302 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 303 {
 304         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 305         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 306 }
 307
 308 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 309                                        struct mlx5e_icosq *sq,
 310                                        struct mlx5e_umr_wqe *wqe)
 311 {
 312         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 313         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 314         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 315
 316         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 317                                       ds_cnt);
 318         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 319         cseg->imm       = rq->mkey_be;
 320
 321         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 322         ucseg->xlt_octowords =
 323                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 324         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 325 }
 326
 327 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 328 {
 329         switch (rq->wq_type) {
 330         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 331                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 332         default:
 333                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 334         }
 335 }
 336
 337 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 338 {
 339         switch (rq->wq_type) {
 340         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 341                 return rq->mpwqe.wq.cur_sz;
 342         default:
 343                 return rq->wqe.wq.cur_sz;
 344         }
 345 }
 346
 347 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 348                                      struct mlx5e_channel *c)
 349 {
 350         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 351
 352         rq->mpwqe.info = kvzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 353                                        GFP_KERNEL, cpu_to_node(c->cpu));
 354         if (!rq->mpwqe.info)
 355                 return -ENOMEM;
 356
 357         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 358
 359         return 0;
 360 }
 361
 362 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 363                                  u64 npages, u8 page_shift,
 364                                  struct mlx5_core_mkey *umr_mkey)
 365 {
 366         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 367         void *mkc;
 368         u32 *in;
 369         int err;
 370
 371         in = kvzalloc(inlen, GFP_KERNEL);
 372         if (!in)
 373                 return -ENOMEM;
 374
 375         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 376
 377         MLX5_SET(mkc, mkc, free, 1);
 378         MLX5_SET(mkc, mkc, umr_en, 1);
 379         MLX5_SET(mkc, mkc, lw, 1);
 380         MLX5_SET(mkc, mkc, lr, 1);
 381         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 382
 383         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 384         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 385         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 386         MLX5_SET(mkc, mkc, translations_octword_size,
 387                  MLX5_MTT_OCTW(npages));
 388         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 389
 390         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 391
 392         kvfree(in);
 393         return err;
 394 }
 395
 396 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 397 {
 398         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 399
 400         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 401 }
 402
 403 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 404 {
 405         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 406 }
 407
 408 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 409 {
 410         struct mlx5e_wqe_frag_info next_frag, *prev;
 411         int i;
 412
 413         next_frag.di = &rq->wqe.di[0];
 414         next_frag.offset = 0;
 415         prev = NULL;
 416
 417         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 418                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 419                 struct mlx5e_wqe_frag_info *frag =
 420                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 421                 int f;
 422
 423                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 424                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 425                                 next_frag.di++;
 426                                 next_frag.offset = 0;
 427                                 if (prev)
 428                                         prev->last_in_page = true;
 429                         }
 430                         *frag = next_frag;
 431
 432                         /* prepare next */
 433                         next_frag.offset += frag_info[f].frag_stride;
 434                         prev = frag;
 435                 }
 436         }
 437
 438         if (prev)
 439                 prev->last_in_page = true;
 440 }
 441
 442 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 443                               struct mlx5e_params *params,
 444                               int wq_sz, int cpu)
 445 {
 446         int len = wq_sz << rq->wqe.info.log_num_frags;
 447
 448         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 449                                    GFP_KERNEL, cpu_to_node(cpu));
 450         if (!rq->wqe.di)
 451                 return -ENOMEM;
 452
 453         mlx5e_init_frags_partition(rq);
 454
 455         return 0;
 456 }
 457
 458 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 459 {
 460         kvfree(rq->wqe.di);
 461 }
 462
 463 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 464                           struct mlx5e_params *params,
 465                           struct mlx5e_rq_param *rqp,
 466                           struct mlx5e_rq *rq)
 467 {
 468         struct page_pool_params pp_params = { 0 };
 469         struct mlx5_core_dev *mdev = c->mdev;
 470         void *rqc = rqp->rqc;
 471         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 472         u32 pool_size;
 473         int wq_sz;
 474         int err;
 475         int i;
 476
 477         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 478
 479         rq->wq_type = params->rq_wq_type;
 480         rq->pdev    = c->pdev;
 481         rq->netdev  = c->netdev;
 482         rq->tstamp  = c->tstamp;
 483         rq->clock   = &mdev->clock;
 484         rq->channel = c;
 485         rq->ix      = c->ix;
 486         rq->mdev    = mdev;
 487         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 488         rq->stats   = &c->priv->channel_stats[c->ix].rq;
 489
 490         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 491         if (IS_ERR(rq->xdp_prog)) {
 492                 err = PTR_ERR(rq->xdp_prog);
 493                 rq->xdp_prog = NULL;
 494                 goto err_rq_wq_destroy;
 495         }
 496
 497         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 498         if (err < 0)
 499                 goto err_rq_wq_destroy;
 500
 501         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 502         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 503         pool_size = 1 << params->log_rq_mtu_frames;
 504
 505         switch (rq->wq_type) {
 506         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 507                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 508                                         &rq->wq_ctrl);
 509                 if (err)
 510                         return err;
 511
 512                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 513
 514                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 515
 516                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 517
 518                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 519                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 520
 521                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 522 #ifdef CONFIG_MLX5_EN_IPSEC
 523                 if (MLX5_IPSEC_DEV(mdev)) {
 524                         err = -EINVAL;
 525                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 526                         goto err_rq_wq_destroy;
 527                 }
 528 #endif
 529                 if (!rq->handle_rx_cqe) {
 530                         err = -EINVAL;
 531                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 532                         goto err_rq_wq_destroy;
 533                 }
 534
 535                 rq->mpwqe.skb_from_cqe_mpwrq =
 536                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 537                         mlx5e_skb_from_cqe_mpwrq_linear :
 538                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 539                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 540                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 541
 542                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 543                 if (err)
 544                         goto err_rq_wq_destroy;
 545                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 546
 547                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 548                 if (err)
 549                         goto err_free;
 550                 break;
 551         default: /* MLX5_WQ_TYPE_CYCLIC */
 552                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 553                                          &rq->wq_ctrl);
 554                 if (err)
 555                         return err;
 556
 557                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 558
 559                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 560
 561                 rq->wqe.info = rqp->frags_info;
 562                 rq->wqe.frags =
 563                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 564                                         (wq_sz << rq->wqe.info.log_num_frags)),
 565                                       GFP_KERNEL, cpu_to_node(c->cpu));
 566                 if (!rq->wqe.frags) {
 567                         err = -ENOMEM;
 568                         goto err_free;
 569                 }
 570
 571                 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
 572                 if (err)
 573                         goto err_free;
 574                 rq->post_wqes = mlx5e_post_rx_wqes;
 575                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 576
 577 #ifdef CONFIG_MLX5_EN_IPSEC
 578                 if (c->priv->ipsec)
 579                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 580                 else
 581 #endif
 582                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 583                 if (!rq->handle_rx_cqe) {
 584                         err = -EINVAL;
 585                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 586                         goto err_free;
 587                 }
 588
 589                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
 590                         mlx5e_skb_from_cqe_linear :
 591                         mlx5e_skb_from_cqe_nonlinear;
 592                 rq->mkey_be = c->mkey_be;
 593         }
 594
 595         /* Create a page_pool and register it with rxq */
 596         pp_params.order     = 0;
 597         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 598         pp_params.pool_size = pool_size;
 599         pp_params.nid       = cpu_to_node(c->cpu);
 600         pp_params.dev       = c->pdev;
 601         pp_params.dma_dir   = rq->buff.map_dir;
 602
 603         /* page_pool can be used even when there is no rq->xdp_prog,
 604          * given page_pool does not handle DMA mapping there is no
 605          * required state to clear. And page_pool gracefully handle
 606          * elevated refcnt.
 607          */
 608         rq->page_pool = page_pool_create(&pp_params);
 609         if (IS_ERR(rq->page_pool)) {
 610                 err = PTR_ERR(rq->page_pool);
 611                 rq->page_pool = NULL;
 612                 goto err_free;
 613         }
 614         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 615                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 616         if (err)
 617                 goto err_free;
 618
 619         for (i = 0; i < wq_sz; i++) {
 620                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 621                         struct mlx5e_rx_wqe_ll *wqe =
 622                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 623                         u32 byte_count =
 624                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 625                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 626
 627                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 628                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 629                         wqe->data[0].lkey = rq->mkey_be;
 630                 } else {
 631                         struct mlx5e_rx_wqe_cyc *wqe =
 632                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 633                         int f;
 634
 635                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 636                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 637                                         MLX5_HW_START_PADDING;
 638
 639                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 640                                 wqe->data[f].lkey = rq->mkey_be;
 641                         }
 642                         /* check if num_frags is not a pow of two */
 643                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 644                                 wqe->data[f].byte_count = 0;
 645                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 646                                 wqe->data[f].addr = 0;
 647                         }
 648                 }
 649         }
 650
 651         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 652
 653         switch (params->rx_cq_moderation.cq_period_mode) {
 654         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 655                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 656                 break;
 657         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 658         default:
 659                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 660         }
 661
 662         rq->page_cache.head = 0;
 663         rq->page_cache.tail = 0;
 664
 665         return 0;
 666
 667 err_free:
 668         switch (rq->wq_type) {
 669         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 670                 kvfree(rq->mpwqe.info);
 671                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 672                 break;
 673         default: /* MLX5_WQ_TYPE_CYCLIC */
 674                 kvfree(rq->wqe.frags);
 675                 mlx5e_free_di_list(rq);
 676         }
 677
 678 err_rq_wq_destroy:
 679         if (rq->xdp_prog)
 680                 bpf_prog_put(rq->xdp_prog);
 681         xdp_rxq_info_unreg(&rq->xdp_rxq);
 682         if (rq->page_pool)
 683                 page_pool_destroy(rq->page_pool);
 684         mlx5_wq_destroy(&rq->wq_ctrl);
 685
 686         return err;
 687 }
 688
 689 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 690 {
 691         int i;
 692
 693         if (rq->xdp_prog)
 694                 bpf_prog_put(rq->xdp_prog);
 695
 696         xdp_rxq_info_unreg(&rq->xdp_rxq);
 697         if (rq->page_pool)
 698                 page_pool_destroy(rq->page_pool);
 699
 700         switch (rq->wq_type) {
 701         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 702                 kvfree(rq->mpwqe.info);
 703                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 704                 break;
 705         default: /* MLX5_WQ_TYPE_CYCLIC */
 706                 kvfree(rq->wqe.frags);
 707                 mlx5e_free_di_list(rq);
 708         }
 709
 710         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 711              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 712                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 713
 714                 mlx5e_page_release(rq, dma_info, false);
 715         }
 716         mlx5_wq_destroy(&rq->wq_ctrl);
 717 }
 718
 719 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 720                            struct mlx5e_rq_param *param)
 721 {
 722         struct mlx5_core_dev *mdev = rq->mdev;
 723
 724         void *in;
 725         void *rqc;
 726         void *wq;
 727         int inlen;
 728         int err;
 729
 730         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 731                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 732         in = kvzalloc(inlen, GFP_KERNEL);
 733         if (!in)
 734                 return -ENOMEM;
 735
 736         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 737         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 738
 739         memcpy(rqc, param->rqc, sizeof(param->rqc));
 740
 741         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 742         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 743         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 744                                                 MLX5_ADAPTER_PAGE_SHIFT);
 745         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 746
 747         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 748                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 749
 750         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 751
 752         kvfree(in);
 753
 754         return err;
 755 }
 756
 757 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 758                                  int next_state)
 759 {
 760         struct mlx5_core_dev *mdev = rq->mdev;
 761
 762         void *in;
 763         void *rqc;
 764         int inlen;
 765         int err;
 766
 767         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 768         in = kvzalloc(inlen, GFP_KERNEL);
 769         if (!in)
 770                 return -ENOMEM;
 771
 772         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 773
 774         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 775         MLX5_SET(rqc, rqc, state, next_state);
 776
 777         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 778
 779         kvfree(in);
 780
 781         return err;
 782 }
 783
 784 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 785 {
 786         struct mlx5e_channel *c = rq->channel;
 787         struct mlx5e_priv *priv = c->priv;
 788         struct mlx5_core_dev *mdev = priv->mdev;
 789
 790         void *in;
 791         void *rqc;
 792         int inlen;
 793         int err;
 794
 795         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 796         in = kvzalloc(inlen, GFP_KERNEL);
 797         if (!in)
 798                 return -ENOMEM;
 799
 800         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 801
 802         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 803         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 804                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 805         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 806         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 807
 808         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 809
 810         kvfree(in);
 811
 812         return err;
 813 }
 814
 815 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 816 {
 817         struct mlx5e_channel *c = rq->channel;
 818         struct mlx5_core_dev *mdev = c->mdev;
 819         void *in;
 820         void *rqc;
 821         int inlen;
 822         int err;
 823
 824         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 825         in = kvzalloc(inlen, GFP_KERNEL);
 826         if (!in)
 827                 return -ENOMEM;
 828
 829         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 830
 831         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 832         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 833                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 834         MLX5_SET(rqc, rqc, vsd, vsd);
 835         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 836
 837         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 838
 839         kvfree(in);
 840
 841         return err;
 842 }
 843
 844 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 845 {
 846         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 847 }
 848
 849 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 850 {
 851         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 852         struct mlx5e_channel *c = rq->channel;
 853
 854         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 855
 856         do {
 857                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 858                         return 0;
 859
 860                 msleep(20);
 861         } while (time_before(jiffies, exp_time));
 862
 863         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 864                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 865
 866         return -ETIMEDOUT;
 867 }
 868
 869 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 870 {
 871         __be16 wqe_ix_be;
 872         u16 wqe_ix;
 873
 874         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 875                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 876
 877                 /* UMR WQE (if in progress) is always at wq->head */
 878                 if (rq->mpwqe.umr_in_progress)
 879                         mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 880
 881                 while (!mlx5_wq_ll_is_empty(wq)) {
 882                         struct mlx5e_rx_wqe_ll *wqe;
 883
 884                         wqe_ix_be = *wq->tail_next;
 885                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 886                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 887                         rq->dealloc_wqe(rq, wqe_ix);
 888                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 889                                        &wqe->next.next_wqe_index);
 890                 }
 891         } else {
 892                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 893
 894                 while (!mlx5_wq_cyc_is_empty(wq)) {
 895                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 896                         rq->dealloc_wqe(rq, wqe_ix);
 897                         mlx5_wq_cyc_pop(wq);
 898                 }
 899         }
 900
 901 }
 902
 903 static int mlx5e_open_rq(struct mlx5e_channel *c,
 904                          struct mlx5e_params *params,
 905                          struct mlx5e_rq_param *param,
 906                          struct mlx5e_rq *rq)
 907 {
 908         int err;
 909
 910         err = mlx5e_alloc_rq(c, params, param, rq);
 911         if (err)
 912                 return err;
 913
 914         err = mlx5e_create_rq(rq, param);
 915         if (err)
 916                 goto err_free_rq;
 917
 918         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 919         if (err)
 920                 goto err_destroy_rq;
 921
 922         if (params->rx_dim_enabled)
 923                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 924
 925         return 0;
 926
 927 err_destroy_rq:
 928         mlx5e_destroy_rq(rq);
 929 err_free_rq:
 930         mlx5e_free_rq(rq);
 931
 932         return err;
 933 }
 934
 935 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 936 {
 937         struct mlx5e_icosq *sq = &rq->channel->icosq;
 938         struct mlx5_wq_cyc *wq = &sq->wq;
 939         struct mlx5e_tx_wqe *nopwqe;
 940
 941         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 942
 943         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 944         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 945         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 946         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 947 }
 948
 949 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 950 {
 951         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 952         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 953 }
 954
 955 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 956 {
 957         cancel_work_sync(&rq->dim.work);
 958         mlx5e_destroy_rq(rq);
 959         mlx5e_free_rx_descs(rq);
 960         mlx5e_free_rq(rq);
 961 }
 962
 963 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 964 {
 965         kvfree(sq->db.di);
 966 }
 967
 968 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 969 {
 970         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 971
 972         sq->db.di = kvzalloc_node(sizeof(*sq->db.di) * wq_sz,
 973                                   GFP_KERNEL, numa);
 974         if (!sq->db.di) {
 975                 mlx5e_free_xdpsq_db(sq);
 976                 return -ENOMEM;
 977         }
 978
 979         return 0;
 980 }
 981
 982 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 983                              struct mlx5e_params *params,
 984                              struct mlx5e_sq_param *param,
 985                              struct mlx5e_xdpsq *sq)
 986 {
 987         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 988         struct mlx5_core_dev *mdev = c->mdev;
 989         struct mlx5_wq_cyc *wq = &sq->wq;
 990         int err;
 991
 992         sq->pdev      = c->pdev;
 993         sq->mkey_be   = c->mkey_be;
 994         sq->channel   = c;
 995         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 996         sq->min_inline_mode = params->tx_min_inline_mode;
 997
 998         param->wq.db_numa_node = cpu_to_node(c->cpu);
 999         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1000         if (err)
1001                 return err;
1002         wq->db = &wq->db[MLX5_SND_DBR];
1003
1004         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1005         if (err)
1006                 goto err_sq_wq_destroy;
1007
1008         return 0;
1009
1010 err_sq_wq_destroy:
1011         mlx5_wq_destroy(&sq->wq_ctrl);
1012
1013         return err;
1014 }
1015
1016 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1017 {
1018         mlx5e_free_xdpsq_db(sq);
1019         mlx5_wq_destroy(&sq->wq_ctrl);
1020 }
1021
1022 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1023 {
1024         kvfree(sq->db.ico_wqe);
1025 }
1026
1027 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1028 {
1029         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1030
1031         sq->db.ico_wqe = kvzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1032                                        GFP_KERNEL, numa);
1033         if (!sq->db.ico_wqe)
1034                 return -ENOMEM;
1035
1036         return 0;
1037 }
1038
1039 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1040                              struct mlx5e_sq_param *param,
1041                              struct mlx5e_icosq *sq)
1042 {
1043         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1044         struct mlx5_core_dev *mdev = c->mdev;
1045         struct mlx5_wq_cyc *wq = &sq->wq;
1046         int err;
1047
1048         sq->channel   = c;
1049         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1050
1051         param->wq.db_numa_node = cpu_to_node(c->cpu);
1052         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1053         if (err)
1054                 return err;
1055         wq->db = &wq->db[MLX5_SND_DBR];
1056
1057         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1058         if (err)
1059                 goto err_sq_wq_destroy;
1060
1061         return 0;
1062
1063 err_sq_wq_destroy:
1064         mlx5_wq_destroy(&sq->wq_ctrl);
1065
1066         return err;
1067 }
1068
1069 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1070 {
1071         mlx5e_free_icosq_db(sq);
1072         mlx5_wq_destroy(&sq->wq_ctrl);
1073 }
1074
1075 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1076 {
1077         kvfree(sq->db.wqe_info);
1078         kvfree(sq->db.dma_fifo);
1079 }
1080
1081 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1082 {
1083         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1084         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1085
1086         sq->db.dma_fifo = kvzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1087                                         GFP_KERNEL, numa);
1088         sq->db.wqe_info = kvzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1089                                         GFP_KERNEL, numa);
1090         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1091                 mlx5e_free_txqsq_db(sq);
1092                 return -ENOMEM;
1093         }
1094
1095         sq->dma_fifo_mask = df_sz - 1;
1096
1097         return 0;
1098 }
1099
1100 static void mlx5e_sq_recover(struct work_struct *work);
1101 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1102                              int txq_ix,
1103                              struct mlx5e_params *params,
1104                              struct mlx5e_sq_param *param,
1105                              struct mlx5e_txqsq *sq,
1106                              int tc)
1107 {
1108         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1109         struct mlx5_core_dev *mdev = c->mdev;
1110         struct mlx5_wq_cyc *wq = &sq->wq;
1111         int err;
1112
1113         sq->pdev      = c->pdev;
1114         sq->tstamp    = c->tstamp;
1115         sq->clock     = &mdev->clock;
1116         sq->mkey_be   = c->mkey_be;
1117         sq->channel   = c;
1118         sq->txq_ix    = txq_ix;
1119         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1120         sq->min_inline_mode = params->tx_min_inline_mode;
1121         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1122         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1123         if (MLX5_IPSEC_DEV(c->priv->mdev))
1124                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1125         if (mlx5_accel_is_tls_device(c->priv->mdev))
1126                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1127
1128         param->wq.db_numa_node = cpu_to_node(c->cpu);
1129         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1130         if (err)
1131                 return err;
1132         wq->db    = &wq->db[MLX5_SND_DBR];
1133
1134         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1135         if (err)
1136                 goto err_sq_wq_destroy;
1137
1138         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1139         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1140
1141         return 0;
1142
1143 err_sq_wq_destroy:
1144         mlx5_wq_destroy(&sq->wq_ctrl);
1145
1146         return err;
1147 }
1148
1149 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1150 {
1151         mlx5e_free_txqsq_db(sq);
1152         mlx5_wq_destroy(&sq->wq_ctrl);
1153 }
1154
1155 struct mlx5e_create_sq_param {
1156         struct mlx5_wq_ctrl        *wq_ctrl;
1157         u32                         cqn;
1158         u32                         tisn;
1159         u8                          tis_lst_sz;
1160         u8                          min_inline_mode;
1161 };
1162
1163 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1164                            struct mlx5e_sq_param *param,
1165                            struct mlx5e_create_sq_param *csp,
1166                            u32 *sqn)
1167 {
1168         void *in;
1169         void *sqc;
1170         void *wq;
1171         int inlen;
1172         int err;
1173
1174         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1175                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1176         in = kvzalloc(inlen, GFP_KERNEL);
1177         if (!in)
1178                 return -ENOMEM;
1179
1180         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1181         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1182
1183         memcpy(sqc, param->sqc, sizeof(param->sqc));
1184         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1185         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1186         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1187
1188         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1189                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1190
1191         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1192         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1193
1194         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1195         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1196         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1197                                           MLX5_ADAPTER_PAGE_SHIFT);
1198         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1199
1200         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1201                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1202
1203         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1204
1205         kvfree(in);
1206
1207         return err;
1208 }
1209
1210 struct mlx5e_modify_sq_param {
1211         int curr_state;
1212         int next_state;
1213         bool rl_update;
1214         int rl_index;
1215 };
1216
1217 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1218                            struct mlx5e_modify_sq_param *p)
1219 {
1220         void *in;
1221         void *sqc;
1222         int inlen;
1223         int err;
1224
1225         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1226         in = kvzalloc(inlen, GFP_KERNEL);
1227         if (!in)
1228                 return -ENOMEM;
1229
1230         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1231
1232         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1233         MLX5_SET(sqc, sqc, state, p->next_state);
1234         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1235                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1236                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1237         }
1238
1239         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1240
1241         kvfree(in);
1242
1243         return err;
1244 }
1245
1246 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1247 {
1248         mlx5_core_destroy_sq(mdev, sqn);
1249 }
1250
1251 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1252                                struct mlx5e_sq_param *param,
1253                                struct mlx5e_create_sq_param *csp,
1254                                u32 *sqn)
1255 {
1256         struct mlx5e_modify_sq_param msp = {0};
1257         int err;
1258
1259         err = mlx5e_create_sq(mdev, param, csp, sqn);
1260         if (err)
1261                 return err;
1262
1263         msp.curr_state = MLX5_SQC_STATE_RST;
1264         msp.next_state = MLX5_SQC_STATE_RDY;
1265         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1266         if (err)
1267                 mlx5e_destroy_sq(mdev, *sqn);
1268
1269         return err;
1270 }
1271
1272 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1273                                 struct mlx5e_txqsq *sq, u32 rate);
1274
1275 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1276                             u32 tisn,
1277                             int txq_ix,
1278                             struct mlx5e_params *params,
1279                             struct mlx5e_sq_param *param,
1280                             struct mlx5e_txqsq *sq,
1281                             int tc)
1282 {
1283         struct mlx5e_create_sq_param csp = {};
1284         u32 tx_rate;
1285         int err;
1286
1287         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1288         if (err)
1289                 return err;
1290
1291         csp.tisn            = tisn;
1292         csp.tis_lst_sz      = 1;
1293         csp.cqn             = sq->cq.mcq.cqn;
1294         csp.wq_ctrl         = &sq->wq_ctrl;
1295         csp.min_inline_mode = sq->min_inline_mode;
1296         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1297         if (err)
1298                 goto err_free_txqsq;
1299
1300         tx_rate = c->priv->tx_rates[sq->txq_ix];
1301         if (tx_rate)
1302                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1303
1304         if (params->tx_dim_enabled)
1305                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1306
1307         return 0;
1308
1309 err_free_txqsq:
1310         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1311         mlx5e_free_txqsq(sq);
1312
1313         return err;
1314 }
1315
1316 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1317 {
1318         WARN_ONCE(sq->cc != sq->pc,
1319                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1320                   sq->sqn, sq->cc, sq->pc);
1321         sq->cc = 0;
1322         sq->dma_fifo_cc = 0;
1323         sq->pc = 0;
1324 }
1325
1326 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1327 {
1328         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1329         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1330         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1331         netdev_tx_reset_queue(sq->txq);
1332         netif_tx_start_queue(sq->txq);
1333 }
1334
1335 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1336 {
1337         __netif_tx_lock_bh(txq);
1338         netif_tx_stop_queue(txq);
1339         __netif_tx_unlock_bh(txq);
1340 }
1341
1342 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1343 {
1344         struct mlx5e_channel *c = sq->channel;
1345         struct mlx5_wq_cyc *wq = &sq->wq;
1346
1347         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1348         /* prevent netif_tx_wake_queue */
1349         napi_synchronize(&c->napi);
1350
1351         netif_tx_disable_queue(sq->txq);
1352
1353         /* last doorbell out, godspeed .. */
1354         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1355                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1356                 struct mlx5e_tx_wqe *nop;
1357
1358                 sq->db.wqe_info[pi].skb = NULL;
1359                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1360                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1361         }
1362 }
1363
1364 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1365 {
1366         struct mlx5e_channel *c = sq->channel;
1367         struct mlx5_core_dev *mdev = c->mdev;
1368         struct mlx5_rate_limit rl = {0};
1369
1370         mlx5e_destroy_sq(mdev, sq->sqn);
1371         if (sq->rate_limit) {
1372                 rl.rate = sq->rate_limit;
1373                 mlx5_rl_remove_rate(mdev, &rl);
1374         }
1375         mlx5e_free_txqsq_descs(sq);
1376         mlx5e_free_txqsq(sq);
1377 }
1378
1379 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1380 {
1381         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1382
1383         while (time_before(jiffies, exp_time)) {
1384                 if (sq->cc == sq->pc)
1385                         return 0;
1386
1387                 msleep(20);
1388         }
1389
1390         netdev_err(sq->channel->netdev,
1391                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1392                    sq->sqn, sq->cc, sq->pc);
1393
1394         return -ETIMEDOUT;
1395 }
1396
1397 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1398 {
1399         struct mlx5_core_dev *mdev = sq->channel->mdev;
1400         struct net_device *dev = sq->channel->netdev;
1401         struct mlx5e_modify_sq_param msp = {0};
1402         int err;
1403
1404         msp.curr_state = curr_state;
1405         msp.next_state = MLX5_SQC_STATE_RST;
1406
1407         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1408         if (err) {
1409                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1410                 return err;
1411         }
1412
1413         memset(&msp, 0, sizeof(msp));
1414         msp.curr_state = MLX5_SQC_STATE_RST;
1415         msp.next_state = MLX5_SQC_STATE_RDY;
1416
1417         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1418         if (err) {
1419                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1420                 return err;
1421         }
1422
1423         return 0;
1424 }
1425
1426 static void mlx5e_sq_recover(struct work_struct *work)
1427 {
1428         struct mlx5e_txqsq_recover *recover =
1429                 container_of(work, struct mlx5e_txqsq_recover,
1430                              recover_work);
1431         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1432                                               recover);
1433         struct mlx5_core_dev *mdev = sq->channel->mdev;
1434         struct net_device *dev = sq->channel->netdev;
1435         u8 state;
1436         int err;
1437
1438         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1439         if (err) {
1440                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1441                            sq->sqn, err);
1442                 return;
1443         }
1444
1445         if (state != MLX5_RQC_STATE_ERR) {
1446                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1447                 return;
1448         }
1449
1450         netif_tx_disable_queue(sq->txq);
1451
1452         if (mlx5e_wait_for_sq_flush(sq))
1453                 return;
1454
1455         /* If the interval between two consecutive recovers per SQ is too
1456          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1457          * If we reached this state, there is probably a bug that needs to be
1458          * fixed. let's keep the queue close and let tx timeout cleanup.
1459          */
1460         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1461             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1462                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1463                            sq->sqn);
1464                 return;
1465         }
1466
1467         /* At this point, no new packets will arrive from the stack as TXQ is
1468          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1469          * pending WQEs.  SQ can safely reset the SQ.
1470          */
1471         if (mlx5e_sq_to_ready(sq, state))
1472                 return;
1473
1474         mlx5e_reset_txqsq_cc_pc(sq);
1475         sq->stats->recover++;
1476         recover->last_recover = jiffies;
1477         mlx5e_activate_txqsq(sq);
1478 }
1479
1480 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1481                             struct mlx5e_params *params,
1482                             struct mlx5e_sq_param *param,
1483                             struct mlx5e_icosq *sq)
1484 {
1485         struct mlx5e_create_sq_param csp = {};
1486         int err;
1487
1488         err = mlx5e_alloc_icosq(c, param, sq);
1489         if (err)
1490                 return err;
1491
1492         csp.cqn             = sq->cq.mcq.cqn;
1493         csp.wq_ctrl         = &sq->wq_ctrl;
1494         csp.min_inline_mode = params->tx_min_inline_mode;
1495         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1496         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1497         if (err)
1498                 goto err_free_icosq;
1499
1500         return 0;
1501
1502 err_free_icosq:
1503         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1504         mlx5e_free_icosq(sq);
1505
1506         return err;
1507 }
1508
1509 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1510 {
1511         struct mlx5e_channel *c = sq->channel;
1512
1513         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1514         napi_synchronize(&c->napi);
1515
1516         mlx5e_destroy_sq(c->mdev, sq->sqn);
1517         mlx5e_free_icosq(sq);
1518 }
1519
1520 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1521                             struct mlx5e_params *params,
1522                             struct mlx5e_sq_param *param,
1523                             struct mlx5e_xdpsq *sq)
1524 {
1525         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1526         struct mlx5e_create_sq_param csp = {};
1527         unsigned int inline_hdr_sz = 0;
1528         int err;
1529         int i;
1530
1531         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1532         if (err)
1533                 return err;
1534
1535         csp.tis_lst_sz      = 1;
1536         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1537         csp.cqn             = sq->cq.mcq.cqn;
1538         csp.wq_ctrl         = &sq->wq_ctrl;
1539         csp.min_inline_mode = sq->min_inline_mode;
1540         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1541         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1542         if (err)
1543                 goto err_free_xdpsq;
1544
1545         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1546                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1547                 ds_cnt++;
1548         }
1549
1550         /* Pre initialize fixed WQE fields */
1551         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1552                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1553                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1554                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1555                 struct mlx5_wqe_data_seg *dseg;
1556
1557                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1558                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1559
1560                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1561                 dseg->lkey = sq->mkey_be;
1562         }
1563
1564         return 0;
1565
1566 err_free_xdpsq:
1567         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1568         mlx5e_free_xdpsq(sq);
1569
1570         return err;
1571 }
1572
1573 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1574 {
1575         struct mlx5e_channel *c = sq->channel;
1576
1577         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1578         napi_synchronize(&c->napi);
1579
1580         mlx5e_destroy_sq(c->mdev, sq->sqn);
1581         mlx5e_free_xdpsq_descs(sq);
1582         mlx5e_free_xdpsq(sq);
1583 }
1584
1585 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1586                                  struct mlx5e_cq_param *param,
1587                                  struct mlx5e_cq *cq)
1588 {
1589         struct mlx5_core_cq *mcq = &cq->mcq;
1590         int eqn_not_used;
1591         unsigned int irqn;
1592         int err;
1593         u32 i;
1594
1595         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1596                                &cq->wq_ctrl);
1597         if (err)
1598                 return err;
1599
1600         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1601
1602         mcq->cqe_sz     = 64;
1603         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1604         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1605         *mcq->set_ci_db = 0;
1606         *mcq->arm_db    = 0;
1607         mcq->vector     = param->eq_ix;
1608         mcq->comp       = mlx5e_completion_event;
1609         mcq->event      = mlx5e_cq_error_event;
1610         mcq->irqn       = irqn;
1611
1612         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1613                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1614
1615                 cqe->op_own = 0xf1;
1616         }
1617
1618         cq->mdev = mdev;
1619
1620         return 0;
1621 }
1622
1623 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1624                           struct mlx5e_cq_param *param,
1625                           struct mlx5e_cq *cq)
1626 {
1627         struct mlx5_core_dev *mdev = c->priv->mdev;
1628         int err;
1629
1630         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1631         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1632         param->eq_ix   = c->ix;
1633
1634         err = mlx5e_alloc_cq_common(mdev, param, cq);
1635
1636         cq->napi    = &c->napi;
1637         cq->channel = c;
1638
1639         return err;
1640 }
1641
1642 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1643 {
1644         mlx5_wq_destroy(&cq->wq_ctrl);
1645 }
1646
1647 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1648 {
1649         struct mlx5_core_dev *mdev = cq->mdev;
1650         struct mlx5_core_cq *mcq = &cq->mcq;
1651
1652         void *in;
1653         void *cqc;
1654         int inlen;
1655         unsigned int irqn_not_used;
1656         int eqn;
1657         int err;
1658
1659         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1660                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1661         in = kvzalloc(inlen, GFP_KERNEL);
1662         if (!in)
1663                 return -ENOMEM;
1664
1665         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1666
1667         memcpy(cqc, param->cqc, sizeof(param->cqc));
1668
1669         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1670                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1671
1672         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1673
1674         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1675         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1676         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1677         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1678                                             MLX5_ADAPTER_PAGE_SHIFT);
1679         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1680
1681         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1682
1683         kvfree(in);
1684
1685         if (err)
1686                 return err;
1687
1688         mlx5e_cq_arm(cq);
1689
1690         return 0;
1691 }
1692
1693 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1694 {
1695         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1696 }
1697
1698 static int mlx5e_open_cq(struct mlx5e_channel *c,
1699                          struct net_dim_cq_moder moder,
1700                          struct mlx5e_cq_param *param,
1701                          struct mlx5e_cq *cq)
1702 {
1703         struct mlx5_core_dev *mdev = c->mdev;
1704         int err;
1705
1706         err = mlx5e_alloc_cq(c, param, cq);
1707         if (err)
1708                 return err;
1709
1710         err = mlx5e_create_cq(cq, param);
1711         if (err)
1712                 goto err_free_cq;
1713
1714         if (MLX5_CAP_GEN(mdev, cq_moderation))
1715                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1716         return 0;
1717
1718 err_free_cq:
1719         mlx5e_free_cq(cq);
1720
1721         return err;
1722 }
1723
1724 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1725 {
1726         mlx5e_destroy_cq(cq);
1727         mlx5e_free_cq(cq);
1728 }
1729
1730 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1731 {
1732         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1733 }
1734
1735 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1736                              struct mlx5e_params *params,
1737                              struct mlx5e_channel_param *cparam)
1738 {
1739         int err;
1740         int tc;
1741
1742         for (tc = 0; tc < c->num_tc; tc++) {
1743                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1744                                     &cparam->tx_cq, &c->sq[tc].cq);
1745                 if (err)
1746                         goto err_close_tx_cqs;
1747         }
1748
1749         return 0;
1750
1751 err_close_tx_cqs:
1752         for (tc--; tc >= 0; tc--)
1753                 mlx5e_close_cq(&c->sq[tc].cq);
1754
1755         return err;
1756 }
1757
1758 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1759 {
1760         int tc;
1761
1762         for (tc = 0; tc < c->num_tc; tc++)
1763                 mlx5e_close_cq(&c->sq[tc].cq);
1764 }
1765
1766 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1767                           struct mlx5e_params *params,
1768                           struct mlx5e_channel_param *cparam)
1769 {
1770         struct mlx5e_priv *priv = c->priv;
1771         int err, tc, max_nch = priv->profile->max_nch(priv->mdev);
1772
1773         for (tc = 0; tc < params->num_tc; tc++) {
1774                 int txq_ix = c->ix + tc * max_nch;
1775
1776                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1777                                        params, &cparam->sq, &c->sq[tc], tc);
1778                 if (err)
1779                         goto err_close_sqs;
1780         }
1781
1782         return 0;
1783
1784 err_close_sqs:
1785         for (tc--; tc >= 0; tc--)
1786                 mlx5e_close_txqsq(&c->sq[tc]);
1787
1788         return err;
1789 }
1790
1791 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1792 {
1793         int tc;
1794
1795         for (tc = 0; tc < c->num_tc; tc++)
1796                 mlx5e_close_txqsq(&c->sq[tc]);
1797 }
1798
1799 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1800                                 struct mlx5e_txqsq *sq, u32 rate)
1801 {
1802         struct mlx5e_priv *priv = netdev_priv(dev);
1803         struct mlx5_core_dev *mdev = priv->mdev;
1804         struct mlx5e_modify_sq_param msp = {0};
1805         struct mlx5_rate_limit rl = {0};
1806         u16 rl_index = 0;
1807         int err;
1808
1809         if (rate == sq->rate_limit)
1810                 /* nothing to do */
1811                 return 0;
1812
1813         if (sq->rate_limit) {
1814                 rl.rate = sq->rate_limit;
1815                 /* remove current rl index to free space to next ones */
1816                 mlx5_rl_remove_rate(mdev, &rl);
1817         }
1818
1819         sq->rate_limit = 0;
1820
1821         if (rate) {
1822                 rl.rate = rate;
1823                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1824                 if (err) {
1825                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1826                                    rate, err);
1827                         return err;
1828                 }
1829         }
1830
1831         msp.curr_state = MLX5_SQC_STATE_RDY;
1832         msp.next_state = MLX5_SQC_STATE_RDY;
1833         msp.rl_index   = rl_index;
1834         msp.rl_update  = true;
1835         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1836         if (err) {
1837                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1838                            rate, err);
1839                 /* remove the rate from the table */
1840                 if (rate)
1841                         mlx5_rl_remove_rate(mdev, &rl);
1842                 return err;
1843         }
1844
1845         sq->rate_limit = rate;
1846         return 0;
1847 }
1848
1849 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1850 {
1851         struct mlx5e_priv *priv = netdev_priv(dev);
1852         struct mlx5_core_dev *mdev = priv->mdev;
1853         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1854         int err = 0;
1855
1856         if (!mlx5_rl_is_supported(mdev)) {
1857                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1858                 return -EINVAL;
1859         }
1860
1861         /* rate is given in Mb/sec, HW config is in Kb/sec */
1862         rate = rate << 10;
1863
1864         /* Check whether rate in valid range, 0 is always valid */
1865         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1866                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1867                 return -ERANGE;
1868         }
1869
1870         mutex_lock(&priv->state_lock);
1871         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1872                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1873         if (!err)
1874                 priv->tx_rates[index] = rate;
1875         mutex_unlock(&priv->state_lock);
1876
1877         return err;
1878 }
1879
1880 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1881                               struct mlx5e_params *params,
1882                               struct mlx5e_channel_param *cparam,
1883                               struct mlx5e_channel **cp)
1884 {
1885         struct net_dim_cq_moder icocq_moder = {0, 0};
1886         struct net_device *netdev = priv->netdev;
1887         int cpu = mlx5e_get_cpu(priv, ix);
1888         struct mlx5e_channel *c;
1889         unsigned int irq;
1890         int err;
1891         int eqn;
1892
1893         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1894         if (!c)
1895                 return -ENOMEM;
1896
1897         c->priv     = priv;
1898         c->mdev     = priv->mdev;
1899         c->tstamp   = &priv->tstamp;
1900         c->ix       = ix;
1901         c->cpu      = cpu;
1902         c->pdev     = &priv->mdev->pdev->dev;
1903         c->netdev   = priv->netdev;
1904         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1905         c->num_tc   = params->num_tc;
1906         c->xdp      = !!params->xdp_prog;
1907         c->stats    = &priv->channel_stats[ix].ch;
1908
1909         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1910         c->irq_desc = irq_to_desc(irq);
1911
1912         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1913
1914         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1915         if (err)
1916                 goto err_napi_del;
1917
1918         err = mlx5e_open_tx_cqs(c, params, cparam);
1919         if (err)
1920                 goto err_close_icosq_cq;
1921
1922         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1923         if (err)
1924                 goto err_close_tx_cqs;
1925
1926         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1927         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1928                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1929         if (err)
1930                 goto err_close_rx_cq;
1931
1932         napi_enable(&c->napi);
1933
1934         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1935         if (err)
1936                 goto err_disable_napi;
1937
1938         err = mlx5e_open_sqs(c, params, cparam);
1939         if (err)
1940                 goto err_close_icosq;
1941
1942         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1943         if (err)
1944                 goto err_close_sqs;
1945
1946         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1947         if (err)
1948                 goto err_close_xdp_sq;
1949
1950         *cp = c;
1951
1952         return 0;
1953 err_close_xdp_sq:
1954         if (c->xdp)
1955                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1956
1957 err_close_sqs:
1958         mlx5e_close_sqs(c);
1959
1960 err_close_icosq:
1961         mlx5e_close_icosq(&c->icosq);
1962
1963 err_disable_napi:
1964         napi_disable(&c->napi);
1965         if (c->xdp)
1966                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1967
1968 err_close_rx_cq:
1969         mlx5e_close_cq(&c->rq.cq);
1970
1971 err_close_tx_cqs:
1972         mlx5e_close_tx_cqs(c);
1973
1974 err_close_icosq_cq:
1975         mlx5e_close_cq(&c->icosq.cq);
1976
1977 err_napi_del:
1978         netif_napi_del(&c->napi);
1979         kvfree(c);
1980
1981         return err;
1982 }
1983
1984 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1985 {
1986         int tc;
1987
1988         for (tc = 0; tc < c->num_tc; tc++)
1989                 mlx5e_activate_txqsq(&c->sq[tc]);
1990         mlx5e_activate_rq(&c->rq);
1991         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1992 }
1993
1994 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1995 {
1996         int tc;
1997
1998         mlx5e_deactivate_rq(&c->rq);
1999         for (tc = 0; tc < c->num_tc; tc++)
2000                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2001 }
2002
2003 static void mlx5e_close_channel(struct mlx5e_channel *c)
2004 {
2005         mlx5e_close_rq(&c->rq);
2006         if (c->xdp)
2007                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2008         mlx5e_close_sqs(c);
2009         mlx5e_close_icosq(&c->icosq);
2010         napi_disable(&c->napi);
2011         if (c->xdp)
2012                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2013         mlx5e_close_cq(&c->rq.cq);
2014         mlx5e_close_tx_cqs(c);
2015         mlx5e_close_cq(&c->icosq.cq);
2016         netif_napi_del(&c->napi);
2017
2018         kvfree(c);
2019 }
2020
2021 #define DEFAULT_FRAG_SIZE (2048)
2022
2023 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2024                                       struct mlx5e_params *params,
2025                                       struct mlx5e_rq_frags_info *info)
2026 {
2027         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2028         int frag_size_max = DEFAULT_FRAG_SIZE;
2029         u32 buf_size = 0;
2030         int i;
2031
2032 #ifdef CONFIG_MLX5_EN_IPSEC
2033         if (MLX5_IPSEC_DEV(mdev))
2034                 byte_count += MLX5E_METADATA_ETHER_LEN;
2035 #endif
2036
2037         if (mlx5e_rx_is_linear_skb(mdev, params)) {
2038                 int frag_stride;
2039
2040                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2041                 frag_stride = roundup_pow_of_two(frag_stride);
2042
2043                 info->arr[0].frag_size = byte_count;
2044                 info->arr[0].frag_stride = frag_stride;
2045                 info->num_frags = 1;
2046                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2047                 goto out;
2048         }
2049
2050         if (byte_count > PAGE_SIZE +
2051             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2052                 frag_size_max = PAGE_SIZE;
2053
2054         i = 0;
2055         while (buf_size < byte_count) {
2056                 int frag_size = byte_count - buf_size;
2057
2058                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2059                         frag_size = min(frag_size, frag_size_max);
2060
2061                 info->arr[i].frag_size = frag_size;
2062                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2063
2064                 buf_size += frag_size;
2065                 i++;
2066         }
2067         info->num_frags = i;
2068         /* number of different wqes sharing a page */
2069         info->wqe_bulk = 1 + (info->num_frags % 2);
2070
2071 out:
2072         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2073         info->log_num_frags = order_base_2(info->num_frags);
2074 }
2075
2076 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2077 {
2078         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2079
2080         switch (wq_type) {
2081         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2082                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2083                 break;
2084         default: /* MLX5_WQ_TYPE_CYCLIC */
2085                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2086         }
2087
2088         return order_base_2(sz);
2089 }
2090
2091 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2092                                  struct mlx5e_params *params,
2093                                  struct mlx5e_rq_param *param)
2094 {
2095         struct mlx5_core_dev *mdev = priv->mdev;
2096         void *rqc = param->rqc;
2097         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2098         int ndsegs = 1;
2099
2100         switch (params->rq_wq_type) {
2101         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2102                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2103                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2104                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2105                 MLX5_SET(wq, wq, log_wqe_stride_size,
2106                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2107                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2108                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2109                 break;
2110         default: /* MLX5_WQ_TYPE_CYCLIC */
2111                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2112                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2113                 ndsegs = param->frags_info.num_frags;
2114         }
2115
2116         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2117         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2118         MLX5_SET(wq, wq, log_wq_stride,
2119                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2120         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2121         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2122         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2123         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2124
2125         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2126 }
2127
2128 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2129                                       struct mlx5e_rq_param *param)
2130 {
2131         struct mlx5_core_dev *mdev = priv->mdev;
2132         void *rqc = param->rqc;
2133         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2134
2135         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2136         MLX5_SET(wq, wq, log_wq_stride,
2137                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2138         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2139
2140         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2141 }
2142
2143 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2144                                         struct mlx5e_sq_param *param)
2145 {
2146         void *sqc = param->sqc;
2147         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2148
2149         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2150         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2151
2152         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2153 }
2154
2155 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2156                                  struct mlx5e_params *params,
2157                                  struct mlx5e_sq_param *param)
2158 {
2159         void *sqc = param->sqc;
2160         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2161
2162         mlx5e_build_sq_param_common(priv, param);
2163         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2164         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2165 }
2166
2167 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2168                                         struct mlx5e_cq_param *param)
2169 {
2170         void *cqc = param->cqc;
2171
2172         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2173 }
2174
2175 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2176                                     struct mlx5e_params *params,
2177                                     struct mlx5e_cq_param *param)
2178 {
2179         struct mlx5_core_dev *mdev = priv->mdev;
2180         void *cqc = param->cqc;
2181         u8 log_cq_size;
2182
2183         switch (params->rq_wq_type) {
2184         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2185                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2186                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2187                 break;
2188         default: /* MLX5_WQ_TYPE_CYCLIC */
2189                 log_cq_size = params->log_rq_mtu_frames;
2190         }
2191
2192         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2193         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2194                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2195                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2196         }
2197
2198         mlx5e_build_common_cq_param(priv, param);
2199         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2200 }
2201
2202 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2203                                     struct mlx5e_params *params,
2204                                     struct mlx5e_cq_param *param)
2205 {
2206         void *cqc = param->cqc;
2207
2208         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2209
2210         mlx5e_build_common_cq_param(priv, param);
2211         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2212 }
2213
2214 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2215                                      u8 log_wq_size,
2216                                      struct mlx5e_cq_param *param)
2217 {
2218         void *cqc = param->cqc;
2219
2220         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2221
2222         mlx5e_build_common_cq_param(priv, param);
2223
2224         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2225 }
2226
2227 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2228                                     u8 log_wq_size,
2229                                     struct mlx5e_sq_param *param)
2230 {
2231         void *sqc = param->sqc;
2232         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2233
2234         mlx5e_build_sq_param_common(priv, param);
2235
2236         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2237         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2238 }
2239
2240 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2241                                     struct mlx5e_params *params,
2242                                     struct mlx5e_sq_param *param)
2243 {
2244         void *sqc = param->sqc;
2245         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2246
2247         mlx5e_build_sq_param_common(priv, param);
2248         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2249 }
2250
2251 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2252                                       struct mlx5e_params *params,
2253                                       struct mlx5e_channel_param *cparam)
2254 {
2255         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2256
2257         mlx5e_build_rq_param(priv, params, &cparam->rq);
2258         mlx5e_build_sq_param(priv, params, &cparam->sq);
2259         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2260         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2261         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2262         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2263         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2264 }
2265
2266 int mlx5e_open_channels(struct mlx5e_priv *priv,
2267                         struct mlx5e_channels *chs)
2268 {
2269         struct mlx5e_channel_param *cparam;
2270         int err = -ENOMEM;
2271         int i;
2272
2273         chs->num = chs->params.num_channels;
2274
2275         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2276         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2277         if (!chs->c || !cparam)
2278                 goto err_free;
2279
2280         mlx5e_build_channel_param(priv, &chs->params, cparam);
2281         for (i = 0; i < chs->num; i++) {
2282                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2283                 if (err)
2284                         goto err_close_channels;
2285         }
2286
2287         kvfree(cparam);
2288         return 0;
2289
2290 err_close_channels:
2291         for (i--; i >= 0; i--)
2292                 mlx5e_close_channel(chs->c[i]);
2293
2294 err_free:
2295         kfree(chs->c);
2296         kvfree(cparam);
2297         chs->num = 0;
2298         return err;
2299 }
2300
2301 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2302 {
2303         int i;
2304
2305         for (i = 0; i < chs->num; i++)
2306                 mlx5e_activate_channel(chs->c[i]);
2307 }
2308
2309 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2310 {
2311         int err = 0;
2312         int i;
2313
2314         for (i = 0; i < chs->num; i++)
2315                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2316                                                   err ? 0 : 20000);
2317
2318         return err ? -ETIMEDOUT : 0;
2319 }
2320
2321 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2322 {
2323         int i;
2324
2325         for (i = 0; i < chs->num; i++)
2326                 mlx5e_deactivate_channel(chs->c[i]);
2327 }
2328
2329 void mlx5e_close_channels(struct mlx5e_channels *chs)
2330 {
2331         int i;
2332
2333         for (i = 0; i < chs->num; i++)
2334                 mlx5e_close_channel(chs->c[i]);
2335
2336         kfree(chs->c);
2337         chs->num = 0;
2338 }
2339
2340 static int
2341 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2342 {
2343         struct mlx5_core_dev *mdev = priv->mdev;
2344         void *rqtc;
2345         int inlen;
2346         int err;
2347         u32 *in;
2348         int i;
2349
2350         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2351         in = kvzalloc(inlen, GFP_KERNEL);
2352         if (!in)
2353                 return -ENOMEM;
2354
2355         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2356
2357         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2358         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2359
2360         for (i = 0; i < sz; i++)
2361                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2362
2363         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2364         if (!err)
2365                 rqt->enabled = true;
2366
2367         kvfree(in);
2368         return err;
2369 }
2370
2371 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2372 {
2373         rqt->enabled = false;
2374         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2375 }
2376
2377 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2378 {
2379         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2380         int err;
2381
2382         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2383         if (err)
2384                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2385         return err;
2386 }
2387
2388 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2389 {
2390         struct mlx5e_rqt *rqt;
2391         int err;
2392         int ix;
2393
2394         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2395                 rqt = &priv->direct_tir[ix].rqt;
2396                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2397                 if (err)
2398                         goto err_destroy_rqts;
2399         }
2400
2401         return 0;
2402
2403 err_destroy_rqts:
2404         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2405         for (ix--; ix >= 0; ix--)
2406                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2407
2408         return err;
2409 }
2410
2411 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2412 {
2413         int i;
2414
2415         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2416                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2417 }
2418
2419 static int mlx5e_rx_hash_fn(int hfunc)
2420 {
2421         return (hfunc == ETH_RSS_HASH_TOP) ?
2422                MLX5_RX_HASH_FN_TOEPLITZ :
2423                MLX5_RX_HASH_FN_INVERTED_XOR8;
2424 }
2425
2426 int mlx5e_bits_invert(unsigned long a, int size)
2427 {
2428         int inv = 0;
2429         int i;
2430
2431         for (i = 0; i < size; i++)
2432                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2433
2434         return inv;
2435 }
2436
2437 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2438                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2439 {
2440         int i;
2441
2442         for (i = 0; i < sz; i++) {
2443                 u32 rqn;
2444
2445                 if (rrp.is_rss) {
2446                         int ix = i;
2447
2448                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2449                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2450
2451                         ix = priv->channels.params.indirection_rqt[ix];
2452                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2453                 } else {
2454                         rqn = rrp.rqn;
2455                 }
2456                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2457         }
2458 }
2459
2460 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2461                        struct mlx5e_redirect_rqt_param rrp)
2462 {
2463         struct mlx5_core_dev *mdev = priv->mdev;
2464         void *rqtc;
2465         int inlen;
2466         u32 *in;
2467         int err;
2468
2469         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2470         in = kvzalloc(inlen, GFP_KERNEL);
2471         if (!in)
2472                 return -ENOMEM;
2473
2474         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2475
2476         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2477         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2478         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2479         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2480
2481         kvfree(in);
2482         return err;
2483 }
2484
2485 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2486                                 struct mlx5e_redirect_rqt_param rrp)
2487 {
2488         if (!rrp.is_rss)
2489                 return rrp.rqn;
2490
2491         if (ix >= rrp.rss.channels->num)
2492                 return priv->drop_rq.rqn;
2493
2494         return rrp.rss.channels->c[ix]->rq.rqn;
2495 }
2496
2497 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2498                                 struct mlx5e_redirect_rqt_param rrp)
2499 {
2500         u32 rqtn;
2501         int ix;
2502
2503         if (priv->indir_rqt.enabled) {
2504                 /* RSS RQ table */
2505                 rqtn = priv->indir_rqt.rqtn;
2506                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2507         }
2508
2509         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2510                 struct mlx5e_redirect_rqt_param direct_rrp = {
2511                         .is_rss = false,
2512                         {
2513                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2514                         },
2515                 };
2516
2517                 /* Direct RQ Tables */
2518                 if (!priv->direct_tir[ix].rqt.enabled)
2519                         continue;
2520
2521                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2522                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2523         }
2524 }
2525
2526 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2527                                             struct mlx5e_channels *chs)
2528 {
2529         struct mlx5e_redirect_rqt_param rrp = {
2530                 .is_rss        = true,
2531                 {
2532                         .rss = {
2533                                 .channels  = chs,
2534                                 .hfunc     = chs->params.rss_hfunc,
2535                         }
2536                 },
2537         };
2538
2539         mlx5e_redirect_rqts(priv, rrp);
2540 }
2541
2542 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2543 {
2544         struct mlx5e_redirect_rqt_param drop_rrp = {
2545                 .is_rss = false,
2546                 {
2547                         .rqn = priv->drop_rq.rqn,
2548                 },
2549         };
2550
2551         mlx5e_redirect_rqts(priv, drop_rrp);
2552 }
2553
2554 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2555 {
2556         if (!params->lro_en)
2557                 return;
2558
2559 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2560
2561         MLX5_SET(tirc, tirc, lro_enable_mask,
2562                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2563                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2564         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2565                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2566         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2567 }
2568
2569 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2570                                     enum mlx5e_traffic_types tt,
2571                                     void *tirc, bool inner)
2572 {
2573         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2574                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2575
2576 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2577                                  MLX5_HASH_FIELD_SEL_DST_IP)
2578
2579 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2580                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2581                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2582                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2583
2584 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2585                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2586                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2587
2588         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2589         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2590                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2591                                              rx_hash_toeplitz_key);
2592                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2593                                                rx_hash_toeplitz_key);
2594
2595                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2596                 memcpy(rss_key, params->toeplitz_hash_key, len);
2597         }
2598
2599         switch (tt) {
2600         case MLX5E_TT_IPV4_TCP:
2601                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2602                          MLX5_L3_PROT_TYPE_IPV4);
2603                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2604                          MLX5_L4_PROT_TYPE_TCP);
2605                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2606                          MLX5_HASH_IP_L4PORTS);
2607                 break;
2608
2609         case MLX5E_TT_IPV6_TCP:
2610                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2611                          MLX5_L3_PROT_TYPE_IPV6);
2612                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2613                          MLX5_L4_PROT_TYPE_TCP);
2614                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2615                          MLX5_HASH_IP_L4PORTS);
2616                 break;
2617
2618         case MLX5E_TT_IPV4_UDP:
2619                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2620                          MLX5_L3_PROT_TYPE_IPV4);
2621                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2622                          MLX5_L4_PROT_TYPE_UDP);
2623                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2624                          MLX5_HASH_IP_L4PORTS);
2625                 break;
2626
2627         case MLX5E_TT_IPV6_UDP:
2628                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2629                          MLX5_L3_PROT_TYPE_IPV6);
2630                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2631                          MLX5_L4_PROT_TYPE_UDP);
2632                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2633                          MLX5_HASH_IP_L4PORTS);
2634                 break;
2635
2636         case MLX5E_TT_IPV4_IPSEC_AH:
2637                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2638                          MLX5_L3_PROT_TYPE_IPV4);
2639                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2640                          MLX5_HASH_IP_IPSEC_SPI);
2641                 break;
2642
2643         case MLX5E_TT_IPV6_IPSEC_AH:
2644                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2645                          MLX5_L3_PROT_TYPE_IPV6);
2646                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2647                          MLX5_HASH_IP_IPSEC_SPI);
2648                 break;
2649
2650         case MLX5E_TT_IPV4_IPSEC_ESP:
2651                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2652                          MLX5_L3_PROT_TYPE_IPV4);
2653                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2654                          MLX5_HASH_IP_IPSEC_SPI);
2655                 break;
2656
2657         case MLX5E_TT_IPV6_IPSEC_ESP:
2658                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2659                          MLX5_L3_PROT_TYPE_IPV6);
2660                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2661                          MLX5_HASH_IP_IPSEC_SPI);
2662                 break;
2663
2664         case MLX5E_TT_IPV4:
2665                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2666                          MLX5_L3_PROT_TYPE_IPV4);
2667                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2668                          MLX5_HASH_IP);
2669                 break;
2670
2671         case MLX5E_TT_IPV6:
2672                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2673                          MLX5_L3_PROT_TYPE_IPV6);
2674                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2675                          MLX5_HASH_IP);
2676                 break;
2677         default:
2678                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2679         }
2680 }
2681
2682 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2683 {
2684         struct mlx5_core_dev *mdev = priv->mdev;
2685
2686         void *in;
2687         void *tirc;
2688         int inlen;
2689         int err;
2690         int tt;
2691         int ix;
2692
2693         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2694         in = kvzalloc(inlen, GFP_KERNEL);
2695         if (!in)
2696                 return -ENOMEM;
2697
2698         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2699         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2700
2701         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2702
2703         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2704                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2705                                            inlen);
2706                 if (err)
2707                         goto free_in;
2708         }
2709
2710         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2711                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2712                                            in, inlen);
2713                 if (err)
2714                         goto free_in;
2715         }
2716
2717 free_in:
2718         kvfree(in);
2719
2720         return err;
2721 }
2722
2723 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2724                                             enum mlx5e_traffic_types tt,
2725                                             u32 *tirc)
2726 {
2727         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2728
2729         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2730
2731         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2732         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2733         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2734
2735         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2736 }
2737
2738 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2739                          struct mlx5e_params *params, u16 mtu)
2740 {
2741         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2742         int err;
2743
2744         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2745         if (err)
2746                 return err;
2747
2748         /* Update vport context MTU */
2749         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2750         return 0;
2751 }
2752
2753 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2754                             struct mlx5e_params *params, u16 *mtu)
2755 {
2756         u16 hw_mtu = 0;
2757         int err;
2758
2759         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2760         if (err || !hw_mtu) /* fallback to port oper mtu */
2761                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2762
2763         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2764 }
2765
2766 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2767 {
2768         struct mlx5e_params *params = &priv->channels.params;
2769         struct net_device *netdev = priv->netdev;
2770         struct mlx5_core_dev *mdev = priv->mdev;
2771         u16 mtu;
2772         int err;
2773
2774         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2775         if (err)
2776                 return err;
2777
2778         mlx5e_query_mtu(mdev, params, &mtu);
2779         if (mtu != params->sw_mtu)
2780                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2781                             __func__, mtu, params->sw_mtu);
2782
2783         params->sw_mtu = mtu;
2784         return 0;
2785 }
2786
2787 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2788 {
2789         struct mlx5e_priv *priv = netdev_priv(netdev);
2790         int nch = priv->channels.params.num_channels;
2791         int ntc = priv->channels.params.num_tc;
2792         int tc;
2793
2794         netdev_reset_tc(netdev);
2795
2796         if (ntc == 1)
2797                 return;
2798
2799         netdev_set_num_tc(netdev, ntc);
2800
2801         /* Map netdev TCs to offset 0
2802          * We have our own UP to TXQ mapping for QoS
2803          */
2804         for (tc = 0; tc < ntc; tc++)
2805                 netdev_set_tc_queue(netdev, tc, nch, 0);
2806 }
2807
2808 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2809 {
2810         int max_nch = priv->profile->max_nch(priv->mdev);
2811         int i, tc;
2812
2813         for (i = 0; i < max_nch; i++)
2814                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2815                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2816 }
2817
2818 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2819 {
2820         struct mlx5e_channel *c;
2821         struct mlx5e_txqsq *sq;
2822         int i, tc;
2823
2824         for (i = 0; i < priv->channels.num; i++) {
2825                 c = priv->channels.c[i];
2826                 for (tc = 0; tc < c->num_tc; tc++) {
2827                         sq = &c->sq[tc];
2828                         priv->txq2sq[sq->txq_ix] = sq;
2829                 }
2830         }
2831 }
2832
2833 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2834 {
2835         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2836         struct net_device *netdev = priv->netdev;
2837
2838         mlx5e_netdev_set_tcs(netdev);
2839         netif_set_real_num_tx_queues(netdev, num_txqs);
2840         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2841
2842         mlx5e_build_tx2sq_maps(priv);
2843         mlx5e_activate_channels(&priv->channels);
2844         netif_tx_start_all_queues(priv->netdev);
2845
2846         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2847                 mlx5e_add_sqs_fwd_rules(priv);
2848
2849         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2850         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2851 }
2852
2853 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2854 {
2855         mlx5e_redirect_rqts_to_drop(priv);
2856
2857         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2858                 mlx5e_remove_sqs_fwd_rules(priv);
2859
2860         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2861          * polling for inactive tx queues.
2862          */
2863         netif_tx_stop_all_queues(priv->netdev);
2864         netif_tx_disable(priv->netdev);
2865         mlx5e_deactivate_channels(&priv->channels);
2866 }
2867
2868 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2869                                 struct mlx5e_channels *new_chs,
2870                                 mlx5e_fp_hw_modify hw_modify)
2871 {
2872         struct net_device *netdev = priv->netdev;
2873         int new_num_txqs;
2874         int carrier_ok;
2875         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2876
2877         carrier_ok = netif_carrier_ok(netdev);
2878         netif_carrier_off(netdev);
2879
2880         if (new_num_txqs < netdev->real_num_tx_queues)
2881                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2882
2883         mlx5e_deactivate_priv_channels(priv);
2884         mlx5e_close_channels(&priv->channels);
2885
2886         priv->channels = *new_chs;
2887
2888         /* New channels are ready to roll, modify HW settings if needed */
2889         if (hw_modify)
2890                 hw_modify(priv);
2891
2892         mlx5e_refresh_tirs(priv, false);
2893         mlx5e_activate_priv_channels(priv);
2894
2895         /* return carrier back if needed */
2896         if (carrier_ok)
2897                 netif_carrier_on(netdev);
2898 }
2899
2900 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2901 {
2902         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2903         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2904 }
2905
2906 int mlx5e_open_locked(struct net_device *netdev)
2907 {
2908         struct mlx5e_priv *priv = netdev_priv(netdev);
2909         int err;
2910
2911         set_bit(MLX5E_STATE_OPENED, &priv->state);
2912
2913         err = mlx5e_open_channels(priv, &priv->channels);
2914         if (err)
2915                 goto err_clear_state_opened_flag;
2916
2917         mlx5e_refresh_tirs(priv, false);
2918         mlx5e_activate_priv_channels(priv);
2919         if (priv->profile->update_carrier)
2920                 priv->profile->update_carrier(priv);
2921
2922         if (priv->profile->update_stats)
2923                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2924
2925         return 0;
2926
2927 err_clear_state_opened_flag:
2928         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2929         return err;
2930 }
2931
2932 int mlx5e_open(struct net_device *netdev)
2933 {
2934         struct mlx5e_priv *priv = netdev_priv(netdev);
2935         int err;
2936
2937         mutex_lock(&priv->state_lock);
2938         err = mlx5e_open_locked(netdev);
2939         if (!err)
2940                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2941         mutex_unlock(&priv->state_lock);
2942
2943         if (mlx5e_vxlan_allowed(priv->mdev))
2944                 udp_tunnel_get_rx_info(netdev);
2945
2946         return err;
2947 }
2948
2949 int mlx5e_close_locked(struct net_device *netdev)
2950 {
2951         struct mlx5e_priv *priv = netdev_priv(netdev);
2952
2953         /* May already be CLOSED in case a previous configuration operation
2954          * (e.g RX/TX queue size change) that involves close&open failed.
2955          */
2956         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2957                 return 0;
2958
2959         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2960
2961         netif_carrier_off(priv->netdev);
2962         mlx5e_deactivate_priv_channels(priv);
2963         mlx5e_close_channels(&priv->channels);
2964
2965         return 0;
2966 }
2967
2968 int mlx5e_close(struct net_device *netdev)
2969 {
2970         struct mlx5e_priv *priv = netdev_priv(netdev);
2971         int err;
2972
2973         if (!netif_device_present(netdev))
2974                 return -ENODEV;
2975
2976         mutex_lock(&priv->state_lock);
2977         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2978         err = mlx5e_close_locked(netdev);
2979         mutex_unlock(&priv->state_lock);
2980
2981         return err;
2982 }
2983
2984 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2985                                struct mlx5e_rq *rq,
2986                                struct mlx5e_rq_param *param)
2987 {
2988         void *rqc = param->rqc;
2989         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2990         int err;
2991
2992         param->wq.db_numa_node = param->wq.buf_numa_node;
2993
2994         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2995                                  &rq->wq_ctrl);
2996         if (err)
2997                 return err;
2998
2999         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3000         xdp_rxq_info_unused(&rq->xdp_rxq);
3001
3002         rq->mdev = mdev;
3003
3004         return 0;
3005 }
3006
3007 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3008                                struct mlx5e_cq *cq,
3009                                struct mlx5e_cq_param *param)
3010 {
3011         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3012         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
3013
3014         return mlx5e_alloc_cq_common(mdev, param, cq);
3015 }
3016
3017 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3018                               struct mlx5e_rq *drop_rq)
3019 {
3020         struct mlx5_core_dev *mdev = priv->mdev;
3021         struct mlx5e_cq_param cq_param = {};
3022         struct mlx5e_rq_param rq_param = {};
3023         struct mlx5e_cq *cq = &drop_rq->cq;
3024         int err;
3025
3026         mlx5e_build_drop_rq_param(priv, &rq_param);
3027
3028         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3029         if (err)
3030                 return err;
3031
3032         err = mlx5e_create_cq(cq, &cq_param);
3033         if (err)
3034                 goto err_free_cq;
3035
3036         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3037         if (err)
3038                 goto err_destroy_cq;
3039
3040         err = mlx5e_create_rq(drop_rq, &rq_param);
3041         if (err)
3042                 goto err_free_rq;
3043
3044         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3045         if (err)
3046                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3047
3048         return 0;
3049
3050 err_free_rq:
3051         mlx5e_free_rq(drop_rq);
3052
3053 err_destroy_cq:
3054         mlx5e_destroy_cq(cq);
3055
3056 err_free_cq:
3057         mlx5e_free_cq(cq);
3058
3059         return err;
3060 }
3061
3062 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3063 {
3064         mlx5e_destroy_rq(drop_rq);
3065         mlx5e_free_rq(drop_rq);
3066         mlx5e_destroy_cq(&drop_rq->cq);
3067         mlx5e_free_cq(&drop_rq->cq);
3068 }
3069
3070 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3071                      u32 underlay_qpn, u32 *tisn)
3072 {
3073         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3074         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3075
3076         MLX5_SET(tisc, tisc, prio, tc << 1);
3077         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3078         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3079
3080         if (mlx5_lag_is_lacp_owner(mdev))
3081                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3082
3083         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3084 }
3085
3086 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3087 {
3088         mlx5_core_destroy_tis(mdev, tisn);
3089 }
3090
3091 int mlx5e_create_tises(struct mlx5e_priv *priv)
3092 {
3093         int err;
3094         int tc;
3095
3096         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3097                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3098                 if (err)
3099                         goto err_close_tises;
3100         }
3101
3102         return 0;
3103
3104 err_close_tises:
3105         for (tc--; tc >= 0; tc--)
3106                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3107
3108         return err;
3109 }
3110
3111 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3112 {
3113         int tc;
3114
3115         for (tc = 0; tc < priv->profile->max_tc; tc++)
3116                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3117 }
3118
3119 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3120                                       enum mlx5e_traffic_types tt,
3121                                       u32 *tirc)
3122 {
3123         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3124
3125         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3126
3127         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3128         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3129         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
3130 }
3131
3132 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3133 {
3134         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3135
3136         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3137
3138         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3139         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3140         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3141 }
3142
3143 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
3144 {
3145         struct mlx5e_tir *tir;
3146         void *tirc;
3147         int inlen;
3148         int i = 0;
3149         int err;
3150         u32 *in;
3151         int tt;
3152
3153         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3154         in = kvzalloc(inlen, GFP_KERNEL);
3155         if (!in)
3156                 return -ENOMEM;
3157
3158         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3159                 memset(in, 0, inlen);
3160                 tir = &priv->indir_tir[tt];
3161                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3162                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3163                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3164                 if (err) {
3165                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3166                         goto err_destroy_inner_tirs;
3167                 }
3168         }
3169
3170         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3171                 goto out;
3172
3173         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3174                 memset(in, 0, inlen);
3175                 tir = &priv->inner_indir_tir[i];
3176                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3177                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3178                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3179                 if (err) {
3180                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3181                         goto err_destroy_inner_tirs;
3182                 }
3183         }
3184
3185 out:
3186         kvfree(in);
3187
3188         return 0;
3189
3190 err_destroy_inner_tirs:
3191         for (i--; i >= 0; i--)
3192                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3193
3194         for (tt--; tt >= 0; tt--)
3195                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3196
3197         kvfree(in);
3198
3199         return err;
3200 }
3201
3202 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3203 {
3204         int nch = priv->profile->max_nch(priv->mdev);
3205         struct mlx5e_tir *tir;
3206         void *tirc;
3207         int inlen;
3208         int err;
3209         u32 *in;
3210         int ix;
3211
3212         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3213         in = kvzalloc(inlen, GFP_KERNEL);
3214         if (!in)
3215                 return -ENOMEM;
3216
3217         for (ix = 0; ix < nch; ix++) {
3218                 memset(in, 0, inlen);
3219                 tir = &priv->direct_tir[ix];
3220                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3221                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3222                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3223                 if (err)
3224                         goto err_destroy_ch_tirs;
3225         }
3226
3227         kvfree(in);
3228
3229         return 0;
3230
3231 err_destroy_ch_tirs:
3232         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3233         for (ix--; ix >= 0; ix--)
3234                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3235
3236         kvfree(in);
3237
3238         return err;
3239 }
3240
3241 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3242 {
3243         int i;
3244
3245         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3246                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3247
3248         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3249                 return;
3250
3251         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3252                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3253 }
3254
3255 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3256 {
3257         int nch = priv->profile->max_nch(priv->mdev);
3258         int i;
3259
3260         for (i = 0; i < nch; i++)
3261                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3262 }
3263
3264 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3265 {
3266         int err = 0;
3267         int i;
3268
3269         for (i = 0; i < chs->num; i++) {
3270                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3271                 if (err)
3272                         return err;
3273         }
3274
3275         return 0;
3276 }
3277
3278 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3279 {
3280         int err = 0;
3281         int i;
3282
3283         for (i = 0; i < chs->num; i++) {
3284                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3285                 if (err)
3286                         return err;
3287         }
3288
3289         return 0;
3290 }
3291
3292 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3293                                  struct tc_mqprio_qopt *mqprio)
3294 {
3295         struct mlx5e_priv *priv = netdev_priv(netdev);
3296         struct mlx5e_channels new_channels = {};
3297         u8 tc = mqprio->num_tc;
3298         int err = 0;
3299
3300         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3301
3302         if (tc && tc != MLX5E_MAX_NUM_TC)
3303                 return -EINVAL;
3304
3305         mutex_lock(&priv->state_lock);
3306
3307         new_channels.params = priv->channels.params;
3308         new_channels.params.num_tc = tc ? tc : 1;
3309
3310         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3311                 priv->channels.params = new_channels.params;
3312                 goto out;
3313         }
3314
3315         err = mlx5e_open_channels(priv, &new_channels);
3316         if (err)
3317                 goto out;
3318
3319         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3320                                     new_channels.params.num_tc);
3321         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3322 out:
3323         mutex_unlock(&priv->state_lock);
3324         return err;
3325 }
3326
3327 #ifdef CONFIG_MLX5_ESWITCH
3328 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3329                                      struct tc_cls_flower_offload *cls_flower,
3330                                      int flags)
3331 {
3332         switch (cls_flower->command) {
3333         case TC_CLSFLOWER_REPLACE:
3334                 return mlx5e_configure_flower(priv, cls_flower, flags);
3335         case TC_CLSFLOWER_DESTROY:
3336                 return mlx5e_delete_flower(priv, cls_flower, flags);
3337         case TC_CLSFLOWER_STATS:
3338                 return mlx5e_stats_flower(priv, cls_flower, flags);
3339         default:
3340                 return -EOPNOTSUPP;
3341         }
3342 }
3343
3344 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3345                                    void *cb_priv)
3346 {
3347         struct mlx5e_priv *priv = cb_priv;
3348
3349         if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3350                 return -EOPNOTSUPP;
3351
3352         switch (type) {
3353         case TC_SETUP_CLSFLOWER:
3354                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS);
3355         default:
3356                 return -EOPNOTSUPP;
3357         }
3358 }
3359
3360 static int mlx5e_setup_tc_block(struct net_device *dev,
3361                                 struct tc_block_offload *f)
3362 {
3363         struct mlx5e_priv *priv = netdev_priv(dev);
3364
3365         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3366                 return -EOPNOTSUPP;
3367
3368         switch (f->command) {
3369         case TC_BLOCK_BIND:
3370                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3371                                              priv, priv, f->extack);
3372         case TC_BLOCK_UNBIND:
3373                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3374                                         priv);
3375                 return 0;
3376         default:
3377                 return -EOPNOTSUPP;
3378         }
3379 }
3380 #endif
3381
3382 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3383                           void *type_data)
3384 {
3385         switch (type) {
3386 #ifdef CONFIG_MLX5_ESWITCH
3387         case TC_SETUP_BLOCK:
3388                 return mlx5e_setup_tc_block(dev, type_data);
3389 #endif
3390         case TC_SETUP_QDISC_MQPRIO:
3391                 return mlx5e_setup_tc_mqprio(dev, type_data);
3392         default:
3393                 return -EOPNOTSUPP;
3394         }
3395 }
3396
3397 static void
3398 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3399 {
3400         struct mlx5e_priv *priv = netdev_priv(dev);
3401         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3402         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3403         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3404
3405         /* update HW stats in background for next time */
3406         queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
3407
3408         if (mlx5e_is_uplink_rep(priv)) {
3409                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3410                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3411                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3412                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3413         } else {
3414                 mlx5e_grp_sw_update_stats(priv);
3415                 stats->rx_packets = sstats->rx_packets;
3416                 stats->rx_bytes   = sstats->rx_bytes;
3417                 stats->tx_packets = sstats->tx_packets;
3418                 stats->tx_bytes   = sstats->tx_bytes;
3419                 stats->tx_dropped = sstats->tx_queue_dropped;
3420         }
3421
3422         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3423
3424         stats->rx_length_errors =
3425                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3426                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3427                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3428         stats->rx_crc_errors =
3429                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3430         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3431         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3432         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3433                            stats->rx_frame_errors;
3434         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3435
3436         /* vport multicast also counts packets that are dropped due to steering
3437          * or rx out of buffer
3438          */
3439         stats->multicast =
3440                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3441 }
3442
3443 static void mlx5e_set_rx_mode(struct net_device *dev)
3444 {
3445         struct mlx5e_priv *priv = netdev_priv(dev);
3446
3447         queue_work(priv->wq, &priv->set_rx_mode_work);
3448 }
3449
3450 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3451 {
3452         struct mlx5e_priv *priv = netdev_priv(netdev);
3453         struct sockaddr *saddr = addr;
3454
3455         if (!is_valid_ether_addr(saddr->sa_data))
3456                 return -EADDRNOTAVAIL;
3457
3458         netif_addr_lock_bh(netdev);
3459         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3460         netif_addr_unlock_bh(netdev);
3461
3462         queue_work(priv->wq, &priv->set_rx_mode_work);
3463
3464         return 0;
3465 }
3466
3467 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3468         do {                                            \
3469                 if (enable)                             \
3470                         *features |= feature;           \
3471                 else                                    \
3472                         *features &= ~feature;          \
3473         } while (0)
3474
3475 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3476
3477 static int set_feature_lro(struct net_device *netdev, bool enable)
3478 {
3479         struct mlx5e_priv *priv = netdev_priv(netdev);
3480         struct mlx5_core_dev *mdev = priv->mdev;
3481         struct mlx5e_channels new_channels = {};
3482         struct mlx5e_params *old_params;
3483         int err = 0;
3484         bool reset;
3485
3486         mutex_lock(&priv->state_lock);
3487
3488         old_params = &priv->channels.params;
3489         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3490                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3491                 err = -EINVAL;
3492                 goto out;
3493         }
3494
3495         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3496
3497         new_channels.params = *old_params;
3498         new_channels.params.lro_en = enable;
3499
3500         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3501                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3502                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3503                         reset = false;
3504         }
3505
3506         if (!reset) {
3507                 *old_params = new_channels.params;
3508                 err = mlx5e_modify_tirs_lro(priv);
3509                 goto out;
3510         }
3511
3512         err = mlx5e_open_channels(priv, &new_channels);
3513         if (err)
3514                 goto out;
3515
3516         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3517 out:
3518         mutex_unlock(&priv->state_lock);
3519         return err;
3520 }
3521
3522 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3523 {
3524         struct mlx5e_priv *priv = netdev_priv(netdev);
3525
3526         if (enable)
3527                 mlx5e_enable_cvlan_filter(priv);
3528         else
3529                 mlx5e_disable_cvlan_filter(priv);
3530
3531         return 0;
3532 }
3533
3534 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3535 {
3536         struct mlx5e_priv *priv = netdev_priv(netdev);
3537
3538         if (!enable && mlx5e_tc_num_filters(priv)) {
3539                 netdev_err(netdev,
3540                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3541                 return -EINVAL;
3542         }
3543
3544         return 0;
3545 }
3546
3547 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3548 {
3549         struct mlx5e_priv *priv = netdev_priv(netdev);
3550         struct mlx5_core_dev *mdev = priv->mdev;
3551
3552         return mlx5_set_port_fcs(mdev, !enable);
3553 }
3554
3555 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3556 {
3557         struct mlx5e_priv *priv = netdev_priv(netdev);
3558         int err;
3559
3560         mutex_lock(&priv->state_lock);
3561
3562         priv->channels.params.scatter_fcs_en = enable;
3563         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3564         if (err)
3565                 priv->channels.params.scatter_fcs_en = !enable;
3566
3567         mutex_unlock(&priv->state_lock);
3568
3569         return err;
3570 }
3571
3572 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3573 {
3574         struct mlx5e_priv *priv = netdev_priv(netdev);
3575         int err = 0;
3576
3577         mutex_lock(&priv->state_lock);
3578
3579         priv->channels.params.vlan_strip_disable = !enable;
3580         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3581                 goto unlock;
3582
3583         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3584         if (err)
3585                 priv->channels.params.vlan_strip_disable = enable;
3586
3587 unlock:
3588         mutex_unlock(&priv->state_lock);
3589
3590         return err;
3591 }
3592
3593 #ifdef CONFIG_RFS_ACCEL
3594 static int set_feature_arfs(struct net_device *netdev, bool enable)
3595 {
3596         struct mlx5e_priv *priv = netdev_priv(netdev);
3597         int err;
3598
3599         if (enable)
3600                 err = mlx5e_arfs_enable(priv);
3601         else
3602                 err = mlx5e_arfs_disable(priv);
3603
3604         return err;
3605 }
3606 #endif
3607
3608 static int mlx5e_handle_feature(struct net_device *netdev,
3609                                 netdev_features_t *features,
3610                                 netdev_features_t wanted_features,
3611                                 netdev_features_t feature,
3612                                 mlx5e_feature_handler feature_handler)
3613 {
3614         netdev_features_t changes = wanted_features ^ netdev->features;
3615         bool enable = !!(wanted_features & feature);
3616         int err;
3617
3618         if (!(changes & feature))
3619                 return 0;
3620
3621         err = feature_handler(netdev, enable);
3622         if (err) {
3623                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3624                            enable ? "Enable" : "Disable", &feature, err);
3625                 return err;
3626         }
3627
3628         MLX5E_SET_FEATURE(features, feature, enable);
3629         return 0;
3630 }
3631
3632 static int mlx5e_set_features(struct net_device *netdev,
3633                               netdev_features_t features)
3634 {
3635         netdev_features_t oper_features = netdev->features;
3636         int err = 0;
3637
3638 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3639         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3640
3641         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3642         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3643                                     set_feature_cvlan_filter);
3644         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3645         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3646         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3647         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3648 #ifdef CONFIG_RFS_ACCEL
3649         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3650 #endif
3651
3652         if (err) {
3653                 netdev->features = oper_features;
3654                 return -EINVAL;
3655         }
3656
3657         return 0;
3658 }
3659
3660 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3661                                             netdev_features_t features)
3662 {
3663         struct mlx5e_priv *priv = netdev_priv(netdev);
3664         struct mlx5e_params *params;
3665
3666         mutex_lock(&priv->state_lock);
3667         params = &priv->channels.params;
3668         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3669                 /* HW strips the outer C-tag header, this is a problem
3670                  * for S-tag traffic.
3671                  */
3672                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3673                 if (!params->vlan_strip_disable)
3674                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3675         }
3676         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3677                 features &= ~NETIF_F_LRO;
3678                 if (params->lro_en)
3679                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3680         }
3681
3682         mutex_unlock(&priv->state_lock);
3683
3684         return features;
3685 }
3686
3687 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3688                      change_hw_mtu_cb set_mtu_cb)
3689 {
3690         struct mlx5e_priv *priv = netdev_priv(netdev);
3691         struct mlx5e_channels new_channels = {};
3692         struct mlx5e_params *params;
3693         int err = 0;
3694         bool reset;
3695
3696         mutex_lock(&priv->state_lock);
3697
3698         params = &priv->channels.params;
3699
3700         reset = !params->lro_en;
3701         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3702
3703         new_channels.params = *params;
3704         new_channels.params.sw_mtu = new_mtu;
3705
3706         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3707                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3708                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3709
3710                 reset = reset && (ppw_old != ppw_new);
3711         }
3712
3713         if (!reset) {
3714                 params->sw_mtu = new_mtu;
3715                 set_mtu_cb(priv);
3716                 netdev->mtu = params->sw_mtu;
3717                 goto out;
3718         }
3719
3720         err = mlx5e_open_channels(priv, &new_channels);
3721         if (err)
3722                 goto out;
3723
3724         mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
3725         netdev->mtu = new_channels.params.sw_mtu;
3726
3727 out:
3728         mutex_unlock(&priv->state_lock);
3729         return err;
3730 }
3731
3732 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3733 {
3734         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3735 }
3736
3737 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3738 {
3739         struct hwtstamp_config config;
3740         int err;
3741
3742         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3743                 return -EOPNOTSUPP;
3744
3745         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3746                 return -EFAULT;
3747
3748         /* TX HW timestamp */
3749         switch (config.tx_type) {
3750         case HWTSTAMP_TX_OFF:
3751         case HWTSTAMP_TX_ON:
3752                 break;
3753         default:
3754                 return -ERANGE;
3755         }
3756
3757         mutex_lock(&priv->state_lock);
3758         /* RX HW timestamp */
3759         switch (config.rx_filter) {
3760         case HWTSTAMP_FILTER_NONE:
3761                 /* Reset CQE compression to Admin default */
3762                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3763                 break;
3764         case HWTSTAMP_FILTER_ALL:
3765         case HWTSTAMP_FILTER_SOME:
3766         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3767         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3768         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3769         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3770         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3771         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3772         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3773         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3774         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3775         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3776         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3777         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3778         case HWTSTAMP_FILTER_NTP_ALL:
3779                 /* Disable CQE compression */
3780                 netdev_warn(priv->netdev, "Disabling cqe compression");
3781                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3782                 if (err) {
3783                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3784                         mutex_unlock(&priv->state_lock);
3785                         return err;
3786                 }
3787                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3788                 break;
3789         default:
3790                 mutex_unlock(&priv->state_lock);
3791                 return -ERANGE;
3792         }
3793
3794         memcpy(&priv->tstamp, &config, sizeof(config));
3795         mutex_unlock(&priv->state_lock);
3796
3797         return copy_to_user(ifr->ifr_data, &config,
3798                             sizeof(config)) ? -EFAULT : 0;
3799 }
3800
3801 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3802 {
3803         struct hwtstamp_config *cfg = &priv->tstamp;
3804
3805         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3806                 return -EOPNOTSUPP;
3807
3808         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3809 }
3810
3811 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3812 {
3813         struct mlx5e_priv *priv = netdev_priv(dev);
3814
3815         switch (cmd) {
3816         case SIOCSHWTSTAMP:
3817                 return mlx5e_hwstamp_set(priv, ifr);
3818         case SIOCGHWTSTAMP:
3819                 return mlx5e_hwstamp_get(priv, ifr);
3820         default:
3821                 return -EOPNOTSUPP;
3822         }
3823 }
3824
3825 #ifdef CONFIG_MLX5_ESWITCH
3826 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3827 {
3828         struct mlx5e_priv *priv = netdev_priv(dev);
3829         struct mlx5_core_dev *mdev = priv->mdev;
3830
3831         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3832 }
3833
3834 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3835                              __be16 vlan_proto)
3836 {
3837         struct mlx5e_priv *priv = netdev_priv(dev);
3838         struct mlx5_core_dev *mdev = priv->mdev;
3839
3840         if (vlan_proto != htons(ETH_P_8021Q))
3841                 return -EPROTONOSUPPORT;
3842
3843         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3844                                            vlan, qos);
3845 }
3846
3847 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3848 {
3849         struct mlx5e_priv *priv = netdev_priv(dev);
3850         struct mlx5_core_dev *mdev = priv->mdev;
3851
3852         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3853 }
3854
3855 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3856 {
3857         struct mlx5e_priv *priv = netdev_priv(dev);
3858         struct mlx5_core_dev *mdev = priv->mdev;
3859
3860         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3861 }
3862
3863 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3864                              int max_tx_rate)
3865 {
3866         struct mlx5e_priv *priv = netdev_priv(dev);
3867         struct mlx5_core_dev *mdev = priv->mdev;
3868
3869         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3870                                            max_tx_rate, min_tx_rate);
3871 }
3872
3873 static int mlx5_vport_link2ifla(u8 esw_link)
3874 {
3875         switch (esw_link) {
3876         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3877                 return IFLA_VF_LINK_STATE_DISABLE;
3878         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3879                 return IFLA_VF_LINK_STATE_ENABLE;
3880         }
3881         return IFLA_VF_LINK_STATE_AUTO;
3882 }
3883
3884 static int mlx5_ifla_link2vport(u8 ifla_link)
3885 {
3886         switch (ifla_link) {
3887         case IFLA_VF_LINK_STATE_DISABLE:
3888                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3889         case IFLA_VF_LINK_STATE_ENABLE:
3890                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3891         }
3892         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3893 }
3894
3895 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3896                                    int link_state)
3897 {
3898         struct mlx5e_priv *priv = netdev_priv(dev);
3899         struct mlx5_core_dev *mdev = priv->mdev;
3900
3901         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3902                                             mlx5_ifla_link2vport(link_state));
3903 }
3904
3905 static int mlx5e_get_vf_config(struct net_device *dev,
3906                                int vf, struct ifla_vf_info *ivi)
3907 {
3908         struct mlx5e_priv *priv = netdev_priv(dev);
3909         struct mlx5_core_dev *mdev = priv->mdev;
3910         int err;
3911
3912         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3913         if (err)
3914                 return err;
3915         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3916         return 0;
3917 }
3918
3919 static int mlx5e_get_vf_stats(struct net_device *dev,
3920                               int vf, struct ifla_vf_stats *vf_stats)
3921 {
3922         struct mlx5e_priv *priv = netdev_priv(dev);
3923         struct mlx5_core_dev *mdev = priv->mdev;
3924
3925         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3926                                             vf_stats);
3927 }
3928 #endif
3929
3930 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3931                                  struct udp_tunnel_info *ti)
3932 {
3933         struct mlx5e_priv *priv = netdev_priv(netdev);
3934
3935         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3936                 return;
3937
3938         if (!mlx5e_vxlan_allowed(priv->mdev))
3939                 return;
3940
3941         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3942 }
3943
3944 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3945                                  struct udp_tunnel_info *ti)
3946 {
3947         struct mlx5e_priv *priv = netdev_priv(netdev);
3948
3949         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3950                 return;
3951
3952         if (!mlx5e_vxlan_allowed(priv->mdev))
3953                 return;
3954
3955         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3956 }
3957
3958 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3959                                                      struct sk_buff *skb,
3960                                                      netdev_features_t features)
3961 {
3962         unsigned int offset = 0;
3963         struct udphdr *udph;
3964         u8 proto;
3965         u16 port;
3966
3967         switch (vlan_get_protocol(skb)) {
3968         case htons(ETH_P_IP):
3969                 proto = ip_hdr(skb)->protocol;
3970                 break;
3971         case htons(ETH_P_IPV6):
3972                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3973                 break;
3974         default:
3975                 goto out;
3976         }
3977
3978         switch (proto) {
3979         case IPPROTO_GRE:
3980                 return features;
3981         case IPPROTO_UDP:
3982                 udph = udp_hdr(skb);
3983                 port = be16_to_cpu(udph->dest);
3984
3985                 /* Verify if UDP port is being offloaded by HW */
3986                 if (mlx5e_vxlan_lookup_port(priv, port))
3987                         return features;
3988         }
3989
3990 out:
3991         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3992         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3993 }
3994
3995 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3996                                               struct net_device *netdev,
3997                                               netdev_features_t features)
3998 {
3999         struct mlx5e_priv *priv = netdev_priv(netdev);
4000
4001         features = vlan_features_check(skb, features);
4002         features = vxlan_features_check(skb, features);
4003
4004 #ifdef CONFIG_MLX5_EN_IPSEC
4005         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4006                 return features;
4007 #endif
4008
4009         /* Validate if the tunneled packet is being offloaded by HW */
4010         if (skb->encapsulation &&
4011             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4012                 return mlx5e_tunnel_features_check(priv, skb, features);
4013
4014         return features;
4015 }
4016
4017 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4018                                         struct mlx5e_txqsq *sq)
4019 {
4020         struct mlx5_eq *eq = sq->cq.mcq.eq;
4021         u32 eqe_count;
4022
4023         netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
4024                    eq->eqn, eq->cons_index, eq->irqn);
4025
4026         eqe_count = mlx5_eq_poll_irq_disabled(eq);
4027         if (!eqe_count)
4028                 return false;
4029
4030         netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
4031         sq->channel->stats->eq_rearm++;
4032         return true;
4033 }
4034
4035 static void mlx5e_tx_timeout_work(struct work_struct *work)
4036 {
4037         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4038                                                tx_timeout_work);
4039         struct net_device *dev = priv->netdev;
4040         bool reopen_channels = false;
4041         int i, err;
4042
4043         rtnl_lock();
4044         mutex_lock(&priv->state_lock);
4045
4046         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4047                 goto unlock;
4048
4049         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4050                 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
4051                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4052
4053                 if (!netif_xmit_stopped(dev_queue))
4054                         continue;
4055
4056                 netdev_err(dev,
4057                            "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
4058                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4059                            jiffies_to_usecs(jiffies - dev_queue->trans_start));
4060
4061                 /* If we recover a lost interrupt, most likely TX timeout will
4062                  * be resolved, skip reopening channels
4063                  */
4064                 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4065                         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4066                         reopen_channels = true;
4067                 }
4068         }
4069
4070         if (!reopen_channels)
4071                 goto unlock;
4072
4073         mlx5e_close_locked(dev);
4074         err = mlx5e_open_locked(dev);
4075         if (err)
4076                 netdev_err(priv->netdev,
4077                            "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4078                            err);
4079
4080 unlock:
4081         mutex_unlock(&priv->state_lock);
4082         rtnl_unlock();
4083 }
4084
4085 static void mlx5e_tx_timeout(struct net_device *dev)
4086 {
4087         struct mlx5e_priv *priv = netdev_priv(dev);
4088
4089         netdev_err(dev, "TX timeout detected\n");
4090         queue_work(priv->wq, &priv->tx_timeout_work);
4091 }
4092
4093 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4094 {
4095         struct mlx5e_priv *priv = netdev_priv(netdev);
4096         struct bpf_prog *old_prog;
4097         int err = 0;
4098         bool reset, was_opened;
4099         int i;
4100
4101         mutex_lock(&priv->state_lock);
4102
4103         if ((netdev->features & NETIF_F_LRO) && prog) {
4104                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4105                 err = -EINVAL;
4106                 goto unlock;
4107         }
4108
4109         if ((netdev->features & NETIF_F_HW_ESP) && prog) {
4110                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4111                 err = -EINVAL;
4112                 goto unlock;
4113         }
4114
4115         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4116         /* no need for full reset when exchanging programs */
4117         reset = (!priv->channels.params.xdp_prog || !prog);
4118
4119         if (was_opened && reset)
4120                 mlx5e_close_locked(netdev);
4121         if (was_opened && !reset) {
4122                 /* num_channels is invariant here, so we can take the
4123                  * batched reference right upfront.
4124                  */
4125                 prog = bpf_prog_add(prog, priv->channels.num);
4126                 if (IS_ERR(prog)) {
4127                         err = PTR_ERR(prog);
4128                         goto unlock;
4129                 }
4130         }
4131
4132         /* exchange programs, extra prog reference we got from caller
4133          * as long as we don't fail from this point onwards.
4134          */
4135         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4136         if (old_prog)
4137                 bpf_prog_put(old_prog);
4138
4139         if (reset) /* change RQ type according to priv->xdp_prog */
4140                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4141
4142         if (was_opened && reset)
4143                 mlx5e_open_locked(netdev);
4144
4145         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4146                 goto unlock;
4147
4148         /* exchanging programs w/o reset, we update ref counts on behalf
4149          * of the channels RQs here.
4150          */
4151         for (i = 0; i < priv->channels.num; i++) {
4152                 struct mlx5e_channel *c = priv->channels.c[i];
4153
4154                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4155                 napi_synchronize(&c->napi);
4156                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4157
4158                 old_prog = xchg(&c->rq.xdp_prog, prog);
4159
4160                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4161                 /* napi_schedule in case we have missed anything */
4162                 napi_schedule(&c->napi);
4163
4164                 if (old_prog)
4165                         bpf_prog_put(old_prog);
4166         }
4167
4168 unlock:
4169         mutex_unlock(&priv->state_lock);
4170         return err;
4171 }
4172
4173 static u32 mlx5e_xdp_query(struct net_device *dev)
4174 {
4175         struct mlx5e_priv *priv = netdev_priv(dev);
4176         const struct bpf_prog *xdp_prog;
4177         u32 prog_id = 0;
4178
4179         mutex_lock(&priv->state_lock);
4180         xdp_prog = priv->channels.params.xdp_prog;
4181         if (xdp_prog)
4182                 prog_id = xdp_prog->aux->id;
4183         mutex_unlock(&priv->state_lock);
4184
4185         return prog_id;
4186 }
4187
4188 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4189 {
4190         switch (xdp->command) {
4191         case XDP_SETUP_PROG:
4192                 return mlx5e_xdp_set(dev, xdp->prog);
4193         case XDP_QUERY_PROG:
4194                 xdp->prog_id = mlx5e_xdp_query(dev);
4195                 return 0;
4196         default:
4197                 return -EINVAL;
4198         }
4199 }
4200
4201 #ifdef CONFIG_NET_POLL_CONTROLLER
4202 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
4203  * reenabling interrupts.
4204  */
4205 static void mlx5e_netpoll(struct net_device *dev)
4206 {
4207         struct mlx5e_priv *priv = netdev_priv(dev);
4208         struct mlx5e_channels *chs = &priv->channels;
4209
4210         int i;
4211
4212         for (i = 0; i < chs->num; i++)
4213                 napi_schedule(&chs->c[i]->napi);
4214 }
4215 #endif
4216
4217 static const struct net_device_ops mlx5e_netdev_ops = {
4218         .ndo_open                = mlx5e_open,
4219         .ndo_stop                = mlx5e_close,
4220         .ndo_start_xmit          = mlx5e_xmit,
4221         .ndo_setup_tc            = mlx5e_setup_tc,
4222         .ndo_select_queue        = mlx5e_select_queue,
4223         .ndo_get_stats64         = mlx5e_get_stats,
4224         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4225         .ndo_set_mac_address     = mlx5e_set_mac,
4226         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4227         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4228         .ndo_set_features        = mlx5e_set_features,
4229         .ndo_fix_features        = mlx5e_fix_features,
4230         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4231         .ndo_do_ioctl            = mlx5e_ioctl,
4232         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4233         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4234         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4235         .ndo_features_check      = mlx5e_features_check,
4236 #ifdef CONFIG_RFS_ACCEL
4237         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4238 #endif
4239         .ndo_tx_timeout          = mlx5e_tx_timeout,
4240         .ndo_bpf                 = mlx5e_xdp,
4241 #ifdef CONFIG_NET_POLL_CONTROLLER
4242         .ndo_poll_controller     = mlx5e_netpoll,
4243 #endif
4244 #ifdef CONFIG_MLX5_ESWITCH
4245         /* SRIOV E-Switch NDOs */
4246         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4247         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4248         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4249         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4250         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4251         .ndo_get_vf_config       = mlx5e_get_vf_config,
4252         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4253         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4254         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4255         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4256 #endif
4257 };
4258
4259 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4260 {
4261         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4262                 return -EOPNOTSUPP;
4263         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4264             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4265             !MLX5_CAP_ETH(mdev, csum_cap) ||
4266             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4267             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4268             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4269             MLX5_CAP_FLOWTABLE(mdev,
4270                                flow_table_properties_nic_receive.max_ft_level)
4271                                < 3) {
4272                 mlx5_core_warn(mdev,
4273                                "Not creating net device, some required device capabilities are missing\n");
4274                 return -EOPNOTSUPP;
4275         }
4276         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4277                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4278         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4279                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4280
4281         return 0;
4282 }
4283
4284 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4285                                    int num_channels)
4286 {
4287         int i;
4288
4289         for (i = 0; i < len; i++)
4290                 indirection_rqt[i] = i % num_channels;
4291 }
4292
4293 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4294 {
4295         u32 link_speed = 0;
4296         u32 pci_bw = 0;
4297
4298         mlx5e_port_max_linkspeed(mdev, &link_speed);
4299         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4300         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4301                            link_speed, pci_bw);
4302
4303 #define MLX5E_SLOW_PCI_RATIO (2)
4304
4305         return link_speed && pci_bw &&
4306                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4307 }
4308
4309 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4310 {
4311         struct net_dim_cq_moder moder;
4312
4313         moder.cq_period_mode = cq_period_mode;
4314         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4315         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4316         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4317                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4318
4319         return moder;
4320 }
4321
4322 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4323 {
4324         struct net_dim_cq_moder moder;
4325
4326         moder.cq_period_mode = cq_period_mode;
4327         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4328         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4329         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4330                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4331
4332         return moder;
4333 }
4334
4335 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4336 {
4337         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4338                 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4339                 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4340 }
4341
4342 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4343 {
4344         if (params->tx_dim_enabled) {
4345                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4346
4347                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4348         } else {
4349                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4350         }
4351
4352         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4353                         params->tx_cq_moderation.cq_period_mode ==
4354                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4355 }
4356
4357 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4358 {
4359         if (params->rx_dim_enabled) {
4360                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4361
4362                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4363         } else {
4364                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4365         }
4366
4367         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4368                         params->rx_cq_moderation.cq_period_mode ==
4369                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4370 }
4371
4372 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4373 {
4374         int i;
4375
4376         /* The supported periods are organized in ascending order */
4377         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4378                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4379                         break;
4380
4381         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4382 }
4383
4384 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4385                             struct mlx5e_params *params,
4386                             u16 max_channels, u16 mtu)
4387 {
4388         u8 rx_cq_period_mode;
4389
4390         params->sw_mtu = mtu;
4391         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4392         params->num_channels = max_channels;
4393         params->num_tc       = 1;
4394
4395         /* SQ */
4396         params->log_sq_size = is_kdump_kernel() ?
4397                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4398                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4399
4400         /* set CQE compression */
4401         params->rx_cqe_compress_def = false;
4402         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4403             MLX5_CAP_GEN(mdev, vport_group_manager))
4404                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4405
4406         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4407
4408         /* RQ */
4409         /* Prefer Striding RQ, unless any of the following holds:
4410          * - Striding RQ configuration is not possible/supported.
4411          * - Slow PCI heuristic.
4412          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4413          */
4414         if (!slow_pci_heuristic(mdev) &&
4415             mlx5e_striding_rq_possible(mdev, params) &&
4416             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4417              !mlx5e_rx_is_linear_skb(mdev, params)))
4418                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4419         mlx5e_set_rq_type(mdev, params);
4420         mlx5e_init_rq_type_params(mdev, params);
4421
4422         /* HW LRO */
4423
4424         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4425         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4426                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4427                         params->lro_en = !slow_pci_heuristic(mdev);
4428         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4429
4430         /* CQ moderation params */
4431         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4432                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4433                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4434         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4435         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4436         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4437         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4438
4439         /* TX inline */
4440         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4441
4442         /* RSS */
4443         params->rss_hfunc = ETH_RSS_HASH_XOR;
4444         netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4445         mlx5e_build_default_indir_rqt(params->indirection_rqt,
4446                                       MLX5E_INDIR_RQT_SIZE, max_channels);
4447 }
4448
4449 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4450                                         struct net_device *netdev,
4451                                         const struct mlx5e_profile *profile,
4452                                         void *ppriv)
4453 {
4454         struct mlx5e_priv *priv = netdev_priv(netdev);
4455
4456         priv->mdev        = mdev;
4457         priv->netdev      = netdev;
4458         priv->profile     = profile;
4459         priv->ppriv       = ppriv;
4460         priv->msglevel    = MLX5E_MSG_LEVEL;
4461         priv->max_opened_tc = 1;
4462
4463         mlx5e_build_nic_params(mdev, &priv->channels.params,
4464                                profile->max_nch(mdev), netdev->mtu);
4465
4466         mutex_init(&priv->state_lock);
4467
4468         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4469         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4470         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4471         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4472
4473         mlx5e_timestamp_init(priv);
4474 }
4475
4476 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4477 {
4478         struct mlx5e_priv *priv = netdev_priv(netdev);
4479
4480         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4481         if (is_zero_ether_addr(netdev->dev_addr) &&
4482             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4483                 eth_hw_addr_random(netdev);
4484                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4485         }
4486 }
4487
4488 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4489 static const struct switchdev_ops mlx5e_switchdev_ops = {
4490         .switchdev_port_attr_get        = mlx5e_attr_get,
4491 };
4492 #endif
4493
4494 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4495 {
4496         struct mlx5e_priv *priv = netdev_priv(netdev);
4497         struct mlx5_core_dev *mdev = priv->mdev;
4498         bool fcs_supported;
4499         bool fcs_enabled;
4500
4501         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4502
4503         netdev->netdev_ops = &mlx5e_netdev_ops;
4504
4505 #ifdef CONFIG_MLX5_CORE_EN_DCB
4506         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4507                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4508 #endif
4509
4510         netdev->watchdog_timeo    = 15 * HZ;
4511
4512         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4513
4514         netdev->vlan_features    |= NETIF_F_SG;
4515         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4516         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4517         netdev->vlan_features    |= NETIF_F_GRO;
4518         netdev->vlan_features    |= NETIF_F_TSO;
4519         netdev->vlan_features    |= NETIF_F_TSO6;
4520         netdev->vlan_features    |= NETIF_F_RXCSUM;
4521         netdev->vlan_features    |= NETIF_F_RXHASH;
4522
4523         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4524         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4525
4526         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4527             mlx5e_check_fragmented_striding_rq_cap(mdev))
4528                 netdev->vlan_features    |= NETIF_F_LRO;
4529
4530         netdev->hw_features       = netdev->vlan_features;
4531         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4532         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4533         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4534         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4535
4536         if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4537                 netdev->hw_features     |= NETIF_F_GSO_PARTIAL;
4538                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4539                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4540                 netdev->hw_enc_features |= NETIF_F_TSO;
4541                 netdev->hw_enc_features |= NETIF_F_TSO6;
4542                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4543         }
4544
4545         if (mlx5e_vxlan_allowed(mdev)) {
4546                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4547                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4548                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4549                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4550                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4551         }
4552
4553         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4554                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4555                                            NETIF_F_GSO_GRE_CSUM;
4556                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4557                                            NETIF_F_GSO_GRE_CSUM;
4558                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4559                                                 NETIF_F_GSO_GRE_CSUM;
4560         }
4561
4562         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4563
4564         if (fcs_supported)
4565                 netdev->hw_features |= NETIF_F_RXALL;
4566
4567         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4568                 netdev->hw_features |= NETIF_F_RXFCS;
4569
4570         netdev->features          = netdev->hw_features;
4571         if (!priv->channels.params.lro_en)
4572                 netdev->features  &= ~NETIF_F_LRO;
4573
4574         if (fcs_enabled)
4575                 netdev->features  &= ~NETIF_F_RXALL;
4576
4577         if (!priv->channels.params.scatter_fcs_en)
4578                 netdev->features  &= ~NETIF_F_RXFCS;
4579
4580 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4581         if (FT_CAP(flow_modify_en) &&
4582             FT_CAP(modify_root) &&
4583             FT_CAP(identified_miss_table_mode) &&
4584             FT_CAP(flow_table_modify)) {
4585                 netdev->hw_features      |= NETIF_F_HW_TC;
4586 #ifdef CONFIG_RFS_ACCEL
4587                 netdev->hw_features      |= NETIF_F_NTUPLE;
4588 #endif
4589         }
4590
4591         netdev->features         |= NETIF_F_HIGHDMA;
4592         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4593
4594         netdev->features         |= NETIF_F_GSO_UDP_L4;
4595         netdev->hw_features      |= NETIF_F_GSO_UDP_L4;
4596
4597         netdev->priv_flags       |= IFF_UNICAST_FLT;
4598
4599         mlx5e_set_netdev_dev_addr(netdev);
4600
4601 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4602         if (MLX5_ESWITCH_MANAGER(mdev))
4603                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4604 #endif
4605
4606         mlx5e_ipsec_build_netdev(priv);
4607         mlx5e_tls_build_netdev(priv);
4608 }
4609
4610 static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4611 {
4612         struct mlx5_core_dev *mdev = priv->mdev;
4613         int err;
4614
4615         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4616         if (err) {
4617                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4618                 priv->q_counter = 0;
4619         }
4620
4621         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4622         if (err) {
4623                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4624                 priv->drop_rq_q_counter = 0;
4625         }
4626 }
4627
4628 static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4629 {
4630         if (priv->q_counter)
4631                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4632
4633         if (priv->drop_rq_q_counter)
4634                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4635 }
4636
4637 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4638                            struct net_device *netdev,
4639                            const struct mlx5e_profile *profile,
4640                            void *ppriv)
4641 {
4642         struct mlx5e_priv *priv = netdev_priv(netdev);
4643         int err;
4644
4645         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4646         err = mlx5e_ipsec_init(priv);
4647         if (err)
4648                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4649         err = mlx5e_tls_init(priv);
4650         if (err)
4651                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4652         mlx5e_build_nic_netdev(netdev);
4653         mlx5e_build_tc2txq_maps(priv);
4654         mlx5e_vxlan_init(priv);
4655 }
4656
4657 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4658 {
4659         mlx5e_tls_cleanup(priv);
4660         mlx5e_ipsec_cleanup(priv);
4661         mlx5e_vxlan_cleanup(priv);
4662 }
4663
4664 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4665 {
4666         struct mlx5_core_dev *mdev = priv->mdev;
4667         int err;
4668
4669         err = mlx5e_create_indirect_rqt(priv);
4670         if (err)
4671                 return err;
4672
4673         err = mlx5e_create_direct_rqts(priv);
4674         if (err)
4675                 goto err_destroy_indirect_rqts;
4676
4677         err = mlx5e_create_indirect_tirs(priv);
4678         if (err)
4679                 goto err_destroy_direct_rqts;
4680
4681         err = mlx5e_create_direct_tirs(priv);
4682         if (err)
4683                 goto err_destroy_indirect_tirs;
4684
4685         err = mlx5e_create_flow_steering(priv);
4686         if (err) {
4687                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4688                 goto err_destroy_direct_tirs;
4689         }
4690
4691         err = mlx5e_tc_nic_init(priv);
4692         if (err)
4693                 goto err_destroy_flow_steering;
4694
4695         return 0;
4696
4697 err_destroy_flow_steering:
4698         mlx5e_destroy_flow_steering(priv);
4699 err_destroy_direct_tirs:
4700         mlx5e_destroy_direct_tirs(priv);
4701 err_destroy_indirect_tirs:
4702         mlx5e_destroy_indirect_tirs(priv);
4703 err_destroy_direct_rqts:
4704         mlx5e_destroy_direct_rqts(priv);
4705 err_destroy_indirect_rqts:
4706         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4707         return err;
4708 }
4709
4710 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4711 {
4712         mlx5e_tc_nic_cleanup(priv);
4713         mlx5e_destroy_flow_steering(priv);
4714         mlx5e_destroy_direct_tirs(priv);
4715         mlx5e_destroy_indirect_tirs(priv);
4716         mlx5e_destroy_direct_rqts(priv);
4717         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4718 }
4719
4720 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4721 {
4722         int err;
4723
4724         err = mlx5e_create_tises(priv);
4725         if (err) {
4726                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4727                 return err;
4728         }
4729
4730 #ifdef CONFIG_MLX5_CORE_EN_DCB
4731         mlx5e_dcbnl_initialize(priv);
4732 #endif
4733         return 0;
4734 }
4735
4736 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4737 {
4738         struct net_device *netdev = priv->netdev;
4739         struct mlx5_core_dev *mdev = priv->mdev;
4740         u16 max_mtu;
4741
4742         mlx5e_init_l2_addr(priv);
4743
4744         /* Marking the link as currently not needed by the Driver */
4745         if (!netif_running(netdev))
4746                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4747
4748         /* MTU range: 68 - hw-specific max */
4749         netdev->min_mtu = ETH_MIN_MTU;
4750         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4751         netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4752         mlx5e_set_dev_port_mtu(priv);
4753
4754         mlx5_lag_add(mdev, netdev);
4755
4756         mlx5e_enable_async_events(priv);
4757
4758         if (MLX5_ESWITCH_MANAGER(priv->mdev))
4759                 mlx5e_register_vport_reps(priv);
4760
4761         if (netdev->reg_state != NETREG_REGISTERED)
4762                 return;
4763 #ifdef CONFIG_MLX5_CORE_EN_DCB
4764         mlx5e_dcbnl_init_app(priv);
4765 #endif
4766
4767         queue_work(priv->wq, &priv->set_rx_mode_work);
4768
4769         rtnl_lock();
4770         if (netif_running(netdev))
4771                 mlx5e_open(netdev);
4772         netif_device_attach(netdev);
4773         rtnl_unlock();
4774 }
4775
4776 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4777 {
4778         struct mlx5_core_dev *mdev = priv->mdev;
4779
4780 #ifdef CONFIG_MLX5_CORE_EN_DCB
4781         if (priv->netdev->reg_state == NETREG_REGISTERED)
4782                 mlx5e_dcbnl_delete_app(priv);
4783 #endif
4784
4785         rtnl_lock();
4786         if (netif_running(priv->netdev))
4787                 mlx5e_close(priv->netdev);
4788         netif_device_detach(priv->netdev);
4789         rtnl_unlock();
4790
4791         queue_work(priv->wq, &priv->set_rx_mode_work);
4792
4793         if (MLX5_ESWITCH_MANAGER(priv->mdev))
4794                 mlx5e_unregister_vport_reps(priv);
4795
4796         mlx5e_disable_async_events(priv);
4797         mlx5_lag_remove(mdev);
4798 }
4799
4800 static const struct mlx5e_profile mlx5e_nic_profile = {
4801         .init              = mlx5e_nic_init,
4802         .cleanup           = mlx5e_nic_cleanup,
4803         .init_rx           = mlx5e_init_nic_rx,
4804         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4805         .init_tx           = mlx5e_init_nic_tx,
4806         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4807         .enable            = mlx5e_nic_enable,
4808         .disable           = mlx5e_nic_disable,
4809         .update_stats      = mlx5e_update_ndo_stats,
4810         .max_nch           = mlx5e_get_max_num_channels,
4811         .update_carrier    = mlx5e_update_carrier,
4812         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4813         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4814         .max_tc            = MLX5E_MAX_NUM_TC,
4815 };
4816
4817 /* mlx5e generic netdev management API (move to en_common.c) */
4818
4819 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4820                                        const struct mlx5e_profile *profile,
4821                                        void *ppriv)
4822 {
4823         int nch = profile->max_nch(mdev);
4824         struct net_device *netdev;
4825         struct mlx5e_priv *priv;
4826
4827         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4828                                     nch * profile->max_tc,
4829                                     nch);
4830         if (!netdev) {
4831                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4832                 return NULL;
4833         }
4834
4835 #ifdef CONFIG_RFS_ACCEL
4836         netdev->rx_cpu_rmap = mdev->rmap;
4837 #endif
4838
4839         profile->init(mdev, netdev, profile, ppriv);
4840
4841         netif_carrier_off(netdev);
4842
4843         priv = netdev_priv(netdev);
4844
4845         priv->wq = create_singlethread_workqueue("mlx5e");
4846         if (!priv->wq)
4847                 goto err_cleanup_nic;
4848
4849         return netdev;
4850
4851 err_cleanup_nic:
4852         if (profile->cleanup)
4853                 profile->cleanup(priv);
4854         free_netdev(netdev);
4855
4856         return NULL;
4857 }
4858
4859 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4860 {
4861         struct mlx5_core_dev *mdev = priv->mdev;
4862         const struct mlx5e_profile *profile;
4863         int err;
4864
4865         profile = priv->profile;
4866         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4867
4868         err = profile->init_tx(priv);
4869         if (err)
4870                 goto out;
4871
4872         mlx5e_create_q_counters(priv);
4873
4874         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4875         if (err) {
4876                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4877                 goto err_destroy_q_counters;
4878         }
4879
4880         err = profile->init_rx(priv);
4881         if (err)
4882                 goto err_close_drop_rq;
4883
4884         if (profile->enable)
4885                 profile->enable(priv);
4886
4887         return 0;
4888
4889 err_close_drop_rq:
4890         mlx5e_close_drop_rq(&priv->drop_rq);
4891
4892 err_destroy_q_counters:
4893         mlx5e_destroy_q_counters(priv);
4894         profile->cleanup_tx(priv);
4895
4896 out:
4897         return err;
4898 }
4899
4900 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4901 {
4902         const struct mlx5e_profile *profile = priv->profile;
4903
4904         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4905
4906         if (profile->disable)
4907                 profile->disable(priv);
4908         flush_workqueue(priv->wq);
4909
4910         profile->cleanup_rx(priv);
4911         mlx5e_close_drop_rq(&priv->drop_rq);
4912         mlx5e_destroy_q_counters(priv);
4913         profile->cleanup_tx(priv);
4914         cancel_delayed_work_sync(&priv->update_stats_work);
4915 }
4916
4917 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4918 {
4919         const struct mlx5e_profile *profile = priv->profile;
4920         struct net_device *netdev = priv->netdev;
4921
4922         destroy_workqueue(priv->wq);
4923         if (profile->cleanup)
4924                 profile->cleanup(priv);
4925         free_netdev(netdev);
4926 }
4927
4928 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4929  * hardware contexts and to connect it to the current netdev.
4930  */
4931 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4932 {
4933         struct mlx5e_priv *priv = vpriv;
4934         struct net_device *netdev = priv->netdev;
4935         int err;
4936
4937         if (netif_device_present(netdev))
4938                 return 0;
4939
4940         err = mlx5e_create_mdev_resources(mdev);
4941         if (err)
4942                 return err;
4943
4944         err = mlx5e_attach_netdev(priv);
4945         if (err) {
4946                 mlx5e_destroy_mdev_resources(mdev);
4947                 return err;
4948         }
4949
4950         return 0;
4951 }
4952
4953 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4954 {
4955         struct mlx5e_priv *priv = vpriv;
4956         struct net_device *netdev = priv->netdev;
4957
4958         if (!netif_device_present(netdev))
4959                 return;
4960
4961         mlx5e_detach_netdev(priv);
4962         mlx5e_destroy_mdev_resources(mdev);
4963 }
4964
4965 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4966 {
4967         struct net_device *netdev;
4968         void *rpriv = NULL;
4969         void *priv;
4970         int err;
4971
4972         err = mlx5e_check_required_hca_cap(mdev);
4973         if (err)
4974                 return NULL;
4975
4976 #ifdef CONFIG_MLX5_ESWITCH
4977         if (MLX5_ESWITCH_MANAGER(mdev)) {
4978                 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4979                 if (!rpriv) {
4980                         mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4981                         return NULL;
4982                 }
4983         }
4984 #endif
4985
4986         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4987         if (!netdev) {
4988                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4989                 goto err_free_rpriv;
4990         }
4991
4992         priv = netdev_priv(netdev);
4993
4994         err = mlx5e_attach(mdev, priv);
4995         if (err) {
4996                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4997                 goto err_destroy_netdev;
4998         }
4999
5000         err = register_netdev(netdev);
5001         if (err) {
5002                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5003                 goto err_detach;
5004         }
5005
5006 #ifdef CONFIG_MLX5_CORE_EN_DCB
5007         mlx5e_dcbnl_init_app(priv);
5008 #endif
5009         return priv;
5010
5011 err_detach:
5012         mlx5e_detach(mdev, priv);
5013 err_destroy_netdev:
5014         mlx5e_destroy_netdev(priv);
5015 err_free_rpriv:
5016         kfree(rpriv);
5017         return NULL;
5018 }
5019
5020 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5021 {
5022         struct mlx5e_priv *priv = vpriv;
5023         void *ppriv = priv->ppriv;
5024
5025 #ifdef CONFIG_MLX5_CORE_EN_DCB
5026         mlx5e_dcbnl_delete_app(priv);
5027 #endif
5028         unregister_netdev(priv->netdev);
5029         mlx5e_detach(mdev, vpriv);
5030         mlx5e_destroy_netdev(priv);
5031         kfree(ppriv);
5032 }
5033
5034 static void *mlx5e_get_netdev(void *vpriv)
5035 {
5036         struct mlx5e_priv *priv = vpriv;
5037
5038         return priv->netdev;
5039 }
5040
5041 static struct mlx5_interface mlx5e_interface = {
5042         .add       = mlx5e_add,
5043         .remove    = mlx5e_remove,
5044         .attach    = mlx5e_attach,
5045         .detach    = mlx5e_detach,
5046         .event     = mlx5e_async_event,
5047         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5048         .get_dev   = mlx5e_get_netdev,
5049 };
5050
5051 void mlx5e_init(void)
5052 {
5053         mlx5e_ipsec_build_inverse_table();
5054         mlx5e_build_ptys2ethtool_map();
5055         mlx5_register_interface(&mlx5e_interface);
5056 }
5057
5058 void mlx5e_cleanup(void)
5059 {
5060         mlx5_unregister_interface(&mlx5e_interface);
5061 }