drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include "eswitch.h"
  39 #include "en.h"
  40 #include "en_tc.h"
  41 #include "en_rep.h"
  42 #include "en_accel/ipsec.h"
  43 #include "en_accel/ipsec_rxtx.h"
  44 #include "accel/ipsec.h"
  45 #include "vxlan.h"
  46
  47 struct mlx5e_rq_param {
  48         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  49         struct mlx5_wq_param    wq;
  50 };
  51
  52 struct mlx5e_sq_param {
  53         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  54         struct mlx5_wq_param       wq;
  55 };
  56
  57 struct mlx5e_cq_param {
  58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  59         struct mlx5_wq_param       wq;
  60         u16                        eq_ix;
  61         u8                         cq_period_mode;
  62 };
  63
  64 struct mlx5e_channel_param {
  65         struct mlx5e_rq_param      rq;
  66         struct mlx5e_sq_param      sq;
  67         struct mlx5e_sq_param      xdp_sq;
  68         struct mlx5e_sq_param      icosq;
  69         struct mlx5e_cq_param      rx_cq;
  70         struct mlx5e_cq_param      tx_cq;
  71         struct mlx5e_cq_param      icosq_cq;
  72 };
  73
  74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  75 {
  76         return MLX5_CAP_GEN(mdev, striding_rq) &&
  77                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  78                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  79 }
  80
  81 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  82                                struct mlx5e_params *params, u8 rq_type)
  83 {
  84         params->rq_wq_type = rq_type;
  85         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
  86         switch (params->rq_wq_type) {
  87         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
  88                 params->log_rq_size = is_kdump_kernel() ?
  89                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
  90                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
  91                 params->mpwqe_log_stride_sz = MLX5E_MPWQE_STRIDE_SZ(mdev,
  92                         MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
  93                 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
  94                         params->mpwqe_log_stride_sz;
  95                 break;
  96         default: /* MLX5_WQ_TYPE_LINKED_LIST */
  97                 params->log_rq_size = is_kdump_kernel() ?
  98                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  99                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 100                 params->rq_headroom = params->xdp_prog ?
 101                         XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 102                 params->rq_headroom += NET_IP_ALIGN;
 103
 104                 /* Extra room needed for build_skb */
 105                 params->lro_wqe_sz -= params->rq_headroom +
 106                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 107         }
 108
 109         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 110                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 111                        BIT(params->log_rq_size),
 112                        BIT(params->mpwqe_log_stride_sz),
 113                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 114 }
 115
 116 static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev,
 117                                 struct mlx5e_params *params)
 118 {
 119         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 120                     !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
 121                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 122                     MLX5_WQ_TYPE_LINKED_LIST;
 123         mlx5e_init_rq_type_params(mdev, params, rq_type);
 124 }
 125
 126 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 127 {
 128         struct mlx5_core_dev *mdev = priv->mdev;
 129         u8 port_state;
 130
 131         port_state = mlx5_query_vport_state(mdev,
 132                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
 133                                             0);
 134
 135         if (port_state == VPORT_STATE_UP) {
 136                 netdev_info(priv->netdev, "Link up\n");
 137                 netif_carrier_on(priv->netdev);
 138         } else {
 139                 netdev_info(priv->netdev, "Link down\n");
 140                 netif_carrier_off(priv->netdev);
 141         }
 142 }
 143
 144 static void mlx5e_update_carrier_work(struct work_struct *work)
 145 {
 146         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 147                                                update_carrier_work);
 148
 149         mutex_lock(&priv->state_lock);
 150         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 151                 if (priv->profile->update_carrier)
 152                         priv->profile->update_carrier(priv);
 153         mutex_unlock(&priv->state_lock);
 154 }
 155
 156 static void mlx5e_tx_timeout_work(struct work_struct *work)
 157 {
 158         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 159                                                tx_timeout_work);
 160         int err;
 161
 162         rtnl_lock();
 163         mutex_lock(&priv->state_lock);
 164         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 165                 goto unlock;
 166         mlx5e_close_locked(priv->netdev);
 167         err = mlx5e_open_locked(priv->netdev);
 168         if (err)
 169                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 170                            err);
 171 unlock:
 172         mutex_unlock(&priv->state_lock);
 173         rtnl_unlock();
 174 }
 175
 176 void mlx5e_update_stats(struct mlx5e_priv *priv)
 177 {
 178         int i;
 179
 180         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 181                 if (mlx5e_stats_grps[i].update_stats)
 182                         mlx5e_stats_grps[i].update_stats(priv);
 183 }
 184
 185 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 186 {
 187         int i;
 188
 189         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 190                 if (mlx5e_stats_grps[i].update_stats_mask &
 191                     MLX5E_NDO_UPDATE_STATS)
 192                         mlx5e_stats_grps[i].update_stats(priv);
 193 }
 194
 195 void mlx5e_update_stats_work(struct work_struct *work)
 196 {
 197         struct delayed_work *dwork = to_delayed_work(work);
 198         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 199                                                update_stats_work);
 200         mutex_lock(&priv->state_lock);
 201         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 202                 priv->profile->update_stats(priv);
 203                 queue_delayed_work(priv->wq, dwork,
 204                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 205         }
 206         mutex_unlock(&priv->state_lock);
 207 }
 208
 209 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 210                               enum mlx5_dev_event event, unsigned long param)
 211 {
 212         struct mlx5e_priv *priv = vpriv;
 213
 214         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 215                 return;
 216
 217         switch (event) {
 218         case MLX5_DEV_EVENT_PORT_UP:
 219         case MLX5_DEV_EVENT_PORT_DOWN:
 220                 queue_work(priv->wq, &priv->update_carrier_work);
 221                 break;
 222         default:
 223                 break;
 224         }
 225 }
 226
 227 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 228 {
 229         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 230 }
 231
 232 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 233 {
 234         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 235         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 236 }
 237
 238 static inline int mlx5e_get_wqe_mtt_sz(void)
 239 {
 240         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 241          * To avoid copying garbage after the mtt array, we allocate
 242          * a little more.
 243          */
 244         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 245                      MLX5_UMR_MTT_ALIGNMENT);
 246 }
 247
 248 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 249                                        struct mlx5e_icosq *sq,
 250                                        struct mlx5e_umr_wqe *wqe,
 251                                        u16 ix)
 252 {
 253         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 254         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 255         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 256         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 257         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 258         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 259
 260         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 261                                       ds_cnt);
 262         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 263         cseg->imm       = rq->mkey_be;
 264
 265         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 266         ucseg->xlt_octowords =
 267                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 268         ucseg->bsf_octowords =
 269                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 270         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 271
 272         dseg->lkey = sq->mkey_be;
 273         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 274 }
 275
 276 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 277                                      struct mlx5e_channel *c)
 278 {
 279         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 280         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 281         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
 282         int i;
 283
 284         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 285                                       GFP_KERNEL, cpu_to_node(c->cpu));
 286         if (!rq->mpwqe.info)
 287                 goto err_out;
 288
 289         /* We allocate more than mtt_sz as we will align the pointer */
 290         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
 291                                         cpu_to_node(c->cpu));
 292         if (unlikely(!rq->mpwqe.mtt_no_align))
 293                 goto err_free_wqe_info;
 294
 295         for (i = 0; i < wq_sz; i++) {
 296                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 297
 298                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
 299                                         MLX5_UMR_ALIGN);
 300                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
 301                                                   PCI_DMA_TODEVICE);
 302                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
 303                         goto err_unmap_mtts;
 304
 305                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 306         }
 307
 308         return 0;
 309
 310 err_unmap_mtts:
 311         while (--i >= 0) {
 312                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 313
 314                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
 315                                  PCI_DMA_TODEVICE);
 316         }
 317         kfree(rq->mpwqe.mtt_no_align);
 318 err_free_wqe_info:
 319         kfree(rq->mpwqe.info);
 320
 321 err_out:
 322         return -ENOMEM;
 323 }
 324
 325 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
 326 {
 327         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 328         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 329         int i;
 330
 331         for (i = 0; i < wq_sz; i++) {
 332                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 333
 334                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
 335                                  PCI_DMA_TODEVICE);
 336         }
 337         kfree(rq->mpwqe.mtt_no_align);
 338         kfree(rq->mpwqe.info);
 339 }
 340
 341 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 342                                  u64 npages, u8 page_shift,
 343                                  struct mlx5_core_mkey *umr_mkey)
 344 {
 345         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 346         void *mkc;
 347         u32 *in;
 348         int err;
 349
 350         if (!MLX5E_VALID_NUM_MTTS(npages))
 351                 return -EINVAL;
 352
 353         in = kvzalloc(inlen, GFP_KERNEL);
 354         if (!in)
 355                 return -ENOMEM;
 356
 357         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 358
 359         MLX5_SET(mkc, mkc, free, 1);
 360         MLX5_SET(mkc, mkc, umr_en, 1);
 361         MLX5_SET(mkc, mkc, lw, 1);
 362         MLX5_SET(mkc, mkc, lr, 1);
 363         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
 364
 365         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 366         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 367         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 368         MLX5_SET(mkc, mkc, translations_octword_size,
 369                  MLX5_MTT_OCTW(npages));
 370         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 371
 372         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 373
 374         kvfree(in);
 375         return err;
 376 }
 377
 378 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 379 {
 380         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
 381
 382         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 383 }
 384
 385 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 386                           struct mlx5e_params *params,
 387                           struct mlx5e_rq_param *rqp,
 388                           struct mlx5e_rq *rq)
 389 {
 390         struct mlx5_core_dev *mdev = c->mdev;
 391         void *rqc = rqp->rqc;
 392         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 393         u32 byte_count;
 394         int npages;
 395         int wq_sz;
 396         int err;
 397         int i;
 398
 399         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 400
 401         err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
 402                                 &rq->wq_ctrl);
 403         if (err)
 404                 return err;
 405
 406         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 407
 408         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 409
 410         rq->wq_type = params->rq_wq_type;
 411         rq->pdev    = c->pdev;
 412         rq->netdev  = c->netdev;
 413         rq->tstamp  = c->tstamp;
 414         rq->clock   = &mdev->clock;
 415         rq->channel = c;
 416         rq->ix      = c->ix;
 417         rq->mdev    = mdev;
 418
 419         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 420         if (IS_ERR(rq->xdp_prog)) {
 421                 err = PTR_ERR(rq->xdp_prog);
 422                 rq->xdp_prog = NULL;
 423                 goto err_rq_wq_destroy;
 424         }
 425
 426         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 427         if (err < 0)
 428                 goto err_rq_wq_destroy;
 429
 430         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 431         rq->buff.headroom = params->rq_headroom;
 432
 433         switch (rq->wq_type) {
 434         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 435
 436                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 437                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 438
 439                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 440 #ifdef CONFIG_MLX5_EN_IPSEC
 441                 if (MLX5_IPSEC_DEV(mdev)) {
 442                         err = -EINVAL;
 443                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 444                         goto err_rq_wq_destroy;
 445                 }
 446 #endif
 447                 if (!rq->handle_rx_cqe) {
 448                         err = -EINVAL;
 449                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 450                         goto err_rq_wq_destroy;
 451                 }
 452
 453                 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
 454                 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
 455
 456                 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 457
 458                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 459                 if (err)
 460                         goto err_rq_wq_destroy;
 461                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 462
 463                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 464                 if (err)
 465                         goto err_destroy_umr_mkey;
 466                 break;
 467         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 468                 rq->wqe.frag_info =
 469                         kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
 470                                      GFP_KERNEL, cpu_to_node(c->cpu));
 471                 if (!rq->wqe.frag_info) {
 472                         err = -ENOMEM;
 473                         goto err_rq_wq_destroy;
 474                 }
 475                 rq->post_wqes = mlx5e_post_rx_wqes;
 476                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 477
 478 #ifdef CONFIG_MLX5_EN_IPSEC
 479                 if (c->priv->ipsec)
 480                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 481                 else
 482 #endif
 483                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 484                 if (!rq->handle_rx_cqe) {
 485                         kfree(rq->wqe.frag_info);
 486                         err = -EINVAL;
 487                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 488                         goto err_rq_wq_destroy;
 489                 }
 490
 491                 byte_count = params->lro_en  ?
 492                                 params->lro_wqe_sz :
 493                                 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
 494 #ifdef CONFIG_MLX5_EN_IPSEC
 495                 if (MLX5_IPSEC_DEV(mdev))
 496                         byte_count += MLX5E_METADATA_ETHER_LEN;
 497 #endif
 498                 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
 499
 500                 /* calc the required page order */
 501                 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
 502                 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
 503                 rq->buff.page_order = order_base_2(npages);
 504
 505                 byte_count |= MLX5_HW_START_PADDING;
 506                 rq->mkey_be = c->mkey_be;
 507         }
 508
 509         for (i = 0; i < wq_sz; i++) {
 510                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 511
 512                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 513                         u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
 514
 515                         wqe->data.addr = cpu_to_be64(dma_offset);
 516                 }
 517
 518                 wqe->data.byte_count = cpu_to_be32(byte_count);
 519                 wqe->data.lkey = rq->mkey_be;
 520         }
 521
 522         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 523
 524         switch (params->rx_cq_moderation.cq_period_mode) {
 525         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 526                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 527                 break;
 528         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 529         default:
 530                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 531         }
 532
 533         rq->page_cache.head = 0;
 534         rq->page_cache.tail = 0;
 535
 536         return 0;
 537
 538 err_destroy_umr_mkey:
 539         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 540
 541 err_rq_wq_destroy:
 542         if (rq->xdp_prog)
 543                 bpf_prog_put(rq->xdp_prog);
 544         xdp_rxq_info_unreg(&rq->xdp_rxq);
 545         mlx5_wq_destroy(&rq->wq_ctrl);
 546
 547         return err;
 548 }
 549
 550 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 551 {
 552         int i;
 553
 554         if (rq->xdp_prog)
 555                 bpf_prog_put(rq->xdp_prog);
 556
 557         xdp_rxq_info_unreg(&rq->xdp_rxq);
 558
 559         switch (rq->wq_type) {
 560         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 561                 mlx5e_rq_free_mpwqe_info(rq);
 562                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 563                 break;
 564         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 565                 kfree(rq->wqe.frag_info);
 566         }
 567
 568         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 569              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 570                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 571
 572                 mlx5e_page_release(rq, dma_info, false);
 573         }
 574         mlx5_wq_destroy(&rq->wq_ctrl);
 575 }
 576
 577 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 578                            struct mlx5e_rq_param *param)
 579 {
 580         struct mlx5_core_dev *mdev = rq->mdev;
 581
 582         void *in;
 583         void *rqc;
 584         void *wq;
 585         int inlen;
 586         int err;
 587
 588         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 589                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 590         in = kvzalloc(inlen, GFP_KERNEL);
 591         if (!in)
 592                 return -ENOMEM;
 593
 594         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 595         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 596
 597         memcpy(rqc, param->rqc, sizeof(param->rqc));
 598
 599         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 600         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 601         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 602                                                 MLX5_ADAPTER_PAGE_SHIFT);
 603         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 604
 605         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 606                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 607
 608         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 609
 610         kvfree(in);
 611
 612         return err;
 613 }
 614
 615 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 616                                  int next_state)
 617 {
 618         struct mlx5e_channel *c = rq->channel;
 619         struct mlx5_core_dev *mdev = c->mdev;
 620
 621         void *in;
 622         void *rqc;
 623         int inlen;
 624         int err;
 625
 626         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 627         in = kvzalloc(inlen, GFP_KERNEL);
 628         if (!in)
 629                 return -ENOMEM;
 630
 631         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 632
 633         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 634         MLX5_SET(rqc, rqc, state, next_state);
 635
 636         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 637
 638         kvfree(in);
 639
 640         return err;
 641 }
 642
 643 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 644 {
 645         struct mlx5e_channel *c = rq->channel;
 646         struct mlx5e_priv *priv = c->priv;
 647         struct mlx5_core_dev *mdev = priv->mdev;
 648
 649         void *in;
 650         void *rqc;
 651         int inlen;
 652         int err;
 653
 654         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 655         in = kvzalloc(inlen, GFP_KERNEL);
 656         if (!in)
 657                 return -ENOMEM;
 658
 659         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 660
 661         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 662         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 663                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 664         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 665         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 666
 667         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 668
 669         kvfree(in);
 670
 671         return err;
 672 }
 673
 674 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 675 {
 676         struct mlx5e_channel *c = rq->channel;
 677         struct mlx5_core_dev *mdev = c->mdev;
 678         void *in;
 679         void *rqc;
 680         int inlen;
 681         int err;
 682
 683         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 684         in = kvzalloc(inlen, GFP_KERNEL);
 685         if (!in)
 686                 return -ENOMEM;
 687
 688         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 689
 690         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 691         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 692                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 693         MLX5_SET(rqc, rqc, vsd, vsd);
 694         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 695
 696         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 697
 698         kvfree(in);
 699
 700         return err;
 701 }
 702
 703 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 704 {
 705         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 706 }
 707
 708 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 709 {
 710         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 711         struct mlx5e_channel *c = rq->channel;
 712
 713         struct mlx5_wq_ll *wq = &rq->wq;
 714         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
 715
 716         while (time_before(jiffies, exp_time)) {
 717                 if (wq->cur_sz >= min_wqes)
 718                         return 0;
 719
 720                 msleep(20);
 721         }
 722
 723         netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 724                     rq->rqn, wq->cur_sz, min_wqes);
 725         return -ETIMEDOUT;
 726 }
 727
 728 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 729 {
 730         struct mlx5_wq_ll *wq = &rq->wq;
 731         struct mlx5e_rx_wqe *wqe;
 732         __be16 wqe_ix_be;
 733         u16 wqe_ix;
 734
 735         /* UMR WQE (if in progress) is always at wq->head */
 736         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
 737             rq->mpwqe.umr_in_progress)
 738                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 739
 740         while (!mlx5_wq_ll_is_empty(wq)) {
 741                 wqe_ix_be = *wq->tail_next;
 742                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 743                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 744                 rq->dealloc_wqe(rq, wqe_ix);
 745                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 746                                &wqe->next.next_wqe_index);
 747         }
 748
 749         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
 750                 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
 751                  * but yet to be re-posted.
 752                  */
 753                 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 754
 755                 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
 756                         rq->dealloc_wqe(rq, wqe_ix);
 757         }
 758 }
 759
 760 static int mlx5e_open_rq(struct mlx5e_channel *c,
 761                          struct mlx5e_params *params,
 762                          struct mlx5e_rq_param *param,
 763                          struct mlx5e_rq *rq)
 764 {
 765         int err;
 766
 767         err = mlx5e_alloc_rq(c, params, param, rq);
 768         if (err)
 769                 return err;
 770
 771         err = mlx5e_create_rq(rq, param);
 772         if (err)
 773                 goto err_free_rq;
 774
 775         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 776         if (err)
 777                 goto err_destroy_rq;
 778
 779         if (params->rx_dim_enabled)
 780                 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
 781
 782         return 0;
 783
 784 err_destroy_rq:
 785         mlx5e_destroy_rq(rq);
 786 err_free_rq:
 787         mlx5e_free_rq(rq);
 788
 789         return err;
 790 }
 791
 792 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 793 {
 794         struct mlx5e_icosq *sq = &rq->channel->icosq;
 795         u16 pi = sq->pc & sq->wq.sz_m1;
 796         struct mlx5e_tx_wqe *nopwqe;
 797
 798         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 799         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 800         nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
 801         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 802 }
 803
 804 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 805 {
 806         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 807         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 808 }
 809
 810 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 811 {
 812         cancel_work_sync(&rq->dim.work);
 813         mlx5e_destroy_rq(rq);
 814         mlx5e_free_rx_descs(rq);
 815         mlx5e_free_rq(rq);
 816 }
 817
 818 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 819 {
 820         kfree(sq->db.di);
 821 }
 822
 823 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 824 {
 825         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 826
 827         sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
 828                                      GFP_KERNEL, numa);
 829         if (!sq->db.di) {
 830                 mlx5e_free_xdpsq_db(sq);
 831                 return -ENOMEM;
 832         }
 833
 834         return 0;
 835 }
 836
 837 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 838                              struct mlx5e_params *params,
 839                              struct mlx5e_sq_param *param,
 840                              struct mlx5e_xdpsq *sq)
 841 {
 842         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 843         struct mlx5_core_dev *mdev = c->mdev;
 844         int err;
 845
 846         sq->pdev      = c->pdev;
 847         sq->mkey_be   = c->mkey_be;
 848         sq->channel   = c;
 849         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 850         sq->min_inline_mode = params->tx_min_inline_mode;
 851
 852         param->wq.db_numa_node = cpu_to_node(c->cpu);
 853         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 854         if (err)
 855                 return err;
 856         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 857
 858         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 859         if (err)
 860                 goto err_sq_wq_destroy;
 861
 862         return 0;
 863
 864 err_sq_wq_destroy:
 865         mlx5_wq_destroy(&sq->wq_ctrl);
 866
 867         return err;
 868 }
 869
 870 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
 871 {
 872         mlx5e_free_xdpsq_db(sq);
 873         mlx5_wq_destroy(&sq->wq_ctrl);
 874 }
 875
 876 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
 877 {
 878         kfree(sq->db.ico_wqe);
 879 }
 880
 881 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
 882 {
 883         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 884
 885         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 886                                       GFP_KERNEL, numa);
 887         if (!sq->db.ico_wqe)
 888                 return -ENOMEM;
 889
 890         return 0;
 891 }
 892
 893 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
 894                              struct mlx5e_sq_param *param,
 895                              struct mlx5e_icosq *sq)
 896 {
 897         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 898         struct mlx5_core_dev *mdev = c->mdev;
 899         int err;
 900
 901         sq->mkey_be   = c->mkey_be;
 902         sq->channel   = c;
 903         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 904
 905         param->wq.db_numa_node = cpu_to_node(c->cpu);
 906         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 907         if (err)
 908                 return err;
 909         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 910
 911         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
 912         if (err)
 913                 goto err_sq_wq_destroy;
 914
 915         sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
 916
 917         return 0;
 918
 919 err_sq_wq_destroy:
 920         mlx5_wq_destroy(&sq->wq_ctrl);
 921
 922         return err;
 923 }
 924
 925 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
 926 {
 927         mlx5e_free_icosq_db(sq);
 928         mlx5_wq_destroy(&sq->wq_ctrl);
 929 }
 930
 931 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
 932 {
 933         kfree(sq->db.wqe_info);
 934         kfree(sq->db.dma_fifo);
 935 }
 936
 937 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
 938 {
 939         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 940         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 941
 942         sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
 943                                            GFP_KERNEL, numa);
 944         sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
 945                                            GFP_KERNEL, numa);
 946         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
 947                 mlx5e_free_txqsq_db(sq);
 948                 return -ENOMEM;
 949         }
 950
 951         sq->dma_fifo_mask = df_sz - 1;
 952
 953         return 0;
 954 }
 955
 956 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
 957                              int txq_ix,
 958                              struct mlx5e_params *params,
 959                              struct mlx5e_sq_param *param,
 960                              struct mlx5e_txqsq *sq)
 961 {
 962         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 963         struct mlx5_core_dev *mdev = c->mdev;
 964         int err;
 965
 966         sq->pdev      = c->pdev;
 967         sq->tstamp    = c->tstamp;
 968         sq->clock     = &mdev->clock;
 969         sq->mkey_be   = c->mkey_be;
 970         sq->channel   = c;
 971         sq->txq_ix    = txq_ix;
 972         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 973         sq->max_inline      = params->tx_max_inline;
 974         sq->min_inline_mode = params->tx_min_inline_mode;
 975         if (MLX5_IPSEC_DEV(c->priv->mdev))
 976                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
 977
 978         param->wq.db_numa_node = cpu_to_node(c->cpu);
 979         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 980         if (err)
 981                 return err;
 982         sq->wq.db    = &sq->wq.db[MLX5_SND_DBR];
 983
 984         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
 985         if (err)
 986                 goto err_sq_wq_destroy;
 987
 988         sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 989
 990         return 0;
 991
 992 err_sq_wq_destroy:
 993         mlx5_wq_destroy(&sq->wq_ctrl);
 994
 995         return err;
 996 }
 997
 998 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
 999 {
1000         mlx5e_free_txqsq_db(sq);
1001         mlx5_wq_destroy(&sq->wq_ctrl);
1002 }
1003
1004 struct mlx5e_create_sq_param {
1005         struct mlx5_wq_ctrl        *wq_ctrl;
1006         u32                         cqn;
1007         u32                         tisn;
1008         u8                          tis_lst_sz;
1009         u8                          min_inline_mode;
1010 };
1011
1012 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1013                            struct mlx5e_sq_param *param,
1014                            struct mlx5e_create_sq_param *csp,
1015                            u32 *sqn)
1016 {
1017         void *in;
1018         void *sqc;
1019         void *wq;
1020         int inlen;
1021         int err;
1022
1023         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1024                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1025         in = kvzalloc(inlen, GFP_KERNEL);
1026         if (!in)
1027                 return -ENOMEM;
1028
1029         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1030         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1031
1032         memcpy(sqc, param->sqc, sizeof(param->sqc));
1033         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1034         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1035         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1036
1037         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1038                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1039
1040         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1041
1042         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1043         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1044         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1045                                           MLX5_ADAPTER_PAGE_SHIFT);
1046         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1047
1048         mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1049
1050         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1051
1052         kvfree(in);
1053
1054         return err;
1055 }
1056
1057 struct mlx5e_modify_sq_param {
1058         int curr_state;
1059         int next_state;
1060         bool rl_update;
1061         int rl_index;
1062 };
1063
1064 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1065                            struct mlx5e_modify_sq_param *p)
1066 {
1067         void *in;
1068         void *sqc;
1069         int inlen;
1070         int err;
1071
1072         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1073         in = kvzalloc(inlen, GFP_KERNEL);
1074         if (!in)
1075                 return -ENOMEM;
1076
1077         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1078
1079         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1080         MLX5_SET(sqc, sqc, state, p->next_state);
1081         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1082                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1083                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1084         }
1085
1086         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1087
1088         kvfree(in);
1089
1090         return err;
1091 }
1092
1093 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1094 {
1095         mlx5_core_destroy_sq(mdev, sqn);
1096 }
1097
1098 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1099                                struct mlx5e_sq_param *param,
1100                                struct mlx5e_create_sq_param *csp,
1101                                u32 *sqn)
1102 {
1103         struct mlx5e_modify_sq_param msp = {0};
1104         int err;
1105
1106         err = mlx5e_create_sq(mdev, param, csp, sqn);
1107         if (err)
1108                 return err;
1109
1110         msp.curr_state = MLX5_SQC_STATE_RST;
1111         msp.next_state = MLX5_SQC_STATE_RDY;
1112         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1113         if (err)
1114                 mlx5e_destroy_sq(mdev, *sqn);
1115
1116         return err;
1117 }
1118
1119 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1120                                 struct mlx5e_txqsq *sq, u32 rate);
1121
1122 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1123                             u32 tisn,
1124                             int txq_ix,
1125                             struct mlx5e_params *params,
1126                             struct mlx5e_sq_param *param,
1127                             struct mlx5e_txqsq *sq)
1128 {
1129         struct mlx5e_create_sq_param csp = {};
1130         u32 tx_rate;
1131         int err;
1132
1133         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1134         if (err)
1135                 return err;
1136
1137         csp.tisn            = tisn;
1138         csp.tis_lst_sz      = 1;
1139         csp.cqn             = sq->cq.mcq.cqn;
1140         csp.wq_ctrl         = &sq->wq_ctrl;
1141         csp.min_inline_mode = sq->min_inline_mode;
1142         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1143         if (err)
1144                 goto err_free_txqsq;
1145
1146         tx_rate = c->priv->tx_rates[sq->txq_ix];
1147         if (tx_rate)
1148                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1149
1150         return 0;
1151
1152 err_free_txqsq:
1153         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1154         mlx5e_free_txqsq(sq);
1155
1156         return err;
1157 }
1158
1159 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1160 {
1161         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1162         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1163         netdev_tx_reset_queue(sq->txq);
1164         netif_tx_start_queue(sq->txq);
1165 }
1166
1167 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1168 {
1169         __netif_tx_lock_bh(txq);
1170         netif_tx_stop_queue(txq);
1171         __netif_tx_unlock_bh(txq);
1172 }
1173
1174 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1175 {
1176         struct mlx5e_channel *c = sq->channel;
1177
1178         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1179         /* prevent netif_tx_wake_queue */
1180         napi_synchronize(&c->napi);
1181
1182         netif_tx_disable_queue(sq->txq);
1183
1184         /* last doorbell out, godspeed .. */
1185         if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1186                 struct mlx5e_tx_wqe *nop;
1187
1188                 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1189                 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1190                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1191         }
1192 }
1193
1194 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1195 {
1196         struct mlx5e_channel *c = sq->channel;
1197         struct mlx5_core_dev *mdev = c->mdev;
1198
1199         mlx5e_destroy_sq(mdev, sq->sqn);
1200         if (sq->rate_limit)
1201                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1202         mlx5e_free_txqsq_descs(sq);
1203         mlx5e_free_txqsq(sq);
1204 }
1205
1206 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1207                             struct mlx5e_params *params,
1208                             struct mlx5e_sq_param *param,
1209                             struct mlx5e_icosq *sq)
1210 {
1211         struct mlx5e_create_sq_param csp = {};
1212         int err;
1213
1214         err = mlx5e_alloc_icosq(c, param, sq);
1215         if (err)
1216                 return err;
1217
1218         csp.cqn             = sq->cq.mcq.cqn;
1219         csp.wq_ctrl         = &sq->wq_ctrl;
1220         csp.min_inline_mode = params->tx_min_inline_mode;
1221         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1222         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1223         if (err)
1224                 goto err_free_icosq;
1225
1226         return 0;
1227
1228 err_free_icosq:
1229         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1230         mlx5e_free_icosq(sq);
1231
1232         return err;
1233 }
1234
1235 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1236 {
1237         struct mlx5e_channel *c = sq->channel;
1238
1239         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1240         napi_synchronize(&c->napi);
1241
1242         mlx5e_destroy_sq(c->mdev, sq->sqn);
1243         mlx5e_free_icosq(sq);
1244 }
1245
1246 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1247                             struct mlx5e_params *params,
1248                             struct mlx5e_sq_param *param,
1249                             struct mlx5e_xdpsq *sq)
1250 {
1251         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1252         struct mlx5e_create_sq_param csp = {};
1253         unsigned int inline_hdr_sz = 0;
1254         int err;
1255         int i;
1256
1257         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1258         if (err)
1259                 return err;
1260
1261         csp.tis_lst_sz      = 1;
1262         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1263         csp.cqn             = sq->cq.mcq.cqn;
1264         csp.wq_ctrl         = &sq->wq_ctrl;
1265         csp.min_inline_mode = sq->min_inline_mode;
1266         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1267         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1268         if (err)
1269                 goto err_free_xdpsq;
1270
1271         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1272                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1273                 ds_cnt++;
1274         }
1275
1276         /* Pre initialize fixed WQE fields */
1277         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1278                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1279                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1280                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1281                 struct mlx5_wqe_data_seg *dseg;
1282
1283                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1284                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1285
1286                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1287                 dseg->lkey = sq->mkey_be;
1288         }
1289
1290         return 0;
1291
1292 err_free_xdpsq:
1293         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1294         mlx5e_free_xdpsq(sq);
1295
1296         return err;
1297 }
1298
1299 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1300 {
1301         struct mlx5e_channel *c = sq->channel;
1302
1303         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1304         napi_synchronize(&c->napi);
1305
1306         mlx5e_destroy_sq(c->mdev, sq->sqn);
1307         mlx5e_free_xdpsq_descs(sq);
1308         mlx5e_free_xdpsq(sq);
1309 }
1310
1311 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1312                                  struct mlx5e_cq_param *param,
1313                                  struct mlx5e_cq *cq)
1314 {
1315         struct mlx5_core_cq *mcq = &cq->mcq;
1316         int eqn_not_used;
1317         unsigned int irqn;
1318         int err;
1319         u32 i;
1320
1321         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1322                                &cq->wq_ctrl);
1323         if (err)
1324                 return err;
1325
1326         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1327
1328         mcq->cqe_sz     = 64;
1329         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1330         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1331         *mcq->set_ci_db = 0;
1332         *mcq->arm_db    = 0;
1333         mcq->vector     = param->eq_ix;
1334         mcq->comp       = mlx5e_completion_event;
1335         mcq->event      = mlx5e_cq_error_event;
1336         mcq->irqn       = irqn;
1337
1338         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1339                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1340
1341                 cqe->op_own = 0xf1;
1342         }
1343
1344         cq->mdev = mdev;
1345
1346         return 0;
1347 }
1348
1349 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1350                           struct mlx5e_cq_param *param,
1351                           struct mlx5e_cq *cq)
1352 {
1353         struct mlx5_core_dev *mdev = c->priv->mdev;
1354         int err;
1355
1356         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1357         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1358         param->eq_ix   = c->ix;
1359
1360         err = mlx5e_alloc_cq_common(mdev, param, cq);
1361
1362         cq->napi    = &c->napi;
1363         cq->channel = c;
1364
1365         return err;
1366 }
1367
1368 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1369 {
1370         mlx5_cqwq_destroy(&cq->wq_ctrl);
1371 }
1372
1373 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1374 {
1375         struct mlx5_core_dev *mdev = cq->mdev;
1376         struct mlx5_core_cq *mcq = &cq->mcq;
1377
1378         void *in;
1379         void *cqc;
1380         int inlen;
1381         unsigned int irqn_not_used;
1382         int eqn;
1383         int err;
1384
1385         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1386                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1387         in = kvzalloc(inlen, GFP_KERNEL);
1388         if (!in)
1389                 return -ENOMEM;
1390
1391         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1392
1393         memcpy(cqc, param->cqc, sizeof(param->cqc));
1394
1395         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1396                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1397
1398         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1399
1400         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1401         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1402         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1403         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1404                                             MLX5_ADAPTER_PAGE_SHIFT);
1405         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1406
1407         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1408
1409         kvfree(in);
1410
1411         if (err)
1412                 return err;
1413
1414         mlx5e_cq_arm(cq);
1415
1416         return 0;
1417 }
1418
1419 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1420 {
1421         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1422 }
1423
1424 static int mlx5e_open_cq(struct mlx5e_channel *c,
1425                          struct net_dim_cq_moder moder,
1426                          struct mlx5e_cq_param *param,
1427                          struct mlx5e_cq *cq)
1428 {
1429         struct mlx5_core_dev *mdev = c->mdev;
1430         int err;
1431
1432         err = mlx5e_alloc_cq(c, param, cq);
1433         if (err)
1434                 return err;
1435
1436         err = mlx5e_create_cq(cq, param);
1437         if (err)
1438                 goto err_free_cq;
1439
1440         if (MLX5_CAP_GEN(mdev, cq_moderation))
1441                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1442         return 0;
1443
1444 err_free_cq:
1445         mlx5e_free_cq(cq);
1446
1447         return err;
1448 }
1449
1450 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1451 {
1452         mlx5e_destroy_cq(cq);
1453         mlx5e_free_cq(cq);
1454 }
1455
1456 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1457 {
1458         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1459 }
1460
1461 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1462                              struct mlx5e_params *params,
1463                              struct mlx5e_channel_param *cparam)
1464 {
1465         int err;
1466         int tc;
1467
1468         for (tc = 0; tc < c->num_tc; tc++) {
1469                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1470                                     &cparam->tx_cq, &c->sq[tc].cq);
1471                 if (err)
1472                         goto err_close_tx_cqs;
1473         }
1474
1475         return 0;
1476
1477 err_close_tx_cqs:
1478         for (tc--; tc >= 0; tc--)
1479                 mlx5e_close_cq(&c->sq[tc].cq);
1480
1481         return err;
1482 }
1483
1484 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1485 {
1486         int tc;
1487
1488         for (tc = 0; tc < c->num_tc; tc++)
1489                 mlx5e_close_cq(&c->sq[tc].cq);
1490 }
1491
1492 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1493                           struct mlx5e_params *params,
1494                           struct mlx5e_channel_param *cparam)
1495 {
1496         int err;
1497         int tc;
1498
1499         for (tc = 0; tc < params->num_tc; tc++) {
1500                 int txq_ix = c->ix + tc * params->num_channels;
1501
1502                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1503                                        params, &cparam->sq, &c->sq[tc]);
1504                 if (err)
1505                         goto err_close_sqs;
1506         }
1507
1508         return 0;
1509
1510 err_close_sqs:
1511         for (tc--; tc >= 0; tc--)
1512                 mlx5e_close_txqsq(&c->sq[tc]);
1513
1514         return err;
1515 }
1516
1517 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1518 {
1519         int tc;
1520
1521         for (tc = 0; tc < c->num_tc; tc++)
1522                 mlx5e_close_txqsq(&c->sq[tc]);
1523 }
1524
1525 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1526                                 struct mlx5e_txqsq *sq, u32 rate)
1527 {
1528         struct mlx5e_priv *priv = netdev_priv(dev);
1529         struct mlx5_core_dev *mdev = priv->mdev;
1530         struct mlx5e_modify_sq_param msp = {0};
1531         u16 rl_index = 0;
1532         int err;
1533
1534         if (rate == sq->rate_limit)
1535                 /* nothing to do */
1536                 return 0;
1537
1538         if (sq->rate_limit)
1539                 /* remove current rl index to free space to next ones */
1540                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1541
1542         sq->rate_limit = 0;
1543
1544         if (rate) {
1545                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1546                 if (err) {
1547                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1548                                    rate, err);
1549                         return err;
1550                 }
1551         }
1552
1553         msp.curr_state = MLX5_SQC_STATE_RDY;
1554         msp.next_state = MLX5_SQC_STATE_RDY;
1555         msp.rl_index   = rl_index;
1556         msp.rl_update  = true;
1557         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1558         if (err) {
1559                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1560                            rate, err);
1561                 /* remove the rate from the table */
1562                 if (rate)
1563                         mlx5_rl_remove_rate(mdev, rate);
1564                 return err;
1565         }
1566
1567         sq->rate_limit = rate;
1568         return 0;
1569 }
1570
1571 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1572 {
1573         struct mlx5e_priv *priv = netdev_priv(dev);
1574         struct mlx5_core_dev *mdev = priv->mdev;
1575         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1576         int err = 0;
1577
1578         if (!mlx5_rl_is_supported(mdev)) {
1579                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1580                 return -EINVAL;
1581         }
1582
1583         /* rate is given in Mb/sec, HW config is in Kb/sec */
1584         rate = rate << 10;
1585
1586         /* Check whether rate in valid range, 0 is always valid */
1587         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1588                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1589                 return -ERANGE;
1590         }
1591
1592         mutex_lock(&priv->state_lock);
1593         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1594                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1595         if (!err)
1596                 priv->tx_rates[index] = rate;
1597         mutex_unlock(&priv->state_lock);
1598
1599         return err;
1600 }
1601
1602 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1603                               struct mlx5e_params *params,
1604                               struct mlx5e_channel_param *cparam,
1605                               struct mlx5e_channel **cp)
1606 {
1607         struct net_dim_cq_moder icocq_moder = {0, 0};
1608         struct net_device *netdev = priv->netdev;
1609         int cpu = mlx5e_get_cpu(priv, ix);
1610         struct mlx5e_channel *c;
1611         unsigned int irq;
1612         int err;
1613         int eqn;
1614
1615         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1616         if (!c)
1617                 return -ENOMEM;
1618
1619         c->priv     = priv;
1620         c->mdev     = priv->mdev;
1621         c->tstamp   = &priv->tstamp;
1622         c->ix       = ix;
1623         c->cpu      = cpu;
1624         c->pdev     = &priv->mdev->pdev->dev;
1625         c->netdev   = priv->netdev;
1626         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1627         c->num_tc   = params->num_tc;
1628         c->xdp      = !!params->xdp_prog;
1629
1630         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1631         c->irq_desc = irq_to_desc(irq);
1632
1633         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1634
1635         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1636         if (err)
1637                 goto err_napi_del;
1638
1639         err = mlx5e_open_tx_cqs(c, params, cparam);
1640         if (err)
1641                 goto err_close_icosq_cq;
1642
1643         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1644         if (err)
1645                 goto err_close_tx_cqs;
1646
1647         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1648         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1649                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1650         if (err)
1651                 goto err_close_rx_cq;
1652
1653         napi_enable(&c->napi);
1654
1655         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1656         if (err)
1657                 goto err_disable_napi;
1658
1659         err = mlx5e_open_sqs(c, params, cparam);
1660         if (err)
1661                 goto err_close_icosq;
1662
1663         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1664         if (err)
1665                 goto err_close_sqs;
1666
1667         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1668         if (err)
1669                 goto err_close_xdp_sq;
1670
1671         *cp = c;
1672
1673         return 0;
1674 err_close_xdp_sq:
1675         if (c->xdp)
1676                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1677
1678 err_close_sqs:
1679         mlx5e_close_sqs(c);
1680
1681 err_close_icosq:
1682         mlx5e_close_icosq(&c->icosq);
1683
1684 err_disable_napi:
1685         napi_disable(&c->napi);
1686         if (c->xdp)
1687                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1688
1689 err_close_rx_cq:
1690         mlx5e_close_cq(&c->rq.cq);
1691
1692 err_close_tx_cqs:
1693         mlx5e_close_tx_cqs(c);
1694
1695 err_close_icosq_cq:
1696         mlx5e_close_cq(&c->icosq.cq);
1697
1698 err_napi_del:
1699         netif_napi_del(&c->napi);
1700         kfree(c);
1701
1702         return err;
1703 }
1704
1705 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1706 {
1707         int tc;
1708
1709         for (tc = 0; tc < c->num_tc; tc++)
1710                 mlx5e_activate_txqsq(&c->sq[tc]);
1711         mlx5e_activate_rq(&c->rq);
1712         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1713 }
1714
1715 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1716 {
1717         int tc;
1718
1719         mlx5e_deactivate_rq(&c->rq);
1720         for (tc = 0; tc < c->num_tc; tc++)
1721                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1722 }
1723
1724 static void mlx5e_close_channel(struct mlx5e_channel *c)
1725 {
1726         mlx5e_close_rq(&c->rq);
1727         if (c->xdp)
1728                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1729         mlx5e_close_sqs(c);
1730         mlx5e_close_icosq(&c->icosq);
1731         napi_disable(&c->napi);
1732         if (c->xdp)
1733                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1734         mlx5e_close_cq(&c->rq.cq);
1735         mlx5e_close_tx_cqs(c);
1736         mlx5e_close_cq(&c->icosq.cq);
1737         netif_napi_del(&c->napi);
1738
1739         kfree(c);
1740 }
1741
1742 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1743                                  struct mlx5e_params *params,
1744                                  struct mlx5e_rq_param *param)
1745 {
1746         void *rqc = param->rqc;
1747         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1748
1749         switch (params->rq_wq_type) {
1750         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1751                 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1752                 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
1753                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1754                 break;
1755         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1756                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1757         }
1758
1759         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1760         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1761         MLX5_SET(wq, wq, log_wq_sz,        params->log_rq_size);
1762         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1763         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1764         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
1765         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
1766
1767         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1768         param->wq.linear = 1;
1769 }
1770
1771 static void mlx5e_build_drop_rq_param(struct mlx5_core_dev *mdev,
1772                                       struct mlx5e_rq_param *param)
1773 {
1774         void *rqc = param->rqc;
1775         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1776
1777         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1778         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1779
1780         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1781 }
1782
1783 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1784                                         struct mlx5e_sq_param *param)
1785 {
1786         void *sqc = param->sqc;
1787         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1788
1789         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1790         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1791
1792         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1793 }
1794
1795 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1796                                  struct mlx5e_params *params,
1797                                  struct mlx5e_sq_param *param)
1798 {
1799         void *sqc = param->sqc;
1800         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1801
1802         mlx5e_build_sq_param_common(priv, param);
1803         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1804         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1805 }
1806
1807 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1808                                         struct mlx5e_cq_param *param)
1809 {
1810         void *cqc = param->cqc;
1811
1812         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1813 }
1814
1815 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1816                                     struct mlx5e_params *params,
1817                                     struct mlx5e_cq_param *param)
1818 {
1819         void *cqc = param->cqc;
1820         u8 log_cq_size;
1821
1822         switch (params->rq_wq_type) {
1823         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1824                 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
1825                 break;
1826         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1827                 log_cq_size = params->log_rq_size;
1828         }
1829
1830         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1831         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1832                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1833                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1834         }
1835
1836         mlx5e_build_common_cq_param(priv, param);
1837         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
1838 }
1839
1840 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1841                                     struct mlx5e_params *params,
1842                                     struct mlx5e_cq_param *param)
1843 {
1844         void *cqc = param->cqc;
1845
1846         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1847
1848         mlx5e_build_common_cq_param(priv, param);
1849         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
1850 }
1851
1852 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1853                                      u8 log_wq_size,
1854                                      struct mlx5e_cq_param *param)
1855 {
1856         void *cqc = param->cqc;
1857
1858         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1859
1860         mlx5e_build_common_cq_param(priv, param);
1861
1862         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1863 }
1864
1865 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1866                                     u8 log_wq_size,
1867                                     struct mlx5e_sq_param *param)
1868 {
1869         void *sqc = param->sqc;
1870         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1871
1872         mlx5e_build_sq_param_common(priv, param);
1873
1874         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1875         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1876 }
1877
1878 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1879                                     struct mlx5e_params *params,
1880                                     struct mlx5e_sq_param *param)
1881 {
1882         void *sqc = param->sqc;
1883         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1884
1885         mlx5e_build_sq_param_common(priv, param);
1886         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1887 }
1888
1889 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1890                                       struct mlx5e_params *params,
1891                                       struct mlx5e_channel_param *cparam)
1892 {
1893         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1894
1895         mlx5e_build_rq_param(priv, params, &cparam->rq);
1896         mlx5e_build_sq_param(priv, params, &cparam->sq);
1897         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
1898         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
1899         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
1900         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
1901         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
1902 }
1903
1904 int mlx5e_open_channels(struct mlx5e_priv *priv,
1905                         struct mlx5e_channels *chs)
1906 {
1907         struct mlx5e_channel_param *cparam;
1908         int err = -ENOMEM;
1909         int i;
1910
1911         chs->num = chs->params.num_channels;
1912
1913         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
1914         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1915         if (!chs->c || !cparam)
1916                 goto err_free;
1917
1918         mlx5e_build_channel_param(priv, &chs->params, cparam);
1919         for (i = 0; i < chs->num; i++) {
1920                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
1921                 if (err)
1922                         goto err_close_channels;
1923         }
1924
1925         kfree(cparam);
1926         return 0;
1927
1928 err_close_channels:
1929         for (i--; i >= 0; i--)
1930                 mlx5e_close_channel(chs->c[i]);
1931
1932 err_free:
1933         kfree(chs->c);
1934         kfree(cparam);
1935         chs->num = 0;
1936         return err;
1937 }
1938
1939 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
1940 {
1941         int i;
1942
1943         for (i = 0; i < chs->num; i++)
1944                 mlx5e_activate_channel(chs->c[i]);
1945 }
1946
1947 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
1948 {
1949         int err = 0;
1950         int i;
1951
1952         for (i = 0; i < chs->num; i++) {
1953                 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
1954                 if (err)
1955                         break;
1956         }
1957
1958         return err;
1959 }
1960
1961 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
1962 {
1963         int i;
1964
1965         for (i = 0; i < chs->num; i++)
1966                 mlx5e_deactivate_channel(chs->c[i]);
1967 }
1968
1969 void mlx5e_close_channels(struct mlx5e_channels *chs)
1970 {
1971         int i;
1972
1973         for (i = 0; i < chs->num; i++)
1974                 mlx5e_close_channel(chs->c[i]);
1975
1976         kfree(chs->c);
1977         chs->num = 0;
1978 }
1979
1980 static int
1981 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
1982 {
1983         struct mlx5_core_dev *mdev = priv->mdev;
1984         void *rqtc;
1985         int inlen;
1986         int err;
1987         u32 *in;
1988         int i;
1989
1990         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1991         in = kvzalloc(inlen, GFP_KERNEL);
1992         if (!in)
1993                 return -ENOMEM;
1994
1995         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1996
1997         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1998         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1999
2000         for (i = 0; i < sz; i++)
2001                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2002
2003         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2004         if (!err)
2005                 rqt->enabled = true;
2006
2007         kvfree(in);
2008         return err;
2009 }
2010
2011 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2012 {
2013         rqt->enabled = false;
2014         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2015 }
2016
2017 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2018 {
2019         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2020         int err;
2021
2022         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2023         if (err)
2024                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2025         return err;
2026 }
2027
2028 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2029 {
2030         struct mlx5e_rqt *rqt;
2031         int err;
2032         int ix;
2033
2034         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2035                 rqt = &priv->direct_tir[ix].rqt;
2036                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2037                 if (err)
2038                         goto err_destroy_rqts;
2039         }
2040
2041         return 0;
2042
2043 err_destroy_rqts:
2044         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2045         for (ix--; ix >= 0; ix--)
2046                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2047
2048         return err;
2049 }
2050
2051 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2052 {
2053         int i;
2054
2055         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2056                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2057 }
2058
2059 static int mlx5e_rx_hash_fn(int hfunc)
2060 {
2061         return (hfunc == ETH_RSS_HASH_TOP) ?
2062                MLX5_RX_HASH_FN_TOEPLITZ :
2063                MLX5_RX_HASH_FN_INVERTED_XOR8;
2064 }
2065
2066 int mlx5e_bits_invert(unsigned long a, int size)
2067 {
2068         int inv = 0;
2069         int i;
2070
2071         for (i = 0; i < size; i++)
2072                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2073
2074         return inv;
2075 }
2076
2077 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2078                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2079 {
2080         int i;
2081
2082         for (i = 0; i < sz; i++) {
2083                 u32 rqn;
2084
2085                 if (rrp.is_rss) {
2086                         int ix = i;
2087
2088                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2089                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2090
2091                         ix = priv->channels.params.indirection_rqt[ix];
2092                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2093                 } else {
2094                         rqn = rrp.rqn;
2095                 }
2096                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2097         }
2098 }
2099
2100 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2101                        struct mlx5e_redirect_rqt_param rrp)
2102 {
2103         struct mlx5_core_dev *mdev = priv->mdev;
2104         void *rqtc;
2105         int inlen;
2106         u32 *in;
2107         int err;
2108
2109         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2110         in = kvzalloc(inlen, GFP_KERNEL);
2111         if (!in)
2112                 return -ENOMEM;
2113
2114         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2115
2116         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2117         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2118         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2119         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2120
2121         kvfree(in);
2122         return err;
2123 }
2124
2125 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2126                                 struct mlx5e_redirect_rqt_param rrp)
2127 {
2128         if (!rrp.is_rss)
2129                 return rrp.rqn;
2130
2131         if (ix >= rrp.rss.channels->num)
2132                 return priv->drop_rq.rqn;
2133
2134         return rrp.rss.channels->c[ix]->rq.rqn;
2135 }
2136
2137 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2138                                 struct mlx5e_redirect_rqt_param rrp)
2139 {
2140         u32 rqtn;
2141         int ix;
2142
2143         if (priv->indir_rqt.enabled) {
2144                 /* RSS RQ table */
2145                 rqtn = priv->indir_rqt.rqtn;
2146                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2147         }
2148
2149         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2150                 struct mlx5e_redirect_rqt_param direct_rrp = {
2151                         .is_rss = false,
2152                         {
2153                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2154                         },
2155                 };
2156
2157                 /* Direct RQ Tables */
2158                 if (!priv->direct_tir[ix].rqt.enabled)
2159                         continue;
2160
2161                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2162                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2163         }
2164 }
2165
2166 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2167                                             struct mlx5e_channels *chs)
2168 {
2169         struct mlx5e_redirect_rqt_param rrp = {
2170                 .is_rss        = true,
2171                 {
2172                         .rss = {
2173                                 .channels  = chs,
2174                                 .hfunc     = chs->params.rss_hfunc,
2175                         }
2176                 },
2177         };
2178
2179         mlx5e_redirect_rqts(priv, rrp);
2180 }
2181
2182 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2183 {
2184         struct mlx5e_redirect_rqt_param drop_rrp = {
2185                 .is_rss = false,
2186                 {
2187                         .rqn = priv->drop_rq.rqn,
2188                 },
2189         };
2190
2191         mlx5e_redirect_rqts(priv, drop_rrp);
2192 }
2193
2194 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2195 {
2196         if (!params->lro_en)
2197                 return;
2198
2199 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2200
2201         MLX5_SET(tirc, tirc, lro_enable_mask,
2202                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2203                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2204         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2205                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2206         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2207 }
2208
2209 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2210                                     enum mlx5e_traffic_types tt,
2211                                     void *tirc, bool inner)
2212 {
2213         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2214                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2215
2216 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2217                                  MLX5_HASH_FIELD_SEL_DST_IP)
2218
2219 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2220                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2221                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2222                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2223
2224 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2225                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2226                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2227
2228         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2229         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2230                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2231                                              rx_hash_toeplitz_key);
2232                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2233                                                rx_hash_toeplitz_key);
2234
2235                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2236                 memcpy(rss_key, params->toeplitz_hash_key, len);
2237         }
2238
2239         switch (tt) {
2240         case MLX5E_TT_IPV4_TCP:
2241                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2242                          MLX5_L3_PROT_TYPE_IPV4);
2243                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2244                          MLX5_L4_PROT_TYPE_TCP);
2245                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2246                          MLX5_HASH_IP_L4PORTS);
2247                 break;
2248
2249         case MLX5E_TT_IPV6_TCP:
2250                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2251                          MLX5_L3_PROT_TYPE_IPV6);
2252                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2253                          MLX5_L4_PROT_TYPE_TCP);
2254                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2255                          MLX5_HASH_IP_L4PORTS);
2256                 break;
2257
2258         case MLX5E_TT_IPV4_UDP:
2259                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2260                          MLX5_L3_PROT_TYPE_IPV4);
2261                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2262                          MLX5_L4_PROT_TYPE_UDP);
2263                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2264                          MLX5_HASH_IP_L4PORTS);
2265                 break;
2266
2267         case MLX5E_TT_IPV6_UDP:
2268                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2269                          MLX5_L3_PROT_TYPE_IPV6);
2270                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2271                          MLX5_L4_PROT_TYPE_UDP);
2272                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2273                          MLX5_HASH_IP_L4PORTS);
2274                 break;
2275
2276         case MLX5E_TT_IPV4_IPSEC_AH:
2277                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2278                          MLX5_L3_PROT_TYPE_IPV4);
2279                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2280                          MLX5_HASH_IP_IPSEC_SPI);
2281                 break;
2282
2283         case MLX5E_TT_IPV6_IPSEC_AH:
2284                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2285                          MLX5_L3_PROT_TYPE_IPV6);
2286                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2287                          MLX5_HASH_IP_IPSEC_SPI);
2288                 break;
2289
2290         case MLX5E_TT_IPV4_IPSEC_ESP:
2291                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2292                          MLX5_L3_PROT_TYPE_IPV4);
2293                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2294                          MLX5_HASH_IP_IPSEC_SPI);
2295                 break;
2296
2297         case MLX5E_TT_IPV6_IPSEC_ESP:
2298                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2299                          MLX5_L3_PROT_TYPE_IPV6);
2300                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2301                          MLX5_HASH_IP_IPSEC_SPI);
2302                 break;
2303
2304         case MLX5E_TT_IPV4:
2305                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2306                          MLX5_L3_PROT_TYPE_IPV4);
2307                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2308                          MLX5_HASH_IP);
2309                 break;
2310
2311         case MLX5E_TT_IPV6:
2312                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2313                          MLX5_L3_PROT_TYPE_IPV6);
2314                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2315                          MLX5_HASH_IP);
2316                 break;
2317         default:
2318                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2319         }
2320 }
2321
2322 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2323 {
2324         struct mlx5_core_dev *mdev = priv->mdev;
2325
2326         void *in;
2327         void *tirc;
2328         int inlen;
2329         int err;
2330         int tt;
2331         int ix;
2332
2333         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2334         in = kvzalloc(inlen, GFP_KERNEL);
2335         if (!in)
2336                 return -ENOMEM;
2337
2338         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2339         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2340
2341         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2342
2343         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2344                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2345                                            inlen);
2346                 if (err)
2347                         goto free_in;
2348         }
2349
2350         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2351                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2352                                            in, inlen);
2353                 if (err)
2354                         goto free_in;
2355         }
2356
2357 free_in:
2358         kvfree(in);
2359
2360         return err;
2361 }
2362
2363 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2364                                             enum mlx5e_traffic_types tt,
2365                                             u32 *tirc)
2366 {
2367         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2368
2369         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2370
2371         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2372         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2373         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2374
2375         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2376 }
2377
2378 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2379 {
2380         struct mlx5_core_dev *mdev = priv->mdev;
2381         u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
2382         int err;
2383
2384         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2385         if (err)
2386                 return err;
2387
2388         /* Update vport context MTU */
2389         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2390         return 0;
2391 }
2392
2393 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2394 {
2395         struct mlx5_core_dev *mdev = priv->mdev;
2396         u16 hw_mtu = 0;
2397         int err;
2398
2399         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2400         if (err || !hw_mtu) /* fallback to port oper mtu */
2401                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2402
2403         *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
2404 }
2405
2406 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2407 {
2408         struct net_device *netdev = priv->netdev;
2409         u16 mtu;
2410         int err;
2411
2412         err = mlx5e_set_mtu(priv, netdev->mtu);
2413         if (err)
2414                 return err;
2415
2416         mlx5e_query_mtu(priv, &mtu);
2417         if (mtu != netdev->mtu)
2418                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2419                             __func__, mtu, netdev->mtu);
2420
2421         netdev->mtu = mtu;
2422         return 0;
2423 }
2424
2425 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2426 {
2427         struct mlx5e_priv *priv = netdev_priv(netdev);
2428         int nch = priv->channels.params.num_channels;
2429         int ntc = priv->channels.params.num_tc;
2430         int tc;
2431
2432         netdev_reset_tc(netdev);
2433
2434         if (ntc == 1)
2435                 return;
2436
2437         netdev_set_num_tc(netdev, ntc);
2438
2439         /* Map netdev TCs to offset 0
2440          * We have our own UP to TXQ mapping for QoS
2441          */
2442         for (tc = 0; tc < ntc; tc++)
2443                 netdev_set_tc_queue(netdev, tc, nch, 0);
2444 }
2445
2446 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2447 {
2448         struct mlx5e_channel *c;
2449         struct mlx5e_txqsq *sq;
2450         int i, tc;
2451
2452         for (i = 0; i < priv->channels.num; i++)
2453                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2454                         priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2455
2456         for (i = 0; i < priv->channels.num; i++) {
2457                 c = priv->channels.c[i];
2458                 for (tc = 0; tc < c->num_tc; tc++) {
2459                         sq = &c->sq[tc];
2460                         priv->txq2sq[sq->txq_ix] = sq;
2461                 }
2462         }
2463 }
2464
2465 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2466 {
2467         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2468         struct net_device *netdev = priv->netdev;
2469
2470         mlx5e_netdev_set_tcs(netdev);
2471         netif_set_real_num_tx_queues(netdev, num_txqs);
2472         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2473
2474         mlx5e_build_channels_tx_maps(priv);
2475         mlx5e_activate_channels(&priv->channels);
2476         netif_tx_start_all_queues(priv->netdev);
2477
2478         if (MLX5_VPORT_MANAGER(priv->mdev))
2479                 mlx5e_add_sqs_fwd_rules(priv);
2480
2481         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2482         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2483 }
2484
2485 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2486 {
2487         mlx5e_redirect_rqts_to_drop(priv);
2488
2489         if (MLX5_VPORT_MANAGER(priv->mdev))
2490                 mlx5e_remove_sqs_fwd_rules(priv);
2491
2492         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2493          * polling for inactive tx queues.
2494          */
2495         netif_tx_stop_all_queues(priv->netdev);
2496         netif_tx_disable(priv->netdev);
2497         mlx5e_deactivate_channels(&priv->channels);
2498 }
2499
2500 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2501                                 struct mlx5e_channels *new_chs,
2502                                 mlx5e_fp_hw_modify hw_modify)
2503 {
2504         struct net_device *netdev = priv->netdev;
2505         int new_num_txqs;
2506         int carrier_ok;
2507         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2508
2509         carrier_ok = netif_carrier_ok(netdev);
2510         netif_carrier_off(netdev);
2511
2512         if (new_num_txqs < netdev->real_num_tx_queues)
2513                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2514
2515         mlx5e_deactivate_priv_channels(priv);
2516         mlx5e_close_channels(&priv->channels);
2517
2518         priv->channels = *new_chs;
2519
2520         /* New channels are ready to roll, modify HW settings if needed */
2521         if (hw_modify)
2522                 hw_modify(priv);
2523
2524         mlx5e_refresh_tirs(priv, false);
2525         mlx5e_activate_priv_channels(priv);
2526
2527         /* return carrier back if needed */
2528         if (carrier_ok)
2529                 netif_carrier_on(netdev);
2530 }
2531
2532 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2533 {
2534         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2535         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2536 }
2537
2538 int mlx5e_open_locked(struct net_device *netdev)
2539 {
2540         struct mlx5e_priv *priv = netdev_priv(netdev);
2541         int err;
2542
2543         set_bit(MLX5E_STATE_OPENED, &priv->state);
2544
2545         err = mlx5e_open_channels(priv, &priv->channels);
2546         if (err)
2547                 goto err_clear_state_opened_flag;
2548
2549         mlx5e_refresh_tirs(priv, false);
2550         mlx5e_activate_priv_channels(priv);
2551         if (priv->profile->update_carrier)
2552                 priv->profile->update_carrier(priv);
2553
2554         if (priv->profile->update_stats)
2555                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2556
2557         return 0;
2558
2559 err_clear_state_opened_flag:
2560         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2561         return err;
2562 }
2563
2564 int mlx5e_open(struct net_device *netdev)
2565 {
2566         struct mlx5e_priv *priv = netdev_priv(netdev);
2567         int err;
2568
2569         mutex_lock(&priv->state_lock);
2570         err = mlx5e_open_locked(netdev);
2571         if (!err)
2572                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2573         mutex_unlock(&priv->state_lock);
2574
2575         if (mlx5e_vxlan_allowed(priv->mdev))
2576                 udp_tunnel_get_rx_info(netdev);
2577
2578         return err;
2579 }
2580
2581 int mlx5e_close_locked(struct net_device *netdev)
2582 {
2583         struct mlx5e_priv *priv = netdev_priv(netdev);
2584
2585         /* May already be CLOSED in case a previous configuration operation
2586          * (e.g RX/TX queue size change) that involves close&open failed.
2587          */
2588         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2589                 return 0;
2590
2591         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2592
2593         netif_carrier_off(priv->netdev);
2594         mlx5e_deactivate_priv_channels(priv);
2595         mlx5e_close_channels(&priv->channels);
2596
2597         return 0;
2598 }
2599
2600 int mlx5e_close(struct net_device *netdev)
2601 {
2602         struct mlx5e_priv *priv = netdev_priv(netdev);
2603         int err;
2604
2605         if (!netif_device_present(netdev))
2606                 return -ENODEV;
2607
2608         mutex_lock(&priv->state_lock);
2609         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2610         err = mlx5e_close_locked(netdev);
2611         mutex_unlock(&priv->state_lock);
2612
2613         return err;
2614 }
2615
2616 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2617                                struct mlx5e_rq *rq,
2618                                struct mlx5e_rq_param *param)
2619 {
2620         void *rqc = param->rqc;
2621         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2622         int err;
2623
2624         param->wq.db_numa_node = param->wq.buf_numa_node;
2625
2626         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2627                                 &rq->wq_ctrl);
2628         if (err)
2629                 return err;
2630
2631         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2632         xdp_rxq_info_unused(&rq->xdp_rxq);
2633
2634         rq->mdev = mdev;
2635
2636         return 0;
2637 }
2638
2639 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2640                                struct mlx5e_cq *cq,
2641                                struct mlx5e_cq_param *param)
2642 {
2643         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2644         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
2645
2646         return mlx5e_alloc_cq_common(mdev, param, cq);
2647 }
2648
2649 static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2650                               struct mlx5e_rq *drop_rq)
2651 {
2652         struct mlx5e_cq_param cq_param = {};
2653         struct mlx5e_rq_param rq_param = {};
2654         struct mlx5e_cq *cq = &drop_rq->cq;
2655         int err;
2656
2657         mlx5e_build_drop_rq_param(mdev, &rq_param);
2658
2659         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2660         if (err)
2661                 return err;
2662
2663         err = mlx5e_create_cq(cq, &cq_param);
2664         if (err)
2665                 goto err_free_cq;
2666
2667         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2668         if (err)
2669                 goto err_destroy_cq;
2670
2671         err = mlx5e_create_rq(drop_rq, &rq_param);
2672         if (err)
2673                 goto err_free_rq;
2674
2675         return 0;
2676
2677 err_free_rq:
2678         mlx5e_free_rq(drop_rq);
2679
2680 err_destroy_cq:
2681         mlx5e_destroy_cq(cq);
2682
2683 err_free_cq:
2684         mlx5e_free_cq(cq);
2685
2686         return err;
2687 }
2688
2689 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2690 {
2691         mlx5e_destroy_rq(drop_rq);
2692         mlx5e_free_rq(drop_rq);
2693         mlx5e_destroy_cq(&drop_rq->cq);
2694         mlx5e_free_cq(&drop_rq->cq);
2695 }
2696
2697 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2698                      u32 underlay_qpn, u32 *tisn)
2699 {
2700         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2701         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2702
2703         MLX5_SET(tisc, tisc, prio, tc << 1);
2704         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2705         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2706
2707         if (mlx5_lag_is_lacp_owner(mdev))
2708                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2709
2710         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2711 }
2712
2713 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2714 {
2715         mlx5_core_destroy_tis(mdev, tisn);
2716 }
2717
2718 int mlx5e_create_tises(struct mlx5e_priv *priv)
2719 {
2720         int err;
2721         int tc;
2722
2723         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2724                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2725                 if (err)
2726                         goto err_close_tises;
2727         }
2728
2729         return 0;
2730
2731 err_close_tises:
2732         for (tc--; tc >= 0; tc--)
2733                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2734
2735         return err;
2736 }
2737
2738 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2739 {
2740         int tc;
2741
2742         for (tc = 0; tc < priv->profile->max_tc; tc++)
2743                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2744 }
2745
2746 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2747                                       enum mlx5e_traffic_types tt,
2748                                       u32 *tirc)
2749 {
2750         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2751
2752         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2753
2754         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2755         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2756         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2757 }
2758
2759 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2760 {
2761         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2762
2763         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2764
2765         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2766         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2767         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2768 }
2769
2770 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2771 {
2772         struct mlx5e_tir *tir;
2773         void *tirc;
2774         int inlen;
2775         int i = 0;
2776         int err;
2777         u32 *in;
2778         int tt;
2779
2780         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2781         in = kvzalloc(inlen, GFP_KERNEL);
2782         if (!in)
2783                 return -ENOMEM;
2784
2785         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2786                 memset(in, 0, inlen);
2787                 tir = &priv->indir_tir[tt];
2788                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2789                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2790                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2791                 if (err) {
2792                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2793                         goto err_destroy_inner_tirs;
2794                 }
2795         }
2796
2797         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2798                 goto out;
2799
2800         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2801                 memset(in, 0, inlen);
2802                 tir = &priv->inner_indir_tir[i];
2803                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2804                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2805                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2806                 if (err) {
2807                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2808                         goto err_destroy_inner_tirs;
2809                 }
2810         }
2811
2812 out:
2813         kvfree(in);
2814
2815         return 0;
2816
2817 err_destroy_inner_tirs:
2818         for (i--; i >= 0; i--)
2819                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2820
2821         for (tt--; tt >= 0; tt--)
2822                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2823
2824         kvfree(in);
2825
2826         return err;
2827 }
2828
2829 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2830 {
2831         int nch = priv->profile->max_nch(priv->mdev);
2832         struct mlx5e_tir *tir;
2833         void *tirc;
2834         int inlen;
2835         int err;
2836         u32 *in;
2837         int ix;
2838
2839         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2840         in = kvzalloc(inlen, GFP_KERNEL);
2841         if (!in)
2842                 return -ENOMEM;
2843
2844         for (ix = 0; ix < nch; ix++) {
2845                 memset(in, 0, inlen);
2846                 tir = &priv->direct_tir[ix];
2847                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2848                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2849                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2850                 if (err)
2851                         goto err_destroy_ch_tirs;
2852         }
2853
2854         kvfree(in);
2855
2856         return 0;
2857
2858 err_destroy_ch_tirs:
2859         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
2860         for (ix--; ix >= 0; ix--)
2861                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2862
2863         kvfree(in);
2864
2865         return err;
2866 }
2867
2868 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2869 {
2870         int i;
2871
2872         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2873                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2874
2875         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2876                 return;
2877
2878         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2879                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2880 }
2881
2882 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2883 {
2884         int nch = priv->profile->max_nch(priv->mdev);
2885         int i;
2886
2887         for (i = 0; i < nch; i++)
2888                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2889 }
2890
2891 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2892 {
2893         int err = 0;
2894         int i;
2895
2896         for (i = 0; i < chs->num; i++) {
2897                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2898                 if (err)
2899                         return err;
2900         }
2901
2902         return 0;
2903 }
2904
2905 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
2906 {
2907         int err = 0;
2908         int i;
2909
2910         for (i = 0; i < chs->num; i++) {
2911                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
2912                 if (err)
2913                         return err;
2914         }
2915
2916         return 0;
2917 }
2918
2919 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
2920                                  struct tc_mqprio_qopt *mqprio)
2921 {
2922         struct mlx5e_priv *priv = netdev_priv(netdev);
2923         struct mlx5e_channels new_channels = {};
2924         u8 tc = mqprio->num_tc;
2925         int err = 0;
2926
2927         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2928
2929         if (tc && tc != MLX5E_MAX_NUM_TC)
2930                 return -EINVAL;
2931
2932         mutex_lock(&priv->state_lock);
2933
2934         new_channels.params = priv->channels.params;
2935         new_channels.params.num_tc = tc ? tc : 1;
2936
2937         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
2938                 priv->channels.params = new_channels.params;
2939                 goto out;
2940         }
2941
2942         err = mlx5e_open_channels(priv, &new_channels);
2943         if (err)
2944                 goto out;
2945
2946         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
2947 out:
2948         mutex_unlock(&priv->state_lock);
2949         return err;
2950 }
2951
2952 #ifdef CONFIG_MLX5_ESWITCH
2953 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
2954                                      struct tc_cls_flower_offload *cls_flower)
2955 {
2956         switch (cls_flower->command) {
2957         case TC_CLSFLOWER_REPLACE:
2958                 return mlx5e_configure_flower(priv, cls_flower);
2959         case TC_CLSFLOWER_DESTROY:
2960                 return mlx5e_delete_flower(priv, cls_flower);
2961         case TC_CLSFLOWER_STATS:
2962                 return mlx5e_stats_flower(priv, cls_flower);
2963         default:
2964                 return -EOPNOTSUPP;
2965         }
2966 }
2967
2968 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2969                             void *cb_priv)
2970 {
2971         struct mlx5e_priv *priv = cb_priv;
2972
2973         if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2974                 return -EOPNOTSUPP;
2975
2976         switch (type) {
2977         case TC_SETUP_CLSFLOWER:
2978                 return mlx5e_setup_tc_cls_flower(priv, type_data);
2979         default:
2980                 return -EOPNOTSUPP;
2981         }
2982 }
2983
2984 static int mlx5e_setup_tc_block(struct net_device *dev,
2985                                 struct tc_block_offload *f)
2986 {
2987         struct mlx5e_priv *priv = netdev_priv(dev);
2988
2989         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
2990                 return -EOPNOTSUPP;
2991
2992         switch (f->command) {
2993         case TC_BLOCK_BIND:
2994                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
2995                                              priv, priv);
2996         case TC_BLOCK_UNBIND:
2997                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
2998                                         priv);
2999                 return 0;
3000         default:
3001                 return -EOPNOTSUPP;
3002         }
3003 }
3004 #endif
3005
3006 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3007                           void *type_data)
3008 {
3009         switch (type) {
3010 #ifdef CONFIG_MLX5_ESWITCH
3011         case TC_SETUP_BLOCK:
3012                 return mlx5e_setup_tc_block(dev, type_data);
3013 #endif
3014         case TC_SETUP_QDISC_MQPRIO:
3015                 return mlx5e_setup_tc_mqprio(dev, type_data);
3016         default:
3017                 return -EOPNOTSUPP;
3018         }
3019 }
3020
3021 static void
3022 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3023 {
3024         struct mlx5e_priv *priv = netdev_priv(dev);
3025         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3026         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3027         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3028
3029         if (mlx5e_is_uplink_rep(priv)) {
3030                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3031                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3032                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3033                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3034         } else {
3035                 stats->rx_packets = sstats->rx_packets;
3036                 stats->rx_bytes   = sstats->rx_bytes;
3037                 stats->tx_packets = sstats->tx_packets;
3038                 stats->tx_bytes   = sstats->tx_bytes;
3039                 stats->tx_dropped = sstats->tx_queue_dropped;
3040         }
3041
3042         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3043
3044         stats->rx_length_errors =
3045                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3046                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3047                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3048         stats->rx_crc_errors =
3049                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3050         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3051         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3052         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3053                            stats->rx_frame_errors;
3054         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3055
3056         /* vport multicast also counts packets that are dropped due to steering
3057          * or rx out of buffer
3058          */
3059         stats->multicast =
3060                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3061 }
3062
3063 static void mlx5e_set_rx_mode(struct net_device *dev)
3064 {
3065         struct mlx5e_priv *priv = netdev_priv(dev);
3066
3067         queue_work(priv->wq, &priv->set_rx_mode_work);
3068 }
3069
3070 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3071 {
3072         struct mlx5e_priv *priv = netdev_priv(netdev);
3073         struct sockaddr *saddr = addr;
3074
3075         if (!is_valid_ether_addr(saddr->sa_data))
3076                 return -EADDRNOTAVAIL;
3077
3078         netif_addr_lock_bh(netdev);
3079         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3080         netif_addr_unlock_bh(netdev);
3081
3082         queue_work(priv->wq, &priv->set_rx_mode_work);
3083
3084         return 0;
3085 }
3086
3087 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3088         do {                                            \
3089                 if (enable)                             \
3090                         *features |= feature;           \
3091                 else                                    \
3092                         *features &= ~feature;          \
3093         } while (0)
3094
3095 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3096
3097 static int set_feature_lro(struct net_device *netdev, bool enable)
3098 {
3099         struct mlx5e_priv *priv = netdev_priv(netdev);
3100         struct mlx5e_channels new_channels = {};
3101         int err = 0;
3102         bool reset;
3103
3104         mutex_lock(&priv->state_lock);
3105
3106         reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3107         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3108
3109         new_channels.params = priv->channels.params;
3110         new_channels.params.lro_en = enable;
3111
3112         if (!reset) {
3113                 priv->channels.params = new_channels.params;
3114                 err = mlx5e_modify_tirs_lro(priv);
3115                 goto out;
3116         }
3117
3118         err = mlx5e_open_channels(priv, &new_channels);
3119         if (err)
3120                 goto out;
3121
3122         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3123 out:
3124         mutex_unlock(&priv->state_lock);
3125         return err;
3126 }
3127
3128 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3129 {
3130         struct mlx5e_priv *priv = netdev_priv(netdev);
3131
3132         if (enable)
3133                 mlx5e_enable_cvlan_filter(priv);
3134         else
3135                 mlx5e_disable_cvlan_filter(priv);
3136
3137         return 0;
3138 }
3139
3140 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3141 {
3142         struct mlx5e_priv *priv = netdev_priv(netdev);
3143
3144         if (!enable && mlx5e_tc_num_filters(priv)) {
3145                 netdev_err(netdev,
3146                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3147                 return -EINVAL;
3148         }
3149
3150         return 0;
3151 }
3152
3153 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3154 {
3155         struct mlx5e_priv *priv = netdev_priv(netdev);
3156         struct mlx5_core_dev *mdev = priv->mdev;
3157
3158         return mlx5_set_port_fcs(mdev, !enable);
3159 }
3160
3161 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3162 {
3163         struct mlx5e_priv *priv = netdev_priv(netdev);
3164         int err;
3165
3166         mutex_lock(&priv->state_lock);
3167
3168         priv->channels.params.scatter_fcs_en = enable;
3169         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3170         if (err)
3171                 priv->channels.params.scatter_fcs_en = !enable;
3172
3173         mutex_unlock(&priv->state_lock);
3174
3175         return err;
3176 }
3177
3178 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3179 {
3180         struct mlx5e_priv *priv = netdev_priv(netdev);
3181         int err = 0;
3182
3183         mutex_lock(&priv->state_lock);
3184
3185         priv->channels.params.vlan_strip_disable = !enable;
3186         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3187                 goto unlock;
3188
3189         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3190         if (err)
3191                 priv->channels.params.vlan_strip_disable = enable;
3192
3193 unlock:
3194         mutex_unlock(&priv->state_lock);
3195
3196         return err;
3197 }
3198
3199 #ifdef CONFIG_RFS_ACCEL
3200 static int set_feature_arfs(struct net_device *netdev, bool enable)
3201 {
3202         struct mlx5e_priv *priv = netdev_priv(netdev);
3203         int err;
3204
3205         if (enable)
3206                 err = mlx5e_arfs_enable(priv);
3207         else
3208                 err = mlx5e_arfs_disable(priv);
3209
3210         return err;
3211 }
3212 #endif
3213
3214 static int mlx5e_handle_feature(struct net_device *netdev,
3215                                 netdev_features_t *features,
3216                                 netdev_features_t wanted_features,
3217                                 netdev_features_t feature,
3218                                 mlx5e_feature_handler feature_handler)
3219 {
3220         netdev_features_t changes = wanted_features ^ netdev->features;
3221         bool enable = !!(wanted_features & feature);
3222         int err;
3223
3224         if (!(changes & feature))
3225                 return 0;
3226
3227         err = feature_handler(netdev, enable);
3228         if (err) {
3229                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3230                            enable ? "Enable" : "Disable", &feature, err);
3231                 return err;
3232         }
3233
3234         MLX5E_SET_FEATURE(features, feature, enable);
3235         return 0;
3236 }
3237
3238 static int mlx5e_set_features(struct net_device *netdev,
3239                               netdev_features_t features)
3240 {
3241         netdev_features_t oper_features = netdev->features;
3242         int err;
3243
3244         err  = mlx5e_handle_feature(netdev, &oper_features, features,
3245                                     NETIF_F_LRO, set_feature_lro);
3246         err |= mlx5e_handle_feature(netdev, &oper_features, features,
3247                                     NETIF_F_HW_VLAN_CTAG_FILTER,
3248                                     set_feature_cvlan_filter);
3249         err |= mlx5e_handle_feature(netdev, &oper_features, features,
3250                                     NETIF_F_HW_TC, set_feature_tc_num_filters);
3251         err |= mlx5e_handle_feature(netdev, &oper_features, features,
3252                                     NETIF_F_RXALL, set_feature_rx_all);
3253         err |= mlx5e_handle_feature(netdev, &oper_features, features,
3254                                     NETIF_F_RXFCS, set_feature_rx_fcs);
3255         err |= mlx5e_handle_feature(netdev, &oper_features, features,
3256                                     NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3257 #ifdef CONFIG_RFS_ACCEL
3258         err |= mlx5e_handle_feature(netdev, &oper_features, features,
3259                                     NETIF_F_NTUPLE, set_feature_arfs);
3260 #endif
3261
3262         if (err) {
3263                 netdev->features = oper_features;
3264                 return -EINVAL;
3265         }
3266
3267         return 0;
3268 }
3269
3270 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3271                                             netdev_features_t features)
3272 {
3273         struct mlx5e_priv *priv = netdev_priv(netdev);
3274
3275         mutex_lock(&priv->state_lock);
3276         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3277                 /* HW strips the outer C-tag header, this is a problem
3278                  * for S-tag traffic.
3279                  */
3280                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3281                 if (!priv->channels.params.vlan_strip_disable)
3282                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3283         }
3284         mutex_unlock(&priv->state_lock);
3285
3286         return features;
3287 }
3288
3289 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3290 {
3291         struct mlx5e_priv *priv = netdev_priv(netdev);
3292         struct mlx5e_channels new_channels = {};
3293         int curr_mtu;
3294         int err = 0;
3295         bool reset;
3296
3297         mutex_lock(&priv->state_lock);
3298
3299         reset = !priv->channels.params.lro_en &&
3300                 (priv->channels.params.rq_wq_type !=
3301                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3302
3303         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3304
3305         curr_mtu    = netdev->mtu;
3306         netdev->mtu = new_mtu;
3307
3308         if (!reset) {
3309                 mlx5e_set_dev_port_mtu(priv);
3310                 goto out;
3311         }
3312
3313         new_channels.params = priv->channels.params;
3314         err = mlx5e_open_channels(priv, &new_channels);
3315         if (err) {
3316                 netdev->mtu = curr_mtu;
3317                 goto out;
3318         }
3319
3320         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3321
3322 out:
3323         mutex_unlock(&priv->state_lock);
3324         return err;
3325 }
3326
3327 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3328 {
3329         struct hwtstamp_config config;
3330         int err;
3331
3332         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3333                 return -EOPNOTSUPP;
3334
3335         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3336                 return -EFAULT;
3337
3338         /* TX HW timestamp */
3339         switch (config.tx_type) {
3340         case HWTSTAMP_TX_OFF:
3341         case HWTSTAMP_TX_ON:
3342                 break;
3343         default:
3344                 return -ERANGE;
3345         }
3346
3347         mutex_lock(&priv->state_lock);
3348         /* RX HW timestamp */
3349         switch (config.rx_filter) {
3350         case HWTSTAMP_FILTER_NONE:
3351                 /* Reset CQE compression to Admin default */
3352                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3353                 break;
3354         case HWTSTAMP_FILTER_ALL:
3355         case HWTSTAMP_FILTER_SOME:
3356         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3357         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3358         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3359         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3360         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3361         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3362         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3363         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3364         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3365         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3366         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3367         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3368         case HWTSTAMP_FILTER_NTP_ALL:
3369                 /* Disable CQE compression */
3370                 netdev_warn(priv->netdev, "Disabling cqe compression");
3371                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3372                 if (err) {
3373                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3374                         mutex_unlock(&priv->state_lock);
3375                         return err;
3376                 }
3377                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3378                 break;
3379         default:
3380                 mutex_unlock(&priv->state_lock);
3381                 return -ERANGE;
3382         }
3383
3384         memcpy(&priv->tstamp, &config, sizeof(config));
3385         mutex_unlock(&priv->state_lock);
3386
3387         return copy_to_user(ifr->ifr_data, &config,
3388                             sizeof(config)) ? -EFAULT : 0;
3389 }
3390
3391 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3392 {
3393         struct hwtstamp_config *cfg = &priv->tstamp;
3394
3395         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3396                 return -EOPNOTSUPP;
3397
3398         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3399 }
3400
3401 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3402 {
3403         struct mlx5e_priv *priv = netdev_priv(dev);
3404
3405         switch (cmd) {
3406         case SIOCSHWTSTAMP:
3407                 return mlx5e_hwstamp_set(priv, ifr);
3408         case SIOCGHWTSTAMP:
3409                 return mlx5e_hwstamp_get(priv, ifr);
3410         default:
3411                 return -EOPNOTSUPP;
3412         }
3413 }
3414
3415 #ifdef CONFIG_MLX5_ESWITCH
3416 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3417 {
3418         struct mlx5e_priv *priv = netdev_priv(dev);
3419         struct mlx5_core_dev *mdev = priv->mdev;
3420
3421         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3422 }
3423
3424 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3425                              __be16 vlan_proto)
3426 {
3427         struct mlx5e_priv *priv = netdev_priv(dev);
3428         struct mlx5_core_dev *mdev = priv->mdev;
3429
3430         if (vlan_proto != htons(ETH_P_8021Q))
3431                 return -EPROTONOSUPPORT;
3432
3433         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3434                                            vlan, qos);
3435 }
3436
3437 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3438 {
3439         struct mlx5e_priv *priv = netdev_priv(dev);
3440         struct mlx5_core_dev *mdev = priv->mdev;
3441
3442         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3443 }
3444
3445 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3446 {
3447         struct mlx5e_priv *priv = netdev_priv(dev);
3448         struct mlx5_core_dev *mdev = priv->mdev;
3449
3450         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3451 }
3452
3453 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3454                              int max_tx_rate)
3455 {
3456         struct mlx5e_priv *priv = netdev_priv(dev);
3457         struct mlx5_core_dev *mdev = priv->mdev;
3458
3459         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3460                                            max_tx_rate, min_tx_rate);
3461 }
3462
3463 static int mlx5_vport_link2ifla(u8 esw_link)
3464 {
3465         switch (esw_link) {
3466         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3467                 return IFLA_VF_LINK_STATE_DISABLE;
3468         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3469                 return IFLA_VF_LINK_STATE_ENABLE;
3470         }
3471         return IFLA_VF_LINK_STATE_AUTO;
3472 }
3473
3474 static int mlx5_ifla_link2vport(u8 ifla_link)
3475 {
3476         switch (ifla_link) {
3477         case IFLA_VF_LINK_STATE_DISABLE:
3478                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3479         case IFLA_VF_LINK_STATE_ENABLE:
3480                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3481         }
3482         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3483 }
3484
3485 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3486                                    int link_state)
3487 {
3488         struct mlx5e_priv *priv = netdev_priv(dev);
3489         struct mlx5_core_dev *mdev = priv->mdev;
3490
3491         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3492                                             mlx5_ifla_link2vport(link_state));
3493 }
3494
3495 static int mlx5e_get_vf_config(struct net_device *dev,
3496                                int vf, struct ifla_vf_info *ivi)
3497 {
3498         struct mlx5e_priv *priv = netdev_priv(dev);
3499         struct mlx5_core_dev *mdev = priv->mdev;
3500         int err;
3501
3502         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3503         if (err)
3504                 return err;
3505         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3506         return 0;
3507 }
3508
3509 static int mlx5e_get_vf_stats(struct net_device *dev,
3510                               int vf, struct ifla_vf_stats *vf_stats)
3511 {
3512         struct mlx5e_priv *priv = netdev_priv(dev);
3513         struct mlx5_core_dev *mdev = priv->mdev;
3514
3515         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3516                                             vf_stats);
3517 }
3518 #endif
3519
3520 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3521                                  struct udp_tunnel_info *ti)
3522 {
3523         struct mlx5e_priv *priv = netdev_priv(netdev);
3524
3525         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3526                 return;
3527
3528         if (!mlx5e_vxlan_allowed(priv->mdev))
3529                 return;
3530
3531         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3532 }
3533
3534 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3535                                  struct udp_tunnel_info *ti)
3536 {
3537         struct mlx5e_priv *priv = netdev_priv(netdev);
3538
3539         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3540                 return;
3541
3542         if (!mlx5e_vxlan_allowed(priv->mdev))
3543                 return;
3544
3545         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3546 }
3547
3548 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3549                                                      struct sk_buff *skb,
3550                                                      netdev_features_t features)
3551 {
3552         unsigned int offset = 0;
3553         struct udphdr *udph;
3554         u8 proto;
3555         u16 port;
3556
3557         switch (vlan_get_protocol(skb)) {
3558         case htons(ETH_P_IP):
3559                 proto = ip_hdr(skb)->protocol;
3560                 break;
3561         case htons(ETH_P_IPV6):
3562                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3563                 break;
3564         default:
3565                 goto out;
3566         }
3567
3568         switch (proto) {
3569         case IPPROTO_GRE:
3570                 return features;
3571         case IPPROTO_UDP:
3572                 udph = udp_hdr(skb);
3573                 port = be16_to_cpu(udph->dest);
3574
3575                 /* Verify if UDP port is being offloaded by HW */
3576                 if (mlx5e_vxlan_lookup_port(priv, port))
3577                         return features;
3578         }
3579
3580 out:
3581         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3582         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3583 }
3584
3585 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3586                                               struct net_device *netdev,
3587                                               netdev_features_t features)
3588 {
3589         struct mlx5e_priv *priv = netdev_priv(netdev);
3590
3591         features = vlan_features_check(skb, features);
3592         features = vxlan_features_check(skb, features);
3593
3594 #ifdef CONFIG_MLX5_EN_IPSEC
3595         if (mlx5e_ipsec_feature_check(skb, netdev, features))
3596                 return features;
3597 #endif
3598
3599         /* Validate if the tunneled packet is being offloaded by HW */
3600         if (skb->encapsulation &&
3601             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3602                 return mlx5e_tunnel_features_check(priv, skb, features);
3603
3604         return features;
3605 }
3606
3607 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
3608                                         struct mlx5e_txqsq *sq)
3609 {
3610         struct mlx5e_priv *priv = netdev_priv(dev);
3611         struct mlx5_core_dev *mdev = priv->mdev;
3612         int irqn_not_used, eqn;
3613         struct mlx5_eq *eq;
3614         u32 eqe_count;
3615
3616         if (mlx5_vector2eqn(mdev, sq->cq.mcq.vector, &eqn, &irqn_not_used))
3617                 return false;
3618
3619         eq = mlx5_eqn2eq(mdev, eqn);
3620         if (IS_ERR(eq))
3621                 return false;
3622
3623         netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
3624                    eqn, eq->cons_index, eq->irqn);
3625
3626         eqe_count = mlx5_eq_poll_irq_disabled(eq);
3627         if (!eqe_count)
3628                 return false;
3629
3630         netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
3631         sq->channel->stats.eq_rearm++;
3632         return true;
3633 }
3634
3635 static void mlx5e_tx_timeout(struct net_device *dev)
3636 {
3637         struct mlx5e_priv *priv = netdev_priv(dev);
3638         bool reopen_channels = false;
3639         int i;
3640
3641         netdev_err(dev, "TX timeout detected\n");
3642
3643         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3644                 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
3645                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3646
3647                 if (!netif_xmit_stopped(dev_queue))
3648                         continue;
3649                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
3650                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
3651                            jiffies_to_usecs(jiffies - dev_queue->trans_start));
3652
3653                 /* If we recover a lost interrupt, most likely TX timeout will
3654                  * be resolved, skip reopening channels
3655                  */
3656                 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
3657                         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3658                         reopen_channels = true;
3659                 }
3660         }
3661
3662         if (reopen_channels && test_bit(MLX5E_STATE_OPENED, &priv->state))
3663                 schedule_work(&priv->tx_timeout_work);
3664 }
3665
3666 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3667 {
3668         struct mlx5e_priv *priv = netdev_priv(netdev);
3669         struct bpf_prog *old_prog;
3670         int err = 0;
3671         bool reset, was_opened;
3672         int i;
3673
3674         mutex_lock(&priv->state_lock);
3675
3676         if ((netdev->features & NETIF_F_LRO) && prog) {
3677                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3678                 err = -EINVAL;
3679                 goto unlock;
3680         }
3681
3682         if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3683                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3684                 err = -EINVAL;
3685                 goto unlock;
3686         }
3687
3688         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3689         /* no need for full reset when exchanging programs */
3690         reset = (!priv->channels.params.xdp_prog || !prog);
3691
3692         if (was_opened && reset)
3693                 mlx5e_close_locked(netdev);
3694         if (was_opened && !reset) {
3695                 /* num_channels is invariant here, so we can take the
3696                  * batched reference right upfront.
3697                  */
3698                 prog = bpf_prog_add(prog, priv->channels.num);
3699                 if (IS_ERR(prog)) {
3700                         err = PTR_ERR(prog);
3701                         goto unlock;
3702                 }
3703         }
3704
3705         /* exchange programs, extra prog reference we got from caller
3706          * as long as we don't fail from this point onwards.
3707          */
3708         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3709         if (old_prog)
3710                 bpf_prog_put(old_prog);
3711
3712         if (reset) /* change RQ type according to priv->xdp_prog */
3713                 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
3714
3715         if (was_opened && reset)
3716                 mlx5e_open_locked(netdev);
3717
3718         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3719                 goto unlock;
3720
3721         /* exchanging programs w/o reset, we update ref counts on behalf
3722          * of the channels RQs here.
3723          */
3724         for (i = 0; i < priv->channels.num; i++) {
3725                 struct mlx5e_channel *c = priv->channels.c[i];
3726
3727                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3728                 napi_synchronize(&c->napi);
3729                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3730
3731                 old_prog = xchg(&c->rq.xdp_prog, prog);
3732
3733                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3734                 /* napi_schedule in case we have missed anything */
3735                 napi_schedule(&c->napi);
3736
3737                 if (old_prog)
3738                         bpf_prog_put(old_prog);
3739         }
3740
3741 unlock:
3742         mutex_unlock(&priv->state_lock);
3743         return err;
3744 }
3745
3746 static u32 mlx5e_xdp_query(struct net_device *dev)
3747 {
3748         struct mlx5e_priv *priv = netdev_priv(dev);
3749         const struct bpf_prog *xdp_prog;
3750         u32 prog_id = 0;
3751
3752         mutex_lock(&priv->state_lock);
3753         xdp_prog = priv->channels.params.xdp_prog;
3754         if (xdp_prog)
3755                 prog_id = xdp_prog->aux->id;
3756         mutex_unlock(&priv->state_lock);
3757
3758         return prog_id;
3759 }
3760
3761 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3762 {
3763         switch (xdp->command) {
3764         case XDP_SETUP_PROG:
3765                 return mlx5e_xdp_set(dev, xdp->prog);
3766         case XDP_QUERY_PROG:
3767                 xdp->prog_id = mlx5e_xdp_query(dev);
3768                 xdp->prog_attached = !!xdp->prog_id;
3769                 return 0;
3770         default:
3771                 return -EINVAL;
3772         }
3773 }
3774
3775 #ifdef CONFIG_NET_POLL_CONTROLLER
3776 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3777  * reenabling interrupts.
3778  */
3779 static void mlx5e_netpoll(struct net_device *dev)
3780 {
3781         struct mlx5e_priv *priv = netdev_priv(dev);
3782         struct mlx5e_channels *chs = &priv->channels;
3783
3784         int i;
3785
3786         for (i = 0; i < chs->num; i++)
3787                 napi_schedule(&chs->c[i]->napi);
3788 }
3789 #endif
3790
3791 static const struct net_device_ops mlx5e_netdev_ops = {
3792         .ndo_open                = mlx5e_open,
3793         .ndo_stop                = mlx5e_close,
3794         .ndo_start_xmit          = mlx5e_xmit,
3795         .ndo_setup_tc            = mlx5e_setup_tc,
3796         .ndo_select_queue        = mlx5e_select_queue,
3797         .ndo_get_stats64         = mlx5e_get_stats,
3798         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3799         .ndo_set_mac_address     = mlx5e_set_mac,
3800         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3801         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3802         .ndo_set_features        = mlx5e_set_features,
3803         .ndo_fix_features        = mlx5e_fix_features,
3804         .ndo_change_mtu          = mlx5e_change_mtu,
3805         .ndo_do_ioctl            = mlx5e_ioctl,
3806         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3807         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
3808         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
3809         .ndo_features_check      = mlx5e_features_check,
3810 #ifdef CONFIG_RFS_ACCEL
3811         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3812 #endif
3813         .ndo_tx_timeout          = mlx5e_tx_timeout,
3814         .ndo_bpf                 = mlx5e_xdp,
3815 #ifdef CONFIG_NET_POLL_CONTROLLER
3816         .ndo_poll_controller     = mlx5e_netpoll,
3817 #endif
3818 #ifdef CONFIG_MLX5_ESWITCH
3819         /* SRIOV E-Switch NDOs */
3820         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
3821         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
3822         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
3823         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
3824         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
3825         .ndo_get_vf_config       = mlx5e_get_vf_config,
3826         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
3827         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
3828         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
3829         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
3830 #endif
3831 };
3832
3833 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3834 {
3835         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3836                 return -EOPNOTSUPP;
3837         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3838             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3839             !MLX5_CAP_ETH(mdev, csum_cap) ||
3840             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3841             !MLX5_CAP_ETH(mdev, vlan_cap) ||
3842             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3843             MLX5_CAP_FLOWTABLE(mdev,
3844                                flow_table_properties_nic_receive.max_ft_level)
3845                                < 3) {
3846                 mlx5_core_warn(mdev,
3847                                "Not creating net device, some required device capabilities are missing\n");
3848                 return -EOPNOTSUPP;
3849         }
3850         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3851                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3852         if (!MLX5_CAP_GEN(mdev, cq_moderation))
3853                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
3854
3855         return 0;
3856 }
3857
3858 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3859 {
3860         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3861
3862         return bf_buf_size -
3863                sizeof(struct mlx5e_tx_wqe) +
3864                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3865 }
3866
3867 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
3868                                    int num_channels)
3869 {
3870         int i;
3871
3872         for (i = 0; i < len; i++)
3873                 indirection_rqt[i] = i % num_channels;
3874 }
3875
3876 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3877 {
3878         enum pcie_link_width width;
3879         enum pci_bus_speed speed;
3880         int err = 0;
3881
3882         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3883         if (err)
3884                 return err;
3885
3886         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3887                 return -EINVAL;
3888
3889         switch (speed) {
3890         case PCIE_SPEED_2_5GT:
3891                 *pci_bw = 2500 * width;
3892                 break;
3893         case PCIE_SPEED_5_0GT:
3894                 *pci_bw = 5000 * width;
3895                 break;
3896         case PCIE_SPEED_8_0GT:
3897                 *pci_bw = 8000 * width;
3898                 break;
3899         default:
3900                 return -EINVAL;
3901         }
3902
3903         return 0;
3904 }
3905
3906 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3907 {
3908         return (link_speed && pci_bw &&
3909                 (pci_bw < 40000) && (pci_bw < link_speed));
3910 }
3911
3912 static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
3913 {
3914         return !(link_speed && pci_bw &&
3915                  (pci_bw <= 16000) && (pci_bw < link_speed));
3916 }
3917
3918 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3919 {
3920         params->tx_cq_moderation.cq_period_mode = cq_period_mode;
3921
3922         params->tx_cq_moderation.pkts =
3923                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3924         params->tx_cq_moderation.usec =
3925                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3926
3927         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3928                 params->tx_cq_moderation.usec =
3929                         MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
3930
3931         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
3932                         params->tx_cq_moderation.cq_period_mode ==
3933                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3934 }
3935
3936 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3937 {
3938         params->rx_cq_moderation.cq_period_mode = cq_period_mode;
3939
3940         params->rx_cq_moderation.pkts =
3941                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3942         params->rx_cq_moderation.usec =
3943                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3944
3945         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3946                 params->rx_cq_moderation.usec =
3947                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3948
3949         if (params->rx_dim_enabled) {
3950                 switch (cq_period_mode) {
3951                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
3952                         params->rx_cq_moderation =
3953                                 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE);
3954                         break;
3955                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
3956                 default:
3957                         params->rx_cq_moderation =
3958                                 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE);
3959                 }
3960         }
3961
3962         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3963                         params->rx_cq_moderation.cq_period_mode ==
3964                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3965 }
3966
3967 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3968 {
3969         int i;
3970
3971         /* The supported periods are organized in ascending order */
3972         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3973                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3974                         break;
3975
3976         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3977 }
3978
3979 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3980                             struct mlx5e_params *params,
3981                             u16 max_channels)
3982 {
3983         u8 cq_period_mode = 0;
3984         u32 link_speed = 0;
3985         u32 pci_bw = 0;
3986
3987         params->num_channels = max_channels;
3988         params->num_tc       = 1;
3989
3990         mlx5e_get_max_linkspeed(mdev, &link_speed);
3991         mlx5e_get_pci_bw(mdev, &pci_bw);
3992         mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3993                       link_speed, pci_bw);
3994
3995         /* SQ */
3996         params->log_sq_size = is_kdump_kernel() ?
3997                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3998                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3999
4000         /* set CQE compression */
4001         params->rx_cqe_compress_def = false;
4002         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4003             MLX5_CAP_GEN(mdev, vport_group_manager))
4004                 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
4005
4006         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4007
4008         /* RQ */
4009         mlx5e_set_rq_params(mdev, params);
4010
4011         /* HW LRO */
4012
4013         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4014         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4015                 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
4016         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4017
4018         /* CQ moderation params */
4019         cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4020                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4021                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4022         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4023         mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
4024         mlx5e_set_tx_cq_mode_params(params, cq_period_mode);
4025
4026         /* TX inline */
4027         params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
4028         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4029
4030         /* RSS */
4031         params->rss_hfunc = ETH_RSS_HASH_XOR;
4032         netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4033         mlx5e_build_default_indir_rqt(params->indirection_rqt,
4034                                       MLX5E_INDIR_RQT_SIZE, max_channels);
4035 }
4036
4037 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4038                                         struct net_device *netdev,
4039                                         const struct mlx5e_profile *profile,
4040                                         void *ppriv)
4041 {
4042         struct mlx5e_priv *priv = netdev_priv(netdev);
4043
4044         priv->mdev        = mdev;
4045         priv->netdev      = netdev;
4046         priv->profile     = profile;
4047         priv->ppriv       = ppriv;
4048         priv->msglevel    = MLX5E_MSG_LEVEL;
4049         priv->hard_mtu = MLX5E_ETH_HARD_MTU;
4050
4051         mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
4052
4053         mutex_init(&priv->state_lock);
4054
4055         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4056         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4057         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4058         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4059
4060         mlx5e_timestamp_init(priv);
4061 }
4062
4063 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4064 {
4065         struct mlx5e_priv *priv = netdev_priv(netdev);
4066
4067         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4068         if (is_zero_ether_addr(netdev->dev_addr) &&
4069             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4070                 eth_hw_addr_random(netdev);
4071                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4072         }
4073 }
4074
4075 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4076 static const struct switchdev_ops mlx5e_switchdev_ops = {
4077         .switchdev_port_attr_get        = mlx5e_attr_get,
4078 };
4079 #endif
4080
4081 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4082 {
4083         struct mlx5e_priv *priv = netdev_priv(netdev);
4084         struct mlx5_core_dev *mdev = priv->mdev;
4085         bool fcs_supported;
4086         bool fcs_enabled;
4087
4088         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4089
4090         netdev->netdev_ops = &mlx5e_netdev_ops;
4091
4092 #ifdef CONFIG_MLX5_CORE_EN_DCB
4093         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4094                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4095 #endif
4096
4097         netdev->watchdog_timeo    = 15 * HZ;
4098
4099         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4100
4101         netdev->vlan_features    |= NETIF_F_SG;
4102         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4103         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4104         netdev->vlan_features    |= NETIF_F_GRO;
4105         netdev->vlan_features    |= NETIF_F_TSO;
4106         netdev->vlan_features    |= NETIF_F_TSO6;
4107         netdev->vlan_features    |= NETIF_F_RXCSUM;
4108         netdev->vlan_features    |= NETIF_F_RXHASH;
4109
4110         if (!!MLX5_CAP_ETH(mdev, lro_cap))
4111                 netdev->vlan_features    |= NETIF_F_LRO;
4112
4113         netdev->hw_features       = netdev->vlan_features;
4114         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4115         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4116         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4117         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4118
4119         if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4120                 netdev->hw_features     |= NETIF_F_GSO_PARTIAL;
4121                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4122                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4123                 netdev->hw_enc_features |= NETIF_F_TSO;
4124                 netdev->hw_enc_features |= NETIF_F_TSO6;
4125                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4126         }
4127
4128         if (mlx5e_vxlan_allowed(mdev)) {
4129                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4130                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4131                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4132                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4133                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4134         }
4135
4136         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4137                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4138                                            NETIF_F_GSO_GRE_CSUM;
4139                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4140                                            NETIF_F_GSO_GRE_CSUM;
4141                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4142                                                 NETIF_F_GSO_GRE_CSUM;
4143         }
4144
4145         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4146
4147         if (fcs_supported)
4148                 netdev->hw_features |= NETIF_F_RXALL;
4149
4150         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4151                 netdev->hw_features |= NETIF_F_RXFCS;
4152
4153         netdev->features          = netdev->hw_features;
4154         if (!priv->channels.params.lro_en)
4155                 netdev->features  &= ~NETIF_F_LRO;
4156
4157         if (fcs_enabled)
4158                 netdev->features  &= ~NETIF_F_RXALL;
4159
4160         if (!priv->channels.params.scatter_fcs_en)
4161                 netdev->features  &= ~NETIF_F_RXFCS;
4162
4163 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4164         if (FT_CAP(flow_modify_en) &&
4165             FT_CAP(modify_root) &&
4166             FT_CAP(identified_miss_table_mode) &&
4167             FT_CAP(flow_table_modify)) {
4168                 netdev->hw_features      |= NETIF_F_HW_TC;
4169 #ifdef CONFIG_RFS_ACCEL
4170                 netdev->hw_features      |= NETIF_F_NTUPLE;
4171 #endif
4172         }
4173
4174         netdev->features         |= NETIF_F_HIGHDMA;
4175         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4176
4177         netdev->priv_flags       |= IFF_UNICAST_FLT;
4178
4179         mlx5e_set_netdev_dev_addr(netdev);
4180
4181 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4182         if (MLX5_VPORT_MANAGER(mdev))
4183                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4184 #endif
4185
4186         mlx5e_ipsec_build_netdev(priv);
4187 }
4188
4189 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4190 {
4191         struct mlx5_core_dev *mdev = priv->mdev;
4192         int err;
4193
4194         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4195         if (err) {
4196                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4197                 priv->q_counter = 0;
4198         }
4199 }
4200
4201 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4202 {
4203         if (!priv->q_counter)
4204                 return;
4205
4206         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4207 }
4208
4209 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4210                            struct net_device *netdev,
4211                            const struct mlx5e_profile *profile,
4212                            void *ppriv)
4213 {
4214         struct mlx5e_priv *priv = netdev_priv(netdev);
4215         int err;
4216
4217         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4218         err = mlx5e_ipsec_init(priv);
4219         if (err)
4220                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4221         mlx5e_build_nic_netdev(netdev);
4222         mlx5e_vxlan_init(priv);
4223 }
4224
4225 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4226 {
4227         mlx5e_ipsec_cleanup(priv);
4228         mlx5e_vxlan_cleanup(priv);
4229 }
4230
4231 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4232 {
4233         struct mlx5_core_dev *mdev = priv->mdev;
4234         int err;
4235
4236         err = mlx5e_create_indirect_rqt(priv);
4237         if (err)
4238                 return err;
4239
4240         err = mlx5e_create_direct_rqts(priv);
4241         if (err)
4242                 goto err_destroy_indirect_rqts;
4243
4244         err = mlx5e_create_indirect_tirs(priv);
4245         if (err)
4246                 goto err_destroy_direct_rqts;
4247
4248         err = mlx5e_create_direct_tirs(priv);
4249         if (err)
4250                 goto err_destroy_indirect_tirs;
4251
4252         err = mlx5e_create_flow_steering(priv);
4253         if (err) {
4254                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4255                 goto err_destroy_direct_tirs;
4256         }
4257
4258         err = mlx5e_tc_init(priv);
4259         if (err)
4260                 goto err_destroy_flow_steering;
4261
4262         return 0;
4263
4264 err_destroy_flow_steering:
4265         mlx5e_destroy_flow_steering(priv);
4266 err_destroy_direct_tirs:
4267         mlx5e_destroy_direct_tirs(priv);
4268 err_destroy_indirect_tirs:
4269         mlx5e_destroy_indirect_tirs(priv);
4270 err_destroy_direct_rqts:
4271         mlx5e_destroy_direct_rqts(priv);
4272 err_destroy_indirect_rqts:
4273         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4274         return err;
4275 }
4276
4277 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4278 {
4279         mlx5e_tc_cleanup(priv);
4280         mlx5e_destroy_flow_steering(priv);
4281         mlx5e_destroy_direct_tirs(priv);
4282         mlx5e_destroy_indirect_tirs(priv);
4283         mlx5e_destroy_direct_rqts(priv);
4284         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4285 }
4286
4287 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4288 {
4289         int err;
4290
4291         err = mlx5e_create_tises(priv);
4292         if (err) {
4293                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4294                 return err;
4295         }
4296
4297 #ifdef CONFIG_MLX5_CORE_EN_DCB
4298         mlx5e_dcbnl_initialize(priv);
4299 #endif
4300         return 0;
4301 }
4302
4303 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4304 {
4305         struct net_device *netdev = priv->netdev;
4306         struct mlx5_core_dev *mdev = priv->mdev;
4307         u16 max_mtu;
4308
4309         mlx5e_init_l2_addr(priv);
4310
4311         /* Marking the link as currently not needed by the Driver */
4312         if (!netif_running(netdev))
4313                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4314
4315         /* MTU range: 68 - hw-specific max */
4316         netdev->min_mtu = ETH_MIN_MTU;
4317         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4318         netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
4319         mlx5e_set_dev_port_mtu(priv);
4320
4321         mlx5_lag_add(mdev, netdev);
4322
4323         mlx5e_enable_async_events(priv);
4324
4325         if (MLX5_VPORT_MANAGER(priv->mdev))
4326                 mlx5e_register_vport_reps(priv);
4327
4328         if (netdev->reg_state != NETREG_REGISTERED)
4329                 return;
4330 #ifdef CONFIG_MLX5_CORE_EN_DCB
4331         mlx5e_dcbnl_init_app(priv);
4332 #endif
4333
4334         queue_work(priv->wq, &priv->set_rx_mode_work);
4335
4336         rtnl_lock();
4337         if (netif_running(netdev))
4338                 mlx5e_open(netdev);
4339         netif_device_attach(netdev);
4340         rtnl_unlock();
4341 }
4342
4343 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4344 {
4345         struct mlx5_core_dev *mdev = priv->mdev;
4346
4347 #ifdef CONFIG_MLX5_CORE_EN_DCB
4348         if (priv->netdev->reg_state == NETREG_REGISTERED)
4349                 mlx5e_dcbnl_delete_app(priv);
4350 #endif
4351
4352         rtnl_lock();
4353         if (netif_running(priv->netdev))
4354                 mlx5e_close(priv->netdev);
4355         netif_device_detach(priv->netdev);
4356         rtnl_unlock();
4357
4358         queue_work(priv->wq, &priv->set_rx_mode_work);
4359
4360         if (MLX5_VPORT_MANAGER(priv->mdev))
4361                 mlx5e_unregister_vport_reps(priv);
4362
4363         mlx5e_disable_async_events(priv);
4364         mlx5_lag_remove(mdev);
4365 }
4366
4367 static const struct mlx5e_profile mlx5e_nic_profile = {
4368         .init              = mlx5e_nic_init,
4369         .cleanup           = mlx5e_nic_cleanup,
4370         .init_rx           = mlx5e_init_nic_rx,
4371         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4372         .init_tx           = mlx5e_init_nic_tx,
4373         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4374         .enable            = mlx5e_nic_enable,
4375         .disable           = mlx5e_nic_disable,
4376         .update_stats      = mlx5e_update_ndo_stats,
4377         .max_nch           = mlx5e_get_max_num_channels,
4378         .update_carrier    = mlx5e_update_carrier,
4379         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4380         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4381         .max_tc            = MLX5E_MAX_NUM_TC,
4382 };
4383
4384 /* mlx5e generic netdev management API (move to en_common.c) */
4385
4386 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4387                                        const struct mlx5e_profile *profile,
4388                                        void *ppriv)
4389 {
4390         int nch = profile->max_nch(mdev);
4391         struct net_device *netdev;
4392         struct mlx5e_priv *priv;
4393
4394         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4395                                     nch * profile->max_tc,
4396                                     nch);
4397         if (!netdev) {
4398                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4399                 return NULL;
4400         }
4401
4402 #ifdef CONFIG_RFS_ACCEL
4403         netdev->rx_cpu_rmap = mdev->rmap;
4404 #endif
4405
4406         profile->init(mdev, netdev, profile, ppriv);
4407
4408         netif_carrier_off(netdev);
4409
4410         priv = netdev_priv(netdev);
4411
4412         priv->wq = create_singlethread_workqueue("mlx5e");
4413         if (!priv->wq)
4414                 goto err_cleanup_nic;
4415
4416         return netdev;
4417
4418 err_cleanup_nic:
4419         if (profile->cleanup)
4420                 profile->cleanup(priv);
4421         free_netdev(netdev);
4422
4423         return NULL;
4424 }
4425
4426 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4427 {
4428         struct mlx5_core_dev *mdev = priv->mdev;
4429         const struct mlx5e_profile *profile;
4430         int err;
4431
4432         profile = priv->profile;
4433         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4434
4435         err = profile->init_tx(priv);
4436         if (err)
4437                 goto out;
4438
4439         err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
4440         if (err) {
4441                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4442                 goto err_cleanup_tx;
4443         }
4444
4445         err = profile->init_rx(priv);
4446         if (err)
4447                 goto err_close_drop_rq;
4448
4449         mlx5e_create_q_counter(priv);
4450
4451         if (profile->enable)
4452                 profile->enable(priv);
4453
4454         return 0;
4455
4456 err_close_drop_rq:
4457         mlx5e_close_drop_rq(&priv->drop_rq);
4458
4459 err_cleanup_tx:
4460         profile->cleanup_tx(priv);
4461
4462 out:
4463         return err;
4464 }
4465
4466 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4467 {
4468         const struct mlx5e_profile *profile = priv->profile;
4469
4470         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4471
4472         if (profile->disable)
4473                 profile->disable(priv);
4474         flush_workqueue(priv->wq);
4475
4476         mlx5e_destroy_q_counter(priv);
4477         profile->cleanup_rx(priv);
4478         mlx5e_close_drop_rq(&priv->drop_rq);
4479         profile->cleanup_tx(priv);
4480         cancel_delayed_work_sync(&priv->update_stats_work);
4481 }
4482
4483 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4484 {
4485         const struct mlx5e_profile *profile = priv->profile;
4486         struct net_device *netdev = priv->netdev;
4487
4488         destroy_workqueue(priv->wq);
4489         if (profile->cleanup)
4490                 profile->cleanup(priv);
4491         free_netdev(netdev);
4492 }
4493
4494 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4495  * hardware contexts and to connect it to the current netdev.
4496  */
4497 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4498 {
4499         struct mlx5e_priv *priv = vpriv;
4500         struct net_device *netdev = priv->netdev;
4501         int err;
4502
4503         if (netif_device_present(netdev))
4504                 return 0;
4505
4506         err = mlx5e_create_mdev_resources(mdev);
4507         if (err)
4508                 return err;
4509
4510         err = mlx5e_attach_netdev(priv);
4511         if (err) {
4512                 mlx5e_destroy_mdev_resources(mdev);
4513                 return err;
4514         }
4515
4516         return 0;
4517 }
4518
4519 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4520 {
4521         struct mlx5e_priv *priv = vpriv;
4522         struct net_device *netdev = priv->netdev;
4523
4524         if (!netif_device_present(netdev))
4525                 return;
4526
4527         mlx5e_detach_netdev(priv);
4528         mlx5e_destroy_mdev_resources(mdev);
4529 }
4530
4531 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4532 {
4533         struct net_device *netdev;
4534         void *rpriv = NULL;
4535         void *priv;
4536         int err;
4537
4538         err = mlx5e_check_required_hca_cap(mdev);
4539         if (err)
4540                 return NULL;
4541
4542 #ifdef CONFIG_MLX5_ESWITCH
4543         if (MLX5_VPORT_MANAGER(mdev)) {
4544                 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4545                 if (!rpriv) {
4546                         mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4547                         return NULL;
4548                 }
4549         }
4550 #endif
4551
4552         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4553         if (!netdev) {
4554                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4555                 goto err_free_rpriv;
4556         }
4557
4558         priv = netdev_priv(netdev);
4559
4560         err = mlx5e_attach(mdev, priv);
4561         if (err) {
4562                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4563                 goto err_destroy_netdev;
4564         }
4565
4566         err = register_netdev(netdev);
4567         if (err) {
4568                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4569                 goto err_detach;
4570         }
4571
4572 #ifdef CONFIG_MLX5_CORE_EN_DCB
4573         mlx5e_dcbnl_init_app(priv);
4574 #endif
4575         return priv;
4576
4577 err_detach:
4578         mlx5e_detach(mdev, priv);
4579 err_destroy_netdev:
4580         mlx5e_destroy_netdev(priv);
4581 err_free_rpriv:
4582         kfree(rpriv);
4583         return NULL;
4584 }
4585
4586 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4587 {
4588         struct mlx5e_priv *priv = vpriv;
4589         void *ppriv = priv->ppriv;
4590
4591 #ifdef CONFIG_MLX5_CORE_EN_DCB
4592         mlx5e_dcbnl_delete_app(priv);
4593 #endif
4594         unregister_netdev(priv->netdev);
4595         mlx5e_detach(mdev, vpriv);
4596         mlx5e_destroy_netdev(priv);
4597         kfree(ppriv);
4598 }
4599
4600 static void *mlx5e_get_netdev(void *vpriv)
4601 {
4602         struct mlx5e_priv *priv = vpriv;
4603
4604         return priv->netdev;
4605 }
4606
4607 static struct mlx5_interface mlx5e_interface = {
4608         .add       = mlx5e_add,
4609         .remove    = mlx5e_remove,
4610         .attach    = mlx5e_attach,
4611         .detach    = mlx5e_detach,
4612         .event     = mlx5e_async_event,
4613         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
4614         .get_dev   = mlx5e_get_netdev,
4615 };
4616
4617 void mlx5e_init(void)
4618 {
4619         mlx5e_ipsec_build_inverse_table();
4620         mlx5e_build_ptys2ethtool_map();
4621         mlx5_register_interface(&mlx5e_interface);
4622 }
4623
4624 void mlx5e_cleanup(void)
4625 {
4626         mlx5_unregister_interface(&mlx5e_interface);
4627 }