2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include <net/page_pool.h>
43 #include "en_accel/ipsec.h"
44 #include "en_accel/ipsec_rxtx.h"
45 #include "en_accel/tls.h"
46 #include "accel/ipsec.h"
47 #include "accel/tls.h"
50 struct mlx5e_rq_param {
51 u32 rqc[MLX5_ST_SZ_DW(rqc)];
52 struct mlx5_wq_param wq;
55 struct mlx5e_sq_param {
56 u32 sqc[MLX5_ST_SZ_DW(sqc)];
57 struct mlx5_wq_param wq;
60 struct mlx5e_cq_param {
61 u32 cqc[MLX5_ST_SZ_DW(cqc)];
62 struct mlx5_wq_param wq;
67 struct mlx5e_channel_param {
68 struct mlx5e_rq_param rq;
69 struct mlx5e_sq_param sq;
70 struct mlx5e_sq_param xdp_sq;
71 struct mlx5e_sq_param icosq;
72 struct mlx5e_cq_param rx_cq;
73 struct mlx5e_cq_param tx_cq;
74 struct mlx5e_cq_param icosq_cq;
77 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
79 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
80 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
81 MLX5_CAP_ETH(mdev, reg_umr_sq);
82 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
83 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
88 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
89 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
95 static u32 mlx5e_mpwqe_get_linear_frag_sz(struct mlx5e_params *params)
97 if (!params->xdp_prog) {
98 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
99 u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN;
101 return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu);
107 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
109 u32 linear_frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
111 return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
114 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
115 struct mlx5e_params *params)
117 u32 frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
118 s8 signed_log_num_strides_param;
121 if (params->lro_en || frag_sz > PAGE_SIZE)
124 if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
127 log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
128 signed_log_num_strides_param =
129 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
131 return signed_log_num_strides_param >= 0;
134 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
136 if (params->log_rq_mtu_frames <
137 mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
138 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
140 return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
143 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
144 struct mlx5e_params *params)
146 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
147 return order_base_2(mlx5e_mpwqe_get_linear_frag_sz(params));
149 return MLX5E_MPWQE_STRIDE_SZ(mdev,
150 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
153 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
154 struct mlx5e_params *params)
156 return MLX5_MPWRQ_LOG_WQE_SZ -
157 mlx5e_mpwqe_get_log_stride_size(mdev, params);
160 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
161 struct mlx5e_params *params)
163 u16 linear_rq_headroom = params->xdp_prog ?
164 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
166 linear_rq_headroom += NET_IP_ALIGN;
168 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)
169 return linear_rq_headroom;
171 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
172 return linear_rq_headroom;
177 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
178 struct mlx5e_params *params)
180 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
181 params->log_rq_mtu_frames = is_kdump_kernel() ?
182 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
183 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
184 switch (params->rq_wq_type) {
185 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
187 default: /* MLX5_WQ_TYPE_LINKED_LIST */
188 /* Extra room needed for build_skb */
189 params->lro_wqe_sz -= mlx5e_get_rq_headroom(mdev, params) +
190 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
193 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
194 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
195 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
196 BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
197 BIT(params->log_rq_mtu_frames),
198 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
199 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
202 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
203 struct mlx5e_params *params)
205 return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
206 !MLX5_IPSEC_DEV(mdev) &&
207 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
210 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
212 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
213 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
214 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
215 MLX5_WQ_TYPE_LINKED_LIST;
218 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
220 struct mlx5_core_dev *mdev = priv->mdev;
223 port_state = mlx5_query_vport_state(mdev,
224 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
227 if (port_state == VPORT_STATE_UP) {
228 netdev_info(priv->netdev, "Link up\n");
229 netif_carrier_on(priv->netdev);
231 netdev_info(priv->netdev, "Link down\n");
232 netif_carrier_off(priv->netdev);
236 static void mlx5e_update_carrier_work(struct work_struct *work)
238 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
239 update_carrier_work);
241 mutex_lock(&priv->state_lock);
242 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
243 if (priv->profile->update_carrier)
244 priv->profile->update_carrier(priv);
245 mutex_unlock(&priv->state_lock);
248 void mlx5e_update_stats(struct mlx5e_priv *priv)
252 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
253 if (mlx5e_stats_grps[i].update_stats)
254 mlx5e_stats_grps[i].update_stats(priv);
257 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
261 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
262 if (mlx5e_stats_grps[i].update_stats_mask &
263 MLX5E_NDO_UPDATE_STATS)
264 mlx5e_stats_grps[i].update_stats(priv);
267 void mlx5e_update_stats_work(struct work_struct *work)
269 struct delayed_work *dwork = to_delayed_work(work);
270 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
272 mutex_lock(&priv->state_lock);
273 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
274 priv->profile->update_stats(priv);
275 queue_delayed_work(priv->wq, dwork,
276 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
278 mutex_unlock(&priv->state_lock);
281 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
282 enum mlx5_dev_event event, unsigned long param)
284 struct mlx5e_priv *priv = vpriv;
286 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
290 case MLX5_DEV_EVENT_PORT_UP:
291 case MLX5_DEV_EVENT_PORT_DOWN:
292 queue_work(priv->wq, &priv->update_carrier_work);
299 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
301 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
304 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
306 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
307 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
310 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
311 struct mlx5e_icosq *sq,
312 struct mlx5e_umr_wqe *wqe)
314 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
315 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
316 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
318 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
320 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
321 cseg->imm = rq->mkey_be;
323 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
324 ucseg->xlt_octowords =
325 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
326 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
329 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
330 struct mlx5e_channel *c)
332 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
334 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
335 GFP_KERNEL, cpu_to_node(c->cpu));
339 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
344 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
345 u64 npages, u8 page_shift,
346 struct mlx5_core_mkey *umr_mkey)
348 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
353 in = kvzalloc(inlen, GFP_KERNEL);
357 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
359 MLX5_SET(mkc, mkc, free, 1);
360 MLX5_SET(mkc, mkc, umr_en, 1);
361 MLX5_SET(mkc, mkc, lw, 1);
362 MLX5_SET(mkc, mkc, lr, 1);
363 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
365 MLX5_SET(mkc, mkc, qpn, 0xffffff);
366 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
367 MLX5_SET64(mkc, mkc, len, npages << page_shift);
368 MLX5_SET(mkc, mkc, translations_octword_size,
369 MLX5_MTT_OCTW(npages));
370 MLX5_SET(mkc, mkc, log_page_size, page_shift);
372 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
378 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
380 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
382 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
385 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
387 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
390 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
391 struct mlx5e_params *params,
392 struct mlx5e_rq_param *rqp,
395 struct page_pool_params pp_params = { 0 };
396 struct mlx5_core_dev *mdev = c->mdev;
397 void *rqc = rqp->rqc;
398 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
399 u32 byte_count, pool_size;
405 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
407 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
412 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
414 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
416 rq->wq_type = params->rq_wq_type;
418 rq->netdev = c->netdev;
419 rq->tstamp = c->tstamp;
420 rq->clock = &mdev->clock;
424 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
426 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
427 if (IS_ERR(rq->xdp_prog)) {
428 err = PTR_ERR(rq->xdp_prog);
430 goto err_rq_wq_destroy;
433 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
435 goto err_rq_wq_destroy;
437 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
438 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
439 pool_size = 1 << params->log_rq_mtu_frames;
441 switch (rq->wq_type) {
442 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
444 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
445 rq->post_wqes = mlx5e_post_rx_mpwqes;
446 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
448 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
449 #ifdef CONFIG_MLX5_EN_IPSEC
450 if (MLX5_IPSEC_DEV(mdev)) {
452 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
453 goto err_rq_wq_destroy;
456 if (!rq->handle_rx_cqe) {
458 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
459 goto err_rq_wq_destroy;
462 rq->mpwqe.skb_from_cqe_mpwrq =
463 mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
464 mlx5e_skb_from_cqe_mpwrq_linear :
465 mlx5e_skb_from_cqe_mpwrq_nonlinear;
466 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
467 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
469 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
471 err = mlx5e_create_rq_umr_mkey(mdev, rq);
473 goto err_rq_wq_destroy;
474 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
476 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
478 goto err_destroy_umr_mkey;
480 default: /* MLX5_WQ_TYPE_LINKED_LIST */
482 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
483 GFP_KERNEL, cpu_to_node(c->cpu));
484 if (!rq->wqe.frag_info) {
486 goto err_rq_wq_destroy;
488 rq->post_wqes = mlx5e_post_rx_wqes;
489 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
491 #ifdef CONFIG_MLX5_EN_IPSEC
493 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
496 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
497 if (!rq->handle_rx_cqe) {
498 kfree(rq->wqe.frag_info);
500 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
501 goto err_rq_wq_destroy;
504 byte_count = params->lro_en ?
506 MLX5E_SW2HW_MTU(params, params->sw_mtu);
507 #ifdef CONFIG_MLX5_EN_IPSEC
508 if (MLX5_IPSEC_DEV(mdev))
509 byte_count += MLX5E_METADATA_ETHER_LEN;
511 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
513 /* calc the required page order */
514 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
515 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
516 rq->buff.page_order = order_base_2(npages);
518 byte_count |= MLX5_HW_START_PADDING;
519 rq->mkey_be = c->mkey_be;
522 /* Create a page_pool and register it with rxq */
523 pp_params.order = rq->buff.page_order;
524 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
525 pp_params.pool_size = pool_size;
526 pp_params.nid = cpu_to_node(c->cpu);
527 pp_params.dev = c->pdev;
528 pp_params.dma_dir = rq->buff.map_dir;
530 /* page_pool can be used even when there is no rq->xdp_prog,
531 * given page_pool does not handle DMA mapping there is no
532 * required state to clear. And page_pool gracefully handle
535 rq->page_pool = page_pool_create(&pp_params);
536 if (IS_ERR(rq->page_pool)) {
537 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
538 kfree(rq->wqe.frag_info);
539 err = PTR_ERR(rq->page_pool);
540 rq->page_pool = NULL;
541 goto err_rq_wq_destroy;
543 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
544 MEM_TYPE_PAGE_POOL, rq->page_pool);
546 goto err_rq_wq_destroy;
548 for (i = 0; i < wq_sz; i++) {
549 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
551 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
552 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
554 wqe->data.addr = cpu_to_be64(dma_offset + rq->buff.headroom);
557 wqe->data.byte_count = cpu_to_be32(byte_count);
558 wqe->data.lkey = rq->mkey_be;
561 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
563 switch (params->rx_cq_moderation.cq_period_mode) {
564 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
565 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
567 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
569 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
572 rq->page_cache.head = 0;
573 rq->page_cache.tail = 0;
577 err_destroy_umr_mkey:
578 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
582 bpf_prog_put(rq->xdp_prog);
583 xdp_rxq_info_unreg(&rq->xdp_rxq);
585 page_pool_destroy(rq->page_pool);
586 mlx5_wq_destroy(&rq->wq_ctrl);
591 static void mlx5e_free_rq(struct mlx5e_rq *rq)
596 bpf_prog_put(rq->xdp_prog);
598 xdp_rxq_info_unreg(&rq->xdp_rxq);
600 page_pool_destroy(rq->page_pool);
602 switch (rq->wq_type) {
603 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
604 kfree(rq->mpwqe.info);
605 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
607 default: /* MLX5_WQ_TYPE_LINKED_LIST */
608 kfree(rq->wqe.frag_info);
611 for (i = rq->page_cache.head; i != rq->page_cache.tail;
612 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
613 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
615 mlx5e_page_release(rq, dma_info, false);
617 mlx5_wq_destroy(&rq->wq_ctrl);
620 static int mlx5e_create_rq(struct mlx5e_rq *rq,
621 struct mlx5e_rq_param *param)
623 struct mlx5_core_dev *mdev = rq->mdev;
631 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
632 sizeof(u64) * rq->wq_ctrl.buf.npages;
633 in = kvzalloc(inlen, GFP_KERNEL);
637 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
638 wq = MLX5_ADDR_OF(rqc, rqc, wq);
640 memcpy(rqc, param->rqc, sizeof(param->rqc));
642 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
643 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
644 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
645 MLX5_ADAPTER_PAGE_SHIFT);
646 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
648 mlx5_fill_page_array(&rq->wq_ctrl.buf,
649 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
651 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
658 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
661 struct mlx5_core_dev *mdev = rq->mdev;
668 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
669 in = kvzalloc(inlen, GFP_KERNEL);
673 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
675 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
676 MLX5_SET(rqc, rqc, state, next_state);
678 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
685 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
687 struct mlx5e_channel *c = rq->channel;
688 struct mlx5e_priv *priv = c->priv;
689 struct mlx5_core_dev *mdev = priv->mdev;
696 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
697 in = kvzalloc(inlen, GFP_KERNEL);
701 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
703 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
704 MLX5_SET64(modify_rq_in, in, modify_bitmask,
705 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
706 MLX5_SET(rqc, rqc, scatter_fcs, enable);
707 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
709 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
716 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
718 struct mlx5e_channel *c = rq->channel;
719 struct mlx5_core_dev *mdev = c->mdev;
725 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
726 in = kvzalloc(inlen, GFP_KERNEL);
730 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
732 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
733 MLX5_SET64(modify_rq_in, in, modify_bitmask,
734 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
735 MLX5_SET(rqc, rqc, vsd, vsd);
736 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
738 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
745 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
747 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
750 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
752 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
753 struct mlx5e_channel *c = rq->channel;
755 struct mlx5_wq_ll *wq = &rq->wq;
756 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
759 if (wq->cur_sz >= min_wqes)
763 } while (time_before(jiffies, exp_time));
765 netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
766 c->ix, rq->rqn, wq->cur_sz, min_wqes);
771 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
773 struct mlx5_wq_ll *wq = &rq->wq;
774 struct mlx5e_rx_wqe *wqe;
778 /* UMR WQE (if in progress) is always at wq->head */
779 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
780 rq->mpwqe.umr_in_progress)
781 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
783 while (!mlx5_wq_ll_is_empty(wq)) {
784 wqe_ix_be = *wq->tail_next;
785 wqe_ix = be16_to_cpu(wqe_ix_be);
786 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
787 rq->dealloc_wqe(rq, wqe_ix);
788 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
789 &wqe->next.next_wqe_index);
792 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
793 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
794 * but yet to be re-posted.
796 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
798 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
799 rq->dealloc_wqe(rq, wqe_ix);
803 static int mlx5e_open_rq(struct mlx5e_channel *c,
804 struct mlx5e_params *params,
805 struct mlx5e_rq_param *param,
810 err = mlx5e_alloc_rq(c, params, param, rq);
814 err = mlx5e_create_rq(rq, param);
818 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
822 if (params->rx_dim_enabled)
823 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
828 mlx5e_destroy_rq(rq);
835 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
837 struct mlx5e_icosq *sq = &rq->channel->icosq;
838 u16 pi = sq->pc & sq->wq.sz_m1;
839 struct mlx5e_tx_wqe *nopwqe;
841 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
842 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
843 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
844 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
847 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
849 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
850 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
853 static void mlx5e_close_rq(struct mlx5e_rq *rq)
855 cancel_work_sync(&rq->dim.work);
856 mlx5e_destroy_rq(rq);
857 mlx5e_free_rx_descs(rq);
861 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
866 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
868 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
870 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
873 mlx5e_free_xdpsq_db(sq);
880 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
881 struct mlx5e_params *params,
882 struct mlx5e_sq_param *param,
883 struct mlx5e_xdpsq *sq)
885 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
886 struct mlx5_core_dev *mdev = c->mdev;
890 sq->mkey_be = c->mkey_be;
892 sq->uar_map = mdev->mlx5e_res.bfreg.map;
893 sq->min_inline_mode = params->tx_min_inline_mode;
895 param->wq.db_numa_node = cpu_to_node(c->cpu);
896 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
899 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
901 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
903 goto err_sq_wq_destroy;
908 mlx5_wq_destroy(&sq->wq_ctrl);
913 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
915 mlx5e_free_xdpsq_db(sq);
916 mlx5_wq_destroy(&sq->wq_ctrl);
919 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
921 kfree(sq->db.ico_wqe);
924 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
926 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
928 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
936 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
937 struct mlx5e_sq_param *param,
938 struct mlx5e_icosq *sq)
940 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
941 struct mlx5_core_dev *mdev = c->mdev;
945 sq->uar_map = mdev->mlx5e_res.bfreg.map;
947 param->wq.db_numa_node = cpu_to_node(c->cpu);
948 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
951 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
953 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
955 goto err_sq_wq_destroy;
957 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
962 mlx5_wq_destroy(&sq->wq_ctrl);
967 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
969 mlx5e_free_icosq_db(sq);
970 mlx5_wq_destroy(&sq->wq_ctrl);
973 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
975 kfree(sq->db.wqe_info);
976 kfree(sq->db.dma_fifo);
979 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
981 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
982 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
984 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
986 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
988 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
989 mlx5e_free_txqsq_db(sq);
993 sq->dma_fifo_mask = df_sz - 1;
998 static void mlx5e_sq_recover(struct work_struct *work);
999 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1001 struct mlx5e_params *params,
1002 struct mlx5e_sq_param *param,
1003 struct mlx5e_txqsq *sq)
1005 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1006 struct mlx5_core_dev *mdev = c->mdev;
1010 sq->tstamp = c->tstamp;
1011 sq->clock = &mdev->clock;
1012 sq->mkey_be = c->mkey_be;
1014 sq->txq_ix = txq_ix;
1015 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1016 sq->min_inline_mode = params->tx_min_inline_mode;
1017 INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1018 if (MLX5_IPSEC_DEV(c->priv->mdev))
1019 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1020 if (mlx5_accel_is_tls_device(c->priv->mdev))
1021 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1023 param->wq.db_numa_node = cpu_to_node(c->cpu);
1024 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1027 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1029 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1031 goto err_sq_wq_destroy;
1033 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1034 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1036 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1041 mlx5_wq_destroy(&sq->wq_ctrl);
1046 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1048 mlx5e_free_txqsq_db(sq);
1049 mlx5_wq_destroy(&sq->wq_ctrl);
1052 struct mlx5e_create_sq_param {
1053 struct mlx5_wq_ctrl *wq_ctrl;
1060 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1061 struct mlx5e_sq_param *param,
1062 struct mlx5e_create_sq_param *csp,
1071 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1072 sizeof(u64) * csp->wq_ctrl->buf.npages;
1073 in = kvzalloc(inlen, GFP_KERNEL);
1077 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1078 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1080 memcpy(sqc, param->sqc, sizeof(param->sqc));
1081 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1082 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1083 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1085 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1086 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1088 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1089 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1091 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1092 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1093 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1094 MLX5_ADAPTER_PAGE_SHIFT);
1095 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1097 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1099 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1106 struct mlx5e_modify_sq_param {
1113 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1114 struct mlx5e_modify_sq_param *p)
1121 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1122 in = kvzalloc(inlen, GFP_KERNEL);
1126 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1128 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1129 MLX5_SET(sqc, sqc, state, p->next_state);
1130 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1131 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1132 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1135 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1142 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1144 mlx5_core_destroy_sq(mdev, sqn);
1147 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1148 struct mlx5e_sq_param *param,
1149 struct mlx5e_create_sq_param *csp,
1152 struct mlx5e_modify_sq_param msp = {0};
1155 err = mlx5e_create_sq(mdev, param, csp, sqn);
1159 msp.curr_state = MLX5_SQC_STATE_RST;
1160 msp.next_state = MLX5_SQC_STATE_RDY;
1161 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1163 mlx5e_destroy_sq(mdev, *sqn);
1168 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1169 struct mlx5e_txqsq *sq, u32 rate);
1171 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1174 struct mlx5e_params *params,
1175 struct mlx5e_sq_param *param,
1176 struct mlx5e_txqsq *sq)
1178 struct mlx5e_create_sq_param csp = {};
1182 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1188 csp.cqn = sq->cq.mcq.cqn;
1189 csp.wq_ctrl = &sq->wq_ctrl;
1190 csp.min_inline_mode = sq->min_inline_mode;
1191 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1193 goto err_free_txqsq;
1195 tx_rate = c->priv->tx_rates[sq->txq_ix];
1197 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1199 if (params->tx_dim_enabled)
1200 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1205 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1206 mlx5e_free_txqsq(sq);
1211 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1213 WARN_ONCE(sq->cc != sq->pc,
1214 "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1215 sq->sqn, sq->cc, sq->pc);
1217 sq->dma_fifo_cc = 0;
1221 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1223 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1224 clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1225 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1226 netdev_tx_reset_queue(sq->txq);
1227 netif_tx_start_queue(sq->txq);
1230 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1232 __netif_tx_lock_bh(txq);
1233 netif_tx_stop_queue(txq);
1234 __netif_tx_unlock_bh(txq);
1237 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1239 struct mlx5e_channel *c = sq->channel;
1241 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1242 /* prevent netif_tx_wake_queue */
1243 napi_synchronize(&c->napi);
1245 netif_tx_disable_queue(sq->txq);
1247 /* last doorbell out, godspeed .. */
1248 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1249 struct mlx5e_tx_wqe *nop;
1251 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1252 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1253 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1257 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1259 struct mlx5e_channel *c = sq->channel;
1260 struct mlx5_core_dev *mdev = c->mdev;
1261 struct mlx5_rate_limit rl = {0};
1263 mlx5e_destroy_sq(mdev, sq->sqn);
1264 if (sq->rate_limit) {
1265 rl.rate = sq->rate_limit;
1266 mlx5_rl_remove_rate(mdev, &rl);
1268 mlx5e_free_txqsq_descs(sq);
1269 mlx5e_free_txqsq(sq);
1272 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1274 unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1276 while (time_before(jiffies, exp_time)) {
1277 if (sq->cc == sq->pc)
1283 netdev_err(sq->channel->netdev,
1284 "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1285 sq->sqn, sq->cc, sq->pc);
1290 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1292 struct mlx5_core_dev *mdev = sq->channel->mdev;
1293 struct net_device *dev = sq->channel->netdev;
1294 struct mlx5e_modify_sq_param msp = {0};
1297 msp.curr_state = curr_state;
1298 msp.next_state = MLX5_SQC_STATE_RST;
1300 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1302 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1306 memset(&msp, 0, sizeof(msp));
1307 msp.curr_state = MLX5_SQC_STATE_RST;
1308 msp.next_state = MLX5_SQC_STATE_RDY;
1310 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1312 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1319 static void mlx5e_sq_recover(struct work_struct *work)
1321 struct mlx5e_txqsq_recover *recover =
1322 container_of(work, struct mlx5e_txqsq_recover,
1324 struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1326 struct mlx5_core_dev *mdev = sq->channel->mdev;
1327 struct net_device *dev = sq->channel->netdev;
1331 err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1333 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1338 if (state != MLX5_RQC_STATE_ERR) {
1339 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1343 netif_tx_disable_queue(sq->txq);
1345 if (mlx5e_wait_for_sq_flush(sq))
1348 /* If the interval between two consecutive recovers per SQ is too
1349 * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1350 * If we reached this state, there is probably a bug that needs to be
1351 * fixed. let's keep the queue close and let tx timeout cleanup.
1353 if (jiffies_to_msecs(jiffies - recover->last_recover) <
1354 MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1355 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1360 /* At this point, no new packets will arrive from the stack as TXQ is
1361 * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1362 * pending WQEs. SQ can safely reset the SQ.
1364 if (mlx5e_sq_to_ready(sq, state))
1367 mlx5e_reset_txqsq_cc_pc(sq);
1368 sq->stats.recover++;
1369 recover->last_recover = jiffies;
1370 mlx5e_activate_txqsq(sq);
1373 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1374 struct mlx5e_params *params,
1375 struct mlx5e_sq_param *param,
1376 struct mlx5e_icosq *sq)
1378 struct mlx5e_create_sq_param csp = {};
1381 err = mlx5e_alloc_icosq(c, param, sq);
1385 csp.cqn = sq->cq.mcq.cqn;
1386 csp.wq_ctrl = &sq->wq_ctrl;
1387 csp.min_inline_mode = params->tx_min_inline_mode;
1388 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1389 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1391 goto err_free_icosq;
1396 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1397 mlx5e_free_icosq(sq);
1402 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1404 struct mlx5e_channel *c = sq->channel;
1406 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1407 napi_synchronize(&c->napi);
1409 mlx5e_destroy_sq(c->mdev, sq->sqn);
1410 mlx5e_free_icosq(sq);
1413 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1414 struct mlx5e_params *params,
1415 struct mlx5e_sq_param *param,
1416 struct mlx5e_xdpsq *sq)
1418 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1419 struct mlx5e_create_sq_param csp = {};
1420 unsigned int inline_hdr_sz = 0;
1424 err = mlx5e_alloc_xdpsq(c, params, param, sq);
1429 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1430 csp.cqn = sq->cq.mcq.cqn;
1431 csp.wq_ctrl = &sq->wq_ctrl;
1432 csp.min_inline_mode = sq->min_inline_mode;
1433 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1434 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1436 goto err_free_xdpsq;
1438 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1439 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1443 /* Pre initialize fixed WQE fields */
1444 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1445 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1446 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1447 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1448 struct mlx5_wqe_data_seg *dseg;
1450 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1451 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1453 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1454 dseg->lkey = sq->mkey_be;
1460 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1461 mlx5e_free_xdpsq(sq);
1466 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1468 struct mlx5e_channel *c = sq->channel;
1470 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1471 napi_synchronize(&c->napi);
1473 mlx5e_destroy_sq(c->mdev, sq->sqn);
1474 mlx5e_free_xdpsq_descs(sq);
1475 mlx5e_free_xdpsq(sq);
1478 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1479 struct mlx5e_cq_param *param,
1480 struct mlx5e_cq *cq)
1482 struct mlx5_core_cq *mcq = &cq->mcq;
1488 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1493 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1496 mcq->set_ci_db = cq->wq_ctrl.db.db;
1497 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1498 *mcq->set_ci_db = 0;
1500 mcq->vector = param->eq_ix;
1501 mcq->comp = mlx5e_completion_event;
1502 mcq->event = mlx5e_cq_error_event;
1505 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1506 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1516 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1517 struct mlx5e_cq_param *param,
1518 struct mlx5e_cq *cq)
1520 struct mlx5_core_dev *mdev = c->priv->mdev;
1523 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1524 param->wq.db_numa_node = cpu_to_node(c->cpu);
1525 param->eq_ix = c->ix;
1527 err = mlx5e_alloc_cq_common(mdev, param, cq);
1529 cq->napi = &c->napi;
1535 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1537 mlx5_cqwq_destroy(&cq->wq_ctrl);
1540 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1542 struct mlx5_core_dev *mdev = cq->mdev;
1543 struct mlx5_core_cq *mcq = &cq->mcq;
1548 unsigned int irqn_not_used;
1552 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1553 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1554 in = kvzalloc(inlen, GFP_KERNEL);
1558 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1560 memcpy(cqc, param->cqc, sizeof(param->cqc));
1562 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1563 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1565 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1567 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1568 MLX5_SET(cqc, cqc, c_eqn, eqn);
1569 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1570 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1571 MLX5_ADAPTER_PAGE_SHIFT);
1572 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1574 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1586 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1588 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1591 static int mlx5e_open_cq(struct mlx5e_channel *c,
1592 struct net_dim_cq_moder moder,
1593 struct mlx5e_cq_param *param,
1594 struct mlx5e_cq *cq)
1596 struct mlx5_core_dev *mdev = c->mdev;
1599 err = mlx5e_alloc_cq(c, param, cq);
1603 err = mlx5e_create_cq(cq, param);
1607 if (MLX5_CAP_GEN(mdev, cq_moderation))
1608 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1617 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1619 mlx5e_destroy_cq(cq);
1623 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1625 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1628 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1629 struct mlx5e_params *params,
1630 struct mlx5e_channel_param *cparam)
1635 for (tc = 0; tc < c->num_tc; tc++) {
1636 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1637 &cparam->tx_cq, &c->sq[tc].cq);
1639 goto err_close_tx_cqs;
1645 for (tc--; tc >= 0; tc--)
1646 mlx5e_close_cq(&c->sq[tc].cq);
1651 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1655 for (tc = 0; tc < c->num_tc; tc++)
1656 mlx5e_close_cq(&c->sq[tc].cq);
1659 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1660 struct mlx5e_params *params,
1661 struct mlx5e_channel_param *cparam)
1666 for (tc = 0; tc < params->num_tc; tc++) {
1667 int txq_ix = c->ix + tc * params->num_channels;
1669 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1670 params, &cparam->sq, &c->sq[tc]);
1678 for (tc--; tc >= 0; tc--)
1679 mlx5e_close_txqsq(&c->sq[tc]);
1684 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1688 for (tc = 0; tc < c->num_tc; tc++)
1689 mlx5e_close_txqsq(&c->sq[tc]);
1692 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1693 struct mlx5e_txqsq *sq, u32 rate)
1695 struct mlx5e_priv *priv = netdev_priv(dev);
1696 struct mlx5_core_dev *mdev = priv->mdev;
1697 struct mlx5e_modify_sq_param msp = {0};
1698 struct mlx5_rate_limit rl = {0};
1702 if (rate == sq->rate_limit)
1706 if (sq->rate_limit) {
1707 rl.rate = sq->rate_limit;
1708 /* remove current rl index to free space to next ones */
1709 mlx5_rl_remove_rate(mdev, &rl);
1716 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1718 netdev_err(dev, "Failed configuring rate %u: %d\n",
1724 msp.curr_state = MLX5_SQC_STATE_RDY;
1725 msp.next_state = MLX5_SQC_STATE_RDY;
1726 msp.rl_index = rl_index;
1727 msp.rl_update = true;
1728 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1730 netdev_err(dev, "Failed configuring rate %u: %d\n",
1732 /* remove the rate from the table */
1734 mlx5_rl_remove_rate(mdev, &rl);
1738 sq->rate_limit = rate;
1742 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1744 struct mlx5e_priv *priv = netdev_priv(dev);
1745 struct mlx5_core_dev *mdev = priv->mdev;
1746 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1749 if (!mlx5_rl_is_supported(mdev)) {
1750 netdev_err(dev, "Rate limiting is not supported on this device\n");
1754 /* rate is given in Mb/sec, HW config is in Kb/sec */
1757 /* Check whether rate in valid range, 0 is always valid */
1758 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1759 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1763 mutex_lock(&priv->state_lock);
1764 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1765 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1767 priv->tx_rates[index] = rate;
1768 mutex_unlock(&priv->state_lock);
1773 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1774 struct mlx5e_params *params,
1775 struct mlx5e_channel_param *cparam,
1776 struct mlx5e_channel **cp)
1778 struct net_dim_cq_moder icocq_moder = {0, 0};
1779 struct net_device *netdev = priv->netdev;
1780 int cpu = mlx5e_get_cpu(priv, ix);
1781 struct mlx5e_channel *c;
1786 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1791 c->mdev = priv->mdev;
1792 c->tstamp = &priv->tstamp;
1795 c->pdev = &priv->mdev->pdev->dev;
1796 c->netdev = priv->netdev;
1797 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1798 c->num_tc = params->num_tc;
1799 c->xdp = !!params->xdp_prog;
1801 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1802 c->irq_desc = irq_to_desc(irq);
1804 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1806 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1810 err = mlx5e_open_tx_cqs(c, params, cparam);
1812 goto err_close_icosq_cq;
1814 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1816 goto err_close_tx_cqs;
1818 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1819 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1820 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1822 goto err_close_rx_cq;
1824 napi_enable(&c->napi);
1826 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1828 goto err_disable_napi;
1830 err = mlx5e_open_sqs(c, params, cparam);
1832 goto err_close_icosq;
1834 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1838 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1840 goto err_close_xdp_sq;
1847 mlx5e_close_xdpsq(&c->rq.xdpsq);
1853 mlx5e_close_icosq(&c->icosq);
1856 napi_disable(&c->napi);
1858 mlx5e_close_cq(&c->rq.xdpsq.cq);
1861 mlx5e_close_cq(&c->rq.cq);
1864 mlx5e_close_tx_cqs(c);
1867 mlx5e_close_cq(&c->icosq.cq);
1870 netif_napi_del(&c->napi);
1876 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1880 for (tc = 0; tc < c->num_tc; tc++)
1881 mlx5e_activate_txqsq(&c->sq[tc]);
1882 mlx5e_activate_rq(&c->rq);
1883 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1886 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1890 mlx5e_deactivate_rq(&c->rq);
1891 for (tc = 0; tc < c->num_tc; tc++)
1892 mlx5e_deactivate_txqsq(&c->sq[tc]);
1895 static void mlx5e_close_channel(struct mlx5e_channel *c)
1897 mlx5e_close_rq(&c->rq);
1899 mlx5e_close_xdpsq(&c->rq.xdpsq);
1901 mlx5e_close_icosq(&c->icosq);
1902 napi_disable(&c->napi);
1904 mlx5e_close_cq(&c->rq.xdpsq.cq);
1905 mlx5e_close_cq(&c->rq.cq);
1906 mlx5e_close_tx_cqs(c);
1907 mlx5e_close_cq(&c->icosq.cq);
1908 netif_napi_del(&c->napi);
1913 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1914 struct mlx5e_params *params,
1915 struct mlx5e_rq_param *param)
1917 struct mlx5_core_dev *mdev = priv->mdev;
1918 void *rqc = param->rqc;
1919 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1921 switch (params->rq_wq_type) {
1922 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1923 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1924 mlx5e_mpwqe_get_log_num_strides(mdev, params) -
1925 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
1926 MLX5_SET(wq, wq, log_wqe_stride_size,
1927 mlx5e_mpwqe_get_log_stride_size(mdev, params) -
1928 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
1929 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1930 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
1932 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1933 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1934 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
1937 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1938 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1939 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
1940 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1941 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
1942 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
1944 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1947 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
1948 struct mlx5e_rq_param *param)
1950 struct mlx5_core_dev *mdev = priv->mdev;
1951 void *rqc = param->rqc;
1952 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1954 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1955 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1956 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
1958 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1961 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1962 struct mlx5e_sq_param *param)
1964 void *sqc = param->sqc;
1965 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1967 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1968 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1970 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1973 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1974 struct mlx5e_params *params,
1975 struct mlx5e_sq_param *param)
1977 void *sqc = param->sqc;
1978 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1980 mlx5e_build_sq_param_common(priv, param);
1981 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1982 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1985 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1986 struct mlx5e_cq_param *param)
1988 void *cqc = param->cqc;
1990 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1993 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1994 struct mlx5e_params *params,
1995 struct mlx5e_cq_param *param)
1997 struct mlx5_core_dev *mdev = priv->mdev;
1998 void *cqc = param->cqc;
2001 switch (params->rq_wq_type) {
2002 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2003 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2004 mlx5e_mpwqe_get_log_num_strides(mdev, params);
2006 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2007 log_cq_size = params->log_rq_mtu_frames;
2010 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2011 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2012 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2013 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2016 mlx5e_build_common_cq_param(priv, param);
2017 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2020 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2021 struct mlx5e_params *params,
2022 struct mlx5e_cq_param *param)
2024 void *cqc = param->cqc;
2026 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2028 mlx5e_build_common_cq_param(priv, param);
2029 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2032 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2034 struct mlx5e_cq_param *param)
2036 void *cqc = param->cqc;
2038 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2040 mlx5e_build_common_cq_param(priv, param);
2042 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2045 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2047 struct mlx5e_sq_param *param)
2049 void *sqc = param->sqc;
2050 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2052 mlx5e_build_sq_param_common(priv, param);
2054 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2055 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2058 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2059 struct mlx5e_params *params,
2060 struct mlx5e_sq_param *param)
2062 void *sqc = param->sqc;
2063 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2065 mlx5e_build_sq_param_common(priv, param);
2066 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2069 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2070 struct mlx5e_params *params,
2071 struct mlx5e_channel_param *cparam)
2073 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2075 mlx5e_build_rq_param(priv, params, &cparam->rq);
2076 mlx5e_build_sq_param(priv, params, &cparam->sq);
2077 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2078 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2079 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2080 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2081 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2084 int mlx5e_open_channels(struct mlx5e_priv *priv,
2085 struct mlx5e_channels *chs)
2087 struct mlx5e_channel_param *cparam;
2091 chs->num = chs->params.num_channels;
2093 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2094 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2095 if (!chs->c || !cparam)
2098 mlx5e_build_channel_param(priv, &chs->params, cparam);
2099 for (i = 0; i < chs->num; i++) {
2100 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2102 goto err_close_channels;
2109 for (i--; i >= 0; i--)
2110 mlx5e_close_channel(chs->c[i]);
2119 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2123 for (i = 0; i < chs->num; i++)
2124 mlx5e_activate_channel(chs->c[i]);
2127 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2132 for (i = 0; i < chs->num; i++)
2133 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2136 return err ? -ETIMEDOUT : 0;
2139 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2143 for (i = 0; i < chs->num; i++)
2144 mlx5e_deactivate_channel(chs->c[i]);
2147 void mlx5e_close_channels(struct mlx5e_channels *chs)
2151 for (i = 0; i < chs->num; i++)
2152 mlx5e_close_channel(chs->c[i]);
2159 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2161 struct mlx5_core_dev *mdev = priv->mdev;
2168 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2169 in = kvzalloc(inlen, GFP_KERNEL);
2173 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2175 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2176 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2178 for (i = 0; i < sz; i++)
2179 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2181 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2183 rqt->enabled = true;
2189 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2191 rqt->enabled = false;
2192 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2195 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2197 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2200 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2202 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2206 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2208 struct mlx5e_rqt *rqt;
2212 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2213 rqt = &priv->direct_tir[ix].rqt;
2214 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2216 goto err_destroy_rqts;
2222 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2223 for (ix--; ix >= 0; ix--)
2224 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2229 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2233 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2234 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2237 static int mlx5e_rx_hash_fn(int hfunc)
2239 return (hfunc == ETH_RSS_HASH_TOP) ?
2240 MLX5_RX_HASH_FN_TOEPLITZ :
2241 MLX5_RX_HASH_FN_INVERTED_XOR8;
2244 int mlx5e_bits_invert(unsigned long a, int size)
2249 for (i = 0; i < size; i++)
2250 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2255 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2256 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2260 for (i = 0; i < sz; i++) {
2266 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2267 ix = mlx5e_bits_invert(i, ilog2(sz));
2269 ix = priv->channels.params.indirection_rqt[ix];
2270 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2274 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2278 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2279 struct mlx5e_redirect_rqt_param rrp)
2281 struct mlx5_core_dev *mdev = priv->mdev;
2287 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2288 in = kvzalloc(inlen, GFP_KERNEL);
2292 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2294 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2295 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2296 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2297 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2303 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2304 struct mlx5e_redirect_rqt_param rrp)
2309 if (ix >= rrp.rss.channels->num)
2310 return priv->drop_rq.rqn;
2312 return rrp.rss.channels->c[ix]->rq.rqn;
2315 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2316 struct mlx5e_redirect_rqt_param rrp)
2321 if (priv->indir_rqt.enabled) {
2323 rqtn = priv->indir_rqt.rqtn;
2324 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2327 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2328 struct mlx5e_redirect_rqt_param direct_rrp = {
2331 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2335 /* Direct RQ Tables */
2336 if (!priv->direct_tir[ix].rqt.enabled)
2339 rqtn = priv->direct_tir[ix].rqt.rqtn;
2340 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2344 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2345 struct mlx5e_channels *chs)
2347 struct mlx5e_redirect_rqt_param rrp = {
2352 .hfunc = chs->params.rss_hfunc,
2357 mlx5e_redirect_rqts(priv, rrp);
2360 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2362 struct mlx5e_redirect_rqt_param drop_rrp = {
2365 .rqn = priv->drop_rq.rqn,
2369 mlx5e_redirect_rqts(priv, drop_rrp);
2372 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2374 if (!params->lro_en)
2377 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2379 MLX5_SET(tirc, tirc, lro_enable_mask,
2380 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2381 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2382 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2383 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2384 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2387 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2388 enum mlx5e_traffic_types tt,
2389 void *tirc, bool inner)
2391 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2392 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2394 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2395 MLX5_HASH_FIELD_SEL_DST_IP)
2397 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2398 MLX5_HASH_FIELD_SEL_DST_IP |\
2399 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2400 MLX5_HASH_FIELD_SEL_L4_DPORT)
2402 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2403 MLX5_HASH_FIELD_SEL_DST_IP |\
2404 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2406 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2407 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2408 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2409 rx_hash_toeplitz_key);
2410 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2411 rx_hash_toeplitz_key);
2413 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2414 memcpy(rss_key, params->toeplitz_hash_key, len);
2418 case MLX5E_TT_IPV4_TCP:
2419 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2420 MLX5_L3_PROT_TYPE_IPV4);
2421 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2422 MLX5_L4_PROT_TYPE_TCP);
2423 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2424 MLX5_HASH_IP_L4PORTS);
2427 case MLX5E_TT_IPV6_TCP:
2428 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2429 MLX5_L3_PROT_TYPE_IPV6);
2430 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2431 MLX5_L4_PROT_TYPE_TCP);
2432 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2433 MLX5_HASH_IP_L4PORTS);
2436 case MLX5E_TT_IPV4_UDP:
2437 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2438 MLX5_L3_PROT_TYPE_IPV4);
2439 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2440 MLX5_L4_PROT_TYPE_UDP);
2441 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2442 MLX5_HASH_IP_L4PORTS);
2445 case MLX5E_TT_IPV6_UDP:
2446 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2447 MLX5_L3_PROT_TYPE_IPV6);
2448 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2449 MLX5_L4_PROT_TYPE_UDP);
2450 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2451 MLX5_HASH_IP_L4PORTS);
2454 case MLX5E_TT_IPV4_IPSEC_AH:
2455 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2456 MLX5_L3_PROT_TYPE_IPV4);
2457 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2458 MLX5_HASH_IP_IPSEC_SPI);
2461 case MLX5E_TT_IPV6_IPSEC_AH:
2462 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2463 MLX5_L3_PROT_TYPE_IPV6);
2464 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2465 MLX5_HASH_IP_IPSEC_SPI);
2468 case MLX5E_TT_IPV4_IPSEC_ESP:
2469 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2470 MLX5_L3_PROT_TYPE_IPV4);
2471 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2472 MLX5_HASH_IP_IPSEC_SPI);
2475 case MLX5E_TT_IPV6_IPSEC_ESP:
2476 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2477 MLX5_L3_PROT_TYPE_IPV6);
2478 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2479 MLX5_HASH_IP_IPSEC_SPI);
2483 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2484 MLX5_L3_PROT_TYPE_IPV4);
2485 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2490 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2491 MLX5_L3_PROT_TYPE_IPV6);
2492 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2496 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2500 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2502 struct mlx5_core_dev *mdev = priv->mdev;
2511 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2512 in = kvzalloc(inlen, GFP_KERNEL);
2516 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2517 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2519 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2521 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2522 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2528 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2529 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2541 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2542 enum mlx5e_traffic_types tt,
2545 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2547 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2549 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2550 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2551 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2553 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2556 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2557 struct mlx5e_params *params, u16 mtu)
2559 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2562 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2566 /* Update vport context MTU */
2567 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2571 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2572 struct mlx5e_params *params, u16 *mtu)
2577 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2578 if (err || !hw_mtu) /* fallback to port oper mtu */
2579 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2581 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2584 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2586 struct mlx5e_params *params = &priv->channels.params;
2587 struct net_device *netdev = priv->netdev;
2588 struct mlx5_core_dev *mdev = priv->mdev;
2592 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2596 mlx5e_query_mtu(mdev, params, &mtu);
2597 if (mtu != params->sw_mtu)
2598 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2599 __func__, mtu, params->sw_mtu);
2601 params->sw_mtu = mtu;
2605 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2607 struct mlx5e_priv *priv = netdev_priv(netdev);
2608 int nch = priv->channels.params.num_channels;
2609 int ntc = priv->channels.params.num_tc;
2612 netdev_reset_tc(netdev);
2617 netdev_set_num_tc(netdev, ntc);
2619 /* Map netdev TCs to offset 0
2620 * We have our own UP to TXQ mapping for QoS
2622 for (tc = 0; tc < ntc; tc++)
2623 netdev_set_tc_queue(netdev, tc, nch, 0);
2626 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2628 struct mlx5e_channel *c;
2629 struct mlx5e_txqsq *sq;
2632 for (i = 0; i < priv->channels.num; i++)
2633 for (tc = 0; tc < priv->profile->max_tc; tc++)
2634 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2636 for (i = 0; i < priv->channels.num; i++) {
2637 c = priv->channels.c[i];
2638 for (tc = 0; tc < c->num_tc; tc++) {
2640 priv->txq2sq[sq->txq_ix] = sq;
2645 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2647 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2648 struct net_device *netdev = priv->netdev;
2650 mlx5e_netdev_set_tcs(netdev);
2651 netif_set_real_num_tx_queues(netdev, num_txqs);
2652 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2654 mlx5e_build_channels_tx_maps(priv);
2655 mlx5e_activate_channels(&priv->channels);
2656 netif_tx_start_all_queues(priv->netdev);
2658 if (MLX5_VPORT_MANAGER(priv->mdev))
2659 mlx5e_add_sqs_fwd_rules(priv);
2661 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2662 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2665 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2667 mlx5e_redirect_rqts_to_drop(priv);
2669 if (MLX5_VPORT_MANAGER(priv->mdev))
2670 mlx5e_remove_sqs_fwd_rules(priv);
2672 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2673 * polling for inactive tx queues.
2675 netif_tx_stop_all_queues(priv->netdev);
2676 netif_tx_disable(priv->netdev);
2677 mlx5e_deactivate_channels(&priv->channels);
2680 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2681 struct mlx5e_channels *new_chs,
2682 mlx5e_fp_hw_modify hw_modify)
2684 struct net_device *netdev = priv->netdev;
2687 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2689 carrier_ok = netif_carrier_ok(netdev);
2690 netif_carrier_off(netdev);
2692 if (new_num_txqs < netdev->real_num_tx_queues)
2693 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2695 mlx5e_deactivate_priv_channels(priv);
2696 mlx5e_close_channels(&priv->channels);
2698 priv->channels = *new_chs;
2700 /* New channels are ready to roll, modify HW settings if needed */
2704 mlx5e_refresh_tirs(priv, false);
2705 mlx5e_activate_priv_channels(priv);
2707 /* return carrier back if needed */
2709 netif_carrier_on(netdev);
2712 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2714 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2715 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2718 int mlx5e_open_locked(struct net_device *netdev)
2720 struct mlx5e_priv *priv = netdev_priv(netdev);
2723 set_bit(MLX5E_STATE_OPENED, &priv->state);
2725 err = mlx5e_open_channels(priv, &priv->channels);
2727 goto err_clear_state_opened_flag;
2729 mlx5e_refresh_tirs(priv, false);
2730 mlx5e_activate_priv_channels(priv);
2731 if (priv->profile->update_carrier)
2732 priv->profile->update_carrier(priv);
2734 if (priv->profile->update_stats)
2735 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2739 err_clear_state_opened_flag:
2740 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2744 int mlx5e_open(struct net_device *netdev)
2746 struct mlx5e_priv *priv = netdev_priv(netdev);
2749 mutex_lock(&priv->state_lock);
2750 err = mlx5e_open_locked(netdev);
2752 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2753 mutex_unlock(&priv->state_lock);
2755 if (mlx5e_vxlan_allowed(priv->mdev))
2756 udp_tunnel_get_rx_info(netdev);
2761 int mlx5e_close_locked(struct net_device *netdev)
2763 struct mlx5e_priv *priv = netdev_priv(netdev);
2765 /* May already be CLOSED in case a previous configuration operation
2766 * (e.g RX/TX queue size change) that involves close&open failed.
2768 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2771 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2773 netif_carrier_off(priv->netdev);
2774 mlx5e_deactivate_priv_channels(priv);
2775 mlx5e_close_channels(&priv->channels);
2780 int mlx5e_close(struct net_device *netdev)
2782 struct mlx5e_priv *priv = netdev_priv(netdev);
2785 if (!netif_device_present(netdev))
2788 mutex_lock(&priv->state_lock);
2789 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2790 err = mlx5e_close_locked(netdev);
2791 mutex_unlock(&priv->state_lock);
2796 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2797 struct mlx5e_rq *rq,
2798 struct mlx5e_rq_param *param)
2800 void *rqc = param->rqc;
2801 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2804 param->wq.db_numa_node = param->wq.buf_numa_node;
2806 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
2811 /* Mark as unused given "Drop-RQ" packets never reach XDP */
2812 xdp_rxq_info_unused(&rq->xdp_rxq);
2819 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2820 struct mlx5e_cq *cq,
2821 struct mlx5e_cq_param *param)
2823 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2824 param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev);
2826 return mlx5e_alloc_cq_common(mdev, param, cq);
2829 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2830 struct mlx5e_rq *drop_rq)
2832 struct mlx5_core_dev *mdev = priv->mdev;
2833 struct mlx5e_cq_param cq_param = {};
2834 struct mlx5e_rq_param rq_param = {};
2835 struct mlx5e_cq *cq = &drop_rq->cq;
2838 mlx5e_build_drop_rq_param(priv, &rq_param);
2840 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2844 err = mlx5e_create_cq(cq, &cq_param);
2848 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2850 goto err_destroy_cq;
2852 err = mlx5e_create_rq(drop_rq, &rq_param);
2856 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2858 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2863 mlx5e_free_rq(drop_rq);
2866 mlx5e_destroy_cq(cq);
2874 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2876 mlx5e_destroy_rq(drop_rq);
2877 mlx5e_free_rq(drop_rq);
2878 mlx5e_destroy_cq(&drop_rq->cq);
2879 mlx5e_free_cq(&drop_rq->cq);
2882 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2883 u32 underlay_qpn, u32 *tisn)
2885 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2886 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2888 MLX5_SET(tisc, tisc, prio, tc << 1);
2889 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2890 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2892 if (mlx5_lag_is_lacp_owner(mdev))
2893 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2895 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2898 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2900 mlx5_core_destroy_tis(mdev, tisn);
2903 int mlx5e_create_tises(struct mlx5e_priv *priv)
2908 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2909 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2911 goto err_close_tises;
2917 for (tc--; tc >= 0; tc--)
2918 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2923 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2927 for (tc = 0; tc < priv->profile->max_tc; tc++)
2928 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2931 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2932 enum mlx5e_traffic_types tt,
2935 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2937 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2939 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2940 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2941 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2944 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2946 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2948 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2950 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2951 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2952 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2955 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2957 struct mlx5e_tir *tir;
2965 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2966 in = kvzalloc(inlen, GFP_KERNEL);
2970 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2971 memset(in, 0, inlen);
2972 tir = &priv->indir_tir[tt];
2973 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2974 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2975 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2977 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2978 goto err_destroy_inner_tirs;
2982 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2985 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2986 memset(in, 0, inlen);
2987 tir = &priv->inner_indir_tir[i];
2988 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2989 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2990 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2992 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2993 goto err_destroy_inner_tirs;
3002 err_destroy_inner_tirs:
3003 for (i--; i >= 0; i--)
3004 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3006 for (tt--; tt >= 0; tt--)
3007 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3014 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3016 int nch = priv->profile->max_nch(priv->mdev);
3017 struct mlx5e_tir *tir;
3024 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3025 in = kvzalloc(inlen, GFP_KERNEL);
3029 for (ix = 0; ix < nch; ix++) {
3030 memset(in, 0, inlen);
3031 tir = &priv->direct_tir[ix];
3032 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3033 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3034 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3036 goto err_destroy_ch_tirs;
3043 err_destroy_ch_tirs:
3044 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3045 for (ix--; ix >= 0; ix--)
3046 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3053 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3057 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3058 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3060 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3063 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3064 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3067 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3069 int nch = priv->profile->max_nch(priv->mdev);
3072 for (i = 0; i < nch; i++)
3073 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3076 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3081 for (i = 0; i < chs->num; i++) {
3082 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3090 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3095 for (i = 0; i < chs->num; i++) {
3096 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3104 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3105 struct tc_mqprio_qopt *mqprio)
3107 struct mlx5e_priv *priv = netdev_priv(netdev);
3108 struct mlx5e_channels new_channels = {};
3109 u8 tc = mqprio->num_tc;
3112 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3114 if (tc && tc != MLX5E_MAX_NUM_TC)
3117 mutex_lock(&priv->state_lock);
3119 new_channels.params = priv->channels.params;
3120 new_channels.params.num_tc = tc ? tc : 1;
3122 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3123 priv->channels.params = new_channels.params;
3127 err = mlx5e_open_channels(priv, &new_channels);
3131 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3133 mutex_unlock(&priv->state_lock);
3137 #ifdef CONFIG_MLX5_ESWITCH
3138 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3139 struct tc_cls_flower_offload *cls_flower)
3141 switch (cls_flower->command) {
3142 case TC_CLSFLOWER_REPLACE:
3143 return mlx5e_configure_flower(priv, cls_flower);
3144 case TC_CLSFLOWER_DESTROY:
3145 return mlx5e_delete_flower(priv, cls_flower);
3146 case TC_CLSFLOWER_STATS:
3147 return mlx5e_stats_flower(priv, cls_flower);
3153 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3156 struct mlx5e_priv *priv = cb_priv;
3158 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3162 case TC_SETUP_CLSFLOWER:
3163 return mlx5e_setup_tc_cls_flower(priv, type_data);
3169 static int mlx5e_setup_tc_block(struct net_device *dev,
3170 struct tc_block_offload *f)
3172 struct mlx5e_priv *priv = netdev_priv(dev);
3174 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3177 switch (f->command) {
3179 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3181 case TC_BLOCK_UNBIND:
3182 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3191 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3195 #ifdef CONFIG_MLX5_ESWITCH
3196 case TC_SETUP_BLOCK:
3197 return mlx5e_setup_tc_block(dev, type_data);
3199 case TC_SETUP_QDISC_MQPRIO:
3200 return mlx5e_setup_tc_mqprio(dev, type_data);
3207 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3209 struct mlx5e_priv *priv = netdev_priv(dev);
3210 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3211 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3212 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3214 if (mlx5e_is_uplink_rep(priv)) {
3215 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3216 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3217 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3218 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3220 stats->rx_packets = sstats->rx_packets;
3221 stats->rx_bytes = sstats->rx_bytes;
3222 stats->tx_packets = sstats->tx_packets;
3223 stats->tx_bytes = sstats->tx_bytes;
3224 stats->tx_dropped = sstats->tx_queue_dropped;
3227 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3229 stats->rx_length_errors =
3230 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3231 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3232 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3233 stats->rx_crc_errors =
3234 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3235 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3236 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3237 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3238 stats->rx_frame_errors;
3239 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3241 /* vport multicast also counts packets that are dropped due to steering
3242 * or rx out of buffer
3245 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3248 static void mlx5e_set_rx_mode(struct net_device *dev)
3250 struct mlx5e_priv *priv = netdev_priv(dev);
3252 queue_work(priv->wq, &priv->set_rx_mode_work);
3255 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3257 struct mlx5e_priv *priv = netdev_priv(netdev);
3258 struct sockaddr *saddr = addr;
3260 if (!is_valid_ether_addr(saddr->sa_data))
3261 return -EADDRNOTAVAIL;
3263 netif_addr_lock_bh(netdev);
3264 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3265 netif_addr_unlock_bh(netdev);
3267 queue_work(priv->wq, &priv->set_rx_mode_work);
3272 #define MLX5E_SET_FEATURE(features, feature, enable) \
3275 *features |= feature; \
3277 *features &= ~feature; \
3280 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3282 static int set_feature_lro(struct net_device *netdev, bool enable)
3284 struct mlx5e_priv *priv = netdev_priv(netdev);
3285 struct mlx5_core_dev *mdev = priv->mdev;
3286 struct mlx5e_channels new_channels = {};
3287 struct mlx5e_params *old_params;
3291 mutex_lock(&priv->state_lock);
3293 old_params = &priv->channels.params;
3294 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3296 new_channels.params = *old_params;
3297 new_channels.params.lro_en = enable;
3299 if (old_params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) {
3300 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3301 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3306 *old_params = new_channels.params;
3307 err = mlx5e_modify_tirs_lro(priv);
3311 err = mlx5e_open_channels(priv, &new_channels);
3315 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3317 mutex_unlock(&priv->state_lock);
3321 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3323 struct mlx5e_priv *priv = netdev_priv(netdev);
3326 mlx5e_enable_cvlan_filter(priv);
3328 mlx5e_disable_cvlan_filter(priv);
3333 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3335 struct mlx5e_priv *priv = netdev_priv(netdev);
3337 if (!enable && mlx5e_tc_num_filters(priv)) {
3339 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3346 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3348 struct mlx5e_priv *priv = netdev_priv(netdev);
3349 struct mlx5_core_dev *mdev = priv->mdev;
3351 return mlx5_set_port_fcs(mdev, !enable);
3354 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3356 struct mlx5e_priv *priv = netdev_priv(netdev);
3359 mutex_lock(&priv->state_lock);
3361 priv->channels.params.scatter_fcs_en = enable;
3362 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3364 priv->channels.params.scatter_fcs_en = !enable;
3366 mutex_unlock(&priv->state_lock);
3371 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3373 struct mlx5e_priv *priv = netdev_priv(netdev);
3376 mutex_lock(&priv->state_lock);
3378 priv->channels.params.vlan_strip_disable = !enable;
3379 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3382 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3384 priv->channels.params.vlan_strip_disable = enable;
3387 mutex_unlock(&priv->state_lock);
3392 #ifdef CONFIG_RFS_ACCEL
3393 static int set_feature_arfs(struct net_device *netdev, bool enable)
3395 struct mlx5e_priv *priv = netdev_priv(netdev);
3399 err = mlx5e_arfs_enable(priv);
3401 err = mlx5e_arfs_disable(priv);
3407 static int mlx5e_handle_feature(struct net_device *netdev,
3408 netdev_features_t *features,
3409 netdev_features_t wanted_features,
3410 netdev_features_t feature,
3411 mlx5e_feature_handler feature_handler)
3413 netdev_features_t changes = wanted_features ^ netdev->features;
3414 bool enable = !!(wanted_features & feature);
3417 if (!(changes & feature))
3420 err = feature_handler(netdev, enable);
3422 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3423 enable ? "Enable" : "Disable", &feature, err);
3427 MLX5E_SET_FEATURE(features, feature, enable);
3431 static int mlx5e_set_features(struct net_device *netdev,
3432 netdev_features_t features)
3434 netdev_features_t oper_features = netdev->features;
3437 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3438 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3440 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3441 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3442 set_feature_cvlan_filter);
3443 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3444 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3445 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3446 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3447 #ifdef CONFIG_RFS_ACCEL
3448 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3452 netdev->features = oper_features;
3459 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3460 netdev_features_t features)
3462 struct mlx5e_priv *priv = netdev_priv(netdev);
3464 mutex_lock(&priv->state_lock);
3465 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3466 /* HW strips the outer C-tag header, this is a problem
3467 * for S-tag traffic.
3469 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3470 if (!priv->channels.params.vlan_strip_disable)
3471 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3473 mutex_unlock(&priv->state_lock);
3478 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3480 struct mlx5e_priv *priv = netdev_priv(netdev);
3481 struct mlx5e_channels new_channels = {};
3482 struct mlx5e_params *params;
3486 mutex_lock(&priv->state_lock);
3488 params = &priv->channels.params;
3490 reset = !params->lro_en;
3491 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3493 new_channels.params = *params;
3494 new_channels.params.sw_mtu = new_mtu;
3496 if (params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) {
3497 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3498 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3500 reset = reset && (ppw_old != ppw_new);
3504 params->sw_mtu = new_mtu;
3505 mlx5e_set_dev_port_mtu(priv);
3506 netdev->mtu = params->sw_mtu;
3510 err = mlx5e_open_channels(priv, &new_channels);
3514 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3515 netdev->mtu = new_channels.params.sw_mtu;
3518 mutex_unlock(&priv->state_lock);
3522 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3524 struct hwtstamp_config config;
3527 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3530 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3533 /* TX HW timestamp */
3534 switch (config.tx_type) {
3535 case HWTSTAMP_TX_OFF:
3536 case HWTSTAMP_TX_ON:
3542 mutex_lock(&priv->state_lock);
3543 /* RX HW timestamp */
3544 switch (config.rx_filter) {
3545 case HWTSTAMP_FILTER_NONE:
3546 /* Reset CQE compression to Admin default */
3547 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3549 case HWTSTAMP_FILTER_ALL:
3550 case HWTSTAMP_FILTER_SOME:
3551 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3552 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3553 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3554 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3555 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3556 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3557 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3558 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3559 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3560 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3561 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3562 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3563 case HWTSTAMP_FILTER_NTP_ALL:
3564 /* Disable CQE compression */
3565 netdev_warn(priv->netdev, "Disabling cqe compression");
3566 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3568 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3569 mutex_unlock(&priv->state_lock);
3572 config.rx_filter = HWTSTAMP_FILTER_ALL;
3575 mutex_unlock(&priv->state_lock);
3579 memcpy(&priv->tstamp, &config, sizeof(config));
3580 mutex_unlock(&priv->state_lock);
3582 return copy_to_user(ifr->ifr_data, &config,
3583 sizeof(config)) ? -EFAULT : 0;
3586 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3588 struct hwtstamp_config *cfg = &priv->tstamp;
3590 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3593 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3596 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3598 struct mlx5e_priv *priv = netdev_priv(dev);
3602 return mlx5e_hwstamp_set(priv, ifr);
3604 return mlx5e_hwstamp_get(priv, ifr);
3610 #ifdef CONFIG_MLX5_ESWITCH
3611 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3613 struct mlx5e_priv *priv = netdev_priv(dev);
3614 struct mlx5_core_dev *mdev = priv->mdev;
3616 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3619 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3622 struct mlx5e_priv *priv = netdev_priv(dev);
3623 struct mlx5_core_dev *mdev = priv->mdev;
3625 if (vlan_proto != htons(ETH_P_8021Q))
3626 return -EPROTONOSUPPORT;
3628 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3632 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3634 struct mlx5e_priv *priv = netdev_priv(dev);
3635 struct mlx5_core_dev *mdev = priv->mdev;
3637 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3640 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3642 struct mlx5e_priv *priv = netdev_priv(dev);
3643 struct mlx5_core_dev *mdev = priv->mdev;
3645 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3648 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3651 struct mlx5e_priv *priv = netdev_priv(dev);
3652 struct mlx5_core_dev *mdev = priv->mdev;
3654 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3655 max_tx_rate, min_tx_rate);
3658 static int mlx5_vport_link2ifla(u8 esw_link)
3661 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3662 return IFLA_VF_LINK_STATE_DISABLE;
3663 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3664 return IFLA_VF_LINK_STATE_ENABLE;
3666 return IFLA_VF_LINK_STATE_AUTO;
3669 static int mlx5_ifla_link2vport(u8 ifla_link)
3671 switch (ifla_link) {
3672 case IFLA_VF_LINK_STATE_DISABLE:
3673 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3674 case IFLA_VF_LINK_STATE_ENABLE:
3675 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3677 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3680 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3683 struct mlx5e_priv *priv = netdev_priv(dev);
3684 struct mlx5_core_dev *mdev = priv->mdev;
3686 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3687 mlx5_ifla_link2vport(link_state));
3690 static int mlx5e_get_vf_config(struct net_device *dev,
3691 int vf, struct ifla_vf_info *ivi)
3693 struct mlx5e_priv *priv = netdev_priv(dev);
3694 struct mlx5_core_dev *mdev = priv->mdev;
3697 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3700 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3704 static int mlx5e_get_vf_stats(struct net_device *dev,
3705 int vf, struct ifla_vf_stats *vf_stats)
3707 struct mlx5e_priv *priv = netdev_priv(dev);
3708 struct mlx5_core_dev *mdev = priv->mdev;
3710 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3715 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3716 struct udp_tunnel_info *ti)
3718 struct mlx5e_priv *priv = netdev_priv(netdev);
3720 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3723 if (!mlx5e_vxlan_allowed(priv->mdev))
3726 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3729 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3730 struct udp_tunnel_info *ti)
3732 struct mlx5e_priv *priv = netdev_priv(netdev);
3734 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3737 if (!mlx5e_vxlan_allowed(priv->mdev))
3740 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3743 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3744 struct sk_buff *skb,
3745 netdev_features_t features)
3747 unsigned int offset = 0;
3748 struct udphdr *udph;
3752 switch (vlan_get_protocol(skb)) {
3753 case htons(ETH_P_IP):
3754 proto = ip_hdr(skb)->protocol;
3756 case htons(ETH_P_IPV6):
3757 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3767 udph = udp_hdr(skb);
3768 port = be16_to_cpu(udph->dest);
3770 /* Verify if UDP port is being offloaded by HW */
3771 if (mlx5e_vxlan_lookup_port(priv, port))
3776 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3777 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3780 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3781 struct net_device *netdev,
3782 netdev_features_t features)
3784 struct mlx5e_priv *priv = netdev_priv(netdev);
3786 features = vlan_features_check(skb, features);
3787 features = vxlan_features_check(skb, features);
3789 #ifdef CONFIG_MLX5_EN_IPSEC
3790 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3794 /* Validate if the tunneled packet is being offloaded by HW */
3795 if (skb->encapsulation &&
3796 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3797 return mlx5e_tunnel_features_check(priv, skb, features);
3802 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
3803 struct mlx5e_txqsq *sq)
3805 struct mlx5_eq *eq = sq->cq.mcq.eq;
3808 netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
3809 eq->eqn, eq->cons_index, eq->irqn);
3811 eqe_count = mlx5_eq_poll_irq_disabled(eq);
3815 netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
3816 sq->channel->stats.eq_rearm++;
3820 static void mlx5e_tx_timeout_work(struct work_struct *work)
3822 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
3824 struct net_device *dev = priv->netdev;
3825 bool reopen_channels = false;
3829 mutex_lock(&priv->state_lock);
3831 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3834 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3835 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
3836 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3838 if (!netif_xmit_stopped(dev_queue))
3842 "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
3843 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
3844 jiffies_to_usecs(jiffies - dev_queue->trans_start));
3846 /* If we recover a lost interrupt, most likely TX timeout will
3847 * be resolved, skip reopening channels
3849 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
3850 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3851 reopen_channels = true;
3855 if (!reopen_channels)
3858 mlx5e_close_locked(dev);
3859 err = mlx5e_open_locked(dev);
3861 netdev_err(priv->netdev,
3862 "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
3866 mutex_unlock(&priv->state_lock);
3870 static void mlx5e_tx_timeout(struct net_device *dev)
3872 struct mlx5e_priv *priv = netdev_priv(dev);
3874 netdev_err(dev, "TX timeout detected\n");
3875 queue_work(priv->wq, &priv->tx_timeout_work);
3878 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3880 struct mlx5e_priv *priv = netdev_priv(netdev);
3881 struct bpf_prog *old_prog;
3883 bool reset, was_opened;
3886 mutex_lock(&priv->state_lock);
3888 if ((netdev->features & NETIF_F_LRO) && prog) {
3889 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3894 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3895 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3900 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3901 /* no need for full reset when exchanging programs */
3902 reset = (!priv->channels.params.xdp_prog || !prog);
3904 if (was_opened && reset)
3905 mlx5e_close_locked(netdev);
3906 if (was_opened && !reset) {
3907 /* num_channels is invariant here, so we can take the
3908 * batched reference right upfront.
3910 prog = bpf_prog_add(prog, priv->channels.num);
3912 err = PTR_ERR(prog);
3917 /* exchange programs, extra prog reference we got from caller
3918 * as long as we don't fail from this point onwards.
3920 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3922 bpf_prog_put(old_prog);
3924 if (reset) /* change RQ type according to priv->xdp_prog */
3925 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
3927 if (was_opened && reset)
3928 mlx5e_open_locked(netdev);
3930 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3933 /* exchanging programs w/o reset, we update ref counts on behalf
3934 * of the channels RQs here.
3936 for (i = 0; i < priv->channels.num; i++) {
3937 struct mlx5e_channel *c = priv->channels.c[i];
3939 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3940 napi_synchronize(&c->napi);
3941 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3943 old_prog = xchg(&c->rq.xdp_prog, prog);
3945 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3946 /* napi_schedule in case we have missed anything */
3947 napi_schedule(&c->napi);
3950 bpf_prog_put(old_prog);
3954 mutex_unlock(&priv->state_lock);
3958 static u32 mlx5e_xdp_query(struct net_device *dev)
3960 struct mlx5e_priv *priv = netdev_priv(dev);
3961 const struct bpf_prog *xdp_prog;
3964 mutex_lock(&priv->state_lock);
3965 xdp_prog = priv->channels.params.xdp_prog;
3967 prog_id = xdp_prog->aux->id;
3968 mutex_unlock(&priv->state_lock);
3973 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3975 switch (xdp->command) {
3976 case XDP_SETUP_PROG:
3977 return mlx5e_xdp_set(dev, xdp->prog);
3978 case XDP_QUERY_PROG:
3979 xdp->prog_id = mlx5e_xdp_query(dev);
3980 xdp->prog_attached = !!xdp->prog_id;
3987 #ifdef CONFIG_NET_POLL_CONTROLLER
3988 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3989 * reenabling interrupts.
3991 static void mlx5e_netpoll(struct net_device *dev)
3993 struct mlx5e_priv *priv = netdev_priv(dev);
3994 struct mlx5e_channels *chs = &priv->channels;
3998 for (i = 0; i < chs->num; i++)
3999 napi_schedule(&chs->c[i]->napi);
4003 static const struct net_device_ops mlx5e_netdev_ops = {
4004 .ndo_open = mlx5e_open,
4005 .ndo_stop = mlx5e_close,
4006 .ndo_start_xmit = mlx5e_xmit,
4007 .ndo_setup_tc = mlx5e_setup_tc,
4008 .ndo_select_queue = mlx5e_select_queue,
4009 .ndo_get_stats64 = mlx5e_get_stats,
4010 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4011 .ndo_set_mac_address = mlx5e_set_mac,
4012 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4013 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4014 .ndo_set_features = mlx5e_set_features,
4015 .ndo_fix_features = mlx5e_fix_features,
4016 .ndo_change_mtu = mlx5e_change_mtu,
4017 .ndo_do_ioctl = mlx5e_ioctl,
4018 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4019 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
4020 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
4021 .ndo_features_check = mlx5e_features_check,
4022 #ifdef CONFIG_RFS_ACCEL
4023 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4025 .ndo_tx_timeout = mlx5e_tx_timeout,
4026 .ndo_bpf = mlx5e_xdp,
4027 #ifdef CONFIG_NET_POLL_CONTROLLER
4028 .ndo_poll_controller = mlx5e_netpoll,
4030 #ifdef CONFIG_MLX5_ESWITCH
4031 /* SRIOV E-Switch NDOs */
4032 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4033 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4034 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4035 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4036 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4037 .ndo_get_vf_config = mlx5e_get_vf_config,
4038 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4039 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4040 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4041 .ndo_get_offload_stats = mlx5e_get_offload_stats,
4045 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4047 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4049 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4050 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4051 !MLX5_CAP_ETH(mdev, csum_cap) ||
4052 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4053 !MLX5_CAP_ETH(mdev, vlan_cap) ||
4054 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4055 MLX5_CAP_FLOWTABLE(mdev,
4056 flow_table_properties_nic_receive.max_ft_level)
4058 mlx5_core_warn(mdev,
4059 "Not creating net device, some required device capabilities are missing\n");
4062 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4063 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4064 if (!MLX5_CAP_GEN(mdev, cq_moderation))
4065 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4070 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4075 for (i = 0; i < len; i++)
4076 indirection_rqt[i] = i % num_channels;
4079 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4084 mlx5e_get_max_linkspeed(mdev, &link_speed);
4085 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4086 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4087 link_speed, pci_bw);
4089 #define MLX5E_SLOW_PCI_RATIO (2)
4091 return link_speed && pci_bw &&
4092 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4095 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4097 struct net_dim_cq_moder moder;
4099 moder.cq_period_mode = cq_period_mode;
4100 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4101 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4102 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4103 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4108 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4110 struct net_dim_cq_moder moder;
4112 moder.cq_period_mode = cq_period_mode;
4113 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4114 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4115 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4116 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4121 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4123 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4124 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4125 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4128 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4130 if (params->tx_dim_enabled) {
4131 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4133 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4135 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4138 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4139 params->tx_cq_moderation.cq_period_mode ==
4140 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4143 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4145 if (params->rx_dim_enabled) {
4146 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4148 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4150 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4153 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4154 params->rx_cq_moderation.cq_period_mode ==
4155 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4158 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4162 /* The supported periods are organized in ascending order */
4163 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4164 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4167 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4170 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4171 struct mlx5e_params *params,
4172 u16 max_channels, u16 mtu)
4174 u8 rx_cq_period_mode;
4176 params->sw_mtu = mtu;
4177 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4178 params->num_channels = max_channels;
4182 params->log_sq_size = is_kdump_kernel() ?
4183 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4184 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4186 /* set CQE compression */
4187 params->rx_cqe_compress_def = false;
4188 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4189 MLX5_CAP_GEN(mdev, vport_group_manager))
4190 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4192 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4195 if (mlx5e_striding_rq_possible(mdev, params))
4196 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ,
4197 !slow_pci_heuristic(mdev));
4198 mlx5e_set_rq_type(mdev, params);
4199 mlx5e_init_rq_type_params(mdev, params);
4203 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4204 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4205 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4206 params->lro_en = !slow_pci_heuristic(mdev);
4207 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4209 /* CQ moderation params */
4210 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4211 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4212 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4213 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4214 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4215 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4216 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4219 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4222 params->rss_hfunc = ETH_RSS_HASH_XOR;
4223 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4224 mlx5e_build_default_indir_rqt(params->indirection_rqt,
4225 MLX5E_INDIR_RQT_SIZE, max_channels);
4228 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4229 struct net_device *netdev,
4230 const struct mlx5e_profile *profile,
4233 struct mlx5e_priv *priv = netdev_priv(netdev);
4236 priv->netdev = netdev;
4237 priv->profile = profile;
4238 priv->ppriv = ppriv;
4239 priv->msglevel = MLX5E_MSG_LEVEL;
4241 mlx5e_build_nic_params(mdev, &priv->channels.params,
4242 profile->max_nch(mdev), netdev->mtu);
4244 mutex_init(&priv->state_lock);
4246 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4247 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4248 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4249 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4251 mlx5e_timestamp_init(priv);
4254 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4256 struct mlx5e_priv *priv = netdev_priv(netdev);
4258 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4259 if (is_zero_ether_addr(netdev->dev_addr) &&
4260 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4261 eth_hw_addr_random(netdev);
4262 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4266 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4267 static const struct switchdev_ops mlx5e_switchdev_ops = {
4268 .switchdev_port_attr_get = mlx5e_attr_get,
4272 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4274 struct mlx5e_priv *priv = netdev_priv(netdev);
4275 struct mlx5_core_dev *mdev = priv->mdev;
4279 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4281 netdev->netdev_ops = &mlx5e_netdev_ops;
4283 #ifdef CONFIG_MLX5_CORE_EN_DCB
4284 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4285 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4288 netdev->watchdog_timeo = 15 * HZ;
4290 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4292 netdev->vlan_features |= NETIF_F_SG;
4293 netdev->vlan_features |= NETIF_F_IP_CSUM;
4294 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4295 netdev->vlan_features |= NETIF_F_GRO;
4296 netdev->vlan_features |= NETIF_F_TSO;
4297 netdev->vlan_features |= NETIF_F_TSO6;
4298 netdev->vlan_features |= NETIF_F_RXCSUM;
4299 netdev->vlan_features |= NETIF_F_RXHASH;
4301 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4302 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4304 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4305 netdev->vlan_features |= NETIF_F_LRO;
4307 netdev->hw_features = netdev->vlan_features;
4308 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4309 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4310 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4311 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4313 if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4314 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4315 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4316 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4317 netdev->hw_enc_features |= NETIF_F_TSO;
4318 netdev->hw_enc_features |= NETIF_F_TSO6;
4319 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4322 if (mlx5e_vxlan_allowed(mdev)) {
4323 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4324 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4325 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4326 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4327 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4330 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4331 netdev->hw_features |= NETIF_F_GSO_GRE |
4332 NETIF_F_GSO_GRE_CSUM;
4333 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4334 NETIF_F_GSO_GRE_CSUM;
4335 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4336 NETIF_F_GSO_GRE_CSUM;
4339 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4342 netdev->hw_features |= NETIF_F_RXALL;
4344 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4345 netdev->hw_features |= NETIF_F_RXFCS;
4347 netdev->features = netdev->hw_features;
4348 if (!priv->channels.params.lro_en)
4349 netdev->features &= ~NETIF_F_LRO;
4352 netdev->features &= ~NETIF_F_RXALL;
4354 if (!priv->channels.params.scatter_fcs_en)
4355 netdev->features &= ~NETIF_F_RXFCS;
4357 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4358 if (FT_CAP(flow_modify_en) &&
4359 FT_CAP(modify_root) &&
4360 FT_CAP(identified_miss_table_mode) &&
4361 FT_CAP(flow_table_modify)) {
4362 netdev->hw_features |= NETIF_F_HW_TC;
4363 #ifdef CONFIG_RFS_ACCEL
4364 netdev->hw_features |= NETIF_F_NTUPLE;
4368 netdev->features |= NETIF_F_HIGHDMA;
4369 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4371 netdev->priv_flags |= IFF_UNICAST_FLT;
4373 mlx5e_set_netdev_dev_addr(netdev);
4375 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4376 if (MLX5_VPORT_MANAGER(mdev))
4377 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4380 mlx5e_ipsec_build_netdev(priv);
4381 mlx5e_tls_build_netdev(priv);
4384 static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4386 struct mlx5_core_dev *mdev = priv->mdev;
4389 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4391 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4392 priv->q_counter = 0;
4395 err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4397 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4398 priv->drop_rq_q_counter = 0;
4402 static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4404 if (priv->q_counter)
4405 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4407 if (priv->drop_rq_q_counter)
4408 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4411 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4412 struct net_device *netdev,
4413 const struct mlx5e_profile *profile,
4416 struct mlx5e_priv *priv = netdev_priv(netdev);
4419 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4420 err = mlx5e_ipsec_init(priv);
4422 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4423 err = mlx5e_tls_init(priv);
4425 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4426 mlx5e_build_nic_netdev(netdev);
4427 mlx5e_vxlan_init(priv);
4430 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4432 mlx5e_tls_cleanup(priv);
4433 mlx5e_ipsec_cleanup(priv);
4434 mlx5e_vxlan_cleanup(priv);
4437 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4439 struct mlx5_core_dev *mdev = priv->mdev;
4442 err = mlx5e_create_indirect_rqt(priv);
4446 err = mlx5e_create_direct_rqts(priv);
4448 goto err_destroy_indirect_rqts;
4450 err = mlx5e_create_indirect_tirs(priv);
4452 goto err_destroy_direct_rqts;
4454 err = mlx5e_create_direct_tirs(priv);
4456 goto err_destroy_indirect_tirs;
4458 err = mlx5e_create_flow_steering(priv);
4460 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4461 goto err_destroy_direct_tirs;
4464 err = mlx5e_tc_init(priv);
4466 goto err_destroy_flow_steering;
4470 err_destroy_flow_steering:
4471 mlx5e_destroy_flow_steering(priv);
4472 err_destroy_direct_tirs:
4473 mlx5e_destroy_direct_tirs(priv);
4474 err_destroy_indirect_tirs:
4475 mlx5e_destroy_indirect_tirs(priv);
4476 err_destroy_direct_rqts:
4477 mlx5e_destroy_direct_rqts(priv);
4478 err_destroy_indirect_rqts:
4479 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4483 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4485 mlx5e_tc_cleanup(priv);
4486 mlx5e_destroy_flow_steering(priv);
4487 mlx5e_destroy_direct_tirs(priv);
4488 mlx5e_destroy_indirect_tirs(priv);
4489 mlx5e_destroy_direct_rqts(priv);
4490 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4493 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4497 err = mlx5e_create_tises(priv);
4499 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4503 #ifdef CONFIG_MLX5_CORE_EN_DCB
4504 mlx5e_dcbnl_initialize(priv);
4509 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4511 struct net_device *netdev = priv->netdev;
4512 struct mlx5_core_dev *mdev = priv->mdev;
4515 mlx5e_init_l2_addr(priv);
4517 /* Marking the link as currently not needed by the Driver */
4518 if (!netif_running(netdev))
4519 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4521 /* MTU range: 68 - hw-specific max */
4522 netdev->min_mtu = ETH_MIN_MTU;
4523 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4524 netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4525 mlx5e_set_dev_port_mtu(priv);
4527 mlx5_lag_add(mdev, netdev);
4529 mlx5e_enable_async_events(priv);
4531 if (MLX5_VPORT_MANAGER(priv->mdev))
4532 mlx5e_register_vport_reps(priv);
4534 if (netdev->reg_state != NETREG_REGISTERED)
4536 #ifdef CONFIG_MLX5_CORE_EN_DCB
4537 mlx5e_dcbnl_init_app(priv);
4540 queue_work(priv->wq, &priv->set_rx_mode_work);
4543 if (netif_running(netdev))
4545 netif_device_attach(netdev);
4549 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4551 struct mlx5_core_dev *mdev = priv->mdev;
4553 #ifdef CONFIG_MLX5_CORE_EN_DCB
4554 if (priv->netdev->reg_state == NETREG_REGISTERED)
4555 mlx5e_dcbnl_delete_app(priv);
4559 if (netif_running(priv->netdev))
4560 mlx5e_close(priv->netdev);
4561 netif_device_detach(priv->netdev);
4564 queue_work(priv->wq, &priv->set_rx_mode_work);
4566 if (MLX5_VPORT_MANAGER(priv->mdev))
4567 mlx5e_unregister_vport_reps(priv);
4569 mlx5e_disable_async_events(priv);
4570 mlx5_lag_remove(mdev);
4573 static const struct mlx5e_profile mlx5e_nic_profile = {
4574 .init = mlx5e_nic_init,
4575 .cleanup = mlx5e_nic_cleanup,
4576 .init_rx = mlx5e_init_nic_rx,
4577 .cleanup_rx = mlx5e_cleanup_nic_rx,
4578 .init_tx = mlx5e_init_nic_tx,
4579 .cleanup_tx = mlx5e_cleanup_nic_tx,
4580 .enable = mlx5e_nic_enable,
4581 .disable = mlx5e_nic_disable,
4582 .update_stats = mlx5e_update_ndo_stats,
4583 .max_nch = mlx5e_get_max_num_channels,
4584 .update_carrier = mlx5e_update_carrier,
4585 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4586 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4587 .max_tc = MLX5E_MAX_NUM_TC,
4590 /* mlx5e generic netdev management API (move to en_common.c) */
4592 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4593 const struct mlx5e_profile *profile,
4596 int nch = profile->max_nch(mdev);
4597 struct net_device *netdev;
4598 struct mlx5e_priv *priv;
4600 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4601 nch * profile->max_tc,
4604 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4608 #ifdef CONFIG_RFS_ACCEL
4609 netdev->rx_cpu_rmap = mdev->rmap;
4612 profile->init(mdev, netdev, profile, ppriv);
4614 netif_carrier_off(netdev);
4616 priv = netdev_priv(netdev);
4618 priv->wq = create_singlethread_workqueue("mlx5e");
4620 goto err_cleanup_nic;
4625 if (profile->cleanup)
4626 profile->cleanup(priv);
4627 free_netdev(netdev);
4632 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4634 struct mlx5_core_dev *mdev = priv->mdev;
4635 const struct mlx5e_profile *profile;
4638 profile = priv->profile;
4639 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4641 err = profile->init_tx(priv);
4645 mlx5e_create_q_counters(priv);
4647 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4649 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4650 goto err_destroy_q_counters;
4653 err = profile->init_rx(priv);
4655 goto err_close_drop_rq;
4657 if (profile->enable)
4658 profile->enable(priv);
4663 mlx5e_close_drop_rq(&priv->drop_rq);
4665 err_destroy_q_counters:
4666 mlx5e_destroy_q_counters(priv);
4667 profile->cleanup_tx(priv);
4673 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4675 const struct mlx5e_profile *profile = priv->profile;
4677 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4679 if (profile->disable)
4680 profile->disable(priv);
4681 flush_workqueue(priv->wq);
4683 profile->cleanup_rx(priv);
4684 mlx5e_close_drop_rq(&priv->drop_rq);
4685 mlx5e_destroy_q_counters(priv);
4686 profile->cleanup_tx(priv);
4687 cancel_delayed_work_sync(&priv->update_stats_work);
4690 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4692 const struct mlx5e_profile *profile = priv->profile;
4693 struct net_device *netdev = priv->netdev;
4695 destroy_workqueue(priv->wq);
4696 if (profile->cleanup)
4697 profile->cleanup(priv);
4698 free_netdev(netdev);
4701 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4702 * hardware contexts and to connect it to the current netdev.
4704 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4706 struct mlx5e_priv *priv = vpriv;
4707 struct net_device *netdev = priv->netdev;
4710 if (netif_device_present(netdev))
4713 err = mlx5e_create_mdev_resources(mdev);
4717 err = mlx5e_attach_netdev(priv);
4719 mlx5e_destroy_mdev_resources(mdev);
4726 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4728 struct mlx5e_priv *priv = vpriv;
4729 struct net_device *netdev = priv->netdev;
4731 if (!netif_device_present(netdev))
4734 mlx5e_detach_netdev(priv);
4735 mlx5e_destroy_mdev_resources(mdev);
4738 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4740 struct net_device *netdev;
4745 err = mlx5e_check_required_hca_cap(mdev);
4749 #ifdef CONFIG_MLX5_ESWITCH
4750 if (MLX5_VPORT_MANAGER(mdev)) {
4751 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4753 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4759 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4761 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4762 goto err_free_rpriv;
4765 priv = netdev_priv(netdev);
4767 err = mlx5e_attach(mdev, priv);
4769 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4770 goto err_destroy_netdev;
4773 err = register_netdev(netdev);
4775 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4779 #ifdef CONFIG_MLX5_CORE_EN_DCB
4780 mlx5e_dcbnl_init_app(priv);
4785 mlx5e_detach(mdev, priv);
4787 mlx5e_destroy_netdev(priv);
4793 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4795 struct mlx5e_priv *priv = vpriv;
4796 void *ppriv = priv->ppriv;
4798 #ifdef CONFIG_MLX5_CORE_EN_DCB
4799 mlx5e_dcbnl_delete_app(priv);
4801 unregister_netdev(priv->netdev);
4802 mlx5e_detach(mdev, vpriv);
4803 mlx5e_destroy_netdev(priv);
4807 static void *mlx5e_get_netdev(void *vpriv)
4809 struct mlx5e_priv *priv = vpriv;
4811 return priv->netdev;
4814 static struct mlx5_interface mlx5e_interface = {
4816 .remove = mlx5e_remove,
4817 .attach = mlx5e_attach,
4818 .detach = mlx5e_detach,
4819 .event = mlx5e_async_event,
4820 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4821 .get_dev = mlx5e_get_netdev,
4824 void mlx5e_init(void)
4826 mlx5e_ipsec_build_inverse_table();
4827 mlx5e_build_ptys2ethtool_map();
4828 mlx5_register_interface(&mlx5e_interface);
4831 void mlx5e_cleanup(void)
4833 mlx5_unregister_interface(&mlx5e_interface);