drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include <net/page_pool.h>
  39 #include "eswitch.h"
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "en_rep.h"
  43 #include "en_accel/ipsec.h"
  44 #include "en_accel/ipsec_rxtx.h"
  45 #include "en_accel/tls.h"
  46 #include "accel/ipsec.h"
  47 #include "accel/tls.h"
  48 #include "vxlan.h"
  49 #include "en/port.h"
  50 #include "en/xdp.h"
  51
  52 struct mlx5e_rq_param {
  53         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  54         struct mlx5_wq_param    wq;
  55         struct mlx5e_rq_frags_info frags_info;
  56 };
  57
  58 struct mlx5e_sq_param {
  59         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  60         struct mlx5_wq_param       wq;
  61 };
  62
  63 struct mlx5e_cq_param {
  64         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  65         struct mlx5_wq_param       wq;
  66         u16                        eq_ix;
  67         u8                         cq_period_mode;
  68 };
  69
  70 struct mlx5e_channel_param {
  71         struct mlx5e_rq_param      rq;
  72         struct mlx5e_sq_param      sq;
  73         struct mlx5e_sq_param      xdp_sq;
  74         struct mlx5e_sq_param      icosq;
  75         struct mlx5e_cq_param      rx_cq;
  76         struct mlx5e_cq_param      tx_cq;
  77         struct mlx5e_cq_param      icosq_cq;
  78 };
  79
  80 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  81 {
  82         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  83                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  84                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  85         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  86         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  87
  88         if (!striding_rq_umr)
  89                 return false;
  90         if (!inline_umr) {
  91                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  92                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  93                 return false;
  94         }
  95         return true;
  96 }
  97
  98 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
  99 {
 100         u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 101         u16 linear_rq_headroom = params->xdp_prog ?
 102                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 103         u32 frag_sz;
 104
 105         linear_rq_headroom += NET_IP_ALIGN;
 106
 107         frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
 108
 109         if (params->xdp_prog && frag_sz < PAGE_SIZE)
 110                 frag_sz = PAGE_SIZE;
 111
 112         return frag_sz;
 113 }
 114
 115 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 116 {
 117         u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 118
 119         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 120 }
 121
 122 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
 123                                    struct mlx5e_params *params)
 124 {
 125         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 126
 127         return !params->lro_en && frag_sz <= PAGE_SIZE;
 128 }
 129
 130 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 131                                          struct mlx5e_params *params)
 132 {
 133         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 134         s8 signed_log_num_strides_param;
 135         u8 log_num_strides;
 136
 137         if (!mlx5e_rx_is_linear_skb(mdev, params))
 138                 return false;
 139
 140         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 141                 return true;
 142
 143         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 144         signed_log_num_strides_param =
 145                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 146
 147         return signed_log_num_strides_param >= 0;
 148 }
 149
 150 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 151 {
 152         if (params->log_rq_mtu_frames <
 153             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 154                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 155
 156         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 157 }
 158
 159 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 160                                           struct mlx5e_params *params)
 161 {
 162         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 163                 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
 164
 165         return MLX5E_MPWQE_STRIDE_SZ(mdev,
 166                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 167 }
 168
 169 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 170                                           struct mlx5e_params *params)
 171 {
 172         return MLX5_MPWRQ_LOG_WQE_SZ -
 173                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 174 }
 175
 176 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 177                                  struct mlx5e_params *params)
 178 {
 179         u16 linear_rq_headroom = params->xdp_prog ?
 180                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 181         bool is_linear_skb;
 182
 183         linear_rq_headroom += NET_IP_ALIGN;
 184
 185         is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
 186                 mlx5e_rx_is_linear_skb(mdev, params) :
 187                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
 188
 189         return is_linear_skb ? linear_rq_headroom : 0;
 190 }
 191
 192 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 193                                struct mlx5e_params *params)
 194 {
 195         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 196         params->log_rq_mtu_frames = is_kdump_kernel() ?
 197                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 198                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 199
 200         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 201                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 202                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 203                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 204                        BIT(params->log_rq_mtu_frames),
 205                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 206                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 207 }
 208
 209 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 210                                 struct mlx5e_params *params)
 211 {
 212         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 213                 !MLX5_IPSEC_DEV(mdev) &&
 214                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 215 }
 216
 217 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 218 {
 219         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 220                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 221                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 222                 MLX5_WQ_TYPE_CYCLIC;
 223 }
 224
 225 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 226 {
 227         struct mlx5_core_dev *mdev = priv->mdev;
 228         u8 port_state;
 229
 230         port_state = mlx5_query_vport_state(mdev,
 231                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
 232                                             0);
 233
 234         if (port_state == VPORT_STATE_UP) {
 235                 netdev_info(priv->netdev, "Link up\n");
 236                 netif_carrier_on(priv->netdev);
 237         } else {
 238                 netdev_info(priv->netdev, "Link down\n");
 239                 netif_carrier_off(priv->netdev);
 240         }
 241 }
 242
 243 static void mlx5e_update_carrier_work(struct work_struct *work)
 244 {
 245         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 246                                                update_carrier_work);
 247
 248         mutex_lock(&priv->state_lock);
 249         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 250                 if (priv->profile->update_carrier)
 251                         priv->profile->update_carrier(priv);
 252         mutex_unlock(&priv->state_lock);
 253 }
 254
 255 void mlx5e_update_stats(struct mlx5e_priv *priv)
 256 {
 257         int i;
 258
 259         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 260                 if (mlx5e_stats_grps[i].update_stats)
 261                         mlx5e_stats_grps[i].update_stats(priv);
 262 }
 263
 264 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 265 {
 266         int i;
 267
 268         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 269                 if (mlx5e_stats_grps[i].update_stats_mask &
 270                     MLX5E_NDO_UPDATE_STATS)
 271                         mlx5e_stats_grps[i].update_stats(priv);
 272 }
 273
 274 void mlx5e_update_stats_work(struct work_struct *work)
 275 {
 276         struct delayed_work *dwork = to_delayed_work(work);
 277         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 278                                                update_stats_work);
 279
 280         mutex_lock(&priv->state_lock);
 281         priv->profile->update_stats(priv);
 282         mutex_unlock(&priv->state_lock);
 283 }
 284
 285 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 286                               enum mlx5_dev_event event, unsigned long param)
 287 {
 288         struct mlx5e_priv *priv = vpriv;
 289
 290         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 291                 return;
 292
 293         switch (event) {
 294         case MLX5_DEV_EVENT_PORT_UP:
 295         case MLX5_DEV_EVENT_PORT_DOWN:
 296                 queue_work(priv->wq, &priv->update_carrier_work);
 297                 break;
 298         default:
 299                 break;
 300         }
 301 }
 302
 303 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 304 {
 305         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 306 }
 307
 308 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 309 {
 310         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 311         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 312 }
 313
 314 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 315                                        struct mlx5e_icosq *sq,
 316                                        struct mlx5e_umr_wqe *wqe)
 317 {
 318         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 319         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 320         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 321
 322         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 323                                       ds_cnt);
 324         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 325         cseg->imm       = rq->mkey_be;
 326
 327         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 328         ucseg->xlt_octowords =
 329                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 330         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 331 }
 332
 333 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 334 {
 335         switch (rq->wq_type) {
 336         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 337                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 338         default:
 339                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 340         }
 341 }
 342
 343 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 344 {
 345         switch (rq->wq_type) {
 346         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 347                 return rq->mpwqe.wq.cur_sz;
 348         default:
 349                 return rq->wqe.wq.cur_sz;
 350         }
 351 }
 352
 353 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 354                                      struct mlx5e_channel *c)
 355 {
 356         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 357
 358         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 359                                                   sizeof(*rq->mpwqe.info)),
 360                                        GFP_KERNEL, cpu_to_node(c->cpu));
 361         if (!rq->mpwqe.info)
 362                 return -ENOMEM;
 363
 364         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 365
 366         return 0;
 367 }
 368
 369 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 370                                  u64 npages, u8 page_shift,
 371                                  struct mlx5_core_mkey *umr_mkey)
 372 {
 373         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 374         void *mkc;
 375         u32 *in;
 376         int err;
 377
 378         in = kvzalloc(inlen, GFP_KERNEL);
 379         if (!in)
 380                 return -ENOMEM;
 381
 382         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 383
 384         MLX5_SET(mkc, mkc, free, 1);
 385         MLX5_SET(mkc, mkc, umr_en, 1);
 386         MLX5_SET(mkc, mkc, lw, 1);
 387         MLX5_SET(mkc, mkc, lr, 1);
 388         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 389
 390         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 391         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 392         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 393         MLX5_SET(mkc, mkc, translations_octword_size,
 394                  MLX5_MTT_OCTW(npages));
 395         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 396
 397         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 398
 399         kvfree(in);
 400         return err;
 401 }
 402
 403 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 404 {
 405         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 406
 407         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 408 }
 409
 410 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 411 {
 412         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 413 }
 414
 415 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 416 {
 417         struct mlx5e_wqe_frag_info next_frag, *prev;
 418         int i;
 419
 420         next_frag.di = &rq->wqe.di[0];
 421         next_frag.offset = 0;
 422         prev = NULL;
 423
 424         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 425                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 426                 struct mlx5e_wqe_frag_info *frag =
 427                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 428                 int f;
 429
 430                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 431                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 432                                 next_frag.di++;
 433                                 next_frag.offset = 0;
 434                                 if (prev)
 435                                         prev->last_in_page = true;
 436                         }
 437                         *frag = next_frag;
 438
 439                         /* prepare next */
 440                         next_frag.offset += frag_info[f].frag_stride;
 441                         prev = frag;
 442                 }
 443         }
 444
 445         if (prev)
 446                 prev->last_in_page = true;
 447 }
 448
 449 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 450                               struct mlx5e_params *params,
 451                               int wq_sz, int cpu)
 452 {
 453         int len = wq_sz << rq->wqe.info.log_num_frags;
 454
 455         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 456                                    GFP_KERNEL, cpu_to_node(cpu));
 457         if (!rq->wqe.di)
 458                 return -ENOMEM;
 459
 460         mlx5e_init_frags_partition(rq);
 461
 462         return 0;
 463 }
 464
 465 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 466 {
 467         kvfree(rq->wqe.di);
 468 }
 469
 470 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 471                           struct mlx5e_params *params,
 472                           struct mlx5e_rq_param *rqp,
 473                           struct mlx5e_rq *rq)
 474 {
 475         struct page_pool_params pp_params = { 0 };
 476         struct mlx5_core_dev *mdev = c->mdev;
 477         void *rqc = rqp->rqc;
 478         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 479         u32 pool_size;
 480         int wq_sz;
 481         int err;
 482         int i;
 483
 484         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 485
 486         rq->wq_type = params->rq_wq_type;
 487         rq->pdev    = c->pdev;
 488         rq->netdev  = c->netdev;
 489         rq->tstamp  = c->tstamp;
 490         rq->clock   = &mdev->clock;
 491         rq->channel = c;
 492         rq->ix      = c->ix;
 493         rq->mdev    = mdev;
 494         rq->stats   = &c->priv->channel_stats[c->ix].rq;
 495
 496         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 497         if (IS_ERR(rq->xdp_prog)) {
 498                 err = PTR_ERR(rq->xdp_prog);
 499                 rq->xdp_prog = NULL;
 500                 goto err_rq_wq_destroy;
 501         }
 502
 503         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 504         if (err < 0)
 505                 goto err_rq_wq_destroy;
 506
 507         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 508         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 509         pool_size = 1 << params->log_rq_mtu_frames;
 510
 511         switch (rq->wq_type) {
 512         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 513                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 514                                         &rq->wq_ctrl);
 515                 if (err)
 516                         return err;
 517
 518                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 519
 520                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 521
 522                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 523
 524                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 525                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 526
 527                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 528 #ifdef CONFIG_MLX5_EN_IPSEC
 529                 if (MLX5_IPSEC_DEV(mdev)) {
 530                         err = -EINVAL;
 531                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 532                         goto err_rq_wq_destroy;
 533                 }
 534 #endif
 535                 if (!rq->handle_rx_cqe) {
 536                         err = -EINVAL;
 537                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 538                         goto err_rq_wq_destroy;
 539                 }
 540
 541                 rq->mpwqe.skb_from_cqe_mpwrq =
 542                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 543                         mlx5e_skb_from_cqe_mpwrq_linear :
 544                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 545                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 546                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 547
 548                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 549                 if (err)
 550                         goto err_rq_wq_destroy;
 551                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 552
 553                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 554                 if (err)
 555                         goto err_free;
 556                 break;
 557         default: /* MLX5_WQ_TYPE_CYCLIC */
 558                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 559                                          &rq->wq_ctrl);
 560                 if (err)
 561                         return err;
 562
 563                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 564
 565                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 566
 567                 rq->wqe.info = rqp->frags_info;
 568                 rq->wqe.frags =
 569                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 570                                         (wq_sz << rq->wqe.info.log_num_frags)),
 571                                       GFP_KERNEL, cpu_to_node(c->cpu));
 572                 if (!rq->wqe.frags) {
 573                         err = -ENOMEM;
 574                         goto err_free;
 575                 }
 576
 577                 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
 578                 if (err)
 579                         goto err_free;
 580                 rq->post_wqes = mlx5e_post_rx_wqes;
 581                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 582
 583 #ifdef CONFIG_MLX5_EN_IPSEC
 584                 if (c->priv->ipsec)
 585                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 586                 else
 587 #endif
 588                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 589                 if (!rq->handle_rx_cqe) {
 590                         err = -EINVAL;
 591                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 592                         goto err_free;
 593                 }
 594
 595                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
 596                         mlx5e_skb_from_cqe_linear :
 597                         mlx5e_skb_from_cqe_nonlinear;
 598                 rq->mkey_be = c->mkey_be;
 599         }
 600
 601         /* Create a page_pool and register it with rxq */
 602         pp_params.order     = 0;
 603         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 604         pp_params.pool_size = pool_size;
 605         pp_params.nid       = cpu_to_node(c->cpu);
 606         pp_params.dev       = c->pdev;
 607         pp_params.dma_dir   = rq->buff.map_dir;
 608
 609         /* page_pool can be used even when there is no rq->xdp_prog,
 610          * given page_pool does not handle DMA mapping there is no
 611          * required state to clear. And page_pool gracefully handle
 612          * elevated refcnt.
 613          */
 614         rq->page_pool = page_pool_create(&pp_params);
 615         if (IS_ERR(rq->page_pool)) {
 616                 err = PTR_ERR(rq->page_pool);
 617                 rq->page_pool = NULL;
 618                 goto err_free;
 619         }
 620         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 621                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 622         if (err)
 623                 goto err_free;
 624
 625         for (i = 0; i < wq_sz; i++) {
 626                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 627                         struct mlx5e_rx_wqe_ll *wqe =
 628                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 629                         u32 byte_count =
 630                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 631                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 632
 633                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 634                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 635                         wqe->data[0].lkey = rq->mkey_be;
 636                 } else {
 637                         struct mlx5e_rx_wqe_cyc *wqe =
 638                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 639                         int f;
 640
 641                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 642                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 643                                         MLX5_HW_START_PADDING;
 644
 645                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 646                                 wqe->data[f].lkey = rq->mkey_be;
 647                         }
 648                         /* check if num_frags is not a pow of two */
 649                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 650                                 wqe->data[f].byte_count = 0;
 651                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 652                                 wqe->data[f].addr = 0;
 653                         }
 654                 }
 655         }
 656
 657         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 658
 659         switch (params->rx_cq_moderation.cq_period_mode) {
 660         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 661                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 662                 break;
 663         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 664         default:
 665                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 666         }
 667
 668         rq->page_cache.head = 0;
 669         rq->page_cache.tail = 0;
 670
 671         return 0;
 672
 673 err_free:
 674         switch (rq->wq_type) {
 675         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 676                 kvfree(rq->mpwqe.info);
 677                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 678                 break;
 679         default: /* MLX5_WQ_TYPE_CYCLIC */
 680                 kvfree(rq->wqe.frags);
 681                 mlx5e_free_di_list(rq);
 682         }
 683
 684 err_rq_wq_destroy:
 685         if (rq->xdp_prog)
 686                 bpf_prog_put(rq->xdp_prog);
 687         xdp_rxq_info_unreg(&rq->xdp_rxq);
 688         if (rq->page_pool)
 689                 page_pool_destroy(rq->page_pool);
 690         mlx5_wq_destroy(&rq->wq_ctrl);
 691
 692         return err;
 693 }
 694
 695 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 696 {
 697         int i;
 698
 699         if (rq->xdp_prog)
 700                 bpf_prog_put(rq->xdp_prog);
 701
 702         xdp_rxq_info_unreg(&rq->xdp_rxq);
 703         if (rq->page_pool)
 704                 page_pool_destroy(rq->page_pool);
 705
 706         switch (rq->wq_type) {
 707         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 708                 kvfree(rq->mpwqe.info);
 709                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 710                 break;
 711         default: /* MLX5_WQ_TYPE_CYCLIC */
 712                 kvfree(rq->wqe.frags);
 713                 mlx5e_free_di_list(rq);
 714         }
 715
 716         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 717              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 718                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 719
 720                 mlx5e_page_release(rq, dma_info, false);
 721         }
 722         mlx5_wq_destroy(&rq->wq_ctrl);
 723 }
 724
 725 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 726                            struct mlx5e_rq_param *param)
 727 {
 728         struct mlx5_core_dev *mdev = rq->mdev;
 729
 730         void *in;
 731         void *rqc;
 732         void *wq;
 733         int inlen;
 734         int err;
 735
 736         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 737                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 738         in = kvzalloc(inlen, GFP_KERNEL);
 739         if (!in)
 740                 return -ENOMEM;
 741
 742         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 743         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 744
 745         memcpy(rqc, param->rqc, sizeof(param->rqc));
 746
 747         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 748         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 749         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 750                                                 MLX5_ADAPTER_PAGE_SHIFT);
 751         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 752
 753         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 754                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 755
 756         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 757
 758         kvfree(in);
 759
 760         return err;
 761 }
 762
 763 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 764                                  int next_state)
 765 {
 766         struct mlx5_core_dev *mdev = rq->mdev;
 767
 768         void *in;
 769         void *rqc;
 770         int inlen;
 771         int err;
 772
 773         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 774         in = kvzalloc(inlen, GFP_KERNEL);
 775         if (!in)
 776                 return -ENOMEM;
 777
 778         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 779
 780         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 781         MLX5_SET(rqc, rqc, state, next_state);
 782
 783         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 784
 785         kvfree(in);
 786
 787         return err;
 788 }
 789
 790 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 791 {
 792         struct mlx5e_channel *c = rq->channel;
 793         struct mlx5e_priv *priv = c->priv;
 794         struct mlx5_core_dev *mdev = priv->mdev;
 795
 796         void *in;
 797         void *rqc;
 798         int inlen;
 799         int err;
 800
 801         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 802         in = kvzalloc(inlen, GFP_KERNEL);
 803         if (!in)
 804                 return -ENOMEM;
 805
 806         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 807
 808         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 809         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 810                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 811         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 812         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 813
 814         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 815
 816         kvfree(in);
 817
 818         return err;
 819 }
 820
 821 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 822 {
 823         struct mlx5e_channel *c = rq->channel;
 824         struct mlx5_core_dev *mdev = c->mdev;
 825         void *in;
 826         void *rqc;
 827         int inlen;
 828         int err;
 829
 830         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 831         in = kvzalloc(inlen, GFP_KERNEL);
 832         if (!in)
 833                 return -ENOMEM;
 834
 835         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 836
 837         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 838         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 839                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 840         MLX5_SET(rqc, rqc, vsd, vsd);
 841         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 842
 843         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 844
 845         kvfree(in);
 846
 847         return err;
 848 }
 849
 850 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 851 {
 852         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 853 }
 854
 855 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 856 {
 857         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 858         struct mlx5e_channel *c = rq->channel;
 859
 860         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 861
 862         do {
 863                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 864                         return 0;
 865
 866                 msleep(20);
 867         } while (time_before(jiffies, exp_time));
 868
 869         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 870                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 871
 872         return -ETIMEDOUT;
 873 }
 874
 875 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 876 {
 877         __be16 wqe_ix_be;
 878         u16 wqe_ix;
 879
 880         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 881                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 882
 883                 /* UMR WQE (if in progress) is always at wq->head */
 884                 if (rq->mpwqe.umr_in_progress)
 885                         rq->dealloc_wqe(rq, wq->head);
 886
 887                 while (!mlx5_wq_ll_is_empty(wq)) {
 888                         struct mlx5e_rx_wqe_ll *wqe;
 889
 890                         wqe_ix_be = *wq->tail_next;
 891                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 892                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 893                         rq->dealloc_wqe(rq, wqe_ix);
 894                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 895                                        &wqe->next.next_wqe_index);
 896                 }
 897         } else {
 898                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 899
 900                 while (!mlx5_wq_cyc_is_empty(wq)) {
 901                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 902                         rq->dealloc_wqe(rq, wqe_ix);
 903                         mlx5_wq_cyc_pop(wq);
 904                 }
 905         }
 906
 907 }
 908
 909 static int mlx5e_open_rq(struct mlx5e_channel *c,
 910                          struct mlx5e_params *params,
 911                          struct mlx5e_rq_param *param,
 912                          struct mlx5e_rq *rq)
 913 {
 914         int err;
 915
 916         err = mlx5e_alloc_rq(c, params, param, rq);
 917         if (err)
 918                 return err;
 919
 920         err = mlx5e_create_rq(rq, param);
 921         if (err)
 922                 goto err_free_rq;
 923
 924         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 925         if (err)
 926                 goto err_destroy_rq;
 927
 928         if (params->rx_dim_enabled)
 929                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 930
 931         return 0;
 932
 933 err_destroy_rq:
 934         mlx5e_destroy_rq(rq);
 935 err_free_rq:
 936         mlx5e_free_rq(rq);
 937
 938         return err;
 939 }
 940
 941 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 942 {
 943         struct mlx5e_icosq *sq = &rq->channel->icosq;
 944         struct mlx5_wq_cyc *wq = &sq->wq;
 945         struct mlx5e_tx_wqe *nopwqe;
 946
 947         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 948
 949         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 950         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 951         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 952         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 953 }
 954
 955 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 956 {
 957         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 958         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 959 }
 960
 961 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 962 {
 963         cancel_work_sync(&rq->dim.work);
 964         mlx5e_destroy_rq(rq);
 965         mlx5e_free_rx_descs(rq);
 966         mlx5e_free_rq(rq);
 967 }
 968
 969 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 970 {
 971         kvfree(sq->db.xdpi);
 972 }
 973
 974 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 975 {
 976         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 977
 978         sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)),
 979                                     GFP_KERNEL, numa);
 980         if (!sq->db.xdpi) {
 981                 mlx5e_free_xdpsq_db(sq);
 982                 return -ENOMEM;
 983         }
 984
 985         return 0;
 986 }
 987
 988 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 989                              struct mlx5e_params *params,
 990                              struct mlx5e_sq_param *param,
 991                              struct mlx5e_xdpsq *sq,
 992                              bool is_redirect)
 993 {
 994         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 995         struct mlx5_core_dev *mdev = c->mdev;
 996         struct mlx5_wq_cyc *wq = &sq->wq;
 997         int err;
 998
 999         sq->pdev      = c->pdev;
1000         sq->mkey_be   = c->mkey_be;
1001         sq->channel   = c;
1002         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1003         sq->min_inline_mode = params->tx_min_inline_mode;
1004         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1005         sq->stats     = is_redirect ?
1006                 &c->priv->channel_stats[c->ix].xdpsq :
1007                 &c->priv->channel_stats[c->ix].rq_xdpsq;
1008
1009         param->wq.db_numa_node = cpu_to_node(c->cpu);
1010         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1011         if (err)
1012                 return err;
1013         wq->db = &wq->db[MLX5_SND_DBR];
1014
1015         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1016         if (err)
1017                 goto err_sq_wq_destroy;
1018
1019         return 0;
1020
1021 err_sq_wq_destroy:
1022         mlx5_wq_destroy(&sq->wq_ctrl);
1023
1024         return err;
1025 }
1026
1027 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1028 {
1029         mlx5e_free_xdpsq_db(sq);
1030         mlx5_wq_destroy(&sq->wq_ctrl);
1031 }
1032
1033 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1034 {
1035         kvfree(sq->db.ico_wqe);
1036 }
1037
1038 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1039 {
1040         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1041
1042         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1043                                                   sizeof(*sq->db.ico_wqe)),
1044                                        GFP_KERNEL, numa);
1045         if (!sq->db.ico_wqe)
1046                 return -ENOMEM;
1047
1048         return 0;
1049 }
1050
1051 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1052                              struct mlx5e_sq_param *param,
1053                              struct mlx5e_icosq *sq)
1054 {
1055         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1056         struct mlx5_core_dev *mdev = c->mdev;
1057         struct mlx5_wq_cyc *wq = &sq->wq;
1058         int err;
1059
1060         sq->channel   = c;
1061         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1062
1063         param->wq.db_numa_node = cpu_to_node(c->cpu);
1064         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1065         if (err)
1066                 return err;
1067         wq->db = &wq->db[MLX5_SND_DBR];
1068
1069         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1070         if (err)
1071                 goto err_sq_wq_destroy;
1072
1073         return 0;
1074
1075 err_sq_wq_destroy:
1076         mlx5_wq_destroy(&sq->wq_ctrl);
1077
1078         return err;
1079 }
1080
1081 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1082 {
1083         mlx5e_free_icosq_db(sq);
1084         mlx5_wq_destroy(&sq->wq_ctrl);
1085 }
1086
1087 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1088 {
1089         kvfree(sq->db.wqe_info);
1090         kvfree(sq->db.dma_fifo);
1091 }
1092
1093 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1094 {
1095         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1096         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1097
1098         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1099                                                    sizeof(*sq->db.dma_fifo)),
1100                                         GFP_KERNEL, numa);
1101         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1102                                                    sizeof(*sq->db.wqe_info)),
1103                                         GFP_KERNEL, numa);
1104         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1105                 mlx5e_free_txqsq_db(sq);
1106                 return -ENOMEM;
1107         }
1108
1109         sq->dma_fifo_mask = df_sz - 1;
1110
1111         return 0;
1112 }
1113
1114 static void mlx5e_sq_recover(struct work_struct *work);
1115 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1116                              int txq_ix,
1117                              struct mlx5e_params *params,
1118                              struct mlx5e_sq_param *param,
1119                              struct mlx5e_txqsq *sq,
1120                              int tc)
1121 {
1122         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1123         struct mlx5_core_dev *mdev = c->mdev;
1124         struct mlx5_wq_cyc *wq = &sq->wq;
1125         int err;
1126
1127         sq->pdev      = c->pdev;
1128         sq->tstamp    = c->tstamp;
1129         sq->clock     = &mdev->clock;
1130         sq->mkey_be   = c->mkey_be;
1131         sq->channel   = c;
1132         sq->txq_ix    = txq_ix;
1133         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1134         sq->min_inline_mode = params->tx_min_inline_mode;
1135         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1136         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1137         if (MLX5_IPSEC_DEV(c->priv->mdev))
1138                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1139         if (mlx5_accel_is_tls_device(c->priv->mdev))
1140                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1141
1142         param->wq.db_numa_node = cpu_to_node(c->cpu);
1143         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1144         if (err)
1145                 return err;
1146         wq->db    = &wq->db[MLX5_SND_DBR];
1147
1148         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1149         if (err)
1150                 goto err_sq_wq_destroy;
1151
1152         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1153         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1154
1155         return 0;
1156
1157 err_sq_wq_destroy:
1158         mlx5_wq_destroy(&sq->wq_ctrl);
1159
1160         return err;
1161 }
1162
1163 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1164 {
1165         mlx5e_free_txqsq_db(sq);
1166         mlx5_wq_destroy(&sq->wq_ctrl);
1167 }
1168
1169 struct mlx5e_create_sq_param {
1170         struct mlx5_wq_ctrl        *wq_ctrl;
1171         u32                         cqn;
1172         u32                         tisn;
1173         u8                          tis_lst_sz;
1174         u8                          min_inline_mode;
1175 };
1176
1177 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1178                            struct mlx5e_sq_param *param,
1179                            struct mlx5e_create_sq_param *csp,
1180                            u32 *sqn)
1181 {
1182         void *in;
1183         void *sqc;
1184         void *wq;
1185         int inlen;
1186         int err;
1187
1188         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1189                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1190         in = kvzalloc(inlen, GFP_KERNEL);
1191         if (!in)
1192                 return -ENOMEM;
1193
1194         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1195         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1196
1197         memcpy(sqc, param->sqc, sizeof(param->sqc));
1198         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1199         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1200         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1201
1202         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1203                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1204
1205         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1206         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1207
1208         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1209         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1210         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1211                                           MLX5_ADAPTER_PAGE_SHIFT);
1212         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1213
1214         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1215                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1216
1217         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1218
1219         kvfree(in);
1220
1221         return err;
1222 }
1223
1224 struct mlx5e_modify_sq_param {
1225         int curr_state;
1226         int next_state;
1227         bool rl_update;
1228         int rl_index;
1229 };
1230
1231 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1232                            struct mlx5e_modify_sq_param *p)
1233 {
1234         void *in;
1235         void *sqc;
1236         int inlen;
1237         int err;
1238
1239         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1240         in = kvzalloc(inlen, GFP_KERNEL);
1241         if (!in)
1242                 return -ENOMEM;
1243
1244         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1245
1246         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1247         MLX5_SET(sqc, sqc, state, p->next_state);
1248         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1249                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1250                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1251         }
1252
1253         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1254
1255         kvfree(in);
1256
1257         return err;
1258 }
1259
1260 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1261 {
1262         mlx5_core_destroy_sq(mdev, sqn);
1263 }
1264
1265 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1266                                struct mlx5e_sq_param *param,
1267                                struct mlx5e_create_sq_param *csp,
1268                                u32 *sqn)
1269 {
1270         struct mlx5e_modify_sq_param msp = {0};
1271         int err;
1272
1273         err = mlx5e_create_sq(mdev, param, csp, sqn);
1274         if (err)
1275                 return err;
1276
1277         msp.curr_state = MLX5_SQC_STATE_RST;
1278         msp.next_state = MLX5_SQC_STATE_RDY;
1279         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1280         if (err)
1281                 mlx5e_destroy_sq(mdev, *sqn);
1282
1283         return err;
1284 }
1285
1286 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1287                                 struct mlx5e_txqsq *sq, u32 rate);
1288
1289 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1290                             u32 tisn,
1291                             int txq_ix,
1292                             struct mlx5e_params *params,
1293                             struct mlx5e_sq_param *param,
1294                             struct mlx5e_txqsq *sq,
1295                             int tc)
1296 {
1297         struct mlx5e_create_sq_param csp = {};
1298         u32 tx_rate;
1299         int err;
1300
1301         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1302         if (err)
1303                 return err;
1304
1305         csp.tisn            = tisn;
1306         csp.tis_lst_sz      = 1;
1307         csp.cqn             = sq->cq.mcq.cqn;
1308         csp.wq_ctrl         = &sq->wq_ctrl;
1309         csp.min_inline_mode = sq->min_inline_mode;
1310         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1311         if (err)
1312                 goto err_free_txqsq;
1313
1314         tx_rate = c->priv->tx_rates[sq->txq_ix];
1315         if (tx_rate)
1316                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1317
1318         if (params->tx_dim_enabled)
1319                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1320
1321         return 0;
1322
1323 err_free_txqsq:
1324         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1325         mlx5e_free_txqsq(sq);
1326
1327         return err;
1328 }
1329
1330 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1331 {
1332         WARN_ONCE(sq->cc != sq->pc,
1333                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1334                   sq->sqn, sq->cc, sq->pc);
1335         sq->cc = 0;
1336         sq->dma_fifo_cc = 0;
1337         sq->pc = 0;
1338 }
1339
1340 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1341 {
1342         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1343         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1344         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1345         netdev_tx_reset_queue(sq->txq);
1346         netif_tx_start_queue(sq->txq);
1347 }
1348
1349 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1350 {
1351         __netif_tx_lock_bh(txq);
1352         netif_tx_stop_queue(txq);
1353         __netif_tx_unlock_bh(txq);
1354 }
1355
1356 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1357 {
1358         struct mlx5e_channel *c = sq->channel;
1359         struct mlx5_wq_cyc *wq = &sq->wq;
1360
1361         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1362         /* prevent netif_tx_wake_queue */
1363         napi_synchronize(&c->napi);
1364
1365         netif_tx_disable_queue(sq->txq);
1366
1367         /* last doorbell out, godspeed .. */
1368         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1369                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1370                 struct mlx5e_tx_wqe *nop;
1371
1372                 sq->db.wqe_info[pi].skb = NULL;
1373                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1374                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1375         }
1376 }
1377
1378 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1379 {
1380         struct mlx5e_channel *c = sq->channel;
1381         struct mlx5_core_dev *mdev = c->mdev;
1382         struct mlx5_rate_limit rl = {0};
1383
1384         mlx5e_destroy_sq(mdev, sq->sqn);
1385         if (sq->rate_limit) {
1386                 rl.rate = sq->rate_limit;
1387                 mlx5_rl_remove_rate(mdev, &rl);
1388         }
1389         mlx5e_free_txqsq_descs(sq);
1390         mlx5e_free_txqsq(sq);
1391 }
1392
1393 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1394 {
1395         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1396
1397         while (time_before(jiffies, exp_time)) {
1398                 if (sq->cc == sq->pc)
1399                         return 0;
1400
1401                 msleep(20);
1402         }
1403
1404         netdev_err(sq->channel->netdev,
1405                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1406                    sq->sqn, sq->cc, sq->pc);
1407
1408         return -ETIMEDOUT;
1409 }
1410
1411 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1412 {
1413         struct mlx5_core_dev *mdev = sq->channel->mdev;
1414         struct net_device *dev = sq->channel->netdev;
1415         struct mlx5e_modify_sq_param msp = {0};
1416         int err;
1417
1418         msp.curr_state = curr_state;
1419         msp.next_state = MLX5_SQC_STATE_RST;
1420
1421         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1422         if (err) {
1423                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1424                 return err;
1425         }
1426
1427         memset(&msp, 0, sizeof(msp));
1428         msp.curr_state = MLX5_SQC_STATE_RST;
1429         msp.next_state = MLX5_SQC_STATE_RDY;
1430
1431         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1432         if (err) {
1433                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1434                 return err;
1435         }
1436
1437         return 0;
1438 }
1439
1440 static void mlx5e_sq_recover(struct work_struct *work)
1441 {
1442         struct mlx5e_txqsq_recover *recover =
1443                 container_of(work, struct mlx5e_txqsq_recover,
1444                              recover_work);
1445         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1446                                               recover);
1447         struct mlx5_core_dev *mdev = sq->channel->mdev;
1448         struct net_device *dev = sq->channel->netdev;
1449         u8 state;
1450         int err;
1451
1452         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1453         if (err) {
1454                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1455                            sq->sqn, err);
1456                 return;
1457         }
1458
1459         if (state != MLX5_RQC_STATE_ERR) {
1460                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1461                 return;
1462         }
1463
1464         netif_tx_disable_queue(sq->txq);
1465
1466         if (mlx5e_wait_for_sq_flush(sq))
1467                 return;
1468
1469         /* If the interval between two consecutive recovers per SQ is too
1470          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1471          * If we reached this state, there is probably a bug that needs to be
1472          * fixed. let's keep the queue close and let tx timeout cleanup.
1473          */
1474         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1475             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1476                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1477                            sq->sqn);
1478                 return;
1479         }
1480
1481         /* At this point, no new packets will arrive from the stack as TXQ is
1482          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1483          * pending WQEs.  SQ can safely reset the SQ.
1484          */
1485         if (mlx5e_sq_to_ready(sq, state))
1486                 return;
1487
1488         mlx5e_reset_txqsq_cc_pc(sq);
1489         sq->stats->recover++;
1490         recover->last_recover = jiffies;
1491         mlx5e_activate_txqsq(sq);
1492 }
1493
1494 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1495                             struct mlx5e_params *params,
1496                             struct mlx5e_sq_param *param,
1497                             struct mlx5e_icosq *sq)
1498 {
1499         struct mlx5e_create_sq_param csp = {};
1500         int err;
1501
1502         err = mlx5e_alloc_icosq(c, param, sq);
1503         if (err)
1504                 return err;
1505
1506         csp.cqn             = sq->cq.mcq.cqn;
1507         csp.wq_ctrl         = &sq->wq_ctrl;
1508         csp.min_inline_mode = params->tx_min_inline_mode;
1509         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1510         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1511         if (err)
1512                 goto err_free_icosq;
1513
1514         return 0;
1515
1516 err_free_icosq:
1517         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1518         mlx5e_free_icosq(sq);
1519
1520         return err;
1521 }
1522
1523 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1524 {
1525         struct mlx5e_channel *c = sq->channel;
1526
1527         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1528         napi_synchronize(&c->napi);
1529
1530         mlx5e_destroy_sq(c->mdev, sq->sqn);
1531         mlx5e_free_icosq(sq);
1532 }
1533
1534 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1535                             struct mlx5e_params *params,
1536                             struct mlx5e_sq_param *param,
1537                             struct mlx5e_xdpsq *sq,
1538                             bool is_redirect)
1539 {
1540         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1541         struct mlx5e_create_sq_param csp = {};
1542         unsigned int inline_hdr_sz = 0;
1543         int err;
1544         int i;
1545
1546         err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1547         if (err)
1548                 return err;
1549
1550         csp.tis_lst_sz      = 1;
1551         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1552         csp.cqn             = sq->cq.mcq.cqn;
1553         csp.wq_ctrl         = &sq->wq_ctrl;
1554         csp.min_inline_mode = sq->min_inline_mode;
1555         if (is_redirect)
1556                 set_bit(MLX5E_SQ_STATE_REDIRECT, &sq->state);
1557         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1558         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1559         if (err)
1560                 goto err_free_xdpsq;
1561
1562         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1563                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1564                 ds_cnt++;
1565         }
1566
1567         /* Pre initialize fixed WQE fields */
1568         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1569                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1570                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1571                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1572                 struct mlx5_wqe_data_seg *dseg;
1573
1574                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1575                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1576
1577                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1578                 dseg->lkey = sq->mkey_be;
1579         }
1580
1581         return 0;
1582
1583 err_free_xdpsq:
1584         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1585         mlx5e_free_xdpsq(sq);
1586
1587         return err;
1588 }
1589
1590 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1591 {
1592         struct mlx5e_channel *c = sq->channel;
1593
1594         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1595         napi_synchronize(&c->napi);
1596
1597         mlx5e_destroy_sq(c->mdev, sq->sqn);
1598         mlx5e_free_xdpsq_descs(sq);
1599         mlx5e_free_xdpsq(sq);
1600 }
1601
1602 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1603                                  struct mlx5e_cq_param *param,
1604                                  struct mlx5e_cq *cq)
1605 {
1606         struct mlx5_core_cq *mcq = &cq->mcq;
1607         int eqn_not_used;
1608         unsigned int irqn;
1609         int err;
1610         u32 i;
1611
1612         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1613                                &cq->wq_ctrl);
1614         if (err)
1615                 return err;
1616
1617         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1618
1619         mcq->cqe_sz     = 64;
1620         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1621         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1622         *mcq->set_ci_db = 0;
1623         *mcq->arm_db    = 0;
1624         mcq->vector     = param->eq_ix;
1625         mcq->comp       = mlx5e_completion_event;
1626         mcq->event      = mlx5e_cq_error_event;
1627         mcq->irqn       = irqn;
1628
1629         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1630                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1631
1632                 cqe->op_own = 0xf1;
1633         }
1634
1635         cq->mdev = mdev;
1636
1637         return 0;
1638 }
1639
1640 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1641                           struct mlx5e_cq_param *param,
1642                           struct mlx5e_cq *cq)
1643 {
1644         struct mlx5_core_dev *mdev = c->priv->mdev;
1645         int err;
1646
1647         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1648         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1649         param->eq_ix   = c->ix;
1650
1651         err = mlx5e_alloc_cq_common(mdev, param, cq);
1652
1653         cq->napi    = &c->napi;
1654         cq->channel = c;
1655
1656         return err;
1657 }
1658
1659 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1660 {
1661         mlx5_wq_destroy(&cq->wq_ctrl);
1662 }
1663
1664 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1665 {
1666         struct mlx5_core_dev *mdev = cq->mdev;
1667         struct mlx5_core_cq *mcq = &cq->mcq;
1668
1669         void *in;
1670         void *cqc;
1671         int inlen;
1672         unsigned int irqn_not_used;
1673         int eqn;
1674         int err;
1675
1676         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1677                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1678         in = kvzalloc(inlen, GFP_KERNEL);
1679         if (!in)
1680                 return -ENOMEM;
1681
1682         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1683
1684         memcpy(cqc, param->cqc, sizeof(param->cqc));
1685
1686         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1687                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1688
1689         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1690
1691         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1692         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1693         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1694         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1695                                             MLX5_ADAPTER_PAGE_SHIFT);
1696         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1697
1698         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1699
1700         kvfree(in);
1701
1702         if (err)
1703                 return err;
1704
1705         mlx5e_cq_arm(cq);
1706
1707         return 0;
1708 }
1709
1710 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1711 {
1712         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1713 }
1714
1715 static int mlx5e_open_cq(struct mlx5e_channel *c,
1716                          struct net_dim_cq_moder moder,
1717                          struct mlx5e_cq_param *param,
1718                          struct mlx5e_cq *cq)
1719 {
1720         struct mlx5_core_dev *mdev = c->mdev;
1721         int err;
1722
1723         err = mlx5e_alloc_cq(c, param, cq);
1724         if (err)
1725                 return err;
1726
1727         err = mlx5e_create_cq(cq, param);
1728         if (err)
1729                 goto err_free_cq;
1730
1731         if (MLX5_CAP_GEN(mdev, cq_moderation))
1732                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1733         return 0;
1734
1735 err_free_cq:
1736         mlx5e_free_cq(cq);
1737
1738         return err;
1739 }
1740
1741 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1742 {
1743         mlx5e_destroy_cq(cq);
1744         mlx5e_free_cq(cq);
1745 }
1746
1747 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1748 {
1749         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1750 }
1751
1752 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1753                              struct mlx5e_params *params,
1754                              struct mlx5e_channel_param *cparam)
1755 {
1756         int err;
1757         int tc;
1758
1759         for (tc = 0; tc < c->num_tc; tc++) {
1760                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1761                                     &cparam->tx_cq, &c->sq[tc].cq);
1762                 if (err)
1763                         goto err_close_tx_cqs;
1764         }
1765
1766         return 0;
1767
1768 err_close_tx_cqs:
1769         for (tc--; tc >= 0; tc--)
1770                 mlx5e_close_cq(&c->sq[tc].cq);
1771
1772         return err;
1773 }
1774
1775 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1776 {
1777         int tc;
1778
1779         for (tc = 0; tc < c->num_tc; tc++)
1780                 mlx5e_close_cq(&c->sq[tc].cq);
1781 }
1782
1783 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1784                           struct mlx5e_params *params,
1785                           struct mlx5e_channel_param *cparam)
1786 {
1787         struct mlx5e_priv *priv = c->priv;
1788         int err, tc, max_nch = priv->profile->max_nch(priv->mdev);
1789
1790         for (tc = 0; tc < params->num_tc; tc++) {
1791                 int txq_ix = c->ix + tc * max_nch;
1792
1793                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1794                                        params, &cparam->sq, &c->sq[tc], tc);
1795                 if (err)
1796                         goto err_close_sqs;
1797         }
1798
1799         return 0;
1800
1801 err_close_sqs:
1802         for (tc--; tc >= 0; tc--)
1803                 mlx5e_close_txqsq(&c->sq[tc]);
1804
1805         return err;
1806 }
1807
1808 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1809 {
1810         int tc;
1811
1812         for (tc = 0; tc < c->num_tc; tc++)
1813                 mlx5e_close_txqsq(&c->sq[tc]);
1814 }
1815
1816 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1817                                 struct mlx5e_txqsq *sq, u32 rate)
1818 {
1819         struct mlx5e_priv *priv = netdev_priv(dev);
1820         struct mlx5_core_dev *mdev = priv->mdev;
1821         struct mlx5e_modify_sq_param msp = {0};
1822         struct mlx5_rate_limit rl = {0};
1823         u16 rl_index = 0;
1824         int err;
1825
1826         if (rate == sq->rate_limit)
1827                 /* nothing to do */
1828                 return 0;
1829
1830         if (sq->rate_limit) {
1831                 rl.rate = sq->rate_limit;
1832                 /* remove current rl index to free space to next ones */
1833                 mlx5_rl_remove_rate(mdev, &rl);
1834         }
1835
1836         sq->rate_limit = 0;
1837
1838         if (rate) {
1839                 rl.rate = rate;
1840                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1841                 if (err) {
1842                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1843                                    rate, err);
1844                         return err;
1845                 }
1846         }
1847
1848         msp.curr_state = MLX5_SQC_STATE_RDY;
1849         msp.next_state = MLX5_SQC_STATE_RDY;
1850         msp.rl_index   = rl_index;
1851         msp.rl_update  = true;
1852         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1853         if (err) {
1854                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1855                            rate, err);
1856                 /* remove the rate from the table */
1857                 if (rate)
1858                         mlx5_rl_remove_rate(mdev, &rl);
1859                 return err;
1860         }
1861
1862         sq->rate_limit = rate;
1863         return 0;
1864 }
1865
1866 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1867 {
1868         struct mlx5e_priv *priv = netdev_priv(dev);
1869         struct mlx5_core_dev *mdev = priv->mdev;
1870         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1871         int err = 0;
1872
1873         if (!mlx5_rl_is_supported(mdev)) {
1874                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1875                 return -EINVAL;
1876         }
1877
1878         /* rate is given in Mb/sec, HW config is in Kb/sec */
1879         rate = rate << 10;
1880
1881         /* Check whether rate in valid range, 0 is always valid */
1882         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1883                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1884                 return -ERANGE;
1885         }
1886
1887         mutex_lock(&priv->state_lock);
1888         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1889                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1890         if (!err)
1891                 priv->tx_rates[index] = rate;
1892         mutex_unlock(&priv->state_lock);
1893
1894         return err;
1895 }
1896
1897 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1898                               struct mlx5e_params *params,
1899                               struct mlx5e_channel_param *cparam,
1900                               struct mlx5e_channel **cp)
1901 {
1902         struct net_dim_cq_moder icocq_moder = {0, 0};
1903         struct net_device *netdev = priv->netdev;
1904         int cpu = mlx5e_get_cpu(priv, ix);
1905         struct mlx5e_channel *c;
1906         unsigned int irq;
1907         int err;
1908         int eqn;
1909
1910         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1911         if (!c)
1912                 return -ENOMEM;
1913
1914         c->priv     = priv;
1915         c->mdev     = priv->mdev;
1916         c->tstamp   = &priv->tstamp;
1917         c->ix       = ix;
1918         c->cpu      = cpu;
1919         c->pdev     = &priv->mdev->pdev->dev;
1920         c->netdev   = priv->netdev;
1921         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1922         c->num_tc   = params->num_tc;
1923         c->xdp      = !!params->xdp_prog;
1924         c->stats    = &priv->channel_stats[ix].ch;
1925
1926         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1927         c->irq_desc = irq_to_desc(irq);
1928
1929         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1930
1931         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1932         if (err)
1933                 goto err_napi_del;
1934
1935         err = mlx5e_open_tx_cqs(c, params, cparam);
1936         if (err)
1937                 goto err_close_icosq_cq;
1938
1939         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1940         if (err)
1941                 goto err_close_tx_cqs;
1942
1943         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1944         if (err)
1945                 goto err_close_xdp_tx_cqs;
1946
1947         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1948         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1949                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1950         if (err)
1951                 goto err_close_rx_cq;
1952
1953         napi_enable(&c->napi);
1954
1955         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1956         if (err)
1957                 goto err_disable_napi;
1958
1959         err = mlx5e_open_sqs(c, params, cparam);
1960         if (err)
1961                 goto err_close_icosq;
1962
1963         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1964         if (err)
1965                 goto err_close_sqs;
1966
1967         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1968         if (err)
1969                 goto err_close_xdp_sq;
1970
1971         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1972         if (err)
1973                 goto err_close_rq;
1974
1975         *cp = c;
1976
1977         return 0;
1978
1979 err_close_rq:
1980         mlx5e_close_rq(&c->rq);
1981
1982 err_close_xdp_sq:
1983         if (c->xdp)
1984                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1985
1986 err_close_sqs:
1987         mlx5e_close_sqs(c);
1988
1989 err_close_icosq:
1990         mlx5e_close_icosq(&c->icosq);
1991
1992 err_disable_napi:
1993         napi_disable(&c->napi);
1994         if (c->xdp)
1995                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1996
1997 err_close_rx_cq:
1998         mlx5e_close_cq(&c->rq.cq);
1999
2000 err_close_xdp_tx_cqs:
2001         mlx5e_close_cq(&c->xdpsq.cq);
2002
2003 err_close_tx_cqs:
2004         mlx5e_close_tx_cqs(c);
2005
2006 err_close_icosq_cq:
2007         mlx5e_close_cq(&c->icosq.cq);
2008
2009 err_napi_del:
2010         netif_napi_del(&c->napi);
2011         kvfree(c);
2012
2013         return err;
2014 }
2015
2016 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2017 {
2018         int tc;
2019
2020         for (tc = 0; tc < c->num_tc; tc++)
2021                 mlx5e_activate_txqsq(&c->sq[tc]);
2022         mlx5e_activate_rq(&c->rq);
2023         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
2024 }
2025
2026 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2027 {
2028         int tc;
2029
2030         mlx5e_deactivate_rq(&c->rq);
2031         for (tc = 0; tc < c->num_tc; tc++)
2032                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2033 }
2034
2035 static void mlx5e_close_channel(struct mlx5e_channel *c)
2036 {
2037         mlx5e_close_xdpsq(&c->xdpsq);
2038         mlx5e_close_rq(&c->rq);
2039         if (c->xdp)
2040                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2041         mlx5e_close_sqs(c);
2042         mlx5e_close_icosq(&c->icosq);
2043         napi_disable(&c->napi);
2044         if (c->xdp)
2045                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2046         mlx5e_close_cq(&c->rq.cq);
2047         mlx5e_close_cq(&c->xdpsq.cq);
2048         mlx5e_close_tx_cqs(c);
2049         mlx5e_close_cq(&c->icosq.cq);
2050         netif_napi_del(&c->napi);
2051
2052         kvfree(c);
2053 }
2054
2055 #define DEFAULT_FRAG_SIZE (2048)
2056
2057 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2058                                       struct mlx5e_params *params,
2059                                       struct mlx5e_rq_frags_info *info)
2060 {
2061         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2062         int frag_size_max = DEFAULT_FRAG_SIZE;
2063         u32 buf_size = 0;
2064         int i;
2065
2066 #ifdef CONFIG_MLX5_EN_IPSEC
2067         if (MLX5_IPSEC_DEV(mdev))
2068                 byte_count += MLX5E_METADATA_ETHER_LEN;
2069 #endif
2070
2071         if (mlx5e_rx_is_linear_skb(mdev, params)) {
2072                 int frag_stride;
2073
2074                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2075                 frag_stride = roundup_pow_of_two(frag_stride);
2076
2077                 info->arr[0].frag_size = byte_count;
2078                 info->arr[0].frag_stride = frag_stride;
2079                 info->num_frags = 1;
2080                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2081                 goto out;
2082         }
2083
2084         if (byte_count > PAGE_SIZE +
2085             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2086                 frag_size_max = PAGE_SIZE;
2087
2088         i = 0;
2089         while (buf_size < byte_count) {
2090                 int frag_size = byte_count - buf_size;
2091
2092                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2093                         frag_size = min(frag_size, frag_size_max);
2094
2095                 info->arr[i].frag_size = frag_size;
2096                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2097
2098                 buf_size += frag_size;
2099                 i++;
2100         }
2101         info->num_frags = i;
2102         /* number of different wqes sharing a page */
2103         info->wqe_bulk = 1 + (info->num_frags % 2);
2104
2105 out:
2106         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2107         info->log_num_frags = order_base_2(info->num_frags);
2108 }
2109
2110 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2111 {
2112         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2113
2114         switch (wq_type) {
2115         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2116                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2117                 break;
2118         default: /* MLX5_WQ_TYPE_CYCLIC */
2119                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2120         }
2121
2122         return order_base_2(sz);
2123 }
2124
2125 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2126                                  struct mlx5e_params *params,
2127                                  struct mlx5e_rq_param *param)
2128 {
2129         struct mlx5_core_dev *mdev = priv->mdev;
2130         void *rqc = param->rqc;
2131         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2132         int ndsegs = 1;
2133
2134         switch (params->rq_wq_type) {
2135         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2136                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2137                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2138                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2139                 MLX5_SET(wq, wq, log_wqe_stride_size,
2140                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2141                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2142                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2143                 break;
2144         default: /* MLX5_WQ_TYPE_CYCLIC */
2145                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2146                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2147                 ndsegs = param->frags_info.num_frags;
2148         }
2149
2150         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2151         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2152         MLX5_SET(wq, wq, log_wq_stride,
2153                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2154         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2155         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2156         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2157         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2158
2159         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2160 }
2161
2162 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2163                                       struct mlx5e_rq_param *param)
2164 {
2165         struct mlx5_core_dev *mdev = priv->mdev;
2166         void *rqc = param->rqc;
2167         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2168
2169         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2170         MLX5_SET(wq, wq, log_wq_stride,
2171                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2172         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2173
2174         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2175 }
2176
2177 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2178                                         struct mlx5e_sq_param *param)
2179 {
2180         void *sqc = param->sqc;
2181         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2182
2183         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2184         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2185
2186         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2187 }
2188
2189 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2190                                  struct mlx5e_params *params,
2191                                  struct mlx5e_sq_param *param)
2192 {
2193         void *sqc = param->sqc;
2194         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2195
2196         mlx5e_build_sq_param_common(priv, param);
2197         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2198         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2199 }
2200
2201 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2202                                         struct mlx5e_cq_param *param)
2203 {
2204         void *cqc = param->cqc;
2205
2206         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2207 }
2208
2209 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2210                                     struct mlx5e_params *params,
2211                                     struct mlx5e_cq_param *param)
2212 {
2213         struct mlx5_core_dev *mdev = priv->mdev;
2214         void *cqc = param->cqc;
2215         u8 log_cq_size;
2216
2217         switch (params->rq_wq_type) {
2218         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2219                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2220                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2221                 break;
2222         default: /* MLX5_WQ_TYPE_CYCLIC */
2223                 log_cq_size = params->log_rq_mtu_frames;
2224         }
2225
2226         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2227         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2228                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2229                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2230         }
2231
2232         mlx5e_build_common_cq_param(priv, param);
2233         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2234 }
2235
2236 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2237                                     struct mlx5e_params *params,
2238                                     struct mlx5e_cq_param *param)
2239 {
2240         void *cqc = param->cqc;
2241
2242         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2243
2244         mlx5e_build_common_cq_param(priv, param);
2245         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2246 }
2247
2248 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2249                                      u8 log_wq_size,
2250                                      struct mlx5e_cq_param *param)
2251 {
2252         void *cqc = param->cqc;
2253
2254         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2255
2256         mlx5e_build_common_cq_param(priv, param);
2257
2258         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2259 }
2260
2261 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2262                                     u8 log_wq_size,
2263                                     struct mlx5e_sq_param *param)
2264 {
2265         void *sqc = param->sqc;
2266         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2267
2268         mlx5e_build_sq_param_common(priv, param);
2269
2270         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2271         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2272 }
2273
2274 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2275                                     struct mlx5e_params *params,
2276                                     struct mlx5e_sq_param *param)
2277 {
2278         void *sqc = param->sqc;
2279         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2280
2281         mlx5e_build_sq_param_common(priv, param);
2282         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2283 }
2284
2285 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2286                                       struct mlx5e_params *params,
2287                                       struct mlx5e_channel_param *cparam)
2288 {
2289         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2290
2291         mlx5e_build_rq_param(priv, params, &cparam->rq);
2292         mlx5e_build_sq_param(priv, params, &cparam->sq);
2293         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2294         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2295         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2296         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2297         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2298 }
2299
2300 int mlx5e_open_channels(struct mlx5e_priv *priv,
2301                         struct mlx5e_channels *chs)
2302 {
2303         struct mlx5e_channel_param *cparam;
2304         int err = -ENOMEM;
2305         int i;
2306
2307         chs->num = chs->params.num_channels;
2308
2309         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2310         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2311         if (!chs->c || !cparam)
2312                 goto err_free;
2313
2314         mlx5e_build_channel_param(priv, &chs->params, cparam);
2315         for (i = 0; i < chs->num; i++) {
2316                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2317                 if (err)
2318                         goto err_close_channels;
2319         }
2320
2321         kvfree(cparam);
2322         return 0;
2323
2324 err_close_channels:
2325         for (i--; i >= 0; i--)
2326                 mlx5e_close_channel(chs->c[i]);
2327
2328 err_free:
2329         kfree(chs->c);
2330         kvfree(cparam);
2331         chs->num = 0;
2332         return err;
2333 }
2334
2335 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2336 {
2337         int i;
2338
2339         for (i = 0; i < chs->num; i++)
2340                 mlx5e_activate_channel(chs->c[i]);
2341 }
2342
2343 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2344 {
2345         int err = 0;
2346         int i;
2347
2348         for (i = 0; i < chs->num; i++)
2349                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2350                                                   err ? 0 : 20000);
2351
2352         return err ? -ETIMEDOUT : 0;
2353 }
2354
2355 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2356 {
2357         int i;
2358
2359         for (i = 0; i < chs->num; i++)
2360                 mlx5e_deactivate_channel(chs->c[i]);
2361 }
2362
2363 void mlx5e_close_channels(struct mlx5e_channels *chs)
2364 {
2365         int i;
2366
2367         for (i = 0; i < chs->num; i++)
2368                 mlx5e_close_channel(chs->c[i]);
2369
2370         kfree(chs->c);
2371         chs->num = 0;
2372 }
2373
2374 static int
2375 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2376 {
2377         struct mlx5_core_dev *mdev = priv->mdev;
2378         void *rqtc;
2379         int inlen;
2380         int err;
2381         u32 *in;
2382         int i;
2383
2384         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2385         in = kvzalloc(inlen, GFP_KERNEL);
2386         if (!in)
2387                 return -ENOMEM;
2388
2389         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2390
2391         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2392         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2393
2394         for (i = 0; i < sz; i++)
2395                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2396
2397         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2398         if (!err)
2399                 rqt->enabled = true;
2400
2401         kvfree(in);
2402         return err;
2403 }
2404
2405 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2406 {
2407         rqt->enabled = false;
2408         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2409 }
2410
2411 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2412 {
2413         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2414         int err;
2415
2416         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2417         if (err)
2418                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2419         return err;
2420 }
2421
2422 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2423 {
2424         struct mlx5e_rqt *rqt;
2425         int err;
2426         int ix;
2427
2428         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2429                 rqt = &priv->direct_tir[ix].rqt;
2430                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2431                 if (err)
2432                         goto err_destroy_rqts;
2433         }
2434
2435         return 0;
2436
2437 err_destroy_rqts:
2438         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2439         for (ix--; ix >= 0; ix--)
2440                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2441
2442         return err;
2443 }
2444
2445 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2446 {
2447         int i;
2448
2449         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2450                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2451 }
2452
2453 static int mlx5e_rx_hash_fn(int hfunc)
2454 {
2455         return (hfunc == ETH_RSS_HASH_TOP) ?
2456                MLX5_RX_HASH_FN_TOEPLITZ :
2457                MLX5_RX_HASH_FN_INVERTED_XOR8;
2458 }
2459
2460 int mlx5e_bits_invert(unsigned long a, int size)
2461 {
2462         int inv = 0;
2463         int i;
2464
2465         for (i = 0; i < size; i++)
2466                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2467
2468         return inv;
2469 }
2470
2471 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2472                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2473 {
2474         int i;
2475
2476         for (i = 0; i < sz; i++) {
2477                 u32 rqn;
2478
2479                 if (rrp.is_rss) {
2480                         int ix = i;
2481
2482                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2483                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2484
2485                         ix = priv->channels.params.indirection_rqt[ix];
2486                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2487                 } else {
2488                         rqn = rrp.rqn;
2489                 }
2490                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2491         }
2492 }
2493
2494 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2495                        struct mlx5e_redirect_rqt_param rrp)
2496 {
2497         struct mlx5_core_dev *mdev = priv->mdev;
2498         void *rqtc;
2499         int inlen;
2500         u32 *in;
2501         int err;
2502
2503         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2504         in = kvzalloc(inlen, GFP_KERNEL);
2505         if (!in)
2506                 return -ENOMEM;
2507
2508         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2509
2510         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2511         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2512         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2513         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2514
2515         kvfree(in);
2516         return err;
2517 }
2518
2519 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2520                                 struct mlx5e_redirect_rqt_param rrp)
2521 {
2522         if (!rrp.is_rss)
2523                 return rrp.rqn;
2524
2525         if (ix >= rrp.rss.channels->num)
2526                 return priv->drop_rq.rqn;
2527
2528         return rrp.rss.channels->c[ix]->rq.rqn;
2529 }
2530
2531 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2532                                 struct mlx5e_redirect_rqt_param rrp)
2533 {
2534         u32 rqtn;
2535         int ix;
2536
2537         if (priv->indir_rqt.enabled) {
2538                 /* RSS RQ table */
2539                 rqtn = priv->indir_rqt.rqtn;
2540                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2541         }
2542
2543         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2544                 struct mlx5e_redirect_rqt_param direct_rrp = {
2545                         .is_rss = false,
2546                         {
2547                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2548                         },
2549                 };
2550
2551                 /* Direct RQ Tables */
2552                 if (!priv->direct_tir[ix].rqt.enabled)
2553                         continue;
2554
2555                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2556                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2557         }
2558 }
2559
2560 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2561                                             struct mlx5e_channels *chs)
2562 {
2563         struct mlx5e_redirect_rqt_param rrp = {
2564                 .is_rss        = true,
2565                 {
2566                         .rss = {
2567                                 .channels  = chs,
2568                                 .hfunc     = chs->params.rss_hfunc,
2569                         }
2570                 },
2571         };
2572
2573         mlx5e_redirect_rqts(priv, rrp);
2574 }
2575
2576 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2577 {
2578         struct mlx5e_redirect_rqt_param drop_rrp = {
2579                 .is_rss = false,
2580                 {
2581                         .rqn = priv->drop_rq.rqn,
2582                 },
2583         };
2584
2585         mlx5e_redirect_rqts(priv, drop_rrp);
2586 }
2587
2588 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2589 {
2590         if (!params->lro_en)
2591                 return;
2592
2593 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2594
2595         MLX5_SET(tirc, tirc, lro_enable_mask,
2596                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2597                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2598         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2599                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2600         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2601 }
2602
2603 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2604                                     enum mlx5e_traffic_types tt,
2605                                     void *tirc, bool inner)
2606 {
2607         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2608                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2609
2610 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2611                                  MLX5_HASH_FIELD_SEL_DST_IP)
2612
2613 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2614                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2615                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2616                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2617
2618 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2619                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2620                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2621
2622         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2623         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2624                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2625                                              rx_hash_toeplitz_key);
2626                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2627                                                rx_hash_toeplitz_key);
2628
2629                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2630                 memcpy(rss_key, params->toeplitz_hash_key, len);
2631         }
2632
2633         switch (tt) {
2634         case MLX5E_TT_IPV4_TCP:
2635                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2636                          MLX5_L3_PROT_TYPE_IPV4);
2637                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2638                          MLX5_L4_PROT_TYPE_TCP);
2639                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2640                          MLX5_HASH_IP_L4PORTS);
2641                 break;
2642
2643         case MLX5E_TT_IPV6_TCP:
2644                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2645                          MLX5_L3_PROT_TYPE_IPV6);
2646                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2647                          MLX5_L4_PROT_TYPE_TCP);
2648                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2649                          MLX5_HASH_IP_L4PORTS);
2650                 break;
2651
2652         case MLX5E_TT_IPV4_UDP:
2653                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2654                          MLX5_L3_PROT_TYPE_IPV4);
2655                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2656                          MLX5_L4_PROT_TYPE_UDP);
2657                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2658                          MLX5_HASH_IP_L4PORTS);
2659                 break;
2660
2661         case MLX5E_TT_IPV6_UDP:
2662                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2663                          MLX5_L3_PROT_TYPE_IPV6);
2664                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2665                          MLX5_L4_PROT_TYPE_UDP);
2666                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2667                          MLX5_HASH_IP_L4PORTS);
2668                 break;
2669
2670         case MLX5E_TT_IPV4_IPSEC_AH:
2671                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2672                          MLX5_L3_PROT_TYPE_IPV4);
2673                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2674                          MLX5_HASH_IP_IPSEC_SPI);
2675                 break;
2676
2677         case MLX5E_TT_IPV6_IPSEC_AH:
2678                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2679                          MLX5_L3_PROT_TYPE_IPV6);
2680                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2681                          MLX5_HASH_IP_IPSEC_SPI);
2682                 break;
2683
2684         case MLX5E_TT_IPV4_IPSEC_ESP:
2685                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2686                          MLX5_L3_PROT_TYPE_IPV4);
2687                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2688                          MLX5_HASH_IP_IPSEC_SPI);
2689                 break;
2690
2691         case MLX5E_TT_IPV6_IPSEC_ESP:
2692                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2693                          MLX5_L3_PROT_TYPE_IPV6);
2694                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2695                          MLX5_HASH_IP_IPSEC_SPI);
2696                 break;
2697
2698         case MLX5E_TT_IPV4:
2699                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2700                          MLX5_L3_PROT_TYPE_IPV4);
2701                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2702                          MLX5_HASH_IP);
2703                 break;
2704
2705         case MLX5E_TT_IPV6:
2706                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2707                          MLX5_L3_PROT_TYPE_IPV6);
2708                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2709                          MLX5_HASH_IP);
2710                 break;
2711         default:
2712                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2713         }
2714 }
2715
2716 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2717 {
2718         struct mlx5_core_dev *mdev = priv->mdev;
2719
2720         void *in;
2721         void *tirc;
2722         int inlen;
2723         int err;
2724         int tt;
2725         int ix;
2726
2727         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2728         in = kvzalloc(inlen, GFP_KERNEL);
2729         if (!in)
2730                 return -ENOMEM;
2731
2732         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2733         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2734
2735         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2736
2737         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2738                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2739                                            inlen);
2740                 if (err)
2741                         goto free_in;
2742         }
2743
2744         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2745                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2746                                            in, inlen);
2747                 if (err)
2748                         goto free_in;
2749         }
2750
2751 free_in:
2752         kvfree(in);
2753
2754         return err;
2755 }
2756
2757 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2758                                             enum mlx5e_traffic_types tt,
2759                                             u32 *tirc)
2760 {
2761         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2762
2763         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2764
2765         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2766         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2767         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2768
2769         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2770 }
2771
2772 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2773                          struct mlx5e_params *params, u16 mtu)
2774 {
2775         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2776         int err;
2777
2778         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2779         if (err)
2780                 return err;
2781
2782         /* Update vport context MTU */
2783         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2784         return 0;
2785 }
2786
2787 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2788                             struct mlx5e_params *params, u16 *mtu)
2789 {
2790         u16 hw_mtu = 0;
2791         int err;
2792
2793         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2794         if (err || !hw_mtu) /* fallback to port oper mtu */
2795                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2796
2797         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2798 }
2799
2800 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2801 {
2802         struct mlx5e_params *params = &priv->channels.params;
2803         struct net_device *netdev = priv->netdev;
2804         struct mlx5_core_dev *mdev = priv->mdev;
2805         u16 mtu;
2806         int err;
2807
2808         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2809         if (err)
2810                 return err;
2811
2812         mlx5e_query_mtu(mdev, params, &mtu);
2813         if (mtu != params->sw_mtu)
2814                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2815                             __func__, mtu, params->sw_mtu);
2816
2817         params->sw_mtu = mtu;
2818         return 0;
2819 }
2820
2821 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2822 {
2823         struct mlx5e_priv *priv = netdev_priv(netdev);
2824         int nch = priv->channels.params.num_channels;
2825         int ntc = priv->channels.params.num_tc;
2826         int tc;
2827
2828         netdev_reset_tc(netdev);
2829
2830         if (ntc == 1)
2831                 return;
2832
2833         netdev_set_num_tc(netdev, ntc);
2834
2835         /* Map netdev TCs to offset 0
2836          * We have our own UP to TXQ mapping for QoS
2837          */
2838         for (tc = 0; tc < ntc; tc++)
2839                 netdev_set_tc_queue(netdev, tc, nch, 0);
2840 }
2841
2842 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2843 {
2844         int max_nch = priv->profile->max_nch(priv->mdev);
2845         int i, tc;
2846
2847         for (i = 0; i < max_nch; i++)
2848                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2849                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2850 }
2851
2852 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2853 {
2854         struct mlx5e_channel *c;
2855         struct mlx5e_txqsq *sq;
2856         int i, tc;
2857
2858         for (i = 0; i < priv->channels.num; i++) {
2859                 c = priv->channels.c[i];
2860                 for (tc = 0; tc < c->num_tc; tc++) {
2861                         sq = &c->sq[tc];
2862                         priv->txq2sq[sq->txq_ix] = sq;
2863                 }
2864         }
2865 }
2866
2867 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2868 {
2869         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2870         struct net_device *netdev = priv->netdev;
2871
2872         mlx5e_netdev_set_tcs(netdev);
2873         netif_set_real_num_tx_queues(netdev, num_txqs);
2874         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2875
2876         mlx5e_build_tx2sq_maps(priv);
2877         mlx5e_activate_channels(&priv->channels);
2878         netif_tx_start_all_queues(priv->netdev);
2879
2880         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2881                 mlx5e_add_sqs_fwd_rules(priv);
2882
2883         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2884         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2885 }
2886
2887 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2888 {
2889         mlx5e_redirect_rqts_to_drop(priv);
2890
2891         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2892                 mlx5e_remove_sqs_fwd_rules(priv);
2893
2894         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2895          * polling for inactive tx queues.
2896          */
2897         netif_tx_stop_all_queues(priv->netdev);
2898         netif_tx_disable(priv->netdev);
2899         mlx5e_deactivate_channels(&priv->channels);
2900 }
2901
2902 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2903                                 struct mlx5e_channels *new_chs,
2904                                 mlx5e_fp_hw_modify hw_modify)
2905 {
2906         struct net_device *netdev = priv->netdev;
2907         int new_num_txqs;
2908         int carrier_ok;
2909         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2910
2911         carrier_ok = netif_carrier_ok(netdev);
2912         netif_carrier_off(netdev);
2913
2914         if (new_num_txqs < netdev->real_num_tx_queues)
2915                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2916
2917         mlx5e_deactivate_priv_channels(priv);
2918         mlx5e_close_channels(&priv->channels);
2919
2920         priv->channels = *new_chs;
2921
2922         /* New channels are ready to roll, modify HW settings if needed */
2923         if (hw_modify)
2924                 hw_modify(priv);
2925
2926         mlx5e_refresh_tirs(priv, false);
2927         mlx5e_activate_priv_channels(priv);
2928
2929         /* return carrier back if needed */
2930         if (carrier_ok)
2931                 netif_carrier_on(netdev);
2932 }
2933
2934 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2935 {
2936         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2937         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2938 }
2939
2940 int mlx5e_open_locked(struct net_device *netdev)
2941 {
2942         struct mlx5e_priv *priv = netdev_priv(netdev);
2943         int err;
2944
2945         set_bit(MLX5E_STATE_OPENED, &priv->state);
2946
2947         err = mlx5e_open_channels(priv, &priv->channels);
2948         if (err)
2949                 goto err_clear_state_opened_flag;
2950
2951         mlx5e_refresh_tirs(priv, false);
2952         mlx5e_activate_priv_channels(priv);
2953         if (priv->profile->update_carrier)
2954                 priv->profile->update_carrier(priv);
2955
2956         if (priv->profile->update_stats)
2957                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2958
2959         return 0;
2960
2961 err_clear_state_opened_flag:
2962         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2963         return err;
2964 }
2965
2966 int mlx5e_open(struct net_device *netdev)
2967 {
2968         struct mlx5e_priv *priv = netdev_priv(netdev);
2969         int err;
2970
2971         mutex_lock(&priv->state_lock);
2972         err = mlx5e_open_locked(netdev);
2973         if (!err)
2974                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2975         mutex_unlock(&priv->state_lock);
2976
2977         if (mlx5_vxlan_allowed(priv->vxlan))
2978                 udp_tunnel_get_rx_info(netdev);
2979
2980         return err;
2981 }
2982
2983 int mlx5e_close_locked(struct net_device *netdev)
2984 {
2985         struct mlx5e_priv *priv = netdev_priv(netdev);
2986
2987         /* May already be CLOSED in case a previous configuration operation
2988          * (e.g RX/TX queue size change) that involves close&open failed.
2989          */
2990         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2991                 return 0;
2992
2993         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2994
2995         netif_carrier_off(priv->netdev);
2996         mlx5e_deactivate_priv_channels(priv);
2997         mlx5e_close_channels(&priv->channels);
2998
2999         return 0;
3000 }
3001
3002 int mlx5e_close(struct net_device *netdev)
3003 {
3004         struct mlx5e_priv *priv = netdev_priv(netdev);
3005         int err;
3006
3007         if (!netif_device_present(netdev))
3008                 return -ENODEV;
3009
3010         mutex_lock(&priv->state_lock);
3011         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3012         err = mlx5e_close_locked(netdev);
3013         mutex_unlock(&priv->state_lock);
3014
3015         return err;
3016 }
3017
3018 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3019                                struct mlx5e_rq *rq,
3020                                struct mlx5e_rq_param *param)
3021 {
3022         void *rqc = param->rqc;
3023         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3024         int err;
3025
3026         param->wq.db_numa_node = param->wq.buf_numa_node;
3027
3028         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3029                                  &rq->wq_ctrl);
3030         if (err)
3031                 return err;
3032
3033         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3034         xdp_rxq_info_unused(&rq->xdp_rxq);
3035
3036         rq->mdev = mdev;
3037
3038         return 0;
3039 }
3040
3041 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3042                                struct mlx5e_cq *cq,
3043                                struct mlx5e_cq_param *param)
3044 {
3045         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3046         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
3047
3048         return mlx5e_alloc_cq_common(mdev, param, cq);
3049 }
3050
3051 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3052                               struct mlx5e_rq *drop_rq)
3053 {
3054         struct mlx5_core_dev *mdev = priv->mdev;
3055         struct mlx5e_cq_param cq_param = {};
3056         struct mlx5e_rq_param rq_param = {};
3057         struct mlx5e_cq *cq = &drop_rq->cq;
3058         int err;
3059
3060         mlx5e_build_drop_rq_param(priv, &rq_param);
3061
3062         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3063         if (err)
3064                 return err;
3065
3066         err = mlx5e_create_cq(cq, &cq_param);
3067         if (err)
3068                 goto err_free_cq;
3069
3070         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3071         if (err)
3072                 goto err_destroy_cq;
3073
3074         err = mlx5e_create_rq(drop_rq, &rq_param);
3075         if (err)
3076                 goto err_free_rq;
3077
3078         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3079         if (err)
3080                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3081
3082         return 0;
3083
3084 err_free_rq:
3085         mlx5e_free_rq(drop_rq);
3086
3087 err_destroy_cq:
3088         mlx5e_destroy_cq(cq);
3089
3090 err_free_cq:
3091         mlx5e_free_cq(cq);
3092
3093         return err;
3094 }
3095
3096 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3097 {
3098         mlx5e_destroy_rq(drop_rq);
3099         mlx5e_free_rq(drop_rq);
3100         mlx5e_destroy_cq(&drop_rq->cq);
3101         mlx5e_free_cq(&drop_rq->cq);
3102 }
3103
3104 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3105                      u32 underlay_qpn, u32 *tisn)
3106 {
3107         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3108         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3109
3110         MLX5_SET(tisc, tisc, prio, tc << 1);
3111         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3112         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3113
3114         if (mlx5_lag_is_lacp_owner(mdev))
3115                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3116
3117         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3118 }
3119
3120 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3121 {
3122         mlx5_core_destroy_tis(mdev, tisn);
3123 }
3124
3125 int mlx5e_create_tises(struct mlx5e_priv *priv)
3126 {
3127         int err;
3128         int tc;
3129
3130         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3131                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3132                 if (err)
3133                         goto err_close_tises;
3134         }
3135
3136         return 0;
3137
3138 err_close_tises:
3139         for (tc--; tc >= 0; tc--)
3140                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3141
3142         return err;
3143 }
3144
3145 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3146 {
3147         int tc;
3148
3149         for (tc = 0; tc < priv->profile->max_tc; tc++)
3150                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3151 }
3152
3153 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3154                                       enum mlx5e_traffic_types tt,
3155                                       u32 *tirc)
3156 {
3157         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3158
3159         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3160
3161         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3162         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3163         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
3164 }
3165
3166 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3167 {
3168         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3169
3170         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3171
3172         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3173         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3174         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3175 }
3176
3177 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
3178 {
3179         struct mlx5e_tir *tir;
3180         void *tirc;
3181         int inlen;
3182         int i = 0;
3183         int err;
3184         u32 *in;
3185         int tt;
3186
3187         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3188         in = kvzalloc(inlen, GFP_KERNEL);
3189         if (!in)
3190                 return -ENOMEM;
3191
3192         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3193                 memset(in, 0, inlen);
3194                 tir = &priv->indir_tir[tt];
3195                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3196                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3197                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3198                 if (err) {
3199                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3200                         goto err_destroy_inner_tirs;
3201                 }
3202         }
3203
3204         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3205                 goto out;
3206
3207         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3208                 memset(in, 0, inlen);
3209                 tir = &priv->inner_indir_tir[i];
3210                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3211                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3212                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3213                 if (err) {
3214                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3215                         goto err_destroy_inner_tirs;
3216                 }
3217         }
3218
3219 out:
3220         kvfree(in);
3221
3222         return 0;
3223
3224 err_destroy_inner_tirs:
3225         for (i--; i >= 0; i--)
3226                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3227
3228         for (tt--; tt >= 0; tt--)
3229                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3230
3231         kvfree(in);
3232
3233         return err;
3234 }
3235
3236 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3237 {
3238         int nch = priv->profile->max_nch(priv->mdev);
3239         struct mlx5e_tir *tir;
3240         void *tirc;
3241         int inlen;
3242         int err;
3243         u32 *in;
3244         int ix;
3245
3246         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3247         in = kvzalloc(inlen, GFP_KERNEL);
3248         if (!in)
3249                 return -ENOMEM;
3250
3251         for (ix = 0; ix < nch; ix++) {
3252                 memset(in, 0, inlen);
3253                 tir = &priv->direct_tir[ix];
3254                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3255                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3256                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3257                 if (err)
3258                         goto err_destroy_ch_tirs;
3259         }
3260
3261         kvfree(in);
3262
3263         return 0;
3264
3265 err_destroy_ch_tirs:
3266         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3267         for (ix--; ix >= 0; ix--)
3268                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3269
3270         kvfree(in);
3271
3272         return err;
3273 }
3274
3275 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3276 {
3277         int i;
3278
3279         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3280                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3281
3282         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3283                 return;
3284
3285         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3286                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3287 }
3288
3289 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3290 {
3291         int nch = priv->profile->max_nch(priv->mdev);
3292         int i;
3293
3294         for (i = 0; i < nch; i++)
3295                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3296 }
3297
3298 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3299 {
3300         int err = 0;
3301         int i;
3302
3303         for (i = 0; i < chs->num; i++) {
3304                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3305                 if (err)
3306                         return err;
3307         }
3308
3309         return 0;
3310 }
3311
3312 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3313 {
3314         int err = 0;
3315         int i;
3316
3317         for (i = 0; i < chs->num; i++) {
3318                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3319                 if (err)
3320                         return err;
3321         }
3322
3323         return 0;
3324 }
3325
3326 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3327                                  struct tc_mqprio_qopt *mqprio)
3328 {
3329         struct mlx5e_priv *priv = netdev_priv(netdev);
3330         struct mlx5e_channels new_channels = {};
3331         u8 tc = mqprio->num_tc;
3332         int err = 0;
3333
3334         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3335
3336         if (tc && tc != MLX5E_MAX_NUM_TC)
3337                 return -EINVAL;
3338
3339         mutex_lock(&priv->state_lock);
3340
3341         new_channels.params = priv->channels.params;
3342         new_channels.params.num_tc = tc ? tc : 1;
3343
3344         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3345                 priv->channels.params = new_channels.params;
3346                 goto out;
3347         }
3348
3349         err = mlx5e_open_channels(priv, &new_channels);
3350         if (err)
3351                 goto out;
3352
3353         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3354                                     new_channels.params.num_tc);
3355         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3356 out:
3357         mutex_unlock(&priv->state_lock);
3358         return err;
3359 }
3360
3361 #ifdef CONFIG_MLX5_ESWITCH
3362 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3363                                      struct tc_cls_flower_offload *cls_flower,
3364                                      int flags)
3365 {
3366         switch (cls_flower->command) {
3367         case TC_CLSFLOWER_REPLACE:
3368                 return mlx5e_configure_flower(priv, cls_flower, flags);
3369         case TC_CLSFLOWER_DESTROY:
3370                 return mlx5e_delete_flower(priv, cls_flower, flags);
3371         case TC_CLSFLOWER_STATS:
3372                 return mlx5e_stats_flower(priv, cls_flower, flags);
3373         default:
3374                 return -EOPNOTSUPP;
3375         }
3376 }
3377
3378 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3379                                    void *cb_priv)
3380 {
3381         struct mlx5e_priv *priv = cb_priv;
3382
3383         if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3384                 return -EOPNOTSUPP;
3385
3386         switch (type) {
3387         case TC_SETUP_CLSFLOWER:
3388                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS);
3389         default:
3390                 return -EOPNOTSUPP;
3391         }
3392 }
3393
3394 static int mlx5e_setup_tc_block(struct net_device *dev,
3395                                 struct tc_block_offload *f)
3396 {
3397         struct mlx5e_priv *priv = netdev_priv(dev);
3398
3399         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3400                 return -EOPNOTSUPP;
3401
3402         switch (f->command) {
3403         case TC_BLOCK_BIND:
3404                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3405                                              priv, priv, f->extack);
3406         case TC_BLOCK_UNBIND:
3407                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3408                                         priv);
3409                 return 0;
3410         default:
3411                 return -EOPNOTSUPP;
3412         }
3413 }
3414 #endif
3415
3416 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3417                           void *type_data)
3418 {
3419         switch (type) {
3420 #ifdef CONFIG_MLX5_ESWITCH
3421         case TC_SETUP_BLOCK:
3422                 return mlx5e_setup_tc_block(dev, type_data);
3423 #endif
3424         case TC_SETUP_QDISC_MQPRIO:
3425                 return mlx5e_setup_tc_mqprio(dev, type_data);
3426         default:
3427                 return -EOPNOTSUPP;
3428         }
3429 }
3430
3431 static void
3432 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3433 {
3434         struct mlx5e_priv *priv = netdev_priv(dev);
3435         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3436         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3437         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3438
3439         /* update HW stats in background for next time */
3440         queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
3441
3442         if (mlx5e_is_uplink_rep(priv)) {
3443                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3444                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3445                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3446                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3447         } else {
3448                 mlx5e_grp_sw_update_stats(priv);
3449                 stats->rx_packets = sstats->rx_packets;
3450                 stats->rx_bytes   = sstats->rx_bytes;
3451                 stats->tx_packets = sstats->tx_packets;
3452                 stats->tx_bytes   = sstats->tx_bytes;
3453                 stats->tx_dropped = sstats->tx_queue_dropped;
3454         }
3455
3456         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3457
3458         stats->rx_length_errors =
3459                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3460                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3461                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3462         stats->rx_crc_errors =
3463                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3464         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3465         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3466         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3467                            stats->rx_frame_errors;
3468         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3469
3470         /* vport multicast also counts packets that are dropped due to steering
3471          * or rx out of buffer
3472          */
3473         stats->multicast =
3474                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3475 }
3476
3477 static void mlx5e_set_rx_mode(struct net_device *dev)
3478 {
3479         struct mlx5e_priv *priv = netdev_priv(dev);
3480
3481         queue_work(priv->wq, &priv->set_rx_mode_work);
3482 }
3483
3484 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3485 {
3486         struct mlx5e_priv *priv = netdev_priv(netdev);
3487         struct sockaddr *saddr = addr;
3488
3489         if (!is_valid_ether_addr(saddr->sa_data))
3490                 return -EADDRNOTAVAIL;
3491
3492         netif_addr_lock_bh(netdev);
3493         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3494         netif_addr_unlock_bh(netdev);
3495
3496         queue_work(priv->wq, &priv->set_rx_mode_work);
3497
3498         return 0;
3499 }
3500
3501 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3502         do {                                            \
3503                 if (enable)                             \
3504                         *features |= feature;           \
3505                 else                                    \
3506                         *features &= ~feature;          \
3507         } while (0)
3508
3509 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3510
3511 static int set_feature_lro(struct net_device *netdev, bool enable)
3512 {
3513         struct mlx5e_priv *priv = netdev_priv(netdev);
3514         struct mlx5_core_dev *mdev = priv->mdev;
3515         struct mlx5e_channels new_channels = {};
3516         struct mlx5e_params *old_params;
3517         int err = 0;
3518         bool reset;
3519
3520         mutex_lock(&priv->state_lock);
3521
3522         old_params = &priv->channels.params;
3523         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3524                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3525                 err = -EINVAL;
3526                 goto out;
3527         }
3528
3529         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3530
3531         new_channels.params = *old_params;
3532         new_channels.params.lro_en = enable;
3533
3534         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3535                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3536                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3537                         reset = false;
3538         }
3539
3540         if (!reset) {
3541                 *old_params = new_channels.params;
3542                 err = mlx5e_modify_tirs_lro(priv);
3543                 goto out;
3544         }
3545
3546         err = mlx5e_open_channels(priv, &new_channels);
3547         if (err)
3548                 goto out;
3549
3550         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3551 out:
3552         mutex_unlock(&priv->state_lock);
3553         return err;
3554 }
3555
3556 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3557 {
3558         struct mlx5e_priv *priv = netdev_priv(netdev);
3559
3560         if (enable)
3561                 mlx5e_enable_cvlan_filter(priv);
3562         else
3563                 mlx5e_disable_cvlan_filter(priv);
3564
3565         return 0;
3566 }
3567
3568 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3569 {
3570         struct mlx5e_priv *priv = netdev_priv(netdev);
3571
3572         if (!enable && mlx5e_tc_num_filters(priv)) {
3573                 netdev_err(netdev,
3574                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3575                 return -EINVAL;
3576         }
3577
3578         return 0;
3579 }
3580
3581 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3582 {
3583         struct mlx5e_priv *priv = netdev_priv(netdev);
3584         struct mlx5_core_dev *mdev = priv->mdev;
3585
3586         return mlx5_set_port_fcs(mdev, !enable);
3587 }
3588
3589 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3590 {
3591         struct mlx5e_priv *priv = netdev_priv(netdev);
3592         int err;
3593
3594         mutex_lock(&priv->state_lock);
3595
3596         priv->channels.params.scatter_fcs_en = enable;
3597         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3598         if (err)
3599                 priv->channels.params.scatter_fcs_en = !enable;
3600
3601         mutex_unlock(&priv->state_lock);
3602
3603         return err;
3604 }
3605
3606 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3607 {
3608         struct mlx5e_priv *priv = netdev_priv(netdev);
3609         int err = 0;
3610
3611         mutex_lock(&priv->state_lock);
3612
3613         priv->channels.params.vlan_strip_disable = !enable;
3614         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3615                 goto unlock;
3616
3617         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3618         if (err)
3619                 priv->channels.params.vlan_strip_disable = enable;
3620
3621 unlock:
3622         mutex_unlock(&priv->state_lock);
3623
3624         return err;
3625 }
3626
3627 #ifdef CONFIG_RFS_ACCEL
3628 static int set_feature_arfs(struct net_device *netdev, bool enable)
3629 {
3630         struct mlx5e_priv *priv = netdev_priv(netdev);
3631         int err;
3632
3633         if (enable)
3634                 err = mlx5e_arfs_enable(priv);
3635         else
3636                 err = mlx5e_arfs_disable(priv);
3637
3638         return err;
3639 }
3640 #endif
3641
3642 static int mlx5e_handle_feature(struct net_device *netdev,
3643                                 netdev_features_t *features,
3644                                 netdev_features_t wanted_features,
3645                                 netdev_features_t feature,
3646                                 mlx5e_feature_handler feature_handler)
3647 {
3648         netdev_features_t changes = wanted_features ^ netdev->features;
3649         bool enable = !!(wanted_features & feature);
3650         int err;
3651
3652         if (!(changes & feature))
3653                 return 0;
3654
3655         err = feature_handler(netdev, enable);
3656         if (err) {
3657                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3658                            enable ? "Enable" : "Disable", &feature, err);
3659                 return err;
3660         }
3661
3662         MLX5E_SET_FEATURE(features, feature, enable);
3663         return 0;
3664 }
3665
3666 static int mlx5e_set_features(struct net_device *netdev,
3667                               netdev_features_t features)
3668 {
3669         netdev_features_t oper_features = netdev->features;
3670         int err = 0;
3671
3672 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3673         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3674
3675         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3676         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3677                                     set_feature_cvlan_filter);
3678         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3679         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3680         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3681         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3682 #ifdef CONFIG_RFS_ACCEL
3683         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3684 #endif
3685
3686         if (err) {
3687                 netdev->features = oper_features;
3688                 return -EINVAL;
3689         }
3690
3691         return 0;
3692 }
3693
3694 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3695                                             netdev_features_t features)
3696 {
3697         struct mlx5e_priv *priv = netdev_priv(netdev);
3698         struct mlx5e_params *params;
3699
3700         mutex_lock(&priv->state_lock);
3701         params = &priv->channels.params;
3702         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3703                 /* HW strips the outer C-tag header, this is a problem
3704                  * for S-tag traffic.
3705                  */
3706                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3707                 if (!params->vlan_strip_disable)
3708                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3709         }
3710         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3711                 features &= ~NETIF_F_LRO;
3712                 if (params->lro_en)
3713                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3714         }
3715
3716         mutex_unlock(&priv->state_lock);
3717
3718         return features;
3719 }
3720
3721 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3722                      change_hw_mtu_cb set_mtu_cb)
3723 {
3724         struct mlx5e_priv *priv = netdev_priv(netdev);
3725         struct mlx5e_channels new_channels = {};
3726         struct mlx5e_params *params;
3727         int err = 0;
3728         bool reset;
3729
3730         mutex_lock(&priv->state_lock);
3731
3732         params = &priv->channels.params;
3733
3734         reset = !params->lro_en;
3735         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3736
3737         new_channels.params = *params;
3738         new_channels.params.sw_mtu = new_mtu;
3739
3740         if (params->xdp_prog &&
3741             !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3742                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3743                            new_mtu, MLX5E_XDP_MAX_MTU);
3744                 err = -EINVAL;
3745                 goto out;
3746         }
3747
3748         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3749                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3750                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3751
3752                 reset = reset && (ppw_old != ppw_new);
3753         }
3754
3755         if (!reset) {
3756                 params->sw_mtu = new_mtu;
3757                 set_mtu_cb(priv);
3758                 netdev->mtu = params->sw_mtu;
3759                 goto out;
3760         }
3761
3762         err = mlx5e_open_channels(priv, &new_channels);
3763         if (err)
3764                 goto out;
3765
3766         mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
3767         netdev->mtu = new_channels.params.sw_mtu;
3768
3769 out:
3770         mutex_unlock(&priv->state_lock);
3771         return err;
3772 }
3773
3774 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3775 {
3776         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3777 }
3778
3779 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3780 {
3781         struct hwtstamp_config config;
3782         int err;
3783
3784         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3785                 return -EOPNOTSUPP;
3786
3787         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3788                 return -EFAULT;
3789
3790         /* TX HW timestamp */
3791         switch (config.tx_type) {
3792         case HWTSTAMP_TX_OFF:
3793         case HWTSTAMP_TX_ON:
3794                 break;
3795         default:
3796                 return -ERANGE;
3797         }
3798
3799         mutex_lock(&priv->state_lock);
3800         /* RX HW timestamp */
3801         switch (config.rx_filter) {
3802         case HWTSTAMP_FILTER_NONE:
3803                 /* Reset CQE compression to Admin default */
3804                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3805                 break;
3806         case HWTSTAMP_FILTER_ALL:
3807         case HWTSTAMP_FILTER_SOME:
3808         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3809         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3810         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3811         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3812         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3813         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3814         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3815         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3816         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3817         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3818         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3819         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3820         case HWTSTAMP_FILTER_NTP_ALL:
3821                 /* Disable CQE compression */
3822                 netdev_warn(priv->netdev, "Disabling cqe compression");
3823                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3824                 if (err) {
3825                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3826                         mutex_unlock(&priv->state_lock);
3827                         return err;
3828                 }
3829                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3830                 break;
3831         default:
3832                 mutex_unlock(&priv->state_lock);
3833                 return -ERANGE;
3834         }
3835
3836         memcpy(&priv->tstamp, &config, sizeof(config));
3837         mutex_unlock(&priv->state_lock);
3838
3839         return copy_to_user(ifr->ifr_data, &config,
3840                             sizeof(config)) ? -EFAULT : 0;
3841 }
3842
3843 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3844 {
3845         struct hwtstamp_config *cfg = &priv->tstamp;
3846
3847         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3848                 return -EOPNOTSUPP;
3849
3850         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3851 }
3852
3853 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3854 {
3855         struct mlx5e_priv *priv = netdev_priv(dev);
3856
3857         switch (cmd) {
3858         case SIOCSHWTSTAMP:
3859                 return mlx5e_hwstamp_set(priv, ifr);
3860         case SIOCGHWTSTAMP:
3861                 return mlx5e_hwstamp_get(priv, ifr);
3862         default:
3863                 return -EOPNOTSUPP;
3864         }
3865 }
3866
3867 #ifdef CONFIG_MLX5_ESWITCH
3868 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3869 {
3870         struct mlx5e_priv *priv = netdev_priv(dev);
3871         struct mlx5_core_dev *mdev = priv->mdev;
3872
3873         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3874 }
3875
3876 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3877                              __be16 vlan_proto)
3878 {
3879         struct mlx5e_priv *priv = netdev_priv(dev);
3880         struct mlx5_core_dev *mdev = priv->mdev;
3881
3882         if (vlan_proto != htons(ETH_P_8021Q))
3883                 return -EPROTONOSUPPORT;
3884
3885         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3886                                            vlan, qos);
3887 }
3888
3889 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3890 {
3891         struct mlx5e_priv *priv = netdev_priv(dev);
3892         struct mlx5_core_dev *mdev = priv->mdev;
3893
3894         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3895 }
3896
3897 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3898 {
3899         struct mlx5e_priv *priv = netdev_priv(dev);
3900         struct mlx5_core_dev *mdev = priv->mdev;
3901
3902         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3903 }
3904
3905 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3906                              int max_tx_rate)
3907 {
3908         struct mlx5e_priv *priv = netdev_priv(dev);
3909         struct mlx5_core_dev *mdev = priv->mdev;
3910
3911         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3912                                            max_tx_rate, min_tx_rate);
3913 }
3914
3915 static int mlx5_vport_link2ifla(u8 esw_link)
3916 {
3917         switch (esw_link) {
3918         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3919                 return IFLA_VF_LINK_STATE_DISABLE;
3920         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3921                 return IFLA_VF_LINK_STATE_ENABLE;
3922         }
3923         return IFLA_VF_LINK_STATE_AUTO;
3924 }
3925
3926 static int mlx5_ifla_link2vport(u8 ifla_link)
3927 {
3928         switch (ifla_link) {
3929         case IFLA_VF_LINK_STATE_DISABLE:
3930                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3931         case IFLA_VF_LINK_STATE_ENABLE:
3932                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3933         }
3934         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3935 }
3936
3937 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3938                                    int link_state)
3939 {
3940         struct mlx5e_priv *priv = netdev_priv(dev);
3941         struct mlx5_core_dev *mdev = priv->mdev;
3942
3943         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3944                                             mlx5_ifla_link2vport(link_state));
3945 }
3946
3947 static int mlx5e_get_vf_config(struct net_device *dev,
3948                                int vf, struct ifla_vf_info *ivi)
3949 {
3950         struct mlx5e_priv *priv = netdev_priv(dev);
3951         struct mlx5_core_dev *mdev = priv->mdev;
3952         int err;
3953
3954         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3955         if (err)
3956                 return err;
3957         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3958         return 0;
3959 }
3960
3961 static int mlx5e_get_vf_stats(struct net_device *dev,
3962                               int vf, struct ifla_vf_stats *vf_stats)
3963 {
3964         struct mlx5e_priv *priv = netdev_priv(dev);
3965         struct mlx5_core_dev *mdev = priv->mdev;
3966
3967         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3968                                             vf_stats);
3969 }
3970 #endif
3971
3972 struct mlx5e_vxlan_work {
3973         struct work_struct      work;
3974         struct mlx5e_priv       *priv;
3975         u16                     port;
3976 };
3977
3978 static void mlx5e_vxlan_add_work(struct work_struct *work)
3979 {
3980         struct mlx5e_vxlan_work *vxlan_work =
3981                 container_of(work, struct mlx5e_vxlan_work, work);
3982         struct mlx5e_priv *priv = vxlan_work->priv;
3983         u16 port = vxlan_work->port;
3984
3985         mutex_lock(&priv->state_lock);
3986         mlx5_vxlan_add_port(priv->vxlan, port);
3987         mutex_unlock(&priv->state_lock);
3988
3989         kfree(vxlan_work);
3990 }
3991
3992 static void mlx5e_vxlan_del_work(struct work_struct *work)
3993 {
3994         struct mlx5e_vxlan_work *vxlan_work =
3995                 container_of(work, struct mlx5e_vxlan_work, work);
3996         struct mlx5e_priv *priv         = vxlan_work->priv;
3997         u16 port = vxlan_work->port;
3998
3999         mutex_lock(&priv->state_lock);
4000         mlx5_vxlan_del_port(priv->vxlan, port);
4001         mutex_unlock(&priv->state_lock);
4002         kfree(vxlan_work);
4003 }
4004
4005 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4006 {
4007         struct mlx5e_vxlan_work *vxlan_work;
4008
4009         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4010         if (!vxlan_work)
4011                 return;
4012
4013         if (add)
4014                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4015         else
4016                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4017
4018         vxlan_work->priv = priv;
4019         vxlan_work->port = port;
4020         queue_work(priv->wq, &vxlan_work->work);
4021 }
4022
4023 static void mlx5e_add_vxlan_port(struct net_device *netdev,
4024                                  struct udp_tunnel_info *ti)
4025 {
4026         struct mlx5e_priv *priv = netdev_priv(netdev);
4027
4028         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4029                 return;
4030
4031         if (!mlx5_vxlan_allowed(priv->vxlan))
4032                 return;
4033
4034         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4035 }
4036
4037 static void mlx5e_del_vxlan_port(struct net_device *netdev,
4038                                  struct udp_tunnel_info *ti)
4039 {
4040         struct mlx5e_priv *priv = netdev_priv(netdev);
4041
4042         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4043                 return;
4044
4045         if (!mlx5_vxlan_allowed(priv->vxlan))
4046                 return;
4047
4048         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4049 }
4050
4051 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4052                                                      struct sk_buff *skb,
4053                                                      netdev_features_t features)
4054 {
4055         unsigned int offset = 0;
4056         struct udphdr *udph;
4057         u8 proto;
4058         u16 port;
4059
4060         switch (vlan_get_protocol(skb)) {
4061         case htons(ETH_P_IP):
4062                 proto = ip_hdr(skb)->protocol;
4063                 break;
4064         case htons(ETH_P_IPV6):
4065                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4066                 break;
4067         default:
4068                 goto out;
4069         }
4070
4071         switch (proto) {
4072         case IPPROTO_GRE:
4073                 return features;
4074         case IPPROTO_UDP:
4075                 udph = udp_hdr(skb);
4076                 port = be16_to_cpu(udph->dest);
4077
4078                 /* Verify if UDP port is being offloaded by HW */
4079                 if (mlx5_vxlan_lookup_port(priv->vxlan, port))
4080                         return features;
4081         }
4082
4083 out:
4084         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4085         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4086 }
4087
4088 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4089                                               struct net_device *netdev,
4090                                               netdev_features_t features)
4091 {
4092         struct mlx5e_priv *priv = netdev_priv(netdev);
4093
4094         features = vlan_features_check(skb, features);
4095         features = vxlan_features_check(skb, features);
4096
4097 #ifdef CONFIG_MLX5_EN_IPSEC
4098         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4099                 return features;
4100 #endif
4101
4102         /* Validate if the tunneled packet is being offloaded by HW */
4103         if (skb->encapsulation &&
4104             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4105                 return mlx5e_tunnel_features_check(priv, skb, features);
4106
4107         return features;
4108 }
4109
4110 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4111                                         struct mlx5e_txqsq *sq)
4112 {
4113         struct mlx5_eq *eq = sq->cq.mcq.eq;
4114         u32 eqe_count;
4115
4116         netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
4117                    eq->eqn, eq->cons_index, eq->irqn);
4118
4119         eqe_count = mlx5_eq_poll_irq_disabled(eq);
4120         if (!eqe_count)
4121                 return false;
4122
4123         netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
4124         sq->channel->stats->eq_rearm++;
4125         return true;
4126 }
4127
4128 static void mlx5e_tx_timeout_work(struct work_struct *work)
4129 {
4130         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4131                                                tx_timeout_work);
4132         struct net_device *dev = priv->netdev;
4133         bool reopen_channels = false;
4134         int i, err;
4135
4136         rtnl_lock();
4137         mutex_lock(&priv->state_lock);
4138
4139         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4140                 goto unlock;
4141
4142         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4143                 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
4144                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4145
4146                 if (!netif_xmit_stopped(dev_queue))
4147                         continue;
4148
4149                 netdev_err(dev,
4150                            "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
4151                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4152                            jiffies_to_usecs(jiffies - dev_queue->trans_start));
4153
4154                 /* If we recover a lost interrupt, most likely TX timeout will
4155                  * be resolved, skip reopening channels
4156                  */
4157                 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4158                         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4159                         reopen_channels = true;
4160                 }
4161         }
4162
4163         if (!reopen_channels)
4164                 goto unlock;
4165
4166         mlx5e_close_locked(dev);
4167         err = mlx5e_open_locked(dev);
4168         if (err)
4169                 netdev_err(priv->netdev,
4170                            "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4171                            err);
4172
4173 unlock:
4174         mutex_unlock(&priv->state_lock);
4175         rtnl_unlock();
4176 }
4177
4178 static void mlx5e_tx_timeout(struct net_device *dev)
4179 {
4180         struct mlx5e_priv *priv = netdev_priv(dev);
4181
4182         netdev_err(dev, "TX timeout detected\n");
4183         queue_work(priv->wq, &priv->tx_timeout_work);
4184 }
4185
4186 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4187 {
4188         struct net_device *netdev = priv->netdev;
4189         struct mlx5e_channels new_channels = {};
4190
4191         if (priv->channels.params.lro_en) {
4192                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4193                 return -EINVAL;
4194         }
4195
4196         if (MLX5_IPSEC_DEV(priv->mdev)) {
4197                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4198                 return -EINVAL;
4199         }
4200
4201         new_channels.params = priv->channels.params;
4202         new_channels.params.xdp_prog = prog;
4203
4204         if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4205                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4206                             new_channels.params.sw_mtu, MLX5E_XDP_MAX_MTU);
4207                 return -EINVAL;
4208         }
4209
4210         return 0;
4211 }
4212
4213 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4214 {
4215         struct mlx5e_priv *priv = netdev_priv(netdev);
4216         struct bpf_prog *old_prog;
4217         bool reset, was_opened;
4218         int err;
4219         int i;
4220
4221         mutex_lock(&priv->state_lock);
4222
4223         if (prog) {
4224                 err = mlx5e_xdp_allowed(priv, prog);
4225                 if (err)
4226                         goto unlock;
4227         }
4228
4229         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4230         /* no need for full reset when exchanging programs */
4231         reset = (!priv->channels.params.xdp_prog || !prog);
4232
4233         if (was_opened && reset)
4234                 mlx5e_close_locked(netdev);
4235         if (was_opened && !reset) {
4236                 /* num_channels is invariant here, so we can take the
4237                  * batched reference right upfront.
4238                  */
4239                 prog = bpf_prog_add(prog, priv->channels.num);
4240                 if (IS_ERR(prog)) {
4241                         err = PTR_ERR(prog);
4242                         goto unlock;
4243                 }
4244         }
4245
4246         /* exchange programs, extra prog reference we got from caller
4247          * as long as we don't fail from this point onwards.
4248          */
4249         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4250         if (old_prog)
4251                 bpf_prog_put(old_prog);
4252
4253         if (reset) /* change RQ type according to priv->xdp_prog */
4254                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4255
4256         if (was_opened && reset)
4257                 mlx5e_open_locked(netdev);
4258
4259         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4260                 goto unlock;
4261
4262         /* exchanging programs w/o reset, we update ref counts on behalf
4263          * of the channels RQs here.
4264          */
4265         for (i = 0; i < priv->channels.num; i++) {
4266                 struct mlx5e_channel *c = priv->channels.c[i];
4267
4268                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4269                 napi_synchronize(&c->napi);
4270                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4271
4272                 old_prog = xchg(&c->rq.xdp_prog, prog);
4273
4274                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4275                 /* napi_schedule in case we have missed anything */
4276                 napi_schedule(&c->napi);
4277
4278                 if (old_prog)
4279                         bpf_prog_put(old_prog);
4280         }
4281
4282 unlock:
4283         mutex_unlock(&priv->state_lock);
4284         return err;
4285 }
4286
4287 static u32 mlx5e_xdp_query(struct net_device *dev)
4288 {
4289         struct mlx5e_priv *priv = netdev_priv(dev);
4290         const struct bpf_prog *xdp_prog;
4291         u32 prog_id = 0;
4292
4293         mutex_lock(&priv->state_lock);
4294         xdp_prog = priv->channels.params.xdp_prog;
4295         if (xdp_prog)
4296                 prog_id = xdp_prog->aux->id;
4297         mutex_unlock(&priv->state_lock);
4298
4299         return prog_id;
4300 }
4301
4302 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4303 {
4304         switch (xdp->command) {
4305         case XDP_SETUP_PROG:
4306                 return mlx5e_xdp_set(dev, xdp->prog);
4307         case XDP_QUERY_PROG:
4308                 xdp->prog_id = mlx5e_xdp_query(dev);
4309                 return 0;
4310         default:
4311                 return -EINVAL;
4312         }
4313 }
4314
4315 #ifdef CONFIG_NET_POLL_CONTROLLER
4316 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
4317  * reenabling interrupts.
4318  */
4319 static void mlx5e_netpoll(struct net_device *dev)
4320 {
4321         struct mlx5e_priv *priv = netdev_priv(dev);
4322         struct mlx5e_channels *chs = &priv->channels;
4323
4324         int i;
4325
4326         for (i = 0; i < chs->num; i++)
4327                 napi_schedule(&chs->c[i]->napi);
4328 }
4329 #endif
4330
4331 static const struct net_device_ops mlx5e_netdev_ops = {
4332         .ndo_open                = mlx5e_open,
4333         .ndo_stop                = mlx5e_close,
4334         .ndo_start_xmit          = mlx5e_xmit,
4335         .ndo_setup_tc            = mlx5e_setup_tc,
4336         .ndo_select_queue        = mlx5e_select_queue,
4337         .ndo_get_stats64         = mlx5e_get_stats,
4338         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4339         .ndo_set_mac_address     = mlx5e_set_mac,
4340         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4341         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4342         .ndo_set_features        = mlx5e_set_features,
4343         .ndo_fix_features        = mlx5e_fix_features,
4344         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4345         .ndo_do_ioctl            = mlx5e_ioctl,
4346         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4347         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4348         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4349         .ndo_features_check      = mlx5e_features_check,
4350 #ifdef CONFIG_RFS_ACCEL
4351         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4352 #endif
4353         .ndo_tx_timeout          = mlx5e_tx_timeout,
4354         .ndo_bpf                 = mlx5e_xdp,
4355         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4356 #ifdef CONFIG_NET_POLL_CONTROLLER
4357         .ndo_poll_controller     = mlx5e_netpoll,
4358 #endif
4359 #ifdef CONFIG_MLX5_ESWITCH
4360         /* SRIOV E-Switch NDOs */
4361         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4362         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4363         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4364         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4365         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4366         .ndo_get_vf_config       = mlx5e_get_vf_config,
4367         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4368         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4369         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4370         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4371 #endif
4372 };
4373
4374 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4375 {
4376         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4377                 return -EOPNOTSUPP;
4378         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4379             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4380             !MLX5_CAP_ETH(mdev, csum_cap) ||
4381             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4382             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4383             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4384             MLX5_CAP_FLOWTABLE(mdev,
4385                                flow_table_properties_nic_receive.max_ft_level)
4386                                < 3) {
4387                 mlx5_core_warn(mdev,
4388                                "Not creating net device, some required device capabilities are missing\n");
4389                 return -EOPNOTSUPP;
4390         }
4391         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4392                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4393         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4394                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4395
4396         return 0;
4397 }
4398
4399 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4400                                    int num_channels)
4401 {
4402         int i;
4403
4404         for (i = 0; i < len; i++)
4405                 indirection_rqt[i] = i % num_channels;
4406 }
4407
4408 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4409 {
4410         u32 link_speed = 0;
4411         u32 pci_bw = 0;
4412
4413         mlx5e_port_max_linkspeed(mdev, &link_speed);
4414         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4415         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4416                            link_speed, pci_bw);
4417
4418 #define MLX5E_SLOW_PCI_RATIO (2)
4419
4420         return link_speed && pci_bw &&
4421                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4422 }
4423
4424 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4425 {
4426         struct net_dim_cq_moder moder;
4427
4428         moder.cq_period_mode = cq_period_mode;
4429         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4430         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4431         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4432                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4433
4434         return moder;
4435 }
4436
4437 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4438 {
4439         struct net_dim_cq_moder moder;
4440
4441         moder.cq_period_mode = cq_period_mode;
4442         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4443         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4444         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4445                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4446
4447         return moder;
4448 }
4449
4450 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4451 {
4452         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4453                 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4454                 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4455 }
4456
4457 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4458 {
4459         if (params->tx_dim_enabled) {
4460                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4461
4462                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4463         } else {
4464                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4465         }
4466
4467         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4468                         params->tx_cq_moderation.cq_period_mode ==
4469                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4470 }
4471
4472 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4473 {
4474         if (params->rx_dim_enabled) {
4475                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4476
4477                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4478         } else {
4479                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4480         }
4481
4482         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4483                         params->rx_cq_moderation.cq_period_mode ==
4484                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4485 }
4486
4487 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4488 {
4489         int i;
4490
4491         /* The supported periods are organized in ascending order */
4492         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4493                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4494                         break;
4495
4496         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4497 }
4498
4499 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4500                             struct mlx5e_params *params,
4501                             u16 max_channels, u16 mtu)
4502 {
4503         u8 rx_cq_period_mode;
4504
4505         params->sw_mtu = mtu;
4506         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4507         params->num_channels = max_channels;
4508         params->num_tc       = 1;
4509
4510         /* SQ */
4511         params->log_sq_size = is_kdump_kernel() ?
4512                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4513                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4514
4515         /* set CQE compression */
4516         params->rx_cqe_compress_def = false;
4517         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4518             MLX5_CAP_GEN(mdev, vport_group_manager))
4519                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4520
4521         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4522
4523         /* RQ */
4524         /* Prefer Striding RQ, unless any of the following holds:
4525          * - Striding RQ configuration is not possible/supported.
4526          * - Slow PCI heuristic.
4527          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4528          */
4529         if (!slow_pci_heuristic(mdev) &&
4530             mlx5e_striding_rq_possible(mdev, params) &&
4531             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4532              !mlx5e_rx_is_linear_skb(mdev, params)))
4533                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4534         mlx5e_set_rq_type(mdev, params);
4535         mlx5e_init_rq_type_params(mdev, params);
4536
4537         /* HW LRO */
4538
4539         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4540         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4541                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4542                         params->lro_en = !slow_pci_heuristic(mdev);
4543         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4544
4545         /* CQ moderation params */
4546         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4547                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4548                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4549         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4550         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4551         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4552         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4553
4554         /* TX inline */
4555         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4556
4557         /* RSS */
4558         params->rss_hfunc = ETH_RSS_HASH_XOR;
4559         netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4560         mlx5e_build_default_indir_rqt(params->indirection_rqt,
4561                                       MLX5E_INDIR_RQT_SIZE, max_channels);
4562 }
4563
4564 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4565                                         struct net_device *netdev,
4566                                         const struct mlx5e_profile *profile,
4567                                         void *ppriv)
4568 {
4569         struct mlx5e_priv *priv = netdev_priv(netdev);
4570
4571         priv->mdev        = mdev;
4572         priv->netdev      = netdev;
4573         priv->profile     = profile;
4574         priv->ppriv       = ppriv;
4575         priv->msglevel    = MLX5E_MSG_LEVEL;
4576         priv->max_opened_tc = 1;
4577
4578         mlx5e_build_nic_params(mdev, &priv->channels.params,
4579                                profile->max_nch(mdev), netdev->mtu);
4580
4581         mutex_init(&priv->state_lock);
4582
4583         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4584         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4585         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4586         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4587
4588         mlx5e_timestamp_init(priv);
4589 }
4590
4591 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4592 {
4593         struct mlx5e_priv *priv = netdev_priv(netdev);
4594
4595         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4596         if (is_zero_ether_addr(netdev->dev_addr) &&
4597             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4598                 eth_hw_addr_random(netdev);
4599                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4600         }
4601 }
4602
4603 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4604 static const struct switchdev_ops mlx5e_switchdev_ops = {
4605         .switchdev_port_attr_get        = mlx5e_attr_get,
4606 };
4607 #endif
4608
4609 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4610 {
4611         struct mlx5e_priv *priv = netdev_priv(netdev);
4612         struct mlx5_core_dev *mdev = priv->mdev;
4613         bool fcs_supported;
4614         bool fcs_enabled;
4615
4616         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4617
4618         netdev->netdev_ops = &mlx5e_netdev_ops;
4619
4620 #ifdef CONFIG_MLX5_CORE_EN_DCB
4621         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4622                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4623 #endif
4624
4625         netdev->watchdog_timeo    = 15 * HZ;
4626
4627         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4628
4629         netdev->vlan_features    |= NETIF_F_SG;
4630         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4631         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4632         netdev->vlan_features    |= NETIF_F_GRO;
4633         netdev->vlan_features    |= NETIF_F_TSO;
4634         netdev->vlan_features    |= NETIF_F_TSO6;
4635         netdev->vlan_features    |= NETIF_F_RXCSUM;
4636         netdev->vlan_features    |= NETIF_F_RXHASH;
4637
4638         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4639         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4640
4641         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4642             mlx5e_check_fragmented_striding_rq_cap(mdev))
4643                 netdev->vlan_features    |= NETIF_F_LRO;
4644
4645         netdev->hw_features       = netdev->vlan_features;
4646         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4647         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4648         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4649         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4650
4651         if (mlx5_vxlan_allowed(priv->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4652                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4653                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4654                 netdev->hw_enc_features |= NETIF_F_TSO;
4655                 netdev->hw_enc_features |= NETIF_F_TSO6;
4656                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4657         }
4658
4659         if (mlx5_vxlan_allowed(priv->vxlan)) {
4660                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4661                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4662                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4663                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4664                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4665         }
4666
4667         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4668                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4669                                            NETIF_F_GSO_GRE_CSUM;
4670                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4671                                            NETIF_F_GSO_GRE_CSUM;
4672                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4673                                                 NETIF_F_GSO_GRE_CSUM;
4674         }
4675
4676         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4677         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4678         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4679         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4680
4681         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4682
4683         if (fcs_supported)
4684                 netdev->hw_features |= NETIF_F_RXALL;
4685
4686         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4687                 netdev->hw_features |= NETIF_F_RXFCS;
4688
4689         netdev->features          = netdev->hw_features;
4690         if (!priv->channels.params.lro_en)
4691                 netdev->features  &= ~NETIF_F_LRO;
4692
4693         if (fcs_enabled)
4694                 netdev->features  &= ~NETIF_F_RXALL;
4695
4696         if (!priv->channels.params.scatter_fcs_en)
4697                 netdev->features  &= ~NETIF_F_RXFCS;
4698
4699 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4700         if (FT_CAP(flow_modify_en) &&
4701             FT_CAP(modify_root) &&
4702             FT_CAP(identified_miss_table_mode) &&
4703             FT_CAP(flow_table_modify)) {
4704                 netdev->hw_features      |= NETIF_F_HW_TC;
4705 #ifdef CONFIG_RFS_ACCEL
4706                 netdev->hw_features      |= NETIF_F_NTUPLE;
4707 #endif
4708         }
4709
4710         netdev->features         |= NETIF_F_HIGHDMA;
4711         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4712
4713         netdev->priv_flags       |= IFF_UNICAST_FLT;
4714
4715         mlx5e_set_netdev_dev_addr(netdev);
4716
4717 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4718         if (MLX5_ESWITCH_MANAGER(mdev))
4719                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4720 #endif
4721
4722         mlx5e_ipsec_build_netdev(priv);
4723         mlx5e_tls_build_netdev(priv);
4724 }
4725
4726 static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4727 {
4728         struct mlx5_core_dev *mdev = priv->mdev;
4729         int err;
4730
4731         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4732         if (err) {
4733                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4734                 priv->q_counter = 0;
4735         }
4736
4737         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4738         if (err) {
4739                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4740                 priv->drop_rq_q_counter = 0;
4741         }
4742 }
4743
4744 static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4745 {
4746         if (priv->q_counter)
4747                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4748
4749         if (priv->drop_rq_q_counter)
4750                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4751 }
4752
4753 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4754                            struct net_device *netdev,
4755                            const struct mlx5e_profile *profile,
4756                            void *ppriv)
4757 {
4758         struct mlx5e_priv *priv = netdev_priv(netdev);
4759         int err;
4760
4761         priv->vxlan = mlx5_vxlan_create(mdev);
4762
4763         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4764         err = mlx5e_ipsec_init(priv);
4765         if (err)
4766                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4767         err = mlx5e_tls_init(priv);
4768         if (err)
4769                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4770         mlx5e_build_nic_netdev(netdev);
4771         mlx5e_build_tc2txq_maps(priv);
4772 }
4773
4774 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4775 {
4776         mlx5_vxlan_destroy(priv->vxlan);
4777         mlx5e_tls_cleanup(priv);
4778         mlx5e_ipsec_cleanup(priv);
4779 }
4780
4781 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4782 {
4783         struct mlx5_core_dev *mdev = priv->mdev;
4784         int err;
4785
4786         err = mlx5e_create_indirect_rqt(priv);
4787         if (err)
4788                 return err;
4789
4790         err = mlx5e_create_direct_rqts(priv);
4791         if (err)
4792                 goto err_destroy_indirect_rqts;
4793
4794         err = mlx5e_create_indirect_tirs(priv);
4795         if (err)
4796                 goto err_destroy_direct_rqts;
4797
4798         err = mlx5e_create_direct_tirs(priv);
4799         if (err)
4800                 goto err_destroy_indirect_tirs;
4801
4802         err = mlx5e_create_flow_steering(priv);
4803         if (err) {
4804                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4805                 goto err_destroy_direct_tirs;
4806         }
4807
4808         err = mlx5e_tc_nic_init(priv);
4809         if (err)
4810                 goto err_destroy_flow_steering;
4811
4812         return 0;
4813
4814 err_destroy_flow_steering:
4815         mlx5e_destroy_flow_steering(priv);
4816 err_destroy_direct_tirs:
4817         mlx5e_destroy_direct_tirs(priv);
4818 err_destroy_indirect_tirs:
4819         mlx5e_destroy_indirect_tirs(priv);
4820 err_destroy_direct_rqts:
4821         mlx5e_destroy_direct_rqts(priv);
4822 err_destroy_indirect_rqts:
4823         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4824         return err;
4825 }
4826
4827 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4828 {
4829         mlx5e_tc_nic_cleanup(priv);
4830         mlx5e_destroy_flow_steering(priv);
4831         mlx5e_destroy_direct_tirs(priv);
4832         mlx5e_destroy_indirect_tirs(priv);
4833         mlx5e_destroy_direct_rqts(priv);
4834         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4835 }
4836
4837 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4838 {
4839         int err;
4840
4841         err = mlx5e_create_tises(priv);
4842         if (err) {
4843                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4844                 return err;
4845         }
4846
4847 #ifdef CONFIG_MLX5_CORE_EN_DCB
4848         mlx5e_dcbnl_initialize(priv);
4849 #endif
4850         return 0;
4851 }
4852
4853 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4854 {
4855         struct net_device *netdev = priv->netdev;
4856         struct mlx5_core_dev *mdev = priv->mdev;
4857         u16 max_mtu;
4858
4859         mlx5e_init_l2_addr(priv);
4860
4861         /* Marking the link as currently not needed by the Driver */
4862         if (!netif_running(netdev))
4863                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4864
4865         /* MTU range: 68 - hw-specific max */
4866         netdev->min_mtu = ETH_MIN_MTU;
4867         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4868         netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4869         mlx5e_set_dev_port_mtu(priv);
4870
4871         mlx5_lag_add(mdev, netdev);
4872
4873         mlx5e_enable_async_events(priv);
4874
4875         if (MLX5_ESWITCH_MANAGER(priv->mdev))
4876                 mlx5e_register_vport_reps(priv);
4877
4878         if (netdev->reg_state != NETREG_REGISTERED)
4879                 return;
4880 #ifdef CONFIG_MLX5_CORE_EN_DCB
4881         mlx5e_dcbnl_init_app(priv);
4882 #endif
4883
4884         queue_work(priv->wq, &priv->set_rx_mode_work);
4885
4886         rtnl_lock();
4887         if (netif_running(netdev))
4888                 mlx5e_open(netdev);
4889         netif_device_attach(netdev);
4890         rtnl_unlock();
4891 }
4892
4893 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4894 {
4895         struct mlx5_core_dev *mdev = priv->mdev;
4896
4897 #ifdef CONFIG_MLX5_CORE_EN_DCB
4898         if (priv->netdev->reg_state == NETREG_REGISTERED)
4899                 mlx5e_dcbnl_delete_app(priv);
4900 #endif
4901
4902         rtnl_lock();
4903         if (netif_running(priv->netdev))
4904                 mlx5e_close(priv->netdev);
4905         netif_device_detach(priv->netdev);
4906         rtnl_unlock();
4907
4908         queue_work(priv->wq, &priv->set_rx_mode_work);
4909
4910         if (MLX5_ESWITCH_MANAGER(priv->mdev))
4911                 mlx5e_unregister_vport_reps(priv);
4912
4913         mlx5e_disable_async_events(priv);
4914         mlx5_lag_remove(mdev);
4915 }
4916
4917 static const struct mlx5e_profile mlx5e_nic_profile = {
4918         .init              = mlx5e_nic_init,
4919         .cleanup           = mlx5e_nic_cleanup,
4920         .init_rx           = mlx5e_init_nic_rx,
4921         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4922         .init_tx           = mlx5e_init_nic_tx,
4923         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4924         .enable            = mlx5e_nic_enable,
4925         .disable           = mlx5e_nic_disable,
4926         .update_stats      = mlx5e_update_ndo_stats,
4927         .max_nch           = mlx5e_get_max_num_channels,
4928         .update_carrier    = mlx5e_update_carrier,
4929         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4930         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4931         .max_tc            = MLX5E_MAX_NUM_TC,
4932 };
4933
4934 /* mlx5e generic netdev management API (move to en_common.c) */
4935
4936 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4937                                        const struct mlx5e_profile *profile,
4938                                        void *ppriv)
4939 {
4940         int nch = profile->max_nch(mdev);
4941         struct net_device *netdev;
4942         struct mlx5e_priv *priv;
4943
4944         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4945                                     nch * profile->max_tc,
4946                                     nch);
4947         if (!netdev) {
4948                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4949                 return NULL;
4950         }
4951
4952 #ifdef CONFIG_RFS_ACCEL
4953         netdev->rx_cpu_rmap = mdev->rmap;
4954 #endif
4955
4956         profile->init(mdev, netdev, profile, ppriv);
4957
4958         netif_carrier_off(netdev);
4959
4960         priv = netdev_priv(netdev);
4961
4962         priv->wq = create_singlethread_workqueue("mlx5e");
4963         if (!priv->wq)
4964                 goto err_cleanup_nic;
4965
4966         return netdev;
4967
4968 err_cleanup_nic:
4969         if (profile->cleanup)
4970                 profile->cleanup(priv);
4971         free_netdev(netdev);
4972
4973         return NULL;
4974 }
4975
4976 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4977 {
4978         struct mlx5_core_dev *mdev = priv->mdev;
4979         const struct mlx5e_profile *profile;
4980         int err;
4981
4982         profile = priv->profile;
4983         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4984
4985         err = profile->init_tx(priv);
4986         if (err)
4987                 goto out;
4988
4989         mlx5e_create_q_counters(priv);
4990
4991         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4992         if (err) {
4993                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4994                 goto err_destroy_q_counters;
4995         }
4996
4997         err = profile->init_rx(priv);
4998         if (err)
4999                 goto err_close_drop_rq;
5000
5001         if (profile->enable)
5002                 profile->enable(priv);
5003
5004         return 0;
5005
5006 err_close_drop_rq:
5007         mlx5e_close_drop_rq(&priv->drop_rq);
5008
5009 err_destroy_q_counters:
5010         mlx5e_destroy_q_counters(priv);
5011         profile->cleanup_tx(priv);
5012
5013 out:
5014         return err;
5015 }
5016
5017 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5018 {
5019         const struct mlx5e_profile *profile = priv->profile;
5020
5021         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5022
5023         if (profile->disable)
5024                 profile->disable(priv);
5025         flush_workqueue(priv->wq);
5026
5027         profile->cleanup_rx(priv);
5028         mlx5e_close_drop_rq(&priv->drop_rq);
5029         mlx5e_destroy_q_counters(priv);
5030         profile->cleanup_tx(priv);
5031         cancel_delayed_work_sync(&priv->update_stats_work);
5032 }
5033
5034 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5035 {
5036         const struct mlx5e_profile *profile = priv->profile;
5037         struct net_device *netdev = priv->netdev;
5038
5039         destroy_workqueue(priv->wq);
5040         if (profile->cleanup)
5041                 profile->cleanup(priv);
5042         free_netdev(netdev);
5043 }
5044
5045 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5046  * hardware contexts and to connect it to the current netdev.
5047  */
5048 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5049 {
5050         struct mlx5e_priv *priv = vpriv;
5051         struct net_device *netdev = priv->netdev;
5052         int err;
5053
5054         if (netif_device_present(netdev))
5055                 return 0;
5056
5057         err = mlx5e_create_mdev_resources(mdev);
5058         if (err)
5059                 return err;
5060
5061         err = mlx5e_attach_netdev(priv);
5062         if (err) {
5063                 mlx5e_destroy_mdev_resources(mdev);
5064                 return err;
5065         }
5066
5067         return 0;
5068 }
5069
5070 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5071 {
5072         struct mlx5e_priv *priv = vpriv;
5073         struct net_device *netdev = priv->netdev;
5074
5075         if (!netif_device_present(netdev))
5076                 return;
5077
5078         mlx5e_detach_netdev(priv);
5079         mlx5e_destroy_mdev_resources(mdev);
5080 }
5081
5082 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5083 {
5084         struct net_device *netdev;
5085         void *rpriv = NULL;
5086         void *priv;
5087         int err;
5088
5089         err = mlx5e_check_required_hca_cap(mdev);
5090         if (err)
5091                 return NULL;
5092
5093 #ifdef CONFIG_MLX5_ESWITCH
5094         if (MLX5_ESWITCH_MANAGER(mdev)) {
5095                 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
5096                 if (!rpriv) {
5097                         mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
5098                         return NULL;
5099                 }
5100         }
5101 #endif
5102
5103         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
5104         if (!netdev) {
5105                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5106                 goto err_free_rpriv;
5107         }
5108
5109         priv = netdev_priv(netdev);
5110
5111         err = mlx5e_attach(mdev, priv);
5112         if (err) {
5113                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5114                 goto err_destroy_netdev;
5115         }
5116
5117         err = register_netdev(netdev);
5118         if (err) {
5119                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5120                 goto err_detach;
5121         }
5122
5123 #ifdef CONFIG_MLX5_CORE_EN_DCB
5124         mlx5e_dcbnl_init_app(priv);
5125 #endif
5126         return priv;
5127
5128 err_detach:
5129         mlx5e_detach(mdev, priv);
5130 err_destroy_netdev:
5131         mlx5e_destroy_netdev(priv);
5132 err_free_rpriv:
5133         kfree(rpriv);
5134         return NULL;
5135 }
5136
5137 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5138 {
5139         struct mlx5e_priv *priv = vpriv;
5140         void *ppriv = priv->ppriv;
5141
5142 #ifdef CONFIG_MLX5_CORE_EN_DCB
5143         mlx5e_dcbnl_delete_app(priv);
5144 #endif
5145         unregister_netdev(priv->netdev);
5146         mlx5e_detach(mdev, vpriv);
5147         mlx5e_destroy_netdev(priv);
5148         kfree(ppriv);
5149 }
5150
5151 static void *mlx5e_get_netdev(void *vpriv)
5152 {
5153         struct mlx5e_priv *priv = vpriv;
5154
5155         return priv->netdev;
5156 }
5157
5158 static struct mlx5_interface mlx5e_interface = {
5159         .add       = mlx5e_add,
5160         .remove    = mlx5e_remove,
5161         .attach    = mlx5e_attach,
5162         .detach    = mlx5e_detach,
5163         .event     = mlx5e_async_event,
5164         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5165         .get_dev   = mlx5e_get_netdev,
5166 };
5167
5168 void mlx5e_init(void)
5169 {
5170         mlx5e_ipsec_build_inverse_table();
5171         mlx5e_build_ptys2ethtool_map();
5172         mlx5_register_interface(&mlx5e_interface);
5173 }
5174
5175 void mlx5e_cleanup(void)
5176 {
5177         mlx5_unregister_interface(&mlx5e_interface);
5178 }