drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include "eswitch.h"
  39 #include "en.h"
  40 #include "en_tc.h"
  41 #include "en_rep.h"
  42 #include "en_accel/ipsec.h"
  43 #include "en_accel/ipsec_rxtx.h"
  44 #include "accel/ipsec.h"
  45 #include "vxlan.h"
  46
  47 struct mlx5e_rq_param {
  48         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  49         struct mlx5_wq_param    wq;
  50 };
  51
  52 struct mlx5e_sq_param {
  53         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  54         struct mlx5_wq_param       wq;
  55 };
  56
  57 struct mlx5e_cq_param {
  58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  59         struct mlx5_wq_param       wq;
  60         u16                        eq_ix;
  61         u8                         cq_period_mode;
  62 };
  63
  64 struct mlx5e_channel_param {
  65         struct mlx5e_rq_param      rq;
  66         struct mlx5e_sq_param      sq;
  67         struct mlx5e_sq_param      xdp_sq;
  68         struct mlx5e_sq_param      icosq;
  69         struct mlx5e_cq_param      rx_cq;
  70         struct mlx5e_cq_param      tx_cq;
  71         struct mlx5e_cq_param      icosq_cq;
  72 };
  73
  74 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  75 {
  76         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  77                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  78                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  79         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  80         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  81
  82         if (!striding_rq_umr)
  83                 return false;
  84         if (!inline_umr) {
  85                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  86                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  87                 return false;
  88         }
  89         return true;
  90 }
  91
  92 static u32 mlx5e_mpwqe_get_linear_frag_sz(struct mlx5e_params *params)
  93 {
  94         if (!params->xdp_prog) {
  95                 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
  96                 u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN;
  97
  98                 return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu);
  99         }
 100
 101         return PAGE_SIZE;
 102 }
 103
 104 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 105 {
 106         u32 linear_frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
 107
 108         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 109 }
 110
 111 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 112                                          struct mlx5e_params *params)
 113 {
 114         u32 frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
 115         s8 signed_log_num_strides_param;
 116         u8 log_num_strides;
 117
 118         if (params->lro_en || frag_sz > PAGE_SIZE)
 119                 return false;
 120
 121         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 122                 return true;
 123
 124         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 125         signed_log_num_strides_param =
 126                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 127
 128         return signed_log_num_strides_param >= 0;
 129 }
 130
 131 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 132 {
 133         if (params->log_rq_mtu_frames <
 134             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 135                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 136
 137         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 138 }
 139
 140 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 141                                           struct mlx5e_params *params)
 142 {
 143         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 144                 return order_base_2(mlx5e_mpwqe_get_linear_frag_sz(params));
 145
 146         return MLX5E_MPWQE_STRIDE_SZ(mdev,
 147                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 148 }
 149
 150 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 151                                           struct mlx5e_params *params)
 152 {
 153         return MLX5_MPWRQ_LOG_WQE_SZ -
 154                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 155 }
 156
 157 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 158                                  struct mlx5e_params *params)
 159 {
 160         u16 linear_rq_headroom = params->xdp_prog ?
 161                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 162
 163         linear_rq_headroom += NET_IP_ALIGN;
 164
 165         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)
 166                 return linear_rq_headroom;
 167
 168         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 169                 return linear_rq_headroom;
 170
 171         return 0;
 172 }
 173
 174 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 175                                struct mlx5e_params *params)
 176 {
 177         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 178         params->log_rq_mtu_frames = is_kdump_kernel() ?
 179                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 180                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 181         switch (params->rq_wq_type) {
 182         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 183                 break;
 184         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 185                 /* Extra room needed for build_skb */
 186                 params->lro_wqe_sz -= mlx5e_get_rq_headroom(mdev, params) +
 187                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 188         }
 189
 190         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 191                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 192                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 193                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 194                        BIT(params->log_rq_mtu_frames),
 195                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 196                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 197 }
 198
 199 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 200                                 struct mlx5e_params *params)
 201 {
 202         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 203                 !MLX5_IPSEC_DEV(mdev) &&
 204                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 205 }
 206
 207 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 208 {
 209         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 210                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 211                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 212                 MLX5_WQ_TYPE_LINKED_LIST;
 213 }
 214
 215 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 216 {
 217         struct mlx5_core_dev *mdev = priv->mdev;
 218         u8 port_state;
 219
 220         port_state = mlx5_query_vport_state(mdev,
 221                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
 222                                             0);
 223
 224         if (port_state == VPORT_STATE_UP) {
 225                 netdev_info(priv->netdev, "Link up\n");
 226                 netif_carrier_on(priv->netdev);
 227         } else {
 228                 netdev_info(priv->netdev, "Link down\n");
 229                 netif_carrier_off(priv->netdev);
 230         }
 231 }
 232
 233 static void mlx5e_update_carrier_work(struct work_struct *work)
 234 {
 235         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 236                                                update_carrier_work);
 237
 238         mutex_lock(&priv->state_lock);
 239         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 240                 if (priv->profile->update_carrier)
 241                         priv->profile->update_carrier(priv);
 242         mutex_unlock(&priv->state_lock);
 243 }
 244
 245 void mlx5e_update_stats(struct mlx5e_priv *priv)
 246 {
 247         int i;
 248
 249         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 250                 if (mlx5e_stats_grps[i].update_stats)
 251                         mlx5e_stats_grps[i].update_stats(priv);
 252 }
 253
 254 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 255 {
 256         int i;
 257
 258         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 259                 if (mlx5e_stats_grps[i].update_stats_mask &
 260                     MLX5E_NDO_UPDATE_STATS)
 261                         mlx5e_stats_grps[i].update_stats(priv);
 262 }
 263
 264 void mlx5e_update_stats_work(struct work_struct *work)
 265 {
 266         struct delayed_work *dwork = to_delayed_work(work);
 267         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 268                                                update_stats_work);
 269         mutex_lock(&priv->state_lock);
 270         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 271                 priv->profile->update_stats(priv);
 272                 queue_delayed_work(priv->wq, dwork,
 273                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 274         }
 275         mutex_unlock(&priv->state_lock);
 276 }
 277
 278 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 279                               enum mlx5_dev_event event, unsigned long param)
 280 {
 281         struct mlx5e_priv *priv = vpriv;
 282
 283         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 284                 return;
 285
 286         switch (event) {
 287         case MLX5_DEV_EVENT_PORT_UP:
 288         case MLX5_DEV_EVENT_PORT_DOWN:
 289                 queue_work(priv->wq, &priv->update_carrier_work);
 290                 break;
 291         default:
 292                 break;
 293         }
 294 }
 295
 296 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 297 {
 298         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 299 }
 300
 301 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 302 {
 303         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 304         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 305 }
 306
 307 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 308                                        struct mlx5e_icosq *sq,
 309                                        struct mlx5e_umr_wqe *wqe)
 310 {
 311         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 312         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 313         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 314
 315         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 316                                       ds_cnt);
 317         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 318         cseg->imm       = rq->mkey_be;
 319
 320         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 321         ucseg->xlt_octowords =
 322                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 323         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 324 }
 325
 326 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 327                                      struct mlx5e_channel *c)
 328 {
 329         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 330
 331         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 332                                       GFP_KERNEL, cpu_to_node(c->cpu));
 333         if (!rq->mpwqe.info)
 334                 return -ENOMEM;
 335
 336         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 337
 338         return 0;
 339 }
 340
 341 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 342                                  u64 npages, u8 page_shift,
 343                                  struct mlx5_core_mkey *umr_mkey)
 344 {
 345         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 346         void *mkc;
 347         u32 *in;
 348         int err;
 349
 350         in = kvzalloc(inlen, GFP_KERNEL);
 351         if (!in)
 352                 return -ENOMEM;
 353
 354         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 355
 356         MLX5_SET(mkc, mkc, free, 1);
 357         MLX5_SET(mkc, mkc, umr_en, 1);
 358         MLX5_SET(mkc, mkc, lw, 1);
 359         MLX5_SET(mkc, mkc, lr, 1);
 360         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 361
 362         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 363         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 364         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 365         MLX5_SET(mkc, mkc, translations_octword_size,
 366                  MLX5_MTT_OCTW(npages));
 367         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 368
 369         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 370
 371         kvfree(in);
 372         return err;
 373 }
 374
 375 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 376 {
 377         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
 378
 379         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 380 }
 381
 382 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 383 {
 384         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 385 }
 386
 387 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 388                           struct mlx5e_params *params,
 389                           struct mlx5e_rq_param *rqp,
 390                           struct mlx5e_rq *rq)
 391 {
 392         struct mlx5_core_dev *mdev = c->mdev;
 393         void *rqc = rqp->rqc;
 394         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 395         u32 byte_count;
 396         int npages;
 397         int wq_sz;
 398         int err;
 399         int i;
 400
 401         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 402
 403         err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
 404                                 &rq->wq_ctrl);
 405         if (err)
 406                 return err;
 407
 408         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 409
 410         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 411
 412         rq->wq_type = params->rq_wq_type;
 413         rq->pdev    = c->pdev;
 414         rq->netdev  = c->netdev;
 415         rq->tstamp  = c->tstamp;
 416         rq->clock   = &mdev->clock;
 417         rq->channel = c;
 418         rq->ix      = c->ix;
 419         rq->mdev    = mdev;
 420         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 421
 422         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 423         if (IS_ERR(rq->xdp_prog)) {
 424                 err = PTR_ERR(rq->xdp_prog);
 425                 rq->xdp_prog = NULL;
 426                 goto err_rq_wq_destroy;
 427         }
 428
 429         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 430         if (err < 0)
 431                 goto err_rq_wq_destroy;
 432
 433         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 434         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 435
 436         switch (rq->wq_type) {
 437         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 438                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 439                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 440
 441                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 442 #ifdef CONFIG_MLX5_EN_IPSEC
 443                 if (MLX5_IPSEC_DEV(mdev)) {
 444                         err = -EINVAL;
 445                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 446                         goto err_rq_wq_destroy;
 447                 }
 448 #endif
 449                 if (!rq->handle_rx_cqe) {
 450                         err = -EINVAL;
 451                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 452                         goto err_rq_wq_destroy;
 453                 }
 454
 455                 rq->mpwqe.skb_from_cqe_mpwrq =
 456                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 457                         mlx5e_skb_from_cqe_mpwrq_linear :
 458                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 459                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 460                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 461
 462                 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 463
 464                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 465                 if (err)
 466                         goto err_rq_wq_destroy;
 467                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 468
 469                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 470                 if (err)
 471                         goto err_destroy_umr_mkey;
 472                 break;
 473         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 474                 rq->wqe.frag_info =
 475                         kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
 476                                      GFP_KERNEL, cpu_to_node(c->cpu));
 477                 if (!rq->wqe.frag_info) {
 478                         err = -ENOMEM;
 479                         goto err_rq_wq_destroy;
 480                 }
 481                 rq->post_wqes = mlx5e_post_rx_wqes;
 482                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 483
 484 #ifdef CONFIG_MLX5_EN_IPSEC
 485                 if (c->priv->ipsec)
 486                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 487                 else
 488 #endif
 489                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 490                 if (!rq->handle_rx_cqe) {
 491                         kfree(rq->wqe.frag_info);
 492                         err = -EINVAL;
 493                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 494                         goto err_rq_wq_destroy;
 495                 }
 496
 497                 byte_count = params->lro_en  ?
 498                                 params->lro_wqe_sz :
 499                                 MLX5E_SW2HW_MTU(params, params->sw_mtu);
 500 #ifdef CONFIG_MLX5_EN_IPSEC
 501                 if (MLX5_IPSEC_DEV(mdev))
 502                         byte_count += MLX5E_METADATA_ETHER_LEN;
 503 #endif
 504                 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
 505
 506                 /* calc the required page order */
 507                 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
 508                 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
 509                 rq->buff.page_order = order_base_2(npages);
 510
 511                 byte_count |= MLX5_HW_START_PADDING;
 512                 rq->mkey_be = c->mkey_be;
 513         }
 514
 515         /* This must only be activate for order-0 pages */
 516         if (rq->xdp_prog) {
 517                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 518                                                  MEM_TYPE_PAGE_ORDER0, NULL);
 519                 if (err)
 520                         goto err_rq_wq_destroy;
 521         }
 522
 523         for (i = 0; i < wq_sz; i++) {
 524                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 525
 526                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 527                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 528
 529                         wqe->data.addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 530                 }
 531
 532                 wqe->data.byte_count = cpu_to_be32(byte_count);
 533                 wqe->data.lkey = rq->mkey_be;
 534         }
 535
 536         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 537
 538         switch (params->rx_cq_moderation.cq_period_mode) {
 539         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 540                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 541                 break;
 542         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 543         default:
 544                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 545         }
 546
 547         rq->page_cache.head = 0;
 548         rq->page_cache.tail = 0;
 549
 550         return 0;
 551
 552 err_destroy_umr_mkey:
 553         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 554
 555 err_rq_wq_destroy:
 556         if (rq->xdp_prog)
 557                 bpf_prog_put(rq->xdp_prog);
 558         xdp_rxq_info_unreg(&rq->xdp_rxq);
 559         mlx5_wq_destroy(&rq->wq_ctrl);
 560
 561         return err;
 562 }
 563
 564 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 565 {
 566         int i;
 567
 568         if (rq->xdp_prog)
 569                 bpf_prog_put(rq->xdp_prog);
 570
 571         xdp_rxq_info_unreg(&rq->xdp_rxq);
 572
 573         switch (rq->wq_type) {
 574         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 575                 kfree(rq->mpwqe.info);
 576                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 577                 break;
 578         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 579                 kfree(rq->wqe.frag_info);
 580         }
 581
 582         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 583              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 584                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 585
 586                 mlx5e_page_release(rq, dma_info, false);
 587         }
 588         mlx5_wq_destroy(&rq->wq_ctrl);
 589 }
 590
 591 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 592                            struct mlx5e_rq_param *param)
 593 {
 594         struct mlx5_core_dev *mdev = rq->mdev;
 595
 596         void *in;
 597         void *rqc;
 598         void *wq;
 599         int inlen;
 600         int err;
 601
 602         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 603                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 604         in = kvzalloc(inlen, GFP_KERNEL);
 605         if (!in)
 606                 return -ENOMEM;
 607
 608         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 609         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 610
 611         memcpy(rqc, param->rqc, sizeof(param->rqc));
 612
 613         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 614         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 615         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 616                                                 MLX5_ADAPTER_PAGE_SHIFT);
 617         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 618
 619         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 620                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 621
 622         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 623
 624         kvfree(in);
 625
 626         return err;
 627 }
 628
 629 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 630                                  int next_state)
 631 {
 632         struct mlx5_core_dev *mdev = rq->mdev;
 633
 634         void *in;
 635         void *rqc;
 636         int inlen;
 637         int err;
 638
 639         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 640         in = kvzalloc(inlen, GFP_KERNEL);
 641         if (!in)
 642                 return -ENOMEM;
 643
 644         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 645
 646         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 647         MLX5_SET(rqc, rqc, state, next_state);
 648
 649         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 650
 651         kvfree(in);
 652
 653         return err;
 654 }
 655
 656 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 657 {
 658         struct mlx5e_channel *c = rq->channel;
 659         struct mlx5e_priv *priv = c->priv;
 660         struct mlx5_core_dev *mdev = priv->mdev;
 661
 662         void *in;
 663         void *rqc;
 664         int inlen;
 665         int err;
 666
 667         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 668         in = kvzalloc(inlen, GFP_KERNEL);
 669         if (!in)
 670                 return -ENOMEM;
 671
 672         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 673
 674         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 675         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 676                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 677         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 678         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 679
 680         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 681
 682         kvfree(in);
 683
 684         return err;
 685 }
 686
 687 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 688 {
 689         struct mlx5e_channel *c = rq->channel;
 690         struct mlx5_core_dev *mdev = c->mdev;
 691         void *in;
 692         void *rqc;
 693         int inlen;
 694         int err;
 695
 696         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 697         in = kvzalloc(inlen, GFP_KERNEL);
 698         if (!in)
 699                 return -ENOMEM;
 700
 701         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 702
 703         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 704         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 705                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 706         MLX5_SET(rqc, rqc, vsd, vsd);
 707         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 708
 709         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 710
 711         kvfree(in);
 712
 713         return err;
 714 }
 715
 716 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 717 {
 718         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 719 }
 720
 721 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 722 {
 723         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 724         struct mlx5e_channel *c = rq->channel;
 725
 726         struct mlx5_wq_ll *wq = &rq->wq;
 727         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
 728
 729         while (time_before(jiffies, exp_time)) {
 730                 if (wq->cur_sz >= min_wqes)
 731                         return 0;
 732
 733                 msleep(20);
 734         }
 735
 736         netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 737                     rq->rqn, wq->cur_sz, min_wqes);
 738         return -ETIMEDOUT;
 739 }
 740
 741 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 742 {
 743         struct mlx5_wq_ll *wq = &rq->wq;
 744         struct mlx5e_rx_wqe *wqe;
 745         __be16 wqe_ix_be;
 746         u16 wqe_ix;
 747
 748         /* UMR WQE (if in progress) is always at wq->head */
 749         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
 750             rq->mpwqe.umr_in_progress)
 751                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 752
 753         while (!mlx5_wq_ll_is_empty(wq)) {
 754                 wqe_ix_be = *wq->tail_next;
 755                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 756                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 757                 rq->dealloc_wqe(rq, wqe_ix);
 758                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 759                                &wqe->next.next_wqe_index);
 760         }
 761
 762         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
 763                 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
 764                  * but yet to be re-posted.
 765                  */
 766                 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 767
 768                 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
 769                         rq->dealloc_wqe(rq, wqe_ix);
 770         }
 771 }
 772
 773 static int mlx5e_open_rq(struct mlx5e_channel *c,
 774                          struct mlx5e_params *params,
 775                          struct mlx5e_rq_param *param,
 776                          struct mlx5e_rq *rq)
 777 {
 778         int err;
 779
 780         err = mlx5e_alloc_rq(c, params, param, rq);
 781         if (err)
 782                 return err;
 783
 784         err = mlx5e_create_rq(rq, param);
 785         if (err)
 786                 goto err_free_rq;
 787
 788         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 789         if (err)
 790                 goto err_destroy_rq;
 791
 792         if (params->rx_dim_enabled)
 793                 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
 794
 795         return 0;
 796
 797 err_destroy_rq:
 798         mlx5e_destroy_rq(rq);
 799 err_free_rq:
 800         mlx5e_free_rq(rq);
 801
 802         return err;
 803 }
 804
 805 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 806 {
 807         struct mlx5e_icosq *sq = &rq->channel->icosq;
 808         u16 pi = sq->pc & sq->wq.sz_m1;
 809         struct mlx5e_tx_wqe *nopwqe;
 810
 811         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 812         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 813         nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
 814         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 815 }
 816
 817 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 818 {
 819         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 820         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 821 }
 822
 823 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 824 {
 825         cancel_work_sync(&rq->dim.work);
 826         mlx5e_destroy_rq(rq);
 827         mlx5e_free_rx_descs(rq);
 828         mlx5e_free_rq(rq);
 829 }
 830
 831 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 832 {
 833         kfree(sq->db.di);
 834 }
 835
 836 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 837 {
 838         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 839
 840         sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
 841                                      GFP_KERNEL, numa);
 842         if (!sq->db.di) {
 843                 mlx5e_free_xdpsq_db(sq);
 844                 return -ENOMEM;
 845         }
 846
 847         return 0;
 848 }
 849
 850 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 851                              struct mlx5e_params *params,
 852                              struct mlx5e_sq_param *param,
 853                              struct mlx5e_xdpsq *sq)
 854 {
 855         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 856         struct mlx5_core_dev *mdev = c->mdev;
 857         int err;
 858
 859         sq->pdev      = c->pdev;
 860         sq->mkey_be   = c->mkey_be;
 861         sq->channel   = c;
 862         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 863         sq->min_inline_mode = params->tx_min_inline_mode;
 864
 865         param->wq.db_numa_node = cpu_to_node(c->cpu);
 866         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 867         if (err)
 868                 return err;
 869         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 870
 871         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 872         if (err)
 873                 goto err_sq_wq_destroy;
 874
 875         return 0;
 876
 877 err_sq_wq_destroy:
 878         mlx5_wq_destroy(&sq->wq_ctrl);
 879
 880         return err;
 881 }
 882
 883 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
 884 {
 885         mlx5e_free_xdpsq_db(sq);
 886         mlx5_wq_destroy(&sq->wq_ctrl);
 887 }
 888
 889 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
 890 {
 891         kfree(sq->db.ico_wqe);
 892 }
 893
 894 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
 895 {
 896         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 897
 898         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 899                                       GFP_KERNEL, numa);
 900         if (!sq->db.ico_wqe)
 901                 return -ENOMEM;
 902
 903         return 0;
 904 }
 905
 906 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
 907                              struct mlx5e_sq_param *param,
 908                              struct mlx5e_icosq *sq)
 909 {
 910         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 911         struct mlx5_core_dev *mdev = c->mdev;
 912         int err;
 913
 914         sq->channel   = c;
 915         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 916
 917         param->wq.db_numa_node = cpu_to_node(c->cpu);
 918         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 919         if (err)
 920                 return err;
 921         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 922
 923         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
 924         if (err)
 925                 goto err_sq_wq_destroy;
 926
 927         sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
 928
 929         return 0;
 930
 931 err_sq_wq_destroy:
 932         mlx5_wq_destroy(&sq->wq_ctrl);
 933
 934         return err;
 935 }
 936
 937 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
 938 {
 939         mlx5e_free_icosq_db(sq);
 940         mlx5_wq_destroy(&sq->wq_ctrl);
 941 }
 942
 943 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
 944 {
 945         kfree(sq->db.wqe_info);
 946         kfree(sq->db.dma_fifo);
 947 }
 948
 949 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
 950 {
 951         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 952         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 953
 954         sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
 955                                            GFP_KERNEL, numa);
 956         sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
 957                                            GFP_KERNEL, numa);
 958         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
 959                 mlx5e_free_txqsq_db(sq);
 960                 return -ENOMEM;
 961         }
 962
 963         sq->dma_fifo_mask = df_sz - 1;
 964
 965         return 0;
 966 }
 967
 968 static void mlx5e_sq_recover(struct work_struct *work);
 969 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
 970                              int txq_ix,
 971                              struct mlx5e_params *params,
 972                              struct mlx5e_sq_param *param,
 973                              struct mlx5e_txqsq *sq)
 974 {
 975         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 976         struct mlx5_core_dev *mdev = c->mdev;
 977         int err;
 978
 979         sq->pdev      = c->pdev;
 980         sq->tstamp    = c->tstamp;
 981         sq->clock     = &mdev->clock;
 982         sq->mkey_be   = c->mkey_be;
 983         sq->channel   = c;
 984         sq->txq_ix    = txq_ix;
 985         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 986         sq->min_inline_mode = params->tx_min_inline_mode;
 987         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
 988         if (MLX5_IPSEC_DEV(c->priv->mdev))
 989                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
 990
 991         param->wq.db_numa_node = cpu_to_node(c->cpu);
 992         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 993         if (err)
 994                 return err;
 995         sq->wq.db    = &sq->wq.db[MLX5_SND_DBR];
 996
 997         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
 998         if (err)
 999                 goto err_sq_wq_destroy;
1000
1001         sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1002
1003         return 0;
1004
1005 err_sq_wq_destroy:
1006         mlx5_wq_destroy(&sq->wq_ctrl);
1007
1008         return err;
1009 }
1010
1011 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1012 {
1013         mlx5e_free_txqsq_db(sq);
1014         mlx5_wq_destroy(&sq->wq_ctrl);
1015 }
1016
1017 struct mlx5e_create_sq_param {
1018         struct mlx5_wq_ctrl        *wq_ctrl;
1019         u32                         cqn;
1020         u32                         tisn;
1021         u8                          tis_lst_sz;
1022         u8                          min_inline_mode;
1023 };
1024
1025 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1026                            struct mlx5e_sq_param *param,
1027                            struct mlx5e_create_sq_param *csp,
1028                            u32 *sqn)
1029 {
1030         void *in;
1031         void *sqc;
1032         void *wq;
1033         int inlen;
1034         int err;
1035
1036         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1037                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1038         in = kvzalloc(inlen, GFP_KERNEL);
1039         if (!in)
1040                 return -ENOMEM;
1041
1042         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1043         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1044
1045         memcpy(sqc, param->sqc, sizeof(param->sqc));
1046         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1047         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1048         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1049
1050         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1051                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1052
1053         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1054         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1055
1056         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1057         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1058         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1059                                           MLX5_ADAPTER_PAGE_SHIFT);
1060         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1061
1062         mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1063
1064         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1065
1066         kvfree(in);
1067
1068         return err;
1069 }
1070
1071 struct mlx5e_modify_sq_param {
1072         int curr_state;
1073         int next_state;
1074         bool rl_update;
1075         int rl_index;
1076 };
1077
1078 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1079                            struct mlx5e_modify_sq_param *p)
1080 {
1081         void *in;
1082         void *sqc;
1083         int inlen;
1084         int err;
1085
1086         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1087         in = kvzalloc(inlen, GFP_KERNEL);
1088         if (!in)
1089                 return -ENOMEM;
1090
1091         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1092
1093         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1094         MLX5_SET(sqc, sqc, state, p->next_state);
1095         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1096                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1097                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1098         }
1099
1100         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1101
1102         kvfree(in);
1103
1104         return err;
1105 }
1106
1107 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1108 {
1109         mlx5_core_destroy_sq(mdev, sqn);
1110 }
1111
1112 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1113                                struct mlx5e_sq_param *param,
1114                                struct mlx5e_create_sq_param *csp,
1115                                u32 *sqn)
1116 {
1117         struct mlx5e_modify_sq_param msp = {0};
1118         int err;
1119
1120         err = mlx5e_create_sq(mdev, param, csp, sqn);
1121         if (err)
1122                 return err;
1123
1124         msp.curr_state = MLX5_SQC_STATE_RST;
1125         msp.next_state = MLX5_SQC_STATE_RDY;
1126         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1127         if (err)
1128                 mlx5e_destroy_sq(mdev, *sqn);
1129
1130         return err;
1131 }
1132
1133 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1134                                 struct mlx5e_txqsq *sq, u32 rate);
1135
1136 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1137                             u32 tisn,
1138                             int txq_ix,
1139                             struct mlx5e_params *params,
1140                             struct mlx5e_sq_param *param,
1141                             struct mlx5e_txqsq *sq)
1142 {
1143         struct mlx5e_create_sq_param csp = {};
1144         u32 tx_rate;
1145         int err;
1146
1147         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1148         if (err)
1149                 return err;
1150
1151         csp.tisn            = tisn;
1152         csp.tis_lst_sz      = 1;
1153         csp.cqn             = sq->cq.mcq.cqn;
1154         csp.wq_ctrl         = &sq->wq_ctrl;
1155         csp.min_inline_mode = sq->min_inline_mode;
1156         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1157         if (err)
1158                 goto err_free_txqsq;
1159
1160         tx_rate = c->priv->tx_rates[sq->txq_ix];
1161         if (tx_rate)
1162                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1163
1164         return 0;
1165
1166 err_free_txqsq:
1167         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1168         mlx5e_free_txqsq(sq);
1169
1170         return err;
1171 }
1172
1173 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1174 {
1175         WARN_ONCE(sq->cc != sq->pc,
1176                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1177                   sq->sqn, sq->cc, sq->pc);
1178         sq->cc = 0;
1179         sq->dma_fifo_cc = 0;
1180         sq->pc = 0;
1181 }
1182
1183 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1184 {
1185         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1186         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1187         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1188         netdev_tx_reset_queue(sq->txq);
1189         netif_tx_start_queue(sq->txq);
1190 }
1191
1192 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1193 {
1194         __netif_tx_lock_bh(txq);
1195         netif_tx_stop_queue(txq);
1196         __netif_tx_unlock_bh(txq);
1197 }
1198
1199 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1200 {
1201         struct mlx5e_channel *c = sq->channel;
1202
1203         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1204         /* prevent netif_tx_wake_queue */
1205         napi_synchronize(&c->napi);
1206
1207         netif_tx_disable_queue(sq->txq);
1208
1209         /* last doorbell out, godspeed .. */
1210         if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1211                 struct mlx5e_tx_wqe *nop;
1212
1213                 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1214                 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1215                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1216         }
1217 }
1218
1219 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1220 {
1221         struct mlx5e_channel *c = sq->channel;
1222         struct mlx5_core_dev *mdev = c->mdev;
1223         struct mlx5_rate_limit rl = {0};
1224
1225         mlx5e_destroy_sq(mdev, sq->sqn);
1226         if (sq->rate_limit) {
1227                 rl.rate = sq->rate_limit;
1228                 mlx5_rl_remove_rate(mdev, &rl);
1229         }
1230         mlx5e_free_txqsq_descs(sq);
1231         mlx5e_free_txqsq(sq);
1232 }
1233
1234 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1235 {
1236         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1237
1238         while (time_before(jiffies, exp_time)) {
1239                 if (sq->cc == sq->pc)
1240                         return 0;
1241
1242                 msleep(20);
1243         }
1244
1245         netdev_err(sq->channel->netdev,
1246                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1247                    sq->sqn, sq->cc, sq->pc);
1248
1249         return -ETIMEDOUT;
1250 }
1251
1252 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1253 {
1254         struct mlx5_core_dev *mdev = sq->channel->mdev;
1255         struct net_device *dev = sq->channel->netdev;
1256         struct mlx5e_modify_sq_param msp = {0};
1257         int err;
1258
1259         msp.curr_state = curr_state;
1260         msp.next_state = MLX5_SQC_STATE_RST;
1261
1262         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1263         if (err) {
1264                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1265                 return err;
1266         }
1267
1268         memset(&msp, 0, sizeof(msp));
1269         msp.curr_state = MLX5_SQC_STATE_RST;
1270         msp.next_state = MLX5_SQC_STATE_RDY;
1271
1272         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1273         if (err) {
1274                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1275                 return err;
1276         }
1277
1278         return 0;
1279 }
1280
1281 static void mlx5e_sq_recover(struct work_struct *work)
1282 {
1283         struct mlx5e_txqsq_recover *recover =
1284                 container_of(work, struct mlx5e_txqsq_recover,
1285                              recover_work);
1286         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1287                                               recover);
1288         struct mlx5_core_dev *mdev = sq->channel->mdev;
1289         struct net_device *dev = sq->channel->netdev;
1290         u8 state;
1291         int err;
1292
1293         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1294         if (err) {
1295                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1296                            sq->sqn, err);
1297                 return;
1298         }
1299
1300         if (state != MLX5_RQC_STATE_ERR) {
1301                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1302                 return;
1303         }
1304
1305         netif_tx_disable_queue(sq->txq);
1306
1307         if (mlx5e_wait_for_sq_flush(sq))
1308                 return;
1309
1310         /* If the interval between two consecutive recovers per SQ is too
1311          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1312          * If we reached this state, there is probably a bug that needs to be
1313          * fixed. let's keep the queue close and let tx timeout cleanup.
1314          */
1315         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1316             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1317                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1318                            sq->sqn);
1319                 return;
1320         }
1321
1322         /* At this point, no new packets will arrive from the stack as TXQ is
1323          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1324          * pending WQEs.  SQ can safely reset the SQ.
1325          */
1326         if (mlx5e_sq_to_ready(sq, state))
1327                 return;
1328
1329         mlx5e_reset_txqsq_cc_pc(sq);
1330         sq->stats.recover++;
1331         recover->last_recover = jiffies;
1332         mlx5e_activate_txqsq(sq);
1333 }
1334
1335 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1336                             struct mlx5e_params *params,
1337                             struct mlx5e_sq_param *param,
1338                             struct mlx5e_icosq *sq)
1339 {
1340         struct mlx5e_create_sq_param csp = {};
1341         int err;
1342
1343         err = mlx5e_alloc_icosq(c, param, sq);
1344         if (err)
1345                 return err;
1346
1347         csp.cqn             = sq->cq.mcq.cqn;
1348         csp.wq_ctrl         = &sq->wq_ctrl;
1349         csp.min_inline_mode = params->tx_min_inline_mode;
1350         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1351         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1352         if (err)
1353                 goto err_free_icosq;
1354
1355         return 0;
1356
1357 err_free_icosq:
1358         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1359         mlx5e_free_icosq(sq);
1360
1361         return err;
1362 }
1363
1364 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1365 {
1366         struct mlx5e_channel *c = sq->channel;
1367
1368         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1369         napi_synchronize(&c->napi);
1370
1371         mlx5e_destroy_sq(c->mdev, sq->sqn);
1372         mlx5e_free_icosq(sq);
1373 }
1374
1375 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1376                             struct mlx5e_params *params,
1377                             struct mlx5e_sq_param *param,
1378                             struct mlx5e_xdpsq *sq)
1379 {
1380         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1381         struct mlx5e_create_sq_param csp = {};
1382         unsigned int inline_hdr_sz = 0;
1383         int err;
1384         int i;
1385
1386         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1387         if (err)
1388                 return err;
1389
1390         csp.tis_lst_sz      = 1;
1391         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1392         csp.cqn             = sq->cq.mcq.cqn;
1393         csp.wq_ctrl         = &sq->wq_ctrl;
1394         csp.min_inline_mode = sq->min_inline_mode;
1395         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1396         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1397         if (err)
1398                 goto err_free_xdpsq;
1399
1400         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1401                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1402                 ds_cnt++;
1403         }
1404
1405         /* Pre initialize fixed WQE fields */
1406         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1407                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1408                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1409                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1410                 struct mlx5_wqe_data_seg *dseg;
1411
1412                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1413                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1414
1415                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1416                 dseg->lkey = sq->mkey_be;
1417         }
1418
1419         return 0;
1420
1421 err_free_xdpsq:
1422         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1423         mlx5e_free_xdpsq(sq);
1424
1425         return err;
1426 }
1427
1428 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1429 {
1430         struct mlx5e_channel *c = sq->channel;
1431
1432         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1433         napi_synchronize(&c->napi);
1434
1435         mlx5e_destroy_sq(c->mdev, sq->sqn);
1436         mlx5e_free_xdpsq_descs(sq);
1437         mlx5e_free_xdpsq(sq);
1438 }
1439
1440 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1441                                  struct mlx5e_cq_param *param,
1442                                  struct mlx5e_cq *cq)
1443 {
1444         struct mlx5_core_cq *mcq = &cq->mcq;
1445         int eqn_not_used;
1446         unsigned int irqn;
1447         int err;
1448         u32 i;
1449
1450         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1451                                &cq->wq_ctrl);
1452         if (err)
1453                 return err;
1454
1455         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1456
1457         mcq->cqe_sz     = 64;
1458         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1459         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1460         *mcq->set_ci_db = 0;
1461         *mcq->arm_db    = 0;
1462         mcq->vector     = param->eq_ix;
1463         mcq->comp       = mlx5e_completion_event;
1464         mcq->event      = mlx5e_cq_error_event;
1465         mcq->irqn       = irqn;
1466
1467         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1468                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1469
1470                 cqe->op_own = 0xf1;
1471         }
1472
1473         cq->mdev = mdev;
1474
1475         return 0;
1476 }
1477
1478 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1479                           struct mlx5e_cq_param *param,
1480                           struct mlx5e_cq *cq)
1481 {
1482         struct mlx5_core_dev *mdev = c->priv->mdev;
1483         int err;
1484
1485         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1486         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1487         param->eq_ix   = c->ix;
1488
1489         err = mlx5e_alloc_cq_common(mdev, param, cq);
1490
1491         cq->napi    = &c->napi;
1492         cq->channel = c;
1493
1494         return err;
1495 }
1496
1497 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1498 {
1499         mlx5_cqwq_destroy(&cq->wq_ctrl);
1500 }
1501
1502 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1503 {
1504         struct mlx5_core_dev *mdev = cq->mdev;
1505         struct mlx5_core_cq *mcq = &cq->mcq;
1506
1507         void *in;
1508         void *cqc;
1509         int inlen;
1510         unsigned int irqn_not_used;
1511         int eqn;
1512         int err;
1513
1514         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1515                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1516         in = kvzalloc(inlen, GFP_KERNEL);
1517         if (!in)
1518                 return -ENOMEM;
1519
1520         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1521
1522         memcpy(cqc, param->cqc, sizeof(param->cqc));
1523
1524         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1525                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1526
1527         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1528
1529         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1530         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1531         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1532         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1533                                             MLX5_ADAPTER_PAGE_SHIFT);
1534         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1535
1536         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1537
1538         kvfree(in);
1539
1540         if (err)
1541                 return err;
1542
1543         mlx5e_cq_arm(cq);
1544
1545         return 0;
1546 }
1547
1548 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1549 {
1550         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1551 }
1552
1553 static int mlx5e_open_cq(struct mlx5e_channel *c,
1554                          struct net_dim_cq_moder moder,
1555                          struct mlx5e_cq_param *param,
1556                          struct mlx5e_cq *cq)
1557 {
1558         struct mlx5_core_dev *mdev = c->mdev;
1559         int err;
1560
1561         err = mlx5e_alloc_cq(c, param, cq);
1562         if (err)
1563                 return err;
1564
1565         err = mlx5e_create_cq(cq, param);
1566         if (err)
1567                 goto err_free_cq;
1568
1569         if (MLX5_CAP_GEN(mdev, cq_moderation))
1570                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1571         return 0;
1572
1573 err_free_cq:
1574         mlx5e_free_cq(cq);
1575
1576         return err;
1577 }
1578
1579 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1580 {
1581         mlx5e_destroy_cq(cq);
1582         mlx5e_free_cq(cq);
1583 }
1584
1585 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1586 {
1587         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1588 }
1589
1590 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1591                              struct mlx5e_params *params,
1592                              struct mlx5e_channel_param *cparam)
1593 {
1594         int err;
1595         int tc;
1596
1597         for (tc = 0; tc < c->num_tc; tc++) {
1598                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1599                                     &cparam->tx_cq, &c->sq[tc].cq);
1600                 if (err)
1601                         goto err_close_tx_cqs;
1602         }
1603
1604         return 0;
1605
1606 err_close_tx_cqs:
1607         for (tc--; tc >= 0; tc--)
1608                 mlx5e_close_cq(&c->sq[tc].cq);
1609
1610         return err;
1611 }
1612
1613 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1614 {
1615         int tc;
1616
1617         for (tc = 0; tc < c->num_tc; tc++)
1618                 mlx5e_close_cq(&c->sq[tc].cq);
1619 }
1620
1621 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1622                           struct mlx5e_params *params,
1623                           struct mlx5e_channel_param *cparam)
1624 {
1625         int err;
1626         int tc;
1627
1628         for (tc = 0; tc < params->num_tc; tc++) {
1629                 int txq_ix = c->ix + tc * params->num_channels;
1630
1631                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1632                                        params, &cparam->sq, &c->sq[tc]);
1633                 if (err)
1634                         goto err_close_sqs;
1635         }
1636
1637         return 0;
1638
1639 err_close_sqs:
1640         for (tc--; tc >= 0; tc--)
1641                 mlx5e_close_txqsq(&c->sq[tc]);
1642
1643         return err;
1644 }
1645
1646 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1647 {
1648         int tc;
1649
1650         for (tc = 0; tc < c->num_tc; tc++)
1651                 mlx5e_close_txqsq(&c->sq[tc]);
1652 }
1653
1654 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1655                                 struct mlx5e_txqsq *sq, u32 rate)
1656 {
1657         struct mlx5e_priv *priv = netdev_priv(dev);
1658         struct mlx5_core_dev *mdev = priv->mdev;
1659         struct mlx5e_modify_sq_param msp = {0};
1660         struct mlx5_rate_limit rl = {0};
1661         u16 rl_index = 0;
1662         int err;
1663
1664         if (rate == sq->rate_limit)
1665                 /* nothing to do */
1666                 return 0;
1667
1668         if (sq->rate_limit) {
1669                 rl.rate = sq->rate_limit;
1670                 /* remove current rl index to free space to next ones */
1671                 mlx5_rl_remove_rate(mdev, &rl);
1672         }
1673
1674         sq->rate_limit = 0;
1675
1676         if (rate) {
1677                 rl.rate = rate;
1678                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1679                 if (err) {
1680                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1681                                    rate, err);
1682                         return err;
1683                 }
1684         }
1685
1686         msp.curr_state = MLX5_SQC_STATE_RDY;
1687         msp.next_state = MLX5_SQC_STATE_RDY;
1688         msp.rl_index   = rl_index;
1689         msp.rl_update  = true;
1690         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1691         if (err) {
1692                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1693                            rate, err);
1694                 /* remove the rate from the table */
1695                 if (rate)
1696                         mlx5_rl_remove_rate(mdev, &rl);
1697                 return err;
1698         }
1699
1700         sq->rate_limit = rate;
1701         return 0;
1702 }
1703
1704 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1705 {
1706         struct mlx5e_priv *priv = netdev_priv(dev);
1707         struct mlx5_core_dev *mdev = priv->mdev;
1708         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1709         int err = 0;
1710
1711         if (!mlx5_rl_is_supported(mdev)) {
1712                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1713                 return -EINVAL;
1714         }
1715
1716         /* rate is given in Mb/sec, HW config is in Kb/sec */
1717         rate = rate << 10;
1718
1719         /* Check whether rate in valid range, 0 is always valid */
1720         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1721                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1722                 return -ERANGE;
1723         }
1724
1725         mutex_lock(&priv->state_lock);
1726         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1727                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1728         if (!err)
1729                 priv->tx_rates[index] = rate;
1730         mutex_unlock(&priv->state_lock);
1731
1732         return err;
1733 }
1734
1735 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1736                               struct mlx5e_params *params,
1737                               struct mlx5e_channel_param *cparam,
1738                               struct mlx5e_channel **cp)
1739 {
1740         struct net_dim_cq_moder icocq_moder = {0, 0};
1741         struct net_device *netdev = priv->netdev;
1742         int cpu = mlx5e_get_cpu(priv, ix);
1743         struct mlx5e_channel *c;
1744         unsigned int irq;
1745         int err;
1746         int eqn;
1747
1748         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1749         if (!c)
1750                 return -ENOMEM;
1751
1752         c->priv     = priv;
1753         c->mdev     = priv->mdev;
1754         c->tstamp   = &priv->tstamp;
1755         c->ix       = ix;
1756         c->cpu      = cpu;
1757         c->pdev     = &priv->mdev->pdev->dev;
1758         c->netdev   = priv->netdev;
1759         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1760         c->num_tc   = params->num_tc;
1761         c->xdp      = !!params->xdp_prog;
1762
1763         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1764         c->irq_desc = irq_to_desc(irq);
1765
1766         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1767
1768         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1769         if (err)
1770                 goto err_napi_del;
1771
1772         err = mlx5e_open_tx_cqs(c, params, cparam);
1773         if (err)
1774                 goto err_close_icosq_cq;
1775
1776         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1777         if (err)
1778                 goto err_close_tx_cqs;
1779
1780         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1781         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1782                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1783         if (err)
1784                 goto err_close_rx_cq;
1785
1786         napi_enable(&c->napi);
1787
1788         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1789         if (err)
1790                 goto err_disable_napi;
1791
1792         err = mlx5e_open_sqs(c, params, cparam);
1793         if (err)
1794                 goto err_close_icosq;
1795
1796         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1797         if (err)
1798                 goto err_close_sqs;
1799
1800         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1801         if (err)
1802                 goto err_close_xdp_sq;
1803
1804         *cp = c;
1805
1806         return 0;
1807 err_close_xdp_sq:
1808         if (c->xdp)
1809                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1810
1811 err_close_sqs:
1812         mlx5e_close_sqs(c);
1813
1814 err_close_icosq:
1815         mlx5e_close_icosq(&c->icosq);
1816
1817 err_disable_napi:
1818         napi_disable(&c->napi);
1819         if (c->xdp)
1820                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1821
1822 err_close_rx_cq:
1823         mlx5e_close_cq(&c->rq.cq);
1824
1825 err_close_tx_cqs:
1826         mlx5e_close_tx_cqs(c);
1827
1828 err_close_icosq_cq:
1829         mlx5e_close_cq(&c->icosq.cq);
1830
1831 err_napi_del:
1832         netif_napi_del(&c->napi);
1833         kfree(c);
1834
1835         return err;
1836 }
1837
1838 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1839 {
1840         int tc;
1841
1842         for (tc = 0; tc < c->num_tc; tc++)
1843                 mlx5e_activate_txqsq(&c->sq[tc]);
1844         mlx5e_activate_rq(&c->rq);
1845         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1846 }
1847
1848 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1849 {
1850         int tc;
1851
1852         mlx5e_deactivate_rq(&c->rq);
1853         for (tc = 0; tc < c->num_tc; tc++)
1854                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1855 }
1856
1857 static void mlx5e_close_channel(struct mlx5e_channel *c)
1858 {
1859         mlx5e_close_rq(&c->rq);
1860         if (c->xdp)
1861                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1862         mlx5e_close_sqs(c);
1863         mlx5e_close_icosq(&c->icosq);
1864         napi_disable(&c->napi);
1865         if (c->xdp)
1866                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1867         mlx5e_close_cq(&c->rq.cq);
1868         mlx5e_close_tx_cqs(c);
1869         mlx5e_close_cq(&c->icosq.cq);
1870         netif_napi_del(&c->napi);
1871
1872         kfree(c);
1873 }
1874
1875 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1876                                  struct mlx5e_params *params,
1877                                  struct mlx5e_rq_param *param)
1878 {
1879         struct mlx5_core_dev *mdev = priv->mdev;
1880         void *rqc = param->rqc;
1881         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1882
1883         switch (params->rq_wq_type) {
1884         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1885                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1886                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
1887                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
1888                 MLX5_SET(wq, wq, log_wqe_stride_size,
1889                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
1890                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
1891                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1892                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
1893                 break;
1894         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1895                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1896                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
1897         }
1898
1899         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1900         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1901         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
1902         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1903         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
1904         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
1905
1906         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1907         param->wq.linear = 1;
1908 }
1909
1910 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
1911                                       struct mlx5e_rq_param *param)
1912 {
1913         struct mlx5_core_dev *mdev = priv->mdev;
1914         void *rqc = param->rqc;
1915         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1916
1917         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1918         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1919         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
1920
1921         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1922 }
1923
1924 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1925                                         struct mlx5e_sq_param *param)
1926 {
1927         void *sqc = param->sqc;
1928         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1929
1930         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1931         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1932
1933         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1934 }
1935
1936 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1937                                  struct mlx5e_params *params,
1938                                  struct mlx5e_sq_param *param)
1939 {
1940         void *sqc = param->sqc;
1941         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1942
1943         mlx5e_build_sq_param_common(priv, param);
1944         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1945         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1946 }
1947
1948 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1949                                         struct mlx5e_cq_param *param)
1950 {
1951         void *cqc = param->cqc;
1952
1953         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1954 }
1955
1956 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1957                                     struct mlx5e_params *params,
1958                                     struct mlx5e_cq_param *param)
1959 {
1960         struct mlx5_core_dev *mdev = priv->mdev;
1961         void *cqc = param->cqc;
1962         u8 log_cq_size;
1963
1964         switch (params->rq_wq_type) {
1965         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1966                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
1967                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
1968                 break;
1969         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1970                 log_cq_size = params->log_rq_mtu_frames;
1971         }
1972
1973         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1974         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1975                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1976                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1977         }
1978
1979         mlx5e_build_common_cq_param(priv, param);
1980         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
1981 }
1982
1983 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1984                                     struct mlx5e_params *params,
1985                                     struct mlx5e_cq_param *param)
1986 {
1987         void *cqc = param->cqc;
1988
1989         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1990
1991         mlx5e_build_common_cq_param(priv, param);
1992         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
1993 }
1994
1995 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1996                                      u8 log_wq_size,
1997                                      struct mlx5e_cq_param *param)
1998 {
1999         void *cqc = param->cqc;
2000
2001         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2002
2003         mlx5e_build_common_cq_param(priv, param);
2004
2005         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2006 }
2007
2008 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2009                                     u8 log_wq_size,
2010                                     struct mlx5e_sq_param *param)
2011 {
2012         void *sqc = param->sqc;
2013         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2014
2015         mlx5e_build_sq_param_common(priv, param);
2016
2017         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2018         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2019 }
2020
2021 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2022                                     struct mlx5e_params *params,
2023                                     struct mlx5e_sq_param *param)
2024 {
2025         void *sqc = param->sqc;
2026         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2027
2028         mlx5e_build_sq_param_common(priv, param);
2029         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2030 }
2031
2032 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2033                                       struct mlx5e_params *params,
2034                                       struct mlx5e_channel_param *cparam)
2035 {
2036         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2037
2038         mlx5e_build_rq_param(priv, params, &cparam->rq);
2039         mlx5e_build_sq_param(priv, params, &cparam->sq);
2040         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2041         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2042         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2043         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2044         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2045 }
2046
2047 int mlx5e_open_channels(struct mlx5e_priv *priv,
2048                         struct mlx5e_channels *chs)
2049 {
2050         struct mlx5e_channel_param *cparam;
2051         int err = -ENOMEM;
2052         int i;
2053
2054         chs->num = chs->params.num_channels;
2055
2056         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2057         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2058         if (!chs->c || !cparam)
2059                 goto err_free;
2060
2061         mlx5e_build_channel_param(priv, &chs->params, cparam);
2062         for (i = 0; i < chs->num; i++) {
2063                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2064                 if (err)
2065                         goto err_close_channels;
2066         }
2067
2068         kfree(cparam);
2069         return 0;
2070
2071 err_close_channels:
2072         for (i--; i >= 0; i--)
2073                 mlx5e_close_channel(chs->c[i]);
2074
2075 err_free:
2076         kfree(chs->c);
2077         kfree(cparam);
2078         chs->num = 0;
2079         return err;
2080 }
2081
2082 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2083 {
2084         int i;
2085
2086         for (i = 0; i < chs->num; i++)
2087                 mlx5e_activate_channel(chs->c[i]);
2088 }
2089
2090 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2091 {
2092         int err = 0;
2093         int i;
2094
2095         for (i = 0; i < chs->num; i++) {
2096                 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2097                 if (err)
2098                         break;
2099         }
2100
2101         return err;
2102 }
2103
2104 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2105 {
2106         int i;
2107
2108         for (i = 0; i < chs->num; i++)
2109                 mlx5e_deactivate_channel(chs->c[i]);
2110 }
2111
2112 void mlx5e_close_channels(struct mlx5e_channels *chs)
2113 {
2114         int i;
2115
2116         for (i = 0; i < chs->num; i++)
2117                 mlx5e_close_channel(chs->c[i]);
2118
2119         kfree(chs->c);
2120         chs->num = 0;
2121 }
2122
2123 static int
2124 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2125 {
2126         struct mlx5_core_dev *mdev = priv->mdev;
2127         void *rqtc;
2128         int inlen;
2129         int err;
2130         u32 *in;
2131         int i;
2132
2133         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2134         in = kvzalloc(inlen, GFP_KERNEL);
2135         if (!in)
2136                 return -ENOMEM;
2137
2138         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2139
2140         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2141         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2142
2143         for (i = 0; i < sz; i++)
2144                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2145
2146         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2147         if (!err)
2148                 rqt->enabled = true;
2149
2150         kvfree(in);
2151         return err;
2152 }
2153
2154 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2155 {
2156         rqt->enabled = false;
2157         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2158 }
2159
2160 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2161 {
2162         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2163         int err;
2164
2165         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2166         if (err)
2167                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2168         return err;
2169 }
2170
2171 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2172 {
2173         struct mlx5e_rqt *rqt;
2174         int err;
2175         int ix;
2176
2177         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2178                 rqt = &priv->direct_tir[ix].rqt;
2179                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2180                 if (err)
2181                         goto err_destroy_rqts;
2182         }
2183
2184         return 0;
2185
2186 err_destroy_rqts:
2187         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2188         for (ix--; ix >= 0; ix--)
2189                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2190
2191         return err;
2192 }
2193
2194 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2195 {
2196         int i;
2197
2198         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2199                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2200 }
2201
2202 static int mlx5e_rx_hash_fn(int hfunc)
2203 {
2204         return (hfunc == ETH_RSS_HASH_TOP) ?
2205                MLX5_RX_HASH_FN_TOEPLITZ :
2206                MLX5_RX_HASH_FN_INVERTED_XOR8;
2207 }
2208
2209 int mlx5e_bits_invert(unsigned long a, int size)
2210 {
2211         int inv = 0;
2212         int i;
2213
2214         for (i = 0; i < size; i++)
2215                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2216
2217         return inv;
2218 }
2219
2220 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2221                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2222 {
2223         int i;
2224
2225         for (i = 0; i < sz; i++) {
2226                 u32 rqn;
2227
2228                 if (rrp.is_rss) {
2229                         int ix = i;
2230
2231                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2232                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2233
2234                         ix = priv->channels.params.indirection_rqt[ix];
2235                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2236                 } else {
2237                         rqn = rrp.rqn;
2238                 }
2239                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2240         }
2241 }
2242
2243 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2244                        struct mlx5e_redirect_rqt_param rrp)
2245 {
2246         struct mlx5_core_dev *mdev = priv->mdev;
2247         void *rqtc;
2248         int inlen;
2249         u32 *in;
2250         int err;
2251
2252         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2253         in = kvzalloc(inlen, GFP_KERNEL);
2254         if (!in)
2255                 return -ENOMEM;
2256
2257         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2258
2259         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2260         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2261         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2262         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2263
2264         kvfree(in);
2265         return err;
2266 }
2267
2268 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2269                                 struct mlx5e_redirect_rqt_param rrp)
2270 {
2271         if (!rrp.is_rss)
2272                 return rrp.rqn;
2273
2274         if (ix >= rrp.rss.channels->num)
2275                 return priv->drop_rq.rqn;
2276
2277         return rrp.rss.channels->c[ix]->rq.rqn;
2278 }
2279
2280 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2281                                 struct mlx5e_redirect_rqt_param rrp)
2282 {
2283         u32 rqtn;
2284         int ix;
2285
2286         if (priv->indir_rqt.enabled) {
2287                 /* RSS RQ table */
2288                 rqtn = priv->indir_rqt.rqtn;
2289                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2290         }
2291
2292         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2293                 struct mlx5e_redirect_rqt_param direct_rrp = {
2294                         .is_rss = false,
2295                         {
2296                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2297                         },
2298                 };
2299
2300                 /* Direct RQ Tables */
2301                 if (!priv->direct_tir[ix].rqt.enabled)
2302                         continue;
2303
2304                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2305                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2306         }
2307 }
2308
2309 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2310                                             struct mlx5e_channels *chs)
2311 {
2312         struct mlx5e_redirect_rqt_param rrp = {
2313                 .is_rss        = true,
2314                 {
2315                         .rss = {
2316                                 .channels  = chs,
2317                                 .hfunc     = chs->params.rss_hfunc,
2318                         }
2319                 },
2320         };
2321
2322         mlx5e_redirect_rqts(priv, rrp);
2323 }
2324
2325 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2326 {
2327         struct mlx5e_redirect_rqt_param drop_rrp = {
2328                 .is_rss = false,
2329                 {
2330                         .rqn = priv->drop_rq.rqn,
2331                 },
2332         };
2333
2334         mlx5e_redirect_rqts(priv, drop_rrp);
2335 }
2336
2337 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2338 {
2339         if (!params->lro_en)
2340                 return;
2341
2342 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2343
2344         MLX5_SET(tirc, tirc, lro_enable_mask,
2345                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2346                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2347         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2348                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2349         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2350 }
2351
2352 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2353                                     enum mlx5e_traffic_types tt,
2354                                     void *tirc, bool inner)
2355 {
2356         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2357                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2358
2359 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2360                                  MLX5_HASH_FIELD_SEL_DST_IP)
2361
2362 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2363                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2364                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2365                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2366
2367 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2368                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2369                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2370
2371         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2372         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2373                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2374                                              rx_hash_toeplitz_key);
2375                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2376                                                rx_hash_toeplitz_key);
2377
2378                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2379                 memcpy(rss_key, params->toeplitz_hash_key, len);
2380         }
2381
2382         switch (tt) {
2383         case MLX5E_TT_IPV4_TCP:
2384                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2385                          MLX5_L3_PROT_TYPE_IPV4);
2386                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2387                          MLX5_L4_PROT_TYPE_TCP);
2388                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2389                          MLX5_HASH_IP_L4PORTS);
2390                 break;
2391
2392         case MLX5E_TT_IPV6_TCP:
2393                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2394                          MLX5_L3_PROT_TYPE_IPV6);
2395                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2396                          MLX5_L4_PROT_TYPE_TCP);
2397                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2398                          MLX5_HASH_IP_L4PORTS);
2399                 break;
2400
2401         case MLX5E_TT_IPV4_UDP:
2402                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2403                          MLX5_L3_PROT_TYPE_IPV4);
2404                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2405                          MLX5_L4_PROT_TYPE_UDP);
2406                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2407                          MLX5_HASH_IP_L4PORTS);
2408                 break;
2409
2410         case MLX5E_TT_IPV6_UDP:
2411                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2412                          MLX5_L3_PROT_TYPE_IPV6);
2413                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2414                          MLX5_L4_PROT_TYPE_UDP);
2415                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2416                          MLX5_HASH_IP_L4PORTS);
2417                 break;
2418
2419         case MLX5E_TT_IPV4_IPSEC_AH:
2420                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2421                          MLX5_L3_PROT_TYPE_IPV4);
2422                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2423                          MLX5_HASH_IP_IPSEC_SPI);
2424                 break;
2425
2426         case MLX5E_TT_IPV6_IPSEC_AH:
2427                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2428                          MLX5_L3_PROT_TYPE_IPV6);
2429                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2430                          MLX5_HASH_IP_IPSEC_SPI);
2431                 break;
2432
2433         case MLX5E_TT_IPV4_IPSEC_ESP:
2434                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2435                          MLX5_L3_PROT_TYPE_IPV4);
2436                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2437                          MLX5_HASH_IP_IPSEC_SPI);
2438                 break;
2439
2440         case MLX5E_TT_IPV6_IPSEC_ESP:
2441                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2442                          MLX5_L3_PROT_TYPE_IPV6);
2443                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2444                          MLX5_HASH_IP_IPSEC_SPI);
2445                 break;
2446
2447         case MLX5E_TT_IPV4:
2448                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2449                          MLX5_L3_PROT_TYPE_IPV4);
2450                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2451                          MLX5_HASH_IP);
2452                 break;
2453
2454         case MLX5E_TT_IPV6:
2455                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2456                          MLX5_L3_PROT_TYPE_IPV6);
2457                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2458                          MLX5_HASH_IP);
2459                 break;
2460         default:
2461                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2462         }
2463 }
2464
2465 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2466 {
2467         struct mlx5_core_dev *mdev = priv->mdev;
2468
2469         void *in;
2470         void *tirc;
2471         int inlen;
2472         int err;
2473         int tt;
2474         int ix;
2475
2476         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2477         in = kvzalloc(inlen, GFP_KERNEL);
2478         if (!in)
2479                 return -ENOMEM;
2480
2481         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2482         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2483
2484         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2485
2486         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2487                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2488                                            inlen);
2489                 if (err)
2490                         goto free_in;
2491         }
2492
2493         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2494                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2495                                            in, inlen);
2496                 if (err)
2497                         goto free_in;
2498         }
2499
2500 free_in:
2501         kvfree(in);
2502
2503         return err;
2504 }
2505
2506 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2507                                             enum mlx5e_traffic_types tt,
2508                                             u32 *tirc)
2509 {
2510         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2511
2512         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2513
2514         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2515         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2516         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2517
2518         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2519 }
2520
2521 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2522                          struct mlx5e_params *params, u16 mtu)
2523 {
2524         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2525         int err;
2526
2527         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2528         if (err)
2529                 return err;
2530
2531         /* Update vport context MTU */
2532         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2533         return 0;
2534 }
2535
2536 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2537                             struct mlx5e_params *params, u16 *mtu)
2538 {
2539         u16 hw_mtu = 0;
2540         int err;
2541
2542         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2543         if (err || !hw_mtu) /* fallback to port oper mtu */
2544                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2545
2546         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2547 }
2548
2549 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2550 {
2551         struct mlx5e_params *params = &priv->channels.params;
2552         struct net_device *netdev = priv->netdev;
2553         struct mlx5_core_dev *mdev = priv->mdev;
2554         u16 mtu;
2555         int err;
2556
2557         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2558         if (err)
2559                 return err;
2560
2561         mlx5e_query_mtu(mdev, params, &mtu);
2562         if (mtu != params->sw_mtu)
2563                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2564                             __func__, mtu, params->sw_mtu);
2565
2566         params->sw_mtu = mtu;
2567         return 0;
2568 }
2569
2570 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2571 {
2572         struct mlx5e_priv *priv = netdev_priv(netdev);
2573         int nch = priv->channels.params.num_channels;
2574         int ntc = priv->channels.params.num_tc;
2575         int tc;
2576
2577         netdev_reset_tc(netdev);
2578
2579         if (ntc == 1)
2580                 return;
2581
2582         netdev_set_num_tc(netdev, ntc);
2583
2584         /* Map netdev TCs to offset 0
2585          * We have our own UP to TXQ mapping for QoS
2586          */
2587         for (tc = 0; tc < ntc; tc++)
2588                 netdev_set_tc_queue(netdev, tc, nch, 0);
2589 }
2590
2591 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2592 {
2593         struct mlx5e_channel *c;
2594         struct mlx5e_txqsq *sq;
2595         int i, tc;
2596
2597         for (i = 0; i < priv->channels.num; i++)
2598                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2599                         priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2600
2601         for (i = 0; i < priv->channels.num; i++) {
2602                 c = priv->channels.c[i];
2603                 for (tc = 0; tc < c->num_tc; tc++) {
2604                         sq = &c->sq[tc];
2605                         priv->txq2sq[sq->txq_ix] = sq;
2606                 }
2607         }
2608 }
2609
2610 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2611 {
2612         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2613         struct net_device *netdev = priv->netdev;
2614
2615         mlx5e_netdev_set_tcs(netdev);
2616         netif_set_real_num_tx_queues(netdev, num_txqs);
2617         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2618
2619         mlx5e_build_channels_tx_maps(priv);
2620         mlx5e_activate_channels(&priv->channels);
2621         netif_tx_start_all_queues(priv->netdev);
2622
2623         if (MLX5_VPORT_MANAGER(priv->mdev))
2624                 mlx5e_add_sqs_fwd_rules(priv);
2625
2626         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2627         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2628 }
2629
2630 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2631 {
2632         mlx5e_redirect_rqts_to_drop(priv);
2633
2634         if (MLX5_VPORT_MANAGER(priv->mdev))
2635                 mlx5e_remove_sqs_fwd_rules(priv);
2636
2637         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2638          * polling for inactive tx queues.
2639          */
2640         netif_tx_stop_all_queues(priv->netdev);
2641         netif_tx_disable(priv->netdev);
2642         mlx5e_deactivate_channels(&priv->channels);
2643 }
2644
2645 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2646                                 struct mlx5e_channels *new_chs,
2647                                 mlx5e_fp_hw_modify hw_modify)
2648 {
2649         struct net_device *netdev = priv->netdev;
2650         int new_num_txqs;
2651         int carrier_ok;
2652         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2653
2654         carrier_ok = netif_carrier_ok(netdev);
2655         netif_carrier_off(netdev);
2656
2657         if (new_num_txqs < netdev->real_num_tx_queues)
2658                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2659
2660         mlx5e_deactivate_priv_channels(priv);
2661         mlx5e_close_channels(&priv->channels);
2662
2663         priv->channels = *new_chs;
2664
2665         /* New channels are ready to roll, modify HW settings if needed */
2666         if (hw_modify)
2667                 hw_modify(priv);
2668
2669         mlx5e_refresh_tirs(priv, false);
2670         mlx5e_activate_priv_channels(priv);
2671
2672         /* return carrier back if needed */
2673         if (carrier_ok)
2674                 netif_carrier_on(netdev);
2675 }
2676
2677 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2678 {
2679         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2680         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2681 }
2682
2683 int mlx5e_open_locked(struct net_device *netdev)
2684 {
2685         struct mlx5e_priv *priv = netdev_priv(netdev);
2686         int err;
2687
2688         set_bit(MLX5E_STATE_OPENED, &priv->state);
2689
2690         err = mlx5e_open_channels(priv, &priv->channels);
2691         if (err)
2692                 goto err_clear_state_opened_flag;
2693
2694         mlx5e_refresh_tirs(priv, false);
2695         mlx5e_activate_priv_channels(priv);
2696         if (priv->profile->update_carrier)
2697                 priv->profile->update_carrier(priv);
2698
2699         if (priv->profile->update_stats)
2700                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2701
2702         return 0;
2703
2704 err_clear_state_opened_flag:
2705         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2706         return err;
2707 }
2708
2709 int mlx5e_open(struct net_device *netdev)
2710 {
2711         struct mlx5e_priv *priv = netdev_priv(netdev);
2712         int err;
2713
2714         mutex_lock(&priv->state_lock);
2715         err = mlx5e_open_locked(netdev);
2716         if (!err)
2717                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2718         mutex_unlock(&priv->state_lock);
2719
2720         if (mlx5e_vxlan_allowed(priv->mdev))
2721                 udp_tunnel_get_rx_info(netdev);
2722
2723         return err;
2724 }
2725
2726 int mlx5e_close_locked(struct net_device *netdev)
2727 {
2728         struct mlx5e_priv *priv = netdev_priv(netdev);
2729
2730         /* May already be CLOSED in case a previous configuration operation
2731          * (e.g RX/TX queue size change) that involves close&open failed.
2732          */
2733         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2734                 return 0;
2735
2736         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2737
2738         netif_carrier_off(priv->netdev);
2739         mlx5e_deactivate_priv_channels(priv);
2740         mlx5e_close_channels(&priv->channels);
2741
2742         return 0;
2743 }
2744
2745 int mlx5e_close(struct net_device *netdev)
2746 {
2747         struct mlx5e_priv *priv = netdev_priv(netdev);
2748         int err;
2749
2750         if (!netif_device_present(netdev))
2751                 return -ENODEV;
2752
2753         mutex_lock(&priv->state_lock);
2754         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2755         err = mlx5e_close_locked(netdev);
2756         mutex_unlock(&priv->state_lock);
2757
2758         return err;
2759 }
2760
2761 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2762                                struct mlx5e_rq *rq,
2763                                struct mlx5e_rq_param *param)
2764 {
2765         void *rqc = param->rqc;
2766         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2767         int err;
2768
2769         param->wq.db_numa_node = param->wq.buf_numa_node;
2770
2771         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2772                                 &rq->wq_ctrl);
2773         if (err)
2774                 return err;
2775
2776         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2777         xdp_rxq_info_unused(&rq->xdp_rxq);
2778
2779         rq->mdev = mdev;
2780
2781         return 0;
2782 }
2783
2784 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2785                                struct mlx5e_cq *cq,
2786                                struct mlx5e_cq_param *param)
2787 {
2788         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2789         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
2790
2791         return mlx5e_alloc_cq_common(mdev, param, cq);
2792 }
2793
2794 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2795                               struct mlx5e_rq *drop_rq)
2796 {
2797         struct mlx5_core_dev *mdev = priv->mdev;
2798         struct mlx5e_cq_param cq_param = {};
2799         struct mlx5e_rq_param rq_param = {};
2800         struct mlx5e_cq *cq = &drop_rq->cq;
2801         int err;
2802
2803         mlx5e_build_drop_rq_param(priv, &rq_param);
2804
2805         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2806         if (err)
2807                 return err;
2808
2809         err = mlx5e_create_cq(cq, &cq_param);
2810         if (err)
2811                 goto err_free_cq;
2812
2813         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2814         if (err)
2815                 goto err_destroy_cq;
2816
2817         err = mlx5e_create_rq(drop_rq, &rq_param);
2818         if (err)
2819                 goto err_free_rq;
2820
2821         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2822         if (err)
2823                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2824
2825         return 0;
2826
2827 err_free_rq:
2828         mlx5e_free_rq(drop_rq);
2829
2830 err_destroy_cq:
2831         mlx5e_destroy_cq(cq);
2832
2833 err_free_cq:
2834         mlx5e_free_cq(cq);
2835
2836         return err;
2837 }
2838
2839 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2840 {
2841         mlx5e_destroy_rq(drop_rq);
2842         mlx5e_free_rq(drop_rq);
2843         mlx5e_destroy_cq(&drop_rq->cq);
2844         mlx5e_free_cq(&drop_rq->cq);
2845 }
2846
2847 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2848                      u32 underlay_qpn, u32 *tisn)
2849 {
2850         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2851         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2852
2853         MLX5_SET(tisc, tisc, prio, tc << 1);
2854         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2855         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2856
2857         if (mlx5_lag_is_lacp_owner(mdev))
2858                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2859
2860         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2861 }
2862
2863 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2864 {
2865         mlx5_core_destroy_tis(mdev, tisn);
2866 }
2867
2868 int mlx5e_create_tises(struct mlx5e_priv *priv)
2869 {
2870         int err;
2871         int tc;
2872
2873         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2874                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2875                 if (err)
2876                         goto err_close_tises;
2877         }
2878
2879         return 0;
2880
2881 err_close_tises:
2882         for (tc--; tc >= 0; tc--)
2883                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2884
2885         return err;
2886 }
2887
2888 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2889 {
2890         int tc;
2891
2892         for (tc = 0; tc < priv->profile->max_tc; tc++)
2893                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2894 }
2895
2896 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2897                                       enum mlx5e_traffic_types tt,
2898                                       u32 *tirc)
2899 {
2900         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2901
2902         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2903
2904         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2905         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2906         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2907 }
2908
2909 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2910 {
2911         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2912
2913         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2914
2915         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2916         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2917         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2918 }
2919
2920 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2921 {
2922         struct mlx5e_tir *tir;
2923         void *tirc;
2924         int inlen;
2925         int i = 0;
2926         int err;
2927         u32 *in;
2928         int tt;
2929
2930         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2931         in = kvzalloc(inlen, GFP_KERNEL);
2932         if (!in)
2933                 return -ENOMEM;
2934
2935         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2936                 memset(in, 0, inlen);
2937                 tir = &priv->indir_tir[tt];
2938                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2939                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2940                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2941                 if (err) {
2942                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2943                         goto err_destroy_inner_tirs;
2944                 }
2945         }
2946
2947         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2948                 goto out;
2949
2950         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2951                 memset(in, 0, inlen);
2952                 tir = &priv->inner_indir_tir[i];
2953                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2954                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2955                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2956                 if (err) {
2957                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2958                         goto err_destroy_inner_tirs;
2959                 }
2960         }
2961
2962 out:
2963         kvfree(in);
2964
2965         return 0;
2966
2967 err_destroy_inner_tirs:
2968         for (i--; i >= 0; i--)
2969                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2970
2971         for (tt--; tt >= 0; tt--)
2972                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2973
2974         kvfree(in);
2975
2976         return err;
2977 }
2978
2979 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2980 {
2981         int nch = priv->profile->max_nch(priv->mdev);
2982         struct mlx5e_tir *tir;
2983         void *tirc;
2984         int inlen;
2985         int err;
2986         u32 *in;
2987         int ix;
2988
2989         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2990         in = kvzalloc(inlen, GFP_KERNEL);
2991         if (!in)
2992                 return -ENOMEM;
2993
2994         for (ix = 0; ix < nch; ix++) {
2995                 memset(in, 0, inlen);
2996                 tir = &priv->direct_tir[ix];
2997                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2998                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2999                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3000                 if (err)
3001                         goto err_destroy_ch_tirs;
3002         }
3003
3004         kvfree(in);
3005
3006         return 0;
3007
3008 err_destroy_ch_tirs:
3009         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3010         for (ix--; ix >= 0; ix--)
3011                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3012
3013         kvfree(in);
3014
3015         return err;
3016 }
3017
3018 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3019 {
3020         int i;
3021
3022         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3023                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3024
3025         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3026                 return;
3027
3028         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3029                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3030 }
3031
3032 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3033 {
3034         int nch = priv->profile->max_nch(priv->mdev);
3035         int i;
3036
3037         for (i = 0; i < nch; i++)
3038                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3039 }
3040
3041 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3042 {
3043         int err = 0;
3044         int i;
3045
3046         for (i = 0; i < chs->num; i++) {
3047                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3048                 if (err)
3049                         return err;
3050         }
3051
3052         return 0;
3053 }
3054
3055 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3056 {
3057         int err = 0;
3058         int i;
3059
3060         for (i = 0; i < chs->num; i++) {
3061                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3062                 if (err)
3063                         return err;
3064         }
3065
3066         return 0;
3067 }
3068
3069 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3070                                  struct tc_mqprio_qopt *mqprio)
3071 {
3072         struct mlx5e_priv *priv = netdev_priv(netdev);
3073         struct mlx5e_channels new_channels = {};
3074         u8 tc = mqprio->num_tc;
3075         int err = 0;
3076
3077         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3078
3079         if (tc && tc != MLX5E_MAX_NUM_TC)
3080                 return -EINVAL;
3081
3082         mutex_lock(&priv->state_lock);
3083
3084         new_channels.params = priv->channels.params;
3085         new_channels.params.num_tc = tc ? tc : 1;
3086
3087         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3088                 priv->channels.params = new_channels.params;
3089                 goto out;
3090         }
3091
3092         err = mlx5e_open_channels(priv, &new_channels);
3093         if (err)
3094                 goto out;
3095
3096         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3097 out:
3098         mutex_unlock(&priv->state_lock);
3099         return err;
3100 }
3101
3102 #ifdef CONFIG_MLX5_ESWITCH
3103 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3104                                      struct tc_cls_flower_offload *cls_flower)
3105 {
3106         switch (cls_flower->command) {
3107         case TC_CLSFLOWER_REPLACE:
3108                 return mlx5e_configure_flower(priv, cls_flower);
3109         case TC_CLSFLOWER_DESTROY:
3110                 return mlx5e_delete_flower(priv, cls_flower);
3111         case TC_CLSFLOWER_STATS:
3112                 return mlx5e_stats_flower(priv, cls_flower);
3113         default:
3114                 return -EOPNOTSUPP;
3115         }
3116 }
3117
3118 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3119                             void *cb_priv)
3120 {
3121         struct mlx5e_priv *priv = cb_priv;
3122
3123         if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3124                 return -EOPNOTSUPP;
3125
3126         switch (type) {
3127         case TC_SETUP_CLSFLOWER:
3128                 return mlx5e_setup_tc_cls_flower(priv, type_data);
3129         default:
3130                 return -EOPNOTSUPP;
3131         }
3132 }
3133
3134 static int mlx5e_setup_tc_block(struct net_device *dev,
3135                                 struct tc_block_offload *f)
3136 {
3137         struct mlx5e_priv *priv = netdev_priv(dev);
3138
3139         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3140                 return -EOPNOTSUPP;
3141
3142         switch (f->command) {
3143         case TC_BLOCK_BIND:
3144                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3145                                              priv, priv);
3146         case TC_BLOCK_UNBIND:
3147                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3148                                         priv);
3149                 return 0;
3150         default:
3151                 return -EOPNOTSUPP;
3152         }
3153 }
3154 #endif
3155
3156 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3157                           void *type_data)
3158 {
3159         switch (type) {
3160 #ifdef CONFIG_MLX5_ESWITCH
3161         case TC_SETUP_BLOCK:
3162                 return mlx5e_setup_tc_block(dev, type_data);
3163 #endif
3164         case TC_SETUP_QDISC_MQPRIO:
3165                 return mlx5e_setup_tc_mqprio(dev, type_data);
3166         default:
3167                 return -EOPNOTSUPP;
3168         }
3169 }
3170
3171 static void
3172 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3173 {
3174         struct mlx5e_priv *priv = netdev_priv(dev);
3175         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3176         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3177         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3178
3179         if (mlx5e_is_uplink_rep(priv)) {
3180                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3181                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3182                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3183                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3184         } else {
3185                 stats->rx_packets = sstats->rx_packets;
3186                 stats->rx_bytes   = sstats->rx_bytes;
3187                 stats->tx_packets = sstats->tx_packets;
3188                 stats->tx_bytes   = sstats->tx_bytes;
3189                 stats->tx_dropped = sstats->tx_queue_dropped;
3190         }
3191
3192         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3193
3194         stats->rx_length_errors =
3195                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3196                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3197                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3198         stats->rx_crc_errors =
3199                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3200         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3201         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3202         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3203                            stats->rx_frame_errors;
3204         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3205
3206         /* vport multicast also counts packets that are dropped due to steering
3207          * or rx out of buffer
3208          */
3209         stats->multicast =
3210                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3211 }
3212
3213 static void mlx5e_set_rx_mode(struct net_device *dev)
3214 {
3215         struct mlx5e_priv *priv = netdev_priv(dev);
3216
3217         queue_work(priv->wq, &priv->set_rx_mode_work);
3218 }
3219
3220 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3221 {
3222         struct mlx5e_priv *priv = netdev_priv(netdev);
3223         struct sockaddr *saddr = addr;
3224
3225         if (!is_valid_ether_addr(saddr->sa_data))
3226                 return -EADDRNOTAVAIL;
3227
3228         netif_addr_lock_bh(netdev);
3229         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3230         netif_addr_unlock_bh(netdev);
3231
3232         queue_work(priv->wq, &priv->set_rx_mode_work);
3233
3234         return 0;
3235 }
3236
3237 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3238         do {                                            \
3239                 if (enable)                             \
3240                         *features |= feature;           \
3241                 else                                    \
3242                         *features &= ~feature;          \
3243         } while (0)
3244
3245 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3246
3247 static int set_feature_lro(struct net_device *netdev, bool enable)
3248 {
3249         struct mlx5e_priv *priv = netdev_priv(netdev);
3250         struct mlx5_core_dev *mdev = priv->mdev;
3251         struct mlx5e_channels new_channels = {};
3252         struct mlx5e_params *old_params;
3253         int err = 0;
3254         bool reset;
3255
3256         mutex_lock(&priv->state_lock);
3257
3258         old_params = &priv->channels.params;
3259         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3260
3261         new_channels.params = *old_params;
3262         new_channels.params.lro_en = enable;
3263
3264         if (old_params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) {
3265                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3266                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3267                         reset = false;
3268         }
3269
3270         if (!reset) {
3271                 *old_params = new_channels.params;
3272                 err = mlx5e_modify_tirs_lro(priv);
3273                 goto out;
3274         }
3275
3276         err = mlx5e_open_channels(priv, &new_channels);
3277         if (err)
3278                 goto out;
3279
3280         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3281 out:
3282         mutex_unlock(&priv->state_lock);
3283         return err;
3284 }
3285
3286 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3287 {
3288         struct mlx5e_priv *priv = netdev_priv(netdev);
3289
3290         if (enable)
3291                 mlx5e_enable_cvlan_filter(priv);
3292         else
3293                 mlx5e_disable_cvlan_filter(priv);
3294
3295         return 0;
3296 }
3297
3298 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3299 {
3300         struct mlx5e_priv *priv = netdev_priv(netdev);
3301
3302         if (!enable && mlx5e_tc_num_filters(priv)) {
3303                 netdev_err(netdev,
3304                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3305                 return -EINVAL;
3306         }
3307
3308         return 0;
3309 }
3310
3311 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3312 {
3313         struct mlx5e_priv *priv = netdev_priv(netdev);
3314         struct mlx5_core_dev *mdev = priv->mdev;
3315
3316         return mlx5_set_port_fcs(mdev, !enable);
3317 }
3318
3319 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3320 {
3321         struct mlx5e_priv *priv = netdev_priv(netdev);
3322         int err;
3323
3324         mutex_lock(&priv->state_lock);
3325
3326         priv->channels.params.scatter_fcs_en = enable;
3327         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3328         if (err)
3329                 priv->channels.params.scatter_fcs_en = !enable;
3330
3331         mutex_unlock(&priv->state_lock);
3332
3333         return err;
3334 }
3335
3336 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3337 {
3338         struct mlx5e_priv *priv = netdev_priv(netdev);
3339         int err = 0;
3340
3341         mutex_lock(&priv->state_lock);
3342
3343         priv->channels.params.vlan_strip_disable = !enable;
3344         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3345                 goto unlock;
3346
3347         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3348         if (err)
3349                 priv->channels.params.vlan_strip_disable = enable;
3350
3351 unlock:
3352         mutex_unlock(&priv->state_lock);
3353
3354         return err;
3355 }
3356
3357 #ifdef CONFIG_RFS_ACCEL
3358 static int set_feature_arfs(struct net_device *netdev, bool enable)
3359 {
3360         struct mlx5e_priv *priv = netdev_priv(netdev);
3361         int err;
3362
3363         if (enable)
3364                 err = mlx5e_arfs_enable(priv);
3365         else
3366                 err = mlx5e_arfs_disable(priv);
3367
3368         return err;
3369 }
3370 #endif
3371
3372 static int mlx5e_handle_feature(struct net_device *netdev,
3373                                 netdev_features_t *features,
3374                                 netdev_features_t wanted_features,
3375                                 netdev_features_t feature,
3376                                 mlx5e_feature_handler feature_handler)
3377 {
3378         netdev_features_t changes = wanted_features ^ netdev->features;
3379         bool enable = !!(wanted_features & feature);
3380         int err;
3381
3382         if (!(changes & feature))
3383                 return 0;
3384
3385         err = feature_handler(netdev, enable);
3386         if (err) {
3387                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3388                            enable ? "Enable" : "Disable", &feature, err);
3389                 return err;
3390         }
3391
3392         MLX5E_SET_FEATURE(features, feature, enable);
3393         return 0;
3394 }
3395
3396 static int mlx5e_set_features(struct net_device *netdev,
3397                               netdev_features_t features)
3398 {
3399         netdev_features_t oper_features = netdev->features;
3400         int err = 0;
3401
3402 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3403         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3404
3405         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3406         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3407                                     set_feature_cvlan_filter);
3408         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3409         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3410         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3411         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3412 #ifdef CONFIG_RFS_ACCEL
3413         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3414 #endif
3415
3416         if (err) {
3417                 netdev->features = oper_features;
3418                 return -EINVAL;
3419         }
3420
3421         return 0;
3422 }
3423
3424 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3425                                             netdev_features_t features)
3426 {
3427         struct mlx5e_priv *priv = netdev_priv(netdev);
3428
3429         mutex_lock(&priv->state_lock);
3430         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3431                 /* HW strips the outer C-tag header, this is a problem
3432                  * for S-tag traffic.
3433                  */
3434                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3435                 if (!priv->channels.params.vlan_strip_disable)
3436                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3437         }
3438         mutex_unlock(&priv->state_lock);
3439
3440         return features;
3441 }
3442
3443 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3444 {
3445         struct mlx5e_priv *priv = netdev_priv(netdev);
3446         struct mlx5e_channels new_channels = {};
3447         struct mlx5e_params *params;
3448         int err = 0;
3449         bool reset;
3450
3451         mutex_lock(&priv->state_lock);
3452
3453         params = &priv->channels.params;
3454
3455         reset = !params->lro_en;
3456         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3457
3458         new_channels.params = *params;
3459         new_channels.params.sw_mtu = new_mtu;
3460
3461         if (params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) {
3462                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3463                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3464
3465                 reset = reset && (ppw_old != ppw_new);
3466         }
3467
3468         if (!reset) {
3469                 params->sw_mtu = new_mtu;
3470                 mlx5e_set_dev_port_mtu(priv);
3471                 netdev->mtu = params->sw_mtu;
3472                 goto out;
3473         }
3474
3475         err = mlx5e_open_channels(priv, &new_channels);
3476         if (err)
3477                 goto out;
3478
3479         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3480         netdev->mtu = new_channels.params.sw_mtu;
3481
3482 out:
3483         mutex_unlock(&priv->state_lock);
3484         return err;
3485 }
3486
3487 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3488 {
3489         struct hwtstamp_config config;
3490         int err;
3491
3492         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3493                 return -EOPNOTSUPP;
3494
3495         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3496                 return -EFAULT;
3497
3498         /* TX HW timestamp */
3499         switch (config.tx_type) {
3500         case HWTSTAMP_TX_OFF:
3501         case HWTSTAMP_TX_ON:
3502                 break;
3503         default:
3504                 return -ERANGE;
3505         }
3506
3507         mutex_lock(&priv->state_lock);
3508         /* RX HW timestamp */
3509         switch (config.rx_filter) {
3510         case HWTSTAMP_FILTER_NONE:
3511                 /* Reset CQE compression to Admin default */
3512                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3513                 break;
3514         case HWTSTAMP_FILTER_ALL:
3515         case HWTSTAMP_FILTER_SOME:
3516         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3517         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3518         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3519         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3520         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3521         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3522         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3523         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3524         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3525         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3526         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3527         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3528         case HWTSTAMP_FILTER_NTP_ALL:
3529                 /* Disable CQE compression */
3530                 netdev_warn(priv->netdev, "Disabling cqe compression");
3531                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3532                 if (err) {
3533                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3534                         mutex_unlock(&priv->state_lock);
3535                         return err;
3536                 }
3537                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3538                 break;
3539         default:
3540                 mutex_unlock(&priv->state_lock);
3541                 return -ERANGE;
3542         }
3543
3544         memcpy(&priv->tstamp, &config, sizeof(config));
3545         mutex_unlock(&priv->state_lock);
3546
3547         return copy_to_user(ifr->ifr_data, &config,
3548                             sizeof(config)) ? -EFAULT : 0;
3549 }
3550
3551 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3552 {
3553         struct hwtstamp_config *cfg = &priv->tstamp;
3554
3555         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3556                 return -EOPNOTSUPP;
3557
3558         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3559 }
3560
3561 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3562 {
3563         struct mlx5e_priv *priv = netdev_priv(dev);
3564
3565         switch (cmd) {
3566         case SIOCSHWTSTAMP:
3567                 return mlx5e_hwstamp_set(priv, ifr);
3568         case SIOCGHWTSTAMP:
3569                 return mlx5e_hwstamp_get(priv, ifr);
3570         default:
3571                 return -EOPNOTSUPP;
3572         }
3573 }
3574
3575 #ifdef CONFIG_MLX5_ESWITCH
3576 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3577 {
3578         struct mlx5e_priv *priv = netdev_priv(dev);
3579         struct mlx5_core_dev *mdev = priv->mdev;
3580
3581         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3582 }
3583
3584 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3585                              __be16 vlan_proto)
3586 {
3587         struct mlx5e_priv *priv = netdev_priv(dev);
3588         struct mlx5_core_dev *mdev = priv->mdev;
3589
3590         if (vlan_proto != htons(ETH_P_8021Q))
3591                 return -EPROTONOSUPPORT;
3592
3593         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3594                                            vlan, qos);
3595 }
3596
3597 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3598 {
3599         struct mlx5e_priv *priv = netdev_priv(dev);
3600         struct mlx5_core_dev *mdev = priv->mdev;
3601
3602         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3603 }
3604
3605 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3606 {
3607         struct mlx5e_priv *priv = netdev_priv(dev);
3608         struct mlx5_core_dev *mdev = priv->mdev;
3609
3610         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3611 }
3612
3613 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3614                              int max_tx_rate)
3615 {
3616         struct mlx5e_priv *priv = netdev_priv(dev);
3617         struct mlx5_core_dev *mdev = priv->mdev;
3618
3619         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3620                                            max_tx_rate, min_tx_rate);
3621 }
3622
3623 static int mlx5_vport_link2ifla(u8 esw_link)
3624 {
3625         switch (esw_link) {
3626         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3627                 return IFLA_VF_LINK_STATE_DISABLE;
3628         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3629                 return IFLA_VF_LINK_STATE_ENABLE;
3630         }
3631         return IFLA_VF_LINK_STATE_AUTO;
3632 }
3633
3634 static int mlx5_ifla_link2vport(u8 ifla_link)
3635 {
3636         switch (ifla_link) {
3637         case IFLA_VF_LINK_STATE_DISABLE:
3638                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3639         case IFLA_VF_LINK_STATE_ENABLE:
3640                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3641         }
3642         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3643 }
3644
3645 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3646                                    int link_state)
3647 {
3648         struct mlx5e_priv *priv = netdev_priv(dev);
3649         struct mlx5_core_dev *mdev = priv->mdev;
3650
3651         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3652                                             mlx5_ifla_link2vport(link_state));
3653 }
3654
3655 static int mlx5e_get_vf_config(struct net_device *dev,
3656                                int vf, struct ifla_vf_info *ivi)
3657 {
3658         struct mlx5e_priv *priv = netdev_priv(dev);
3659         struct mlx5_core_dev *mdev = priv->mdev;
3660         int err;
3661
3662         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3663         if (err)
3664                 return err;
3665         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3666         return 0;
3667 }
3668
3669 static int mlx5e_get_vf_stats(struct net_device *dev,
3670                               int vf, struct ifla_vf_stats *vf_stats)
3671 {
3672         struct mlx5e_priv *priv = netdev_priv(dev);
3673         struct mlx5_core_dev *mdev = priv->mdev;
3674
3675         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3676                                             vf_stats);
3677 }
3678 #endif
3679
3680 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3681                                  struct udp_tunnel_info *ti)
3682 {
3683         struct mlx5e_priv *priv = netdev_priv(netdev);
3684
3685         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3686                 return;
3687
3688         if (!mlx5e_vxlan_allowed(priv->mdev))
3689                 return;
3690
3691         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3692 }
3693
3694 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3695                                  struct udp_tunnel_info *ti)
3696 {
3697         struct mlx5e_priv *priv = netdev_priv(netdev);
3698
3699         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3700                 return;
3701
3702         if (!mlx5e_vxlan_allowed(priv->mdev))
3703                 return;
3704
3705         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3706 }
3707
3708 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3709                                                      struct sk_buff *skb,
3710                                                      netdev_features_t features)
3711 {
3712         unsigned int offset = 0;
3713         struct udphdr *udph;
3714         u8 proto;
3715         u16 port;
3716
3717         switch (vlan_get_protocol(skb)) {
3718         case htons(ETH_P_IP):
3719                 proto = ip_hdr(skb)->protocol;
3720                 break;
3721         case htons(ETH_P_IPV6):
3722                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3723                 break;
3724         default:
3725                 goto out;
3726         }
3727
3728         switch (proto) {
3729         case IPPROTO_GRE:
3730                 return features;
3731         case IPPROTO_UDP:
3732                 udph = udp_hdr(skb);
3733                 port = be16_to_cpu(udph->dest);
3734
3735                 /* Verify if UDP port is being offloaded by HW */
3736                 if (mlx5e_vxlan_lookup_port(priv, port))
3737                         return features;
3738         }
3739
3740 out:
3741         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3742         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3743 }
3744
3745 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3746                                               struct net_device *netdev,
3747                                               netdev_features_t features)
3748 {
3749         struct mlx5e_priv *priv = netdev_priv(netdev);
3750
3751         features = vlan_features_check(skb, features);
3752         features = vxlan_features_check(skb, features);
3753
3754 #ifdef CONFIG_MLX5_EN_IPSEC
3755         if (mlx5e_ipsec_feature_check(skb, netdev, features))
3756                 return features;
3757 #endif
3758
3759         /* Validate if the tunneled packet is being offloaded by HW */
3760         if (skb->encapsulation &&
3761             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3762                 return mlx5e_tunnel_features_check(priv, skb, features);
3763
3764         return features;
3765 }
3766
3767 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
3768                                         struct mlx5e_txqsq *sq)
3769 {
3770         struct mlx5_eq *eq = sq->cq.mcq.eq;
3771         u32 eqe_count;
3772
3773         netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
3774                    eq->eqn, eq->cons_index, eq->irqn);
3775
3776         eqe_count = mlx5_eq_poll_irq_disabled(eq);
3777         if (!eqe_count)
3778                 return false;
3779
3780         netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
3781         sq->channel->stats.eq_rearm++;
3782         return true;
3783 }
3784
3785 static void mlx5e_tx_timeout_work(struct work_struct *work)
3786 {
3787         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
3788                                                tx_timeout_work);
3789         struct net_device *dev = priv->netdev;
3790         bool reopen_channels = false;
3791         int i, err;
3792
3793         rtnl_lock();
3794         mutex_lock(&priv->state_lock);
3795
3796         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3797                 goto unlock;
3798
3799         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3800                 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
3801                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3802
3803                 if (!netif_xmit_stopped(dev_queue))
3804                         continue;
3805
3806                 netdev_err(dev,
3807                            "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
3808                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
3809                            jiffies_to_usecs(jiffies - dev_queue->trans_start));
3810
3811                 /* If we recover a lost interrupt, most likely TX timeout will
3812                  * be resolved, skip reopening channels
3813                  */
3814                 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
3815                         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3816                         reopen_channels = true;
3817                 }
3818         }
3819
3820         if (!reopen_channels)
3821                 goto unlock;
3822
3823         mlx5e_close_locked(dev);
3824         err = mlx5e_open_locked(dev);
3825         if (err)
3826                 netdev_err(priv->netdev,
3827                            "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
3828                            err);
3829
3830 unlock:
3831         mutex_unlock(&priv->state_lock);
3832         rtnl_unlock();
3833 }
3834
3835 static void mlx5e_tx_timeout(struct net_device *dev)
3836 {
3837         struct mlx5e_priv *priv = netdev_priv(dev);
3838
3839         netdev_err(dev, "TX timeout detected\n");
3840         queue_work(priv->wq, &priv->tx_timeout_work);
3841 }
3842
3843 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3844 {
3845         struct mlx5e_priv *priv = netdev_priv(netdev);
3846         struct bpf_prog *old_prog;
3847         int err = 0;
3848         bool reset, was_opened;
3849         int i;
3850
3851         mutex_lock(&priv->state_lock);
3852
3853         if ((netdev->features & NETIF_F_LRO) && prog) {
3854                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3855                 err = -EINVAL;
3856                 goto unlock;
3857         }
3858
3859         if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3860                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3861                 err = -EINVAL;
3862                 goto unlock;
3863         }
3864
3865         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3866         /* no need for full reset when exchanging programs */
3867         reset = (!priv->channels.params.xdp_prog || !prog);
3868
3869         if (was_opened && reset)
3870                 mlx5e_close_locked(netdev);
3871         if (was_opened && !reset) {
3872                 /* num_channels is invariant here, so we can take the
3873                  * batched reference right upfront.
3874                  */
3875                 prog = bpf_prog_add(prog, priv->channels.num);
3876                 if (IS_ERR(prog)) {
3877                         err = PTR_ERR(prog);
3878                         goto unlock;
3879                 }
3880         }
3881
3882         /* exchange programs, extra prog reference we got from caller
3883          * as long as we don't fail from this point onwards.
3884          */
3885         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3886         if (old_prog)
3887                 bpf_prog_put(old_prog);
3888
3889         if (reset) /* change RQ type according to priv->xdp_prog */
3890                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
3891
3892         if (was_opened && reset)
3893                 mlx5e_open_locked(netdev);
3894
3895         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3896                 goto unlock;
3897
3898         /* exchanging programs w/o reset, we update ref counts on behalf
3899          * of the channels RQs here.
3900          */
3901         for (i = 0; i < priv->channels.num; i++) {
3902                 struct mlx5e_channel *c = priv->channels.c[i];
3903
3904                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3905                 napi_synchronize(&c->napi);
3906                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3907
3908                 old_prog = xchg(&c->rq.xdp_prog, prog);
3909
3910                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3911                 /* napi_schedule in case we have missed anything */
3912                 napi_schedule(&c->napi);
3913
3914                 if (old_prog)
3915                         bpf_prog_put(old_prog);
3916         }
3917
3918 unlock:
3919         mutex_unlock(&priv->state_lock);
3920         return err;
3921 }
3922
3923 static u32 mlx5e_xdp_query(struct net_device *dev)
3924 {
3925         struct mlx5e_priv *priv = netdev_priv(dev);
3926         const struct bpf_prog *xdp_prog;
3927         u32 prog_id = 0;
3928
3929         mutex_lock(&priv->state_lock);
3930         xdp_prog = priv->channels.params.xdp_prog;
3931         if (xdp_prog)
3932                 prog_id = xdp_prog->aux->id;
3933         mutex_unlock(&priv->state_lock);
3934
3935         return prog_id;
3936 }
3937
3938 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3939 {
3940         switch (xdp->command) {
3941         case XDP_SETUP_PROG:
3942                 return mlx5e_xdp_set(dev, xdp->prog);
3943         case XDP_QUERY_PROG:
3944                 xdp->prog_id = mlx5e_xdp_query(dev);
3945                 xdp->prog_attached = !!xdp->prog_id;
3946                 return 0;
3947         default:
3948                 return -EINVAL;
3949         }
3950 }
3951
3952 #ifdef CONFIG_NET_POLL_CONTROLLER
3953 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3954  * reenabling interrupts.
3955  */
3956 static void mlx5e_netpoll(struct net_device *dev)
3957 {
3958         struct mlx5e_priv *priv = netdev_priv(dev);
3959         struct mlx5e_channels *chs = &priv->channels;
3960
3961         int i;
3962
3963         for (i = 0; i < chs->num; i++)
3964                 napi_schedule(&chs->c[i]->napi);
3965 }
3966 #endif
3967
3968 static const struct net_device_ops mlx5e_netdev_ops = {
3969         .ndo_open                = mlx5e_open,
3970         .ndo_stop                = mlx5e_close,
3971         .ndo_start_xmit          = mlx5e_xmit,
3972         .ndo_setup_tc            = mlx5e_setup_tc,
3973         .ndo_select_queue        = mlx5e_select_queue,
3974         .ndo_get_stats64         = mlx5e_get_stats,
3975         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3976         .ndo_set_mac_address     = mlx5e_set_mac,
3977         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3978         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3979         .ndo_set_features        = mlx5e_set_features,
3980         .ndo_fix_features        = mlx5e_fix_features,
3981         .ndo_change_mtu          = mlx5e_change_mtu,
3982         .ndo_do_ioctl            = mlx5e_ioctl,
3983         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3984         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
3985         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
3986         .ndo_features_check      = mlx5e_features_check,
3987 #ifdef CONFIG_RFS_ACCEL
3988         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3989 #endif
3990         .ndo_tx_timeout          = mlx5e_tx_timeout,
3991         .ndo_bpf                 = mlx5e_xdp,
3992 #ifdef CONFIG_NET_POLL_CONTROLLER
3993         .ndo_poll_controller     = mlx5e_netpoll,
3994 #endif
3995 #ifdef CONFIG_MLX5_ESWITCH
3996         /* SRIOV E-Switch NDOs */
3997         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
3998         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
3999         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4000         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4001         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4002         .ndo_get_vf_config       = mlx5e_get_vf_config,
4003         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4004         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4005         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4006         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4007 #endif
4008 };
4009
4010 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4011 {
4012         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4013                 return -EOPNOTSUPP;
4014         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4015             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4016             !MLX5_CAP_ETH(mdev, csum_cap) ||
4017             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4018             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4019             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4020             MLX5_CAP_FLOWTABLE(mdev,
4021                                flow_table_properties_nic_receive.max_ft_level)
4022                                < 3) {
4023                 mlx5_core_warn(mdev,
4024                                "Not creating net device, some required device capabilities are missing\n");
4025                 return -EOPNOTSUPP;
4026         }
4027         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4028                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4029         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4030                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4031
4032         return 0;
4033 }
4034
4035 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4036                                    int num_channels)
4037 {
4038         int i;
4039
4040         for (i = 0; i < len; i++)
4041                 indirection_rqt[i] = i % num_channels;
4042 }
4043
4044 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4045 {
4046         u32 link_speed = 0;
4047         u32 pci_bw = 0;
4048
4049         mlx5e_get_max_linkspeed(mdev, &link_speed);
4050         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4051         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4052                            link_speed, pci_bw);
4053
4054 #define MLX5E_SLOW_PCI_RATIO (2)
4055
4056         return link_speed && pci_bw &&
4057                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4058 }
4059
4060 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4061 {
4062         params->tx_cq_moderation.cq_period_mode = cq_period_mode;
4063
4064         params->tx_cq_moderation.pkts =
4065                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4066         params->tx_cq_moderation.usec =
4067                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4068
4069         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4070                 params->tx_cq_moderation.usec =
4071                         MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4072
4073         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4074                         params->tx_cq_moderation.cq_period_mode ==
4075                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4076 }
4077
4078 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4079 {
4080         params->rx_cq_moderation.cq_period_mode = cq_period_mode;
4081
4082         params->rx_cq_moderation.pkts =
4083                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4084         params->rx_cq_moderation.usec =
4085                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4086
4087         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4088                 params->rx_cq_moderation.usec =
4089                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4090
4091         if (params->rx_dim_enabled) {
4092                 switch (cq_period_mode) {
4093                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
4094                         params->rx_cq_moderation =
4095                                 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE);
4096                         break;
4097                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
4098                 default:
4099                         params->rx_cq_moderation =
4100                                 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE);
4101                 }
4102         }
4103
4104         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4105                         params->rx_cq_moderation.cq_period_mode ==
4106                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4107 }
4108
4109 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4110 {
4111         int i;
4112
4113         /* The supported periods are organized in ascending order */
4114         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4115                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4116                         break;
4117
4118         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4119 }
4120
4121 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4122                             struct mlx5e_params *params,
4123                             u16 max_channels, u16 mtu)
4124 {
4125         u8 rx_cq_period_mode;
4126
4127         params->sw_mtu = mtu;
4128         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4129         params->num_channels = max_channels;
4130         params->num_tc       = 1;
4131
4132         /* SQ */
4133         params->log_sq_size = is_kdump_kernel() ?
4134                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4135                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4136
4137         /* set CQE compression */
4138         params->rx_cqe_compress_def = false;
4139         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4140             MLX5_CAP_GEN(mdev, vport_group_manager))
4141                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4142
4143         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4144
4145         /* RQ */
4146         if (mlx5e_striding_rq_possible(mdev, params))
4147                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ,
4148                                 !slow_pci_heuristic(mdev));
4149         mlx5e_set_rq_type(mdev, params);
4150         mlx5e_init_rq_type_params(mdev, params);
4151
4152         /* HW LRO */
4153
4154         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4155         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4156                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4157                         params->lro_en = !slow_pci_heuristic(mdev);
4158         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4159
4160         /* CQ moderation params */
4161         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4162                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4163                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4164         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4165         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4166         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4167
4168         /* TX inline */
4169         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4170
4171         /* RSS */
4172         params->rss_hfunc = ETH_RSS_HASH_XOR;
4173         netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4174         mlx5e_build_default_indir_rqt(params->indirection_rqt,
4175                                       MLX5E_INDIR_RQT_SIZE, max_channels);
4176 }
4177
4178 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4179                                         struct net_device *netdev,
4180                                         const struct mlx5e_profile *profile,
4181                                         void *ppriv)
4182 {
4183         struct mlx5e_priv *priv = netdev_priv(netdev);
4184
4185         priv->mdev        = mdev;
4186         priv->netdev      = netdev;
4187         priv->profile     = profile;
4188         priv->ppriv       = ppriv;
4189         priv->msglevel    = MLX5E_MSG_LEVEL;
4190
4191         mlx5e_build_nic_params(mdev, &priv->channels.params,
4192                                profile->max_nch(mdev), netdev->mtu);
4193
4194         mutex_init(&priv->state_lock);
4195
4196         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4197         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4198         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4199         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4200
4201         mlx5e_timestamp_init(priv);
4202 }
4203
4204 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4205 {
4206         struct mlx5e_priv *priv = netdev_priv(netdev);
4207
4208         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4209         if (is_zero_ether_addr(netdev->dev_addr) &&
4210             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4211                 eth_hw_addr_random(netdev);
4212                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4213         }
4214 }
4215
4216 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4217 static const struct switchdev_ops mlx5e_switchdev_ops = {
4218         .switchdev_port_attr_get        = mlx5e_attr_get,
4219 };
4220 #endif
4221
4222 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4223 {
4224         struct mlx5e_priv *priv = netdev_priv(netdev);
4225         struct mlx5_core_dev *mdev = priv->mdev;
4226         bool fcs_supported;
4227         bool fcs_enabled;
4228
4229         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4230
4231         netdev->netdev_ops = &mlx5e_netdev_ops;
4232
4233 #ifdef CONFIG_MLX5_CORE_EN_DCB
4234         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4235                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4236 #endif
4237
4238         netdev->watchdog_timeo    = 15 * HZ;
4239
4240         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4241
4242         netdev->vlan_features    |= NETIF_F_SG;
4243         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4244         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4245         netdev->vlan_features    |= NETIF_F_GRO;
4246         netdev->vlan_features    |= NETIF_F_TSO;
4247         netdev->vlan_features    |= NETIF_F_TSO6;
4248         netdev->vlan_features    |= NETIF_F_RXCSUM;
4249         netdev->vlan_features    |= NETIF_F_RXHASH;
4250
4251         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4252         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4253
4254         if (!!MLX5_CAP_ETH(mdev, lro_cap))
4255                 netdev->vlan_features    |= NETIF_F_LRO;
4256
4257         netdev->hw_features       = netdev->vlan_features;
4258         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4259         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4260         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4261         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4262
4263         if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4264                 netdev->hw_features     |= NETIF_F_GSO_PARTIAL;
4265                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4266                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4267                 netdev->hw_enc_features |= NETIF_F_TSO;
4268                 netdev->hw_enc_features |= NETIF_F_TSO6;
4269                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4270         }
4271
4272         if (mlx5e_vxlan_allowed(mdev)) {
4273                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4274                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4275                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4276                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4277                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4278         }
4279
4280         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4281                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4282                                            NETIF_F_GSO_GRE_CSUM;
4283                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4284                                            NETIF_F_GSO_GRE_CSUM;
4285                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4286                                                 NETIF_F_GSO_GRE_CSUM;
4287         }
4288
4289         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4290
4291         if (fcs_supported)
4292                 netdev->hw_features |= NETIF_F_RXALL;
4293
4294         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4295                 netdev->hw_features |= NETIF_F_RXFCS;
4296
4297         netdev->features          = netdev->hw_features;
4298         if (!priv->channels.params.lro_en)
4299                 netdev->features  &= ~NETIF_F_LRO;
4300
4301         if (fcs_enabled)
4302                 netdev->features  &= ~NETIF_F_RXALL;
4303
4304         if (!priv->channels.params.scatter_fcs_en)
4305                 netdev->features  &= ~NETIF_F_RXFCS;
4306
4307 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4308         if (FT_CAP(flow_modify_en) &&
4309             FT_CAP(modify_root) &&
4310             FT_CAP(identified_miss_table_mode) &&
4311             FT_CAP(flow_table_modify)) {
4312                 netdev->hw_features      |= NETIF_F_HW_TC;
4313 #ifdef CONFIG_RFS_ACCEL
4314                 netdev->hw_features      |= NETIF_F_NTUPLE;
4315 #endif
4316         }
4317
4318         netdev->features         |= NETIF_F_HIGHDMA;
4319         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4320
4321         netdev->priv_flags       |= IFF_UNICAST_FLT;
4322
4323         mlx5e_set_netdev_dev_addr(netdev);
4324
4325 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4326         if (MLX5_VPORT_MANAGER(mdev))
4327                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4328 #endif
4329
4330         mlx5e_ipsec_build_netdev(priv);
4331 }
4332
4333 static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4334 {
4335         struct mlx5_core_dev *mdev = priv->mdev;
4336         int err;
4337
4338         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4339         if (err) {
4340                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4341                 priv->q_counter = 0;
4342         }
4343
4344         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4345         if (err) {
4346                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4347                 priv->drop_rq_q_counter = 0;
4348         }
4349 }
4350
4351 static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4352 {
4353         if (priv->q_counter)
4354                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4355
4356         if (priv->drop_rq_q_counter)
4357                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4358 }
4359
4360 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4361                            struct net_device *netdev,
4362                            const struct mlx5e_profile *profile,
4363                            void *ppriv)
4364 {
4365         struct mlx5e_priv *priv = netdev_priv(netdev);
4366         int err;
4367
4368         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4369         err = mlx5e_ipsec_init(priv);
4370         if (err)
4371                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4372         mlx5e_build_nic_netdev(netdev);
4373         mlx5e_vxlan_init(priv);
4374 }
4375
4376 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4377 {
4378         mlx5e_ipsec_cleanup(priv);
4379         mlx5e_vxlan_cleanup(priv);
4380 }
4381
4382 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4383 {
4384         struct mlx5_core_dev *mdev = priv->mdev;
4385         int err;
4386
4387         err = mlx5e_create_indirect_rqt(priv);
4388         if (err)
4389                 return err;
4390
4391         err = mlx5e_create_direct_rqts(priv);
4392         if (err)
4393                 goto err_destroy_indirect_rqts;
4394
4395         err = mlx5e_create_indirect_tirs(priv);
4396         if (err)
4397                 goto err_destroy_direct_rqts;
4398
4399         err = mlx5e_create_direct_tirs(priv);
4400         if (err)
4401                 goto err_destroy_indirect_tirs;
4402
4403         err = mlx5e_create_flow_steering(priv);
4404         if (err) {
4405                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4406                 goto err_destroy_direct_tirs;
4407         }
4408
4409         err = mlx5e_tc_init(priv);
4410         if (err)
4411                 goto err_destroy_flow_steering;
4412
4413         return 0;
4414
4415 err_destroy_flow_steering:
4416         mlx5e_destroy_flow_steering(priv);
4417 err_destroy_direct_tirs:
4418         mlx5e_destroy_direct_tirs(priv);
4419 err_destroy_indirect_tirs:
4420         mlx5e_destroy_indirect_tirs(priv);
4421 err_destroy_direct_rqts:
4422         mlx5e_destroy_direct_rqts(priv);
4423 err_destroy_indirect_rqts:
4424         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4425         return err;
4426 }
4427
4428 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4429 {
4430         mlx5e_tc_cleanup(priv);
4431         mlx5e_destroy_flow_steering(priv);
4432         mlx5e_destroy_direct_tirs(priv);
4433         mlx5e_destroy_indirect_tirs(priv);
4434         mlx5e_destroy_direct_rqts(priv);
4435         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4436 }
4437
4438 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4439 {
4440         int err;
4441
4442         err = mlx5e_create_tises(priv);
4443         if (err) {
4444                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4445                 return err;
4446         }
4447
4448 #ifdef CONFIG_MLX5_CORE_EN_DCB
4449         mlx5e_dcbnl_initialize(priv);
4450 #endif
4451         return 0;
4452 }
4453
4454 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4455 {
4456         struct net_device *netdev = priv->netdev;
4457         struct mlx5_core_dev *mdev = priv->mdev;
4458         u16 max_mtu;
4459
4460         mlx5e_init_l2_addr(priv);
4461
4462         /* Marking the link as currently not needed by the Driver */
4463         if (!netif_running(netdev))
4464                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4465
4466         /* MTU range: 68 - hw-specific max */
4467         netdev->min_mtu = ETH_MIN_MTU;
4468         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4469         netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4470         mlx5e_set_dev_port_mtu(priv);
4471
4472         mlx5_lag_add(mdev, netdev);
4473
4474         mlx5e_enable_async_events(priv);
4475
4476         if (MLX5_VPORT_MANAGER(priv->mdev))
4477                 mlx5e_register_vport_reps(priv);
4478
4479         if (netdev->reg_state != NETREG_REGISTERED)
4480                 return;
4481 #ifdef CONFIG_MLX5_CORE_EN_DCB
4482         mlx5e_dcbnl_init_app(priv);
4483 #endif
4484
4485         queue_work(priv->wq, &priv->set_rx_mode_work);
4486
4487         rtnl_lock();
4488         if (netif_running(netdev))
4489                 mlx5e_open(netdev);
4490         netif_device_attach(netdev);
4491         rtnl_unlock();
4492 }
4493
4494 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4495 {
4496         struct mlx5_core_dev *mdev = priv->mdev;
4497
4498 #ifdef CONFIG_MLX5_CORE_EN_DCB
4499         if (priv->netdev->reg_state == NETREG_REGISTERED)
4500                 mlx5e_dcbnl_delete_app(priv);
4501 #endif
4502
4503         rtnl_lock();
4504         if (netif_running(priv->netdev))
4505                 mlx5e_close(priv->netdev);
4506         netif_device_detach(priv->netdev);
4507         rtnl_unlock();
4508
4509         queue_work(priv->wq, &priv->set_rx_mode_work);
4510
4511         if (MLX5_VPORT_MANAGER(priv->mdev))
4512                 mlx5e_unregister_vport_reps(priv);
4513
4514         mlx5e_disable_async_events(priv);
4515         mlx5_lag_remove(mdev);
4516 }
4517
4518 static const struct mlx5e_profile mlx5e_nic_profile = {
4519         .init              = mlx5e_nic_init,
4520         .cleanup           = mlx5e_nic_cleanup,
4521         .init_rx           = mlx5e_init_nic_rx,
4522         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4523         .init_tx           = mlx5e_init_nic_tx,
4524         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4525         .enable            = mlx5e_nic_enable,
4526         .disable           = mlx5e_nic_disable,
4527         .update_stats      = mlx5e_update_ndo_stats,
4528         .max_nch           = mlx5e_get_max_num_channels,
4529         .update_carrier    = mlx5e_update_carrier,
4530         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4531         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4532         .max_tc            = MLX5E_MAX_NUM_TC,
4533 };
4534
4535 /* mlx5e generic netdev management API (move to en_common.c) */
4536
4537 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4538                                        const struct mlx5e_profile *profile,
4539                                        void *ppriv)
4540 {
4541         int nch = profile->max_nch(mdev);
4542         struct net_device *netdev;
4543         struct mlx5e_priv *priv;
4544
4545         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4546                                     nch * profile->max_tc,
4547                                     nch);
4548         if (!netdev) {
4549                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4550                 return NULL;
4551         }
4552
4553 #ifdef CONFIG_RFS_ACCEL
4554         netdev->rx_cpu_rmap = mdev->rmap;
4555 #endif
4556
4557         profile->init(mdev, netdev, profile, ppriv);
4558
4559         netif_carrier_off(netdev);
4560
4561         priv = netdev_priv(netdev);
4562
4563         priv->wq = create_singlethread_workqueue("mlx5e");
4564         if (!priv->wq)
4565                 goto err_cleanup_nic;
4566
4567         return netdev;
4568
4569 err_cleanup_nic:
4570         if (profile->cleanup)
4571                 profile->cleanup(priv);
4572         free_netdev(netdev);
4573
4574         return NULL;
4575 }
4576
4577 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4578 {
4579         struct mlx5_core_dev *mdev = priv->mdev;
4580         const struct mlx5e_profile *profile;
4581         int err;
4582
4583         profile = priv->profile;
4584         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4585
4586         err = profile->init_tx(priv);
4587         if (err)
4588                 goto out;
4589
4590         mlx5e_create_q_counters(priv);
4591
4592         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4593         if (err) {
4594                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4595                 goto err_destroy_q_counters;
4596         }
4597
4598         err = profile->init_rx(priv);
4599         if (err)
4600                 goto err_close_drop_rq;
4601
4602         if (profile->enable)
4603                 profile->enable(priv);
4604
4605         return 0;
4606
4607 err_close_drop_rq:
4608         mlx5e_close_drop_rq(&priv->drop_rq);
4609
4610 err_destroy_q_counters:
4611         mlx5e_destroy_q_counters(priv);
4612         profile->cleanup_tx(priv);
4613
4614 out:
4615         return err;
4616 }
4617
4618 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4619 {
4620         const struct mlx5e_profile *profile = priv->profile;
4621
4622         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4623
4624         if (profile->disable)
4625                 profile->disable(priv);
4626         flush_workqueue(priv->wq);
4627
4628         profile->cleanup_rx(priv);
4629         mlx5e_close_drop_rq(&priv->drop_rq);
4630         mlx5e_destroy_q_counters(priv);
4631         profile->cleanup_tx(priv);
4632         cancel_delayed_work_sync(&priv->update_stats_work);
4633 }
4634
4635 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4636 {
4637         const struct mlx5e_profile *profile = priv->profile;
4638         struct net_device *netdev = priv->netdev;
4639
4640         destroy_workqueue(priv->wq);
4641         if (profile->cleanup)
4642                 profile->cleanup(priv);
4643         free_netdev(netdev);
4644 }
4645
4646 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4647  * hardware contexts and to connect it to the current netdev.
4648  */
4649 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4650 {
4651         struct mlx5e_priv *priv = vpriv;
4652         struct net_device *netdev = priv->netdev;
4653         int err;
4654
4655         if (netif_device_present(netdev))
4656                 return 0;
4657
4658         err = mlx5e_create_mdev_resources(mdev);
4659         if (err)
4660                 return err;
4661
4662         err = mlx5e_attach_netdev(priv);
4663         if (err) {
4664                 mlx5e_destroy_mdev_resources(mdev);
4665                 return err;
4666         }
4667
4668         return 0;
4669 }
4670
4671 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4672 {
4673         struct mlx5e_priv *priv = vpriv;
4674         struct net_device *netdev = priv->netdev;
4675
4676         if (!netif_device_present(netdev))
4677                 return;
4678
4679         mlx5e_detach_netdev(priv);
4680         mlx5e_destroy_mdev_resources(mdev);
4681 }
4682
4683 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4684 {
4685         struct net_device *netdev;
4686         void *rpriv = NULL;
4687         void *priv;
4688         int err;
4689
4690         err = mlx5e_check_required_hca_cap(mdev);
4691         if (err)
4692                 return NULL;
4693
4694 #ifdef CONFIG_MLX5_ESWITCH
4695         if (MLX5_VPORT_MANAGER(mdev)) {
4696                 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4697                 if (!rpriv) {
4698                         mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4699                         return NULL;
4700                 }
4701         }
4702 #endif
4703
4704         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4705         if (!netdev) {
4706                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4707                 goto err_free_rpriv;
4708         }
4709
4710         priv = netdev_priv(netdev);
4711
4712         err = mlx5e_attach(mdev, priv);
4713         if (err) {
4714                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4715                 goto err_destroy_netdev;
4716         }
4717
4718         err = register_netdev(netdev);
4719         if (err) {
4720                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4721                 goto err_detach;
4722         }
4723
4724 #ifdef CONFIG_MLX5_CORE_EN_DCB
4725         mlx5e_dcbnl_init_app(priv);
4726 #endif
4727         return priv;
4728
4729 err_detach:
4730         mlx5e_detach(mdev, priv);
4731 err_destroy_netdev:
4732         mlx5e_destroy_netdev(priv);
4733 err_free_rpriv:
4734         kfree(rpriv);
4735         return NULL;
4736 }
4737
4738 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4739 {
4740         struct mlx5e_priv *priv = vpriv;
4741         void *ppriv = priv->ppriv;
4742
4743 #ifdef CONFIG_MLX5_CORE_EN_DCB
4744         mlx5e_dcbnl_delete_app(priv);
4745 #endif
4746         unregister_netdev(priv->netdev);
4747         mlx5e_detach(mdev, vpriv);
4748         mlx5e_destroy_netdev(priv);
4749         kfree(ppriv);
4750 }
4751
4752 static void *mlx5e_get_netdev(void *vpriv)
4753 {
4754         struct mlx5e_priv *priv = vpriv;
4755
4756         return priv->netdev;
4757 }
4758
4759 static struct mlx5_interface mlx5e_interface = {
4760         .add       = mlx5e_add,
4761         .remove    = mlx5e_remove,
4762         .attach    = mlx5e_attach,
4763         .detach    = mlx5e_detach,
4764         .event     = mlx5e_async_event,
4765         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
4766         .get_dev   = mlx5e_get_netdev,
4767 };
4768
4769 void mlx5e_init(void)
4770 {
4771         mlx5e_ipsec_build_inverse_table();
4772         mlx5e_build_ptys2ethtool_map();
4773         mlx5_register_interface(&mlx5e_interface);
4774 }
4775
4776 void mlx5e_cleanup(void)
4777 {
4778         mlx5_unregister_interface(&mlx5e_interface);
4779 }