drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include <net/page_pool.h>
  39 #include "eswitch.h"
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "en_rep.h"
  43 #include "en_accel/ipsec.h"
  44 #include "en_accel/ipsec_rxtx.h"
  45 #include "en_accel/tls.h"
  46 #include "accel/ipsec.h"
  47 #include "accel/tls.h"
  48 #include "vxlan.h"
  49
  50 struct mlx5e_rq_param {
  51         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  52         struct mlx5_wq_param    wq;
  53 };
  54
  55 struct mlx5e_sq_param {
  56         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  57         struct mlx5_wq_param       wq;
  58 };
  59
  60 struct mlx5e_cq_param {
  61         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  62         struct mlx5_wq_param       wq;
  63         u16                        eq_ix;
  64         u8                         cq_period_mode;
  65 };
  66
  67 struct mlx5e_channel_param {
  68         struct mlx5e_rq_param      rq;
  69         struct mlx5e_sq_param      sq;
  70         struct mlx5e_sq_param      xdp_sq;
  71         struct mlx5e_sq_param      icosq;
  72         struct mlx5e_cq_param      rx_cq;
  73         struct mlx5e_cq_param      tx_cq;
  74         struct mlx5e_cq_param      icosq_cq;
  75 };
  76
  77 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  78 {
  79         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  80                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  81                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  82         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  83         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  84
  85         if (!striding_rq_umr)
  86                 return false;
  87         if (!inline_umr) {
  88                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  89                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  90                 return false;
  91         }
  92         return true;
  93 }
  94
  95 static u32 mlx5e_mpwqe_get_linear_frag_sz(struct mlx5e_params *params)
  96 {
  97         if (!params->xdp_prog) {
  98                 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
  99                 u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN;
 100
 101                 return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu);
 102         }
 103
 104         return PAGE_SIZE;
 105 }
 106
 107 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 108 {
 109         u32 linear_frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
 110
 111         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 112 }
 113
 114 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 115                                          struct mlx5e_params *params)
 116 {
 117         u32 frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
 118         s8 signed_log_num_strides_param;
 119         u8 log_num_strides;
 120
 121         if (params->lro_en || frag_sz > PAGE_SIZE)
 122                 return false;
 123
 124         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 125                 return true;
 126
 127         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 128         signed_log_num_strides_param =
 129                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 130
 131         return signed_log_num_strides_param >= 0;
 132 }
 133
 134 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 135 {
 136         if (params->log_rq_mtu_frames <
 137             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 138                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 139
 140         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 141 }
 142
 143 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 144                                           struct mlx5e_params *params)
 145 {
 146         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 147                 return order_base_2(mlx5e_mpwqe_get_linear_frag_sz(params));
 148
 149         return MLX5E_MPWQE_STRIDE_SZ(mdev,
 150                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 151 }
 152
 153 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 154                                           struct mlx5e_params *params)
 155 {
 156         return MLX5_MPWRQ_LOG_WQE_SZ -
 157                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 158 }
 159
 160 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 161                                  struct mlx5e_params *params)
 162 {
 163         u16 linear_rq_headroom = params->xdp_prog ?
 164                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 165
 166         linear_rq_headroom += NET_IP_ALIGN;
 167
 168         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)
 169                 return linear_rq_headroom;
 170
 171         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 172                 return linear_rq_headroom;
 173
 174         return 0;
 175 }
 176
 177 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 178                                struct mlx5e_params *params)
 179 {
 180         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 181         params->log_rq_mtu_frames = is_kdump_kernel() ?
 182                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 183                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 184         switch (params->rq_wq_type) {
 185         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 186                 break;
 187         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 188                 /* Extra room needed for build_skb */
 189                 params->lro_wqe_sz -= mlx5e_get_rq_headroom(mdev, params) +
 190                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 191         }
 192
 193         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 194                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 195                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 196                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 197                        BIT(params->log_rq_mtu_frames),
 198                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 199                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 200 }
 201
 202 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 203                                 struct mlx5e_params *params)
 204 {
 205         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 206                 !MLX5_IPSEC_DEV(mdev) &&
 207                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 208 }
 209
 210 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 211 {
 212         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 213                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 214                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 215                 MLX5_WQ_TYPE_LINKED_LIST;
 216 }
 217
 218 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 219 {
 220         struct mlx5_core_dev *mdev = priv->mdev;
 221         u8 port_state;
 222
 223         port_state = mlx5_query_vport_state(mdev,
 224                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
 225                                             0);
 226
 227         if (port_state == VPORT_STATE_UP) {
 228                 netdev_info(priv->netdev, "Link up\n");
 229                 netif_carrier_on(priv->netdev);
 230         } else {
 231                 netdev_info(priv->netdev, "Link down\n");
 232                 netif_carrier_off(priv->netdev);
 233         }
 234 }
 235
 236 static void mlx5e_update_carrier_work(struct work_struct *work)
 237 {
 238         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 239                                                update_carrier_work);
 240
 241         mutex_lock(&priv->state_lock);
 242         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 243                 if (priv->profile->update_carrier)
 244                         priv->profile->update_carrier(priv);
 245         mutex_unlock(&priv->state_lock);
 246 }
 247
 248 void mlx5e_update_stats(struct mlx5e_priv *priv)
 249 {
 250         int i;
 251
 252         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 253                 if (mlx5e_stats_grps[i].update_stats)
 254                         mlx5e_stats_grps[i].update_stats(priv);
 255 }
 256
 257 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 258 {
 259         int i;
 260
 261         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 262                 if (mlx5e_stats_grps[i].update_stats_mask &
 263                     MLX5E_NDO_UPDATE_STATS)
 264                         mlx5e_stats_grps[i].update_stats(priv);
 265 }
 266
 267 void mlx5e_update_stats_work(struct work_struct *work)
 268 {
 269         struct delayed_work *dwork = to_delayed_work(work);
 270         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 271                                                update_stats_work);
 272         mutex_lock(&priv->state_lock);
 273         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 274                 priv->profile->update_stats(priv);
 275                 queue_delayed_work(priv->wq, dwork,
 276                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 277         }
 278         mutex_unlock(&priv->state_lock);
 279 }
 280
 281 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 282                               enum mlx5_dev_event event, unsigned long param)
 283 {
 284         struct mlx5e_priv *priv = vpriv;
 285
 286         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 287                 return;
 288
 289         switch (event) {
 290         case MLX5_DEV_EVENT_PORT_UP:
 291         case MLX5_DEV_EVENT_PORT_DOWN:
 292                 queue_work(priv->wq, &priv->update_carrier_work);
 293                 break;
 294         default:
 295                 break;
 296         }
 297 }
 298
 299 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 300 {
 301         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 302 }
 303
 304 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 305 {
 306         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 307         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 308 }
 309
 310 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 311                                        struct mlx5e_icosq *sq,
 312                                        struct mlx5e_umr_wqe *wqe)
 313 {
 314         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 315         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 316         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 317
 318         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 319                                       ds_cnt);
 320         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 321         cseg->imm       = rq->mkey_be;
 322
 323         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 324         ucseg->xlt_octowords =
 325                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 326         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 327 }
 328
 329 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 330                                      struct mlx5e_channel *c)
 331 {
 332         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 333
 334         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 335                                       GFP_KERNEL, cpu_to_node(c->cpu));
 336         if (!rq->mpwqe.info)
 337                 return -ENOMEM;
 338
 339         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 340
 341         return 0;
 342 }
 343
 344 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 345                                  u64 npages, u8 page_shift,
 346                                  struct mlx5_core_mkey *umr_mkey)
 347 {
 348         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 349         void *mkc;
 350         u32 *in;
 351         int err;
 352
 353         in = kvzalloc(inlen, GFP_KERNEL);
 354         if (!in)
 355                 return -ENOMEM;
 356
 357         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 358
 359         MLX5_SET(mkc, mkc, free, 1);
 360         MLX5_SET(mkc, mkc, umr_en, 1);
 361         MLX5_SET(mkc, mkc, lw, 1);
 362         MLX5_SET(mkc, mkc, lr, 1);
 363         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 364
 365         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 366         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 367         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 368         MLX5_SET(mkc, mkc, translations_octword_size,
 369                  MLX5_MTT_OCTW(npages));
 370         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 371
 372         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 373
 374         kvfree(in);
 375         return err;
 376 }
 377
 378 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 379 {
 380         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
 381
 382         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 383 }
 384
 385 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 386 {
 387         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 388 }
 389
 390 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 391                           struct mlx5e_params *params,
 392                           struct mlx5e_rq_param *rqp,
 393                           struct mlx5e_rq *rq)
 394 {
 395         struct page_pool_params pp_params = { 0 };
 396         struct mlx5_core_dev *mdev = c->mdev;
 397         void *rqc = rqp->rqc;
 398         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 399         u32 byte_count, pool_size;
 400         int npages;
 401         int wq_sz;
 402         int err;
 403         int i;
 404
 405         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 406
 407         err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
 408                                 &rq->wq_ctrl);
 409         if (err)
 410                 return err;
 411
 412         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 413
 414         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 415
 416         rq->wq_type = params->rq_wq_type;
 417         rq->pdev    = c->pdev;
 418         rq->netdev  = c->netdev;
 419         rq->tstamp  = c->tstamp;
 420         rq->clock   = &mdev->clock;
 421         rq->channel = c;
 422         rq->ix      = c->ix;
 423         rq->mdev    = mdev;
 424         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 425
 426         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 427         if (IS_ERR(rq->xdp_prog)) {
 428                 err = PTR_ERR(rq->xdp_prog);
 429                 rq->xdp_prog = NULL;
 430                 goto err_rq_wq_destroy;
 431         }
 432
 433         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 434         if (err < 0)
 435                 goto err_rq_wq_destroy;
 436
 437         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 438         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 439         pool_size = 1 << params->log_rq_mtu_frames;
 440
 441         switch (rq->wq_type) {
 442         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 443
 444                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 445                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 446                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 447
 448                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 449 #ifdef CONFIG_MLX5_EN_IPSEC
 450                 if (MLX5_IPSEC_DEV(mdev)) {
 451                         err = -EINVAL;
 452                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 453                         goto err_rq_wq_destroy;
 454                 }
 455 #endif
 456                 if (!rq->handle_rx_cqe) {
 457                         err = -EINVAL;
 458                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 459                         goto err_rq_wq_destroy;
 460                 }
 461
 462                 rq->mpwqe.skb_from_cqe_mpwrq =
 463                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 464                         mlx5e_skb_from_cqe_mpwrq_linear :
 465                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 466                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 467                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 468
 469                 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 470
 471                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 472                 if (err)
 473                         goto err_rq_wq_destroy;
 474                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 475
 476                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 477                 if (err)
 478                         goto err_destroy_umr_mkey;
 479                 break;
 480         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 481                 rq->wqe.frag_info =
 482                         kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
 483                                      GFP_KERNEL, cpu_to_node(c->cpu));
 484                 if (!rq->wqe.frag_info) {
 485                         err = -ENOMEM;
 486                         goto err_rq_wq_destroy;
 487                 }
 488                 rq->post_wqes = mlx5e_post_rx_wqes;
 489                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 490
 491 #ifdef CONFIG_MLX5_EN_IPSEC
 492                 if (c->priv->ipsec)
 493                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 494                 else
 495 #endif
 496                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 497                 if (!rq->handle_rx_cqe) {
 498                         kfree(rq->wqe.frag_info);
 499                         err = -EINVAL;
 500                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 501                         goto err_rq_wq_destroy;
 502                 }
 503
 504                 byte_count = params->lro_en  ?
 505                                 params->lro_wqe_sz :
 506                                 MLX5E_SW2HW_MTU(params, params->sw_mtu);
 507 #ifdef CONFIG_MLX5_EN_IPSEC
 508                 if (MLX5_IPSEC_DEV(mdev))
 509                         byte_count += MLX5E_METADATA_ETHER_LEN;
 510 #endif
 511                 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
 512
 513                 /* calc the required page order */
 514                 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
 515                 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
 516                 rq->buff.page_order = order_base_2(npages);
 517
 518                 byte_count |= MLX5_HW_START_PADDING;
 519                 rq->mkey_be = c->mkey_be;
 520         }
 521
 522         /* Create a page_pool and register it with rxq */
 523         pp_params.order     = rq->buff.page_order;
 524         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 525         pp_params.pool_size = pool_size;
 526         pp_params.nid       = cpu_to_node(c->cpu);
 527         pp_params.dev       = c->pdev;
 528         pp_params.dma_dir   = rq->buff.map_dir;
 529
 530         /* page_pool can be used even when there is no rq->xdp_prog,
 531          * given page_pool does not handle DMA mapping there is no
 532          * required state to clear. And page_pool gracefully handle
 533          * elevated refcnt.
 534          */
 535         rq->page_pool = page_pool_create(&pp_params);
 536         if (IS_ERR(rq->page_pool)) {
 537                 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 538                         kfree(rq->wqe.frag_info);
 539                 err = PTR_ERR(rq->page_pool);
 540                 rq->page_pool = NULL;
 541                 goto err_rq_wq_destroy;
 542         }
 543         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 544                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 545         if (err)
 546                 goto err_rq_wq_destroy;
 547
 548         for (i = 0; i < wq_sz; i++) {
 549                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 550
 551                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 552                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 553
 554                         wqe->data.addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 555                 }
 556
 557                 wqe->data.byte_count = cpu_to_be32(byte_count);
 558                 wqe->data.lkey = rq->mkey_be;
 559         }
 560
 561         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 562
 563         switch (params->rx_cq_moderation.cq_period_mode) {
 564         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 565                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 566                 break;
 567         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 568         default:
 569                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 570         }
 571
 572         rq->page_cache.head = 0;
 573         rq->page_cache.tail = 0;
 574
 575         return 0;
 576
 577 err_destroy_umr_mkey:
 578         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 579
 580 err_rq_wq_destroy:
 581         if (rq->xdp_prog)
 582                 bpf_prog_put(rq->xdp_prog);
 583         xdp_rxq_info_unreg(&rq->xdp_rxq);
 584         if (rq->page_pool)
 585                 page_pool_destroy(rq->page_pool);
 586         mlx5_wq_destroy(&rq->wq_ctrl);
 587
 588         return err;
 589 }
 590
 591 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 592 {
 593         int i;
 594
 595         if (rq->xdp_prog)
 596                 bpf_prog_put(rq->xdp_prog);
 597
 598         xdp_rxq_info_unreg(&rq->xdp_rxq);
 599         if (rq->page_pool)
 600                 page_pool_destroy(rq->page_pool);
 601
 602         switch (rq->wq_type) {
 603         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 604                 kfree(rq->mpwqe.info);
 605                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 606                 break;
 607         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 608                 kfree(rq->wqe.frag_info);
 609         }
 610
 611         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 612              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 613                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 614
 615                 mlx5e_page_release(rq, dma_info, false);
 616         }
 617         mlx5_wq_destroy(&rq->wq_ctrl);
 618 }
 619
 620 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 621                            struct mlx5e_rq_param *param)
 622 {
 623         struct mlx5_core_dev *mdev = rq->mdev;
 624
 625         void *in;
 626         void *rqc;
 627         void *wq;
 628         int inlen;
 629         int err;
 630
 631         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 632                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 633         in = kvzalloc(inlen, GFP_KERNEL);
 634         if (!in)
 635                 return -ENOMEM;
 636
 637         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 638         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 639
 640         memcpy(rqc, param->rqc, sizeof(param->rqc));
 641
 642         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 643         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 644         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 645                                                 MLX5_ADAPTER_PAGE_SHIFT);
 646         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 647
 648         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 649                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 650
 651         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 652
 653         kvfree(in);
 654
 655         return err;
 656 }
 657
 658 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 659                                  int next_state)
 660 {
 661         struct mlx5_core_dev *mdev = rq->mdev;
 662
 663         void *in;
 664         void *rqc;
 665         int inlen;
 666         int err;
 667
 668         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 669         in = kvzalloc(inlen, GFP_KERNEL);
 670         if (!in)
 671                 return -ENOMEM;
 672
 673         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 674
 675         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 676         MLX5_SET(rqc, rqc, state, next_state);
 677
 678         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 679
 680         kvfree(in);
 681
 682         return err;
 683 }
 684
 685 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 686 {
 687         struct mlx5e_channel *c = rq->channel;
 688         struct mlx5e_priv *priv = c->priv;
 689         struct mlx5_core_dev *mdev = priv->mdev;
 690
 691         void *in;
 692         void *rqc;
 693         int inlen;
 694         int err;
 695
 696         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 697         in = kvzalloc(inlen, GFP_KERNEL);
 698         if (!in)
 699                 return -ENOMEM;
 700
 701         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 702
 703         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 704         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 705                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 706         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 707         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 708
 709         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 710
 711         kvfree(in);
 712
 713         return err;
 714 }
 715
 716 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 717 {
 718         struct mlx5e_channel *c = rq->channel;
 719         struct mlx5_core_dev *mdev = c->mdev;
 720         void *in;
 721         void *rqc;
 722         int inlen;
 723         int err;
 724
 725         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 726         in = kvzalloc(inlen, GFP_KERNEL);
 727         if (!in)
 728                 return -ENOMEM;
 729
 730         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 731
 732         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 733         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 734                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 735         MLX5_SET(rqc, rqc, vsd, vsd);
 736         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 737
 738         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 739
 740         kvfree(in);
 741
 742         return err;
 743 }
 744
 745 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 746 {
 747         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 748 }
 749
 750 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 751 {
 752         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 753         struct mlx5e_channel *c = rq->channel;
 754
 755         struct mlx5_wq_ll *wq = &rq->wq;
 756         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
 757
 758         while (time_before(jiffies, exp_time)) {
 759                 if (wq->cur_sz >= min_wqes)
 760                         return 0;
 761
 762                 msleep(20);
 763         }
 764
 765         netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 766                     rq->rqn, wq->cur_sz, min_wqes);
 767         return -ETIMEDOUT;
 768 }
 769
 770 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 771 {
 772         struct mlx5_wq_ll *wq = &rq->wq;
 773         struct mlx5e_rx_wqe *wqe;
 774         __be16 wqe_ix_be;
 775         u16 wqe_ix;
 776
 777         /* UMR WQE (if in progress) is always at wq->head */
 778         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
 779             rq->mpwqe.umr_in_progress)
 780                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 781
 782         while (!mlx5_wq_ll_is_empty(wq)) {
 783                 wqe_ix_be = *wq->tail_next;
 784                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 785                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 786                 rq->dealloc_wqe(rq, wqe_ix);
 787                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 788                                &wqe->next.next_wqe_index);
 789         }
 790
 791         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
 792                 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
 793                  * but yet to be re-posted.
 794                  */
 795                 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 796
 797                 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
 798                         rq->dealloc_wqe(rq, wqe_ix);
 799         }
 800 }
 801
 802 static int mlx5e_open_rq(struct mlx5e_channel *c,
 803                          struct mlx5e_params *params,
 804                          struct mlx5e_rq_param *param,
 805                          struct mlx5e_rq *rq)
 806 {
 807         int err;
 808
 809         err = mlx5e_alloc_rq(c, params, param, rq);
 810         if (err)
 811                 return err;
 812
 813         err = mlx5e_create_rq(rq, param);
 814         if (err)
 815                 goto err_free_rq;
 816
 817         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 818         if (err)
 819                 goto err_destroy_rq;
 820
 821         if (params->rx_dim_enabled)
 822                 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
 823
 824         return 0;
 825
 826 err_destroy_rq:
 827         mlx5e_destroy_rq(rq);
 828 err_free_rq:
 829         mlx5e_free_rq(rq);
 830
 831         return err;
 832 }
 833
 834 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 835 {
 836         struct mlx5e_icosq *sq = &rq->channel->icosq;
 837         u16 pi = sq->pc & sq->wq.sz_m1;
 838         struct mlx5e_tx_wqe *nopwqe;
 839
 840         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 841         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 842         nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
 843         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 844 }
 845
 846 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 847 {
 848         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 849         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 850 }
 851
 852 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 853 {
 854         cancel_work_sync(&rq->dim.work);
 855         mlx5e_destroy_rq(rq);
 856         mlx5e_free_rx_descs(rq);
 857         mlx5e_free_rq(rq);
 858 }
 859
 860 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 861 {
 862         kfree(sq->db.di);
 863 }
 864
 865 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 866 {
 867         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 868
 869         sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
 870                                      GFP_KERNEL, numa);
 871         if (!sq->db.di) {
 872                 mlx5e_free_xdpsq_db(sq);
 873                 return -ENOMEM;
 874         }
 875
 876         return 0;
 877 }
 878
 879 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 880                              struct mlx5e_params *params,
 881                              struct mlx5e_sq_param *param,
 882                              struct mlx5e_xdpsq *sq)
 883 {
 884         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 885         struct mlx5_core_dev *mdev = c->mdev;
 886         int err;
 887
 888         sq->pdev      = c->pdev;
 889         sq->mkey_be   = c->mkey_be;
 890         sq->channel   = c;
 891         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 892         sq->min_inline_mode = params->tx_min_inline_mode;
 893
 894         param->wq.db_numa_node = cpu_to_node(c->cpu);
 895         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 896         if (err)
 897                 return err;
 898         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 899
 900         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 901         if (err)
 902                 goto err_sq_wq_destroy;
 903
 904         return 0;
 905
 906 err_sq_wq_destroy:
 907         mlx5_wq_destroy(&sq->wq_ctrl);
 908
 909         return err;
 910 }
 911
 912 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
 913 {
 914         mlx5e_free_xdpsq_db(sq);
 915         mlx5_wq_destroy(&sq->wq_ctrl);
 916 }
 917
 918 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
 919 {
 920         kfree(sq->db.ico_wqe);
 921 }
 922
 923 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
 924 {
 925         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 926
 927         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 928                                       GFP_KERNEL, numa);
 929         if (!sq->db.ico_wqe)
 930                 return -ENOMEM;
 931
 932         return 0;
 933 }
 934
 935 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
 936                              struct mlx5e_sq_param *param,
 937                              struct mlx5e_icosq *sq)
 938 {
 939         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 940         struct mlx5_core_dev *mdev = c->mdev;
 941         int err;
 942
 943         sq->channel   = c;
 944         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 945
 946         param->wq.db_numa_node = cpu_to_node(c->cpu);
 947         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 948         if (err)
 949                 return err;
 950         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 951
 952         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
 953         if (err)
 954                 goto err_sq_wq_destroy;
 955
 956         sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
 957
 958         return 0;
 959
 960 err_sq_wq_destroy:
 961         mlx5_wq_destroy(&sq->wq_ctrl);
 962
 963         return err;
 964 }
 965
 966 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
 967 {
 968         mlx5e_free_icosq_db(sq);
 969         mlx5_wq_destroy(&sq->wq_ctrl);
 970 }
 971
 972 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
 973 {
 974         kfree(sq->db.wqe_info);
 975         kfree(sq->db.dma_fifo);
 976 }
 977
 978 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
 979 {
 980         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 981         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 982
 983         sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
 984                                            GFP_KERNEL, numa);
 985         sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
 986                                            GFP_KERNEL, numa);
 987         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
 988                 mlx5e_free_txqsq_db(sq);
 989                 return -ENOMEM;
 990         }
 991
 992         sq->dma_fifo_mask = df_sz - 1;
 993
 994         return 0;
 995 }
 996
 997 static void mlx5e_sq_recover(struct work_struct *work);
 998 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
 999                              int txq_ix,
1000                              struct mlx5e_params *params,
1001                              struct mlx5e_sq_param *param,
1002                              struct mlx5e_txqsq *sq)
1003 {
1004         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1005         struct mlx5_core_dev *mdev = c->mdev;
1006         int err;
1007
1008         sq->pdev      = c->pdev;
1009         sq->tstamp    = c->tstamp;
1010         sq->clock     = &mdev->clock;
1011         sq->mkey_be   = c->mkey_be;
1012         sq->channel   = c;
1013         sq->txq_ix    = txq_ix;
1014         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1015         sq->min_inline_mode = params->tx_min_inline_mode;
1016         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1017         if (MLX5_IPSEC_DEV(c->priv->mdev))
1018                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1019         if (mlx5_accel_is_tls_device(c->priv->mdev))
1020                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1021
1022         param->wq.db_numa_node = cpu_to_node(c->cpu);
1023         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1024         if (err)
1025                 return err;
1026         sq->wq.db    = &sq->wq.db[MLX5_SND_DBR];
1027
1028         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1029         if (err)
1030                 goto err_sq_wq_destroy;
1031
1032         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1033         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1034
1035         sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1036
1037         return 0;
1038
1039 err_sq_wq_destroy:
1040         mlx5_wq_destroy(&sq->wq_ctrl);
1041
1042         return err;
1043 }
1044
1045 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1046 {
1047         mlx5e_free_txqsq_db(sq);
1048         mlx5_wq_destroy(&sq->wq_ctrl);
1049 }
1050
1051 struct mlx5e_create_sq_param {
1052         struct mlx5_wq_ctrl        *wq_ctrl;
1053         u32                         cqn;
1054         u32                         tisn;
1055         u8                          tis_lst_sz;
1056         u8                          min_inline_mode;
1057 };
1058
1059 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1060                            struct mlx5e_sq_param *param,
1061                            struct mlx5e_create_sq_param *csp,
1062                            u32 *sqn)
1063 {
1064         void *in;
1065         void *sqc;
1066         void *wq;
1067         int inlen;
1068         int err;
1069
1070         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1071                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1072         in = kvzalloc(inlen, GFP_KERNEL);
1073         if (!in)
1074                 return -ENOMEM;
1075
1076         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1077         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1078
1079         memcpy(sqc, param->sqc, sizeof(param->sqc));
1080         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1081         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1082         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1083
1084         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1085                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1086
1087         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1088         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1089
1090         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1091         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1092         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1093                                           MLX5_ADAPTER_PAGE_SHIFT);
1094         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1095
1096         mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1097
1098         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1099
1100         kvfree(in);
1101
1102         return err;
1103 }
1104
1105 struct mlx5e_modify_sq_param {
1106         int curr_state;
1107         int next_state;
1108         bool rl_update;
1109         int rl_index;
1110 };
1111
1112 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1113                            struct mlx5e_modify_sq_param *p)
1114 {
1115         void *in;
1116         void *sqc;
1117         int inlen;
1118         int err;
1119
1120         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1121         in = kvzalloc(inlen, GFP_KERNEL);
1122         if (!in)
1123                 return -ENOMEM;
1124
1125         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1126
1127         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1128         MLX5_SET(sqc, sqc, state, p->next_state);
1129         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1130                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1131                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1132         }
1133
1134         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1135
1136         kvfree(in);
1137
1138         return err;
1139 }
1140
1141 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1142 {
1143         mlx5_core_destroy_sq(mdev, sqn);
1144 }
1145
1146 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1147                                struct mlx5e_sq_param *param,
1148                                struct mlx5e_create_sq_param *csp,
1149                                u32 *sqn)
1150 {
1151         struct mlx5e_modify_sq_param msp = {0};
1152         int err;
1153
1154         err = mlx5e_create_sq(mdev, param, csp, sqn);
1155         if (err)
1156                 return err;
1157
1158         msp.curr_state = MLX5_SQC_STATE_RST;
1159         msp.next_state = MLX5_SQC_STATE_RDY;
1160         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1161         if (err)
1162                 mlx5e_destroy_sq(mdev, *sqn);
1163
1164         return err;
1165 }
1166
1167 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1168                                 struct mlx5e_txqsq *sq, u32 rate);
1169
1170 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1171                             u32 tisn,
1172                             int txq_ix,
1173                             struct mlx5e_params *params,
1174                             struct mlx5e_sq_param *param,
1175                             struct mlx5e_txqsq *sq)
1176 {
1177         struct mlx5e_create_sq_param csp = {};
1178         u32 tx_rate;
1179         int err;
1180
1181         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1182         if (err)
1183                 return err;
1184
1185         csp.tisn            = tisn;
1186         csp.tis_lst_sz      = 1;
1187         csp.cqn             = sq->cq.mcq.cqn;
1188         csp.wq_ctrl         = &sq->wq_ctrl;
1189         csp.min_inline_mode = sq->min_inline_mode;
1190         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1191         if (err)
1192                 goto err_free_txqsq;
1193
1194         tx_rate = c->priv->tx_rates[sq->txq_ix];
1195         if (tx_rate)
1196                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1197
1198         if (params->tx_dim_enabled)
1199                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1200
1201         return 0;
1202
1203 err_free_txqsq:
1204         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1205         mlx5e_free_txqsq(sq);
1206
1207         return err;
1208 }
1209
1210 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1211 {
1212         WARN_ONCE(sq->cc != sq->pc,
1213                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1214                   sq->sqn, sq->cc, sq->pc);
1215         sq->cc = 0;
1216         sq->dma_fifo_cc = 0;
1217         sq->pc = 0;
1218 }
1219
1220 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1221 {
1222         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1223         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1224         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1225         netdev_tx_reset_queue(sq->txq);
1226         netif_tx_start_queue(sq->txq);
1227 }
1228
1229 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1230 {
1231         __netif_tx_lock_bh(txq);
1232         netif_tx_stop_queue(txq);
1233         __netif_tx_unlock_bh(txq);
1234 }
1235
1236 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1237 {
1238         struct mlx5e_channel *c = sq->channel;
1239
1240         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1241         /* prevent netif_tx_wake_queue */
1242         napi_synchronize(&c->napi);
1243
1244         netif_tx_disable_queue(sq->txq);
1245
1246         /* last doorbell out, godspeed .. */
1247         if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1248                 struct mlx5e_tx_wqe *nop;
1249
1250                 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1251                 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1252                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1253         }
1254 }
1255
1256 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1257 {
1258         struct mlx5e_channel *c = sq->channel;
1259         struct mlx5_core_dev *mdev = c->mdev;
1260         struct mlx5_rate_limit rl = {0};
1261
1262         mlx5e_destroy_sq(mdev, sq->sqn);
1263         if (sq->rate_limit) {
1264                 rl.rate = sq->rate_limit;
1265                 mlx5_rl_remove_rate(mdev, &rl);
1266         }
1267         mlx5e_free_txqsq_descs(sq);
1268         mlx5e_free_txqsq(sq);
1269 }
1270
1271 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1272 {
1273         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1274
1275         while (time_before(jiffies, exp_time)) {
1276                 if (sq->cc == sq->pc)
1277                         return 0;
1278
1279                 msleep(20);
1280         }
1281
1282         netdev_err(sq->channel->netdev,
1283                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1284                    sq->sqn, sq->cc, sq->pc);
1285
1286         return -ETIMEDOUT;
1287 }
1288
1289 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1290 {
1291         struct mlx5_core_dev *mdev = sq->channel->mdev;
1292         struct net_device *dev = sq->channel->netdev;
1293         struct mlx5e_modify_sq_param msp = {0};
1294         int err;
1295
1296         msp.curr_state = curr_state;
1297         msp.next_state = MLX5_SQC_STATE_RST;
1298
1299         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1300         if (err) {
1301                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1302                 return err;
1303         }
1304
1305         memset(&msp, 0, sizeof(msp));
1306         msp.curr_state = MLX5_SQC_STATE_RST;
1307         msp.next_state = MLX5_SQC_STATE_RDY;
1308
1309         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1310         if (err) {
1311                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1312                 return err;
1313         }
1314
1315         return 0;
1316 }
1317
1318 static void mlx5e_sq_recover(struct work_struct *work)
1319 {
1320         struct mlx5e_txqsq_recover *recover =
1321                 container_of(work, struct mlx5e_txqsq_recover,
1322                              recover_work);
1323         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1324                                               recover);
1325         struct mlx5_core_dev *mdev = sq->channel->mdev;
1326         struct net_device *dev = sq->channel->netdev;
1327         u8 state;
1328         int err;
1329
1330         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1331         if (err) {
1332                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1333                            sq->sqn, err);
1334                 return;
1335         }
1336
1337         if (state != MLX5_RQC_STATE_ERR) {
1338                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1339                 return;
1340         }
1341
1342         netif_tx_disable_queue(sq->txq);
1343
1344         if (mlx5e_wait_for_sq_flush(sq))
1345                 return;
1346
1347         /* If the interval between two consecutive recovers per SQ is too
1348          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1349          * If we reached this state, there is probably a bug that needs to be
1350          * fixed. let's keep the queue close and let tx timeout cleanup.
1351          */
1352         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1353             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1354                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1355                            sq->sqn);
1356                 return;
1357         }
1358
1359         /* At this point, no new packets will arrive from the stack as TXQ is
1360          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1361          * pending WQEs.  SQ can safely reset the SQ.
1362          */
1363         if (mlx5e_sq_to_ready(sq, state))
1364                 return;
1365
1366         mlx5e_reset_txqsq_cc_pc(sq);
1367         sq->stats.recover++;
1368         recover->last_recover = jiffies;
1369         mlx5e_activate_txqsq(sq);
1370 }
1371
1372 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1373                             struct mlx5e_params *params,
1374                             struct mlx5e_sq_param *param,
1375                             struct mlx5e_icosq *sq)
1376 {
1377         struct mlx5e_create_sq_param csp = {};
1378         int err;
1379
1380         err = mlx5e_alloc_icosq(c, param, sq);
1381         if (err)
1382                 return err;
1383
1384         csp.cqn             = sq->cq.mcq.cqn;
1385         csp.wq_ctrl         = &sq->wq_ctrl;
1386         csp.min_inline_mode = params->tx_min_inline_mode;
1387         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1388         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1389         if (err)
1390                 goto err_free_icosq;
1391
1392         return 0;
1393
1394 err_free_icosq:
1395         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1396         mlx5e_free_icosq(sq);
1397
1398         return err;
1399 }
1400
1401 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1402 {
1403         struct mlx5e_channel *c = sq->channel;
1404
1405         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1406         napi_synchronize(&c->napi);
1407
1408         mlx5e_destroy_sq(c->mdev, sq->sqn);
1409         mlx5e_free_icosq(sq);
1410 }
1411
1412 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1413                             struct mlx5e_params *params,
1414                             struct mlx5e_sq_param *param,
1415                             struct mlx5e_xdpsq *sq)
1416 {
1417         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1418         struct mlx5e_create_sq_param csp = {};
1419         unsigned int inline_hdr_sz = 0;
1420         int err;
1421         int i;
1422
1423         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1424         if (err)
1425                 return err;
1426
1427         csp.tis_lst_sz      = 1;
1428         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1429         csp.cqn             = sq->cq.mcq.cqn;
1430         csp.wq_ctrl         = &sq->wq_ctrl;
1431         csp.min_inline_mode = sq->min_inline_mode;
1432         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1433         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1434         if (err)
1435                 goto err_free_xdpsq;
1436
1437         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1438                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1439                 ds_cnt++;
1440         }
1441
1442         /* Pre initialize fixed WQE fields */
1443         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1444                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1445                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1446                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1447                 struct mlx5_wqe_data_seg *dseg;
1448
1449                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1450                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1451
1452                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1453                 dseg->lkey = sq->mkey_be;
1454         }
1455
1456         return 0;
1457
1458 err_free_xdpsq:
1459         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1460         mlx5e_free_xdpsq(sq);
1461
1462         return err;
1463 }
1464
1465 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1466 {
1467         struct mlx5e_channel *c = sq->channel;
1468
1469         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1470         napi_synchronize(&c->napi);
1471
1472         mlx5e_destroy_sq(c->mdev, sq->sqn);
1473         mlx5e_free_xdpsq_descs(sq);
1474         mlx5e_free_xdpsq(sq);
1475 }
1476
1477 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1478                                  struct mlx5e_cq_param *param,
1479                                  struct mlx5e_cq *cq)
1480 {
1481         struct mlx5_core_cq *mcq = &cq->mcq;
1482         int eqn_not_used;
1483         unsigned int irqn;
1484         int err;
1485         u32 i;
1486
1487         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1488                                &cq->wq_ctrl);
1489         if (err)
1490                 return err;
1491
1492         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1493
1494         mcq->cqe_sz     = 64;
1495         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1496         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1497         *mcq->set_ci_db = 0;
1498         *mcq->arm_db    = 0;
1499         mcq->vector     = param->eq_ix;
1500         mcq->comp       = mlx5e_completion_event;
1501         mcq->event      = mlx5e_cq_error_event;
1502         mcq->irqn       = irqn;
1503
1504         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1505                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1506
1507                 cqe->op_own = 0xf1;
1508         }
1509
1510         cq->mdev = mdev;
1511
1512         return 0;
1513 }
1514
1515 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1516                           struct mlx5e_cq_param *param,
1517                           struct mlx5e_cq *cq)
1518 {
1519         struct mlx5_core_dev *mdev = c->priv->mdev;
1520         int err;
1521
1522         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1523         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1524         param->eq_ix   = c->ix;
1525
1526         err = mlx5e_alloc_cq_common(mdev, param, cq);
1527
1528         cq->napi    = &c->napi;
1529         cq->channel = c;
1530
1531         return err;
1532 }
1533
1534 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1535 {
1536         mlx5_cqwq_destroy(&cq->wq_ctrl);
1537 }
1538
1539 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1540 {
1541         struct mlx5_core_dev *mdev = cq->mdev;
1542         struct mlx5_core_cq *mcq = &cq->mcq;
1543
1544         void *in;
1545         void *cqc;
1546         int inlen;
1547         unsigned int irqn_not_used;
1548         int eqn;
1549         int err;
1550
1551         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1552                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1553         in = kvzalloc(inlen, GFP_KERNEL);
1554         if (!in)
1555                 return -ENOMEM;
1556
1557         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1558
1559         memcpy(cqc, param->cqc, sizeof(param->cqc));
1560
1561         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1562                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1563
1564         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1565
1566         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1567         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1568         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1569         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1570                                             MLX5_ADAPTER_PAGE_SHIFT);
1571         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1572
1573         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1574
1575         kvfree(in);
1576
1577         if (err)
1578                 return err;
1579
1580         mlx5e_cq_arm(cq);
1581
1582         return 0;
1583 }
1584
1585 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1586 {
1587         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1588 }
1589
1590 static int mlx5e_open_cq(struct mlx5e_channel *c,
1591                          struct net_dim_cq_moder moder,
1592                          struct mlx5e_cq_param *param,
1593                          struct mlx5e_cq *cq)
1594 {
1595         struct mlx5_core_dev *mdev = c->mdev;
1596         int err;
1597
1598         err = mlx5e_alloc_cq(c, param, cq);
1599         if (err)
1600                 return err;
1601
1602         err = mlx5e_create_cq(cq, param);
1603         if (err)
1604                 goto err_free_cq;
1605
1606         if (MLX5_CAP_GEN(mdev, cq_moderation))
1607                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1608         return 0;
1609
1610 err_free_cq:
1611         mlx5e_free_cq(cq);
1612
1613         return err;
1614 }
1615
1616 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1617 {
1618         mlx5e_destroy_cq(cq);
1619         mlx5e_free_cq(cq);
1620 }
1621
1622 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1623 {
1624         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1625 }
1626
1627 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1628                              struct mlx5e_params *params,
1629                              struct mlx5e_channel_param *cparam)
1630 {
1631         int err;
1632         int tc;
1633
1634         for (tc = 0; tc < c->num_tc; tc++) {
1635                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1636                                     &cparam->tx_cq, &c->sq[tc].cq);
1637                 if (err)
1638                         goto err_close_tx_cqs;
1639         }
1640
1641         return 0;
1642
1643 err_close_tx_cqs:
1644         for (tc--; tc >= 0; tc--)
1645                 mlx5e_close_cq(&c->sq[tc].cq);
1646
1647         return err;
1648 }
1649
1650 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1651 {
1652         int tc;
1653
1654         for (tc = 0; tc < c->num_tc; tc++)
1655                 mlx5e_close_cq(&c->sq[tc].cq);
1656 }
1657
1658 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1659                           struct mlx5e_params *params,
1660                           struct mlx5e_channel_param *cparam)
1661 {
1662         int err;
1663         int tc;
1664
1665         for (tc = 0; tc < params->num_tc; tc++) {
1666                 int txq_ix = c->ix + tc * params->num_channels;
1667
1668                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1669                                        params, &cparam->sq, &c->sq[tc]);
1670                 if (err)
1671                         goto err_close_sqs;
1672         }
1673
1674         return 0;
1675
1676 err_close_sqs:
1677         for (tc--; tc >= 0; tc--)
1678                 mlx5e_close_txqsq(&c->sq[tc]);
1679
1680         return err;
1681 }
1682
1683 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1684 {
1685         int tc;
1686
1687         for (tc = 0; tc < c->num_tc; tc++)
1688                 mlx5e_close_txqsq(&c->sq[tc]);
1689 }
1690
1691 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1692                                 struct mlx5e_txqsq *sq, u32 rate)
1693 {
1694         struct mlx5e_priv *priv = netdev_priv(dev);
1695         struct mlx5_core_dev *mdev = priv->mdev;
1696         struct mlx5e_modify_sq_param msp = {0};
1697         struct mlx5_rate_limit rl = {0};
1698         u16 rl_index = 0;
1699         int err;
1700
1701         if (rate == sq->rate_limit)
1702                 /* nothing to do */
1703                 return 0;
1704
1705         if (sq->rate_limit) {
1706                 rl.rate = sq->rate_limit;
1707                 /* remove current rl index to free space to next ones */
1708                 mlx5_rl_remove_rate(mdev, &rl);
1709         }
1710
1711         sq->rate_limit = 0;
1712
1713         if (rate) {
1714                 rl.rate = rate;
1715                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1716                 if (err) {
1717                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1718                                    rate, err);
1719                         return err;
1720                 }
1721         }
1722
1723         msp.curr_state = MLX5_SQC_STATE_RDY;
1724         msp.next_state = MLX5_SQC_STATE_RDY;
1725         msp.rl_index   = rl_index;
1726         msp.rl_update  = true;
1727         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1728         if (err) {
1729                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1730                            rate, err);
1731                 /* remove the rate from the table */
1732                 if (rate)
1733                         mlx5_rl_remove_rate(mdev, &rl);
1734                 return err;
1735         }
1736
1737         sq->rate_limit = rate;
1738         return 0;
1739 }
1740
1741 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1742 {
1743         struct mlx5e_priv *priv = netdev_priv(dev);
1744         struct mlx5_core_dev *mdev = priv->mdev;
1745         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1746         int err = 0;
1747
1748         if (!mlx5_rl_is_supported(mdev)) {
1749                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1750                 return -EINVAL;
1751         }
1752
1753         /* rate is given in Mb/sec, HW config is in Kb/sec */
1754         rate = rate << 10;
1755
1756         /* Check whether rate in valid range, 0 is always valid */
1757         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1758                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1759                 return -ERANGE;
1760         }
1761
1762         mutex_lock(&priv->state_lock);
1763         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1764                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1765         if (!err)
1766                 priv->tx_rates[index] = rate;
1767         mutex_unlock(&priv->state_lock);
1768
1769         return err;
1770 }
1771
1772 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1773                               struct mlx5e_params *params,
1774                               struct mlx5e_channel_param *cparam,
1775                               struct mlx5e_channel **cp)
1776 {
1777         struct net_dim_cq_moder icocq_moder = {0, 0};
1778         struct net_device *netdev = priv->netdev;
1779         int cpu = mlx5e_get_cpu(priv, ix);
1780         struct mlx5e_channel *c;
1781         unsigned int irq;
1782         int err;
1783         int eqn;
1784
1785         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1786         if (!c)
1787                 return -ENOMEM;
1788
1789         c->priv     = priv;
1790         c->mdev     = priv->mdev;
1791         c->tstamp   = &priv->tstamp;
1792         c->ix       = ix;
1793         c->cpu      = cpu;
1794         c->pdev     = &priv->mdev->pdev->dev;
1795         c->netdev   = priv->netdev;
1796         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1797         c->num_tc   = params->num_tc;
1798         c->xdp      = !!params->xdp_prog;
1799
1800         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1801         c->irq_desc = irq_to_desc(irq);
1802
1803         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1804
1805         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1806         if (err)
1807                 goto err_napi_del;
1808
1809         err = mlx5e_open_tx_cqs(c, params, cparam);
1810         if (err)
1811                 goto err_close_icosq_cq;
1812
1813         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1814         if (err)
1815                 goto err_close_tx_cqs;
1816
1817         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1818         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1819                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1820         if (err)
1821                 goto err_close_rx_cq;
1822
1823         napi_enable(&c->napi);
1824
1825         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1826         if (err)
1827                 goto err_disable_napi;
1828
1829         err = mlx5e_open_sqs(c, params, cparam);
1830         if (err)
1831                 goto err_close_icosq;
1832
1833         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1834         if (err)
1835                 goto err_close_sqs;
1836
1837         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1838         if (err)
1839                 goto err_close_xdp_sq;
1840
1841         *cp = c;
1842
1843         return 0;
1844 err_close_xdp_sq:
1845         if (c->xdp)
1846                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1847
1848 err_close_sqs:
1849         mlx5e_close_sqs(c);
1850
1851 err_close_icosq:
1852         mlx5e_close_icosq(&c->icosq);
1853
1854 err_disable_napi:
1855         napi_disable(&c->napi);
1856         if (c->xdp)
1857                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1858
1859 err_close_rx_cq:
1860         mlx5e_close_cq(&c->rq.cq);
1861
1862 err_close_tx_cqs:
1863         mlx5e_close_tx_cqs(c);
1864
1865 err_close_icosq_cq:
1866         mlx5e_close_cq(&c->icosq.cq);
1867
1868 err_napi_del:
1869         netif_napi_del(&c->napi);
1870         kfree(c);
1871
1872         return err;
1873 }
1874
1875 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1876 {
1877         int tc;
1878
1879         for (tc = 0; tc < c->num_tc; tc++)
1880                 mlx5e_activate_txqsq(&c->sq[tc]);
1881         mlx5e_activate_rq(&c->rq);
1882         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1883 }
1884
1885 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1886 {
1887         int tc;
1888
1889         mlx5e_deactivate_rq(&c->rq);
1890         for (tc = 0; tc < c->num_tc; tc++)
1891                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1892 }
1893
1894 static void mlx5e_close_channel(struct mlx5e_channel *c)
1895 {
1896         mlx5e_close_rq(&c->rq);
1897         if (c->xdp)
1898                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1899         mlx5e_close_sqs(c);
1900         mlx5e_close_icosq(&c->icosq);
1901         napi_disable(&c->napi);
1902         if (c->xdp)
1903                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1904         mlx5e_close_cq(&c->rq.cq);
1905         mlx5e_close_tx_cqs(c);
1906         mlx5e_close_cq(&c->icosq.cq);
1907         netif_napi_del(&c->napi);
1908
1909         kfree(c);
1910 }
1911
1912 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1913                                  struct mlx5e_params *params,
1914                                  struct mlx5e_rq_param *param)
1915 {
1916         struct mlx5_core_dev *mdev = priv->mdev;
1917         void *rqc = param->rqc;
1918         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1919
1920         switch (params->rq_wq_type) {
1921         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1922                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1923                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
1924                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
1925                 MLX5_SET(wq, wq, log_wqe_stride_size,
1926                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
1927                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
1928                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1929                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
1930                 break;
1931         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1932                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1933                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
1934         }
1935
1936         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1937         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1938         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
1939         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1940         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
1941         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
1942
1943         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1944         param->wq.linear = 1;
1945 }
1946
1947 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
1948                                       struct mlx5e_rq_param *param)
1949 {
1950         struct mlx5_core_dev *mdev = priv->mdev;
1951         void *rqc = param->rqc;
1952         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1953
1954         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1955         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1956         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
1957
1958         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1959 }
1960
1961 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1962                                         struct mlx5e_sq_param *param)
1963 {
1964         void *sqc = param->sqc;
1965         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1966
1967         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1968         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1969
1970         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1971 }
1972
1973 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1974                                  struct mlx5e_params *params,
1975                                  struct mlx5e_sq_param *param)
1976 {
1977         void *sqc = param->sqc;
1978         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1979
1980         mlx5e_build_sq_param_common(priv, param);
1981         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1982         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1983 }
1984
1985 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1986                                         struct mlx5e_cq_param *param)
1987 {
1988         void *cqc = param->cqc;
1989
1990         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1991 }
1992
1993 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1994                                     struct mlx5e_params *params,
1995                                     struct mlx5e_cq_param *param)
1996 {
1997         struct mlx5_core_dev *mdev = priv->mdev;
1998         void *cqc = param->cqc;
1999         u8 log_cq_size;
2000
2001         switch (params->rq_wq_type) {
2002         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2003                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2004                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2005                 break;
2006         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2007                 log_cq_size = params->log_rq_mtu_frames;
2008         }
2009
2010         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2011         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2012                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2013                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2014         }
2015
2016         mlx5e_build_common_cq_param(priv, param);
2017         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2018 }
2019
2020 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2021                                     struct mlx5e_params *params,
2022                                     struct mlx5e_cq_param *param)
2023 {
2024         void *cqc = param->cqc;
2025
2026         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2027
2028         mlx5e_build_common_cq_param(priv, param);
2029         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2030 }
2031
2032 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2033                                      u8 log_wq_size,
2034                                      struct mlx5e_cq_param *param)
2035 {
2036         void *cqc = param->cqc;
2037
2038         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2039
2040         mlx5e_build_common_cq_param(priv, param);
2041
2042         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2043 }
2044
2045 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2046                                     u8 log_wq_size,
2047                                     struct mlx5e_sq_param *param)
2048 {
2049         void *sqc = param->sqc;
2050         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2051
2052         mlx5e_build_sq_param_common(priv, param);
2053
2054         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2055         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2056 }
2057
2058 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2059                                     struct mlx5e_params *params,
2060                                     struct mlx5e_sq_param *param)
2061 {
2062         void *sqc = param->sqc;
2063         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2064
2065         mlx5e_build_sq_param_common(priv, param);
2066         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2067 }
2068
2069 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2070                                       struct mlx5e_params *params,
2071                                       struct mlx5e_channel_param *cparam)
2072 {
2073         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2074
2075         mlx5e_build_rq_param(priv, params, &cparam->rq);
2076         mlx5e_build_sq_param(priv, params, &cparam->sq);
2077         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2078         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2079         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2080         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2081         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2082 }
2083
2084 int mlx5e_open_channels(struct mlx5e_priv *priv,
2085                         struct mlx5e_channels *chs)
2086 {
2087         struct mlx5e_channel_param *cparam;
2088         int err = -ENOMEM;
2089         int i;
2090
2091         chs->num = chs->params.num_channels;
2092
2093         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2094         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2095         if (!chs->c || !cparam)
2096                 goto err_free;
2097
2098         mlx5e_build_channel_param(priv, &chs->params, cparam);
2099         for (i = 0; i < chs->num; i++) {
2100                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2101                 if (err)
2102                         goto err_close_channels;
2103         }
2104
2105         kfree(cparam);
2106         return 0;
2107
2108 err_close_channels:
2109         for (i--; i >= 0; i--)
2110                 mlx5e_close_channel(chs->c[i]);
2111
2112 err_free:
2113         kfree(chs->c);
2114         kfree(cparam);
2115         chs->num = 0;
2116         return err;
2117 }
2118
2119 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2120 {
2121         int i;
2122
2123         for (i = 0; i < chs->num; i++)
2124                 mlx5e_activate_channel(chs->c[i]);
2125 }
2126
2127 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2128 {
2129         int err = 0;
2130         int i;
2131
2132         for (i = 0; i < chs->num; i++) {
2133                 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2134                 if (err)
2135                         break;
2136         }
2137
2138         return err;
2139 }
2140
2141 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2142 {
2143         int i;
2144
2145         for (i = 0; i < chs->num; i++)
2146                 mlx5e_deactivate_channel(chs->c[i]);
2147 }
2148
2149 void mlx5e_close_channels(struct mlx5e_channels *chs)
2150 {
2151         int i;
2152
2153         for (i = 0; i < chs->num; i++)
2154                 mlx5e_close_channel(chs->c[i]);
2155
2156         kfree(chs->c);
2157         chs->num = 0;
2158 }
2159
2160 static int
2161 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2162 {
2163         struct mlx5_core_dev *mdev = priv->mdev;
2164         void *rqtc;
2165         int inlen;
2166         int err;
2167         u32 *in;
2168         int i;
2169
2170         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2171         in = kvzalloc(inlen, GFP_KERNEL);
2172         if (!in)
2173                 return -ENOMEM;
2174
2175         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2176
2177         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2178         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2179
2180         for (i = 0; i < sz; i++)
2181                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2182
2183         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2184         if (!err)
2185                 rqt->enabled = true;
2186
2187         kvfree(in);
2188         return err;
2189 }
2190
2191 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2192 {
2193         rqt->enabled = false;
2194         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2195 }
2196
2197 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2198 {
2199         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2200         int err;
2201
2202         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2203         if (err)
2204                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2205         return err;
2206 }
2207
2208 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2209 {
2210         struct mlx5e_rqt *rqt;
2211         int err;
2212         int ix;
2213
2214         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2215                 rqt = &priv->direct_tir[ix].rqt;
2216                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2217                 if (err)
2218                         goto err_destroy_rqts;
2219         }
2220
2221         return 0;
2222
2223 err_destroy_rqts:
2224         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2225         for (ix--; ix >= 0; ix--)
2226                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2227
2228         return err;
2229 }
2230
2231 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2232 {
2233         int i;
2234
2235         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2236                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2237 }
2238
2239 static int mlx5e_rx_hash_fn(int hfunc)
2240 {
2241         return (hfunc == ETH_RSS_HASH_TOP) ?
2242                MLX5_RX_HASH_FN_TOEPLITZ :
2243                MLX5_RX_HASH_FN_INVERTED_XOR8;
2244 }
2245
2246 int mlx5e_bits_invert(unsigned long a, int size)
2247 {
2248         int inv = 0;
2249         int i;
2250
2251         for (i = 0; i < size; i++)
2252                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2253
2254         return inv;
2255 }
2256
2257 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2258                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2259 {
2260         int i;
2261
2262         for (i = 0; i < sz; i++) {
2263                 u32 rqn;
2264
2265                 if (rrp.is_rss) {
2266                         int ix = i;
2267
2268                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2269                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2270
2271                         ix = priv->channels.params.indirection_rqt[ix];
2272                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2273                 } else {
2274                         rqn = rrp.rqn;
2275                 }
2276                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2277         }
2278 }
2279
2280 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2281                        struct mlx5e_redirect_rqt_param rrp)
2282 {
2283         struct mlx5_core_dev *mdev = priv->mdev;
2284         void *rqtc;
2285         int inlen;
2286         u32 *in;
2287         int err;
2288
2289         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2290         in = kvzalloc(inlen, GFP_KERNEL);
2291         if (!in)
2292                 return -ENOMEM;
2293
2294         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2295
2296         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2297         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2298         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2299         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2300
2301         kvfree(in);
2302         return err;
2303 }
2304
2305 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2306                                 struct mlx5e_redirect_rqt_param rrp)
2307 {
2308         if (!rrp.is_rss)
2309                 return rrp.rqn;
2310
2311         if (ix >= rrp.rss.channels->num)
2312                 return priv->drop_rq.rqn;
2313
2314         return rrp.rss.channels->c[ix]->rq.rqn;
2315 }
2316
2317 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2318                                 struct mlx5e_redirect_rqt_param rrp)
2319 {
2320         u32 rqtn;
2321         int ix;
2322
2323         if (priv->indir_rqt.enabled) {
2324                 /* RSS RQ table */
2325                 rqtn = priv->indir_rqt.rqtn;
2326                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2327         }
2328
2329         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2330                 struct mlx5e_redirect_rqt_param direct_rrp = {
2331                         .is_rss = false,
2332                         {
2333                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2334                         },
2335                 };
2336
2337                 /* Direct RQ Tables */
2338                 if (!priv->direct_tir[ix].rqt.enabled)
2339                         continue;
2340
2341                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2342                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2343         }
2344 }
2345
2346 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2347                                             struct mlx5e_channels *chs)
2348 {
2349         struct mlx5e_redirect_rqt_param rrp = {
2350                 .is_rss        = true,
2351                 {
2352                         .rss = {
2353                                 .channels  = chs,
2354                                 .hfunc     = chs->params.rss_hfunc,
2355                         }
2356                 },
2357         };
2358
2359         mlx5e_redirect_rqts(priv, rrp);
2360 }
2361
2362 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2363 {
2364         struct mlx5e_redirect_rqt_param drop_rrp = {
2365                 .is_rss = false,
2366                 {
2367                         .rqn = priv->drop_rq.rqn,
2368                 },
2369         };
2370
2371         mlx5e_redirect_rqts(priv, drop_rrp);
2372 }
2373
2374 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2375 {
2376         if (!params->lro_en)
2377                 return;
2378
2379 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2380
2381         MLX5_SET(tirc, tirc, lro_enable_mask,
2382                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2383                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2384         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2385                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2386         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2387 }
2388
2389 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2390                                     enum mlx5e_traffic_types tt,
2391                                     void *tirc, bool inner)
2392 {
2393         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2394                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2395
2396 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2397                                  MLX5_HASH_FIELD_SEL_DST_IP)
2398
2399 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2400                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2401                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2402                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2403
2404 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2405                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2406                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2407
2408         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2409         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2410                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2411                                              rx_hash_toeplitz_key);
2412                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2413                                                rx_hash_toeplitz_key);
2414
2415                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2416                 memcpy(rss_key, params->toeplitz_hash_key, len);
2417         }
2418
2419         switch (tt) {
2420         case MLX5E_TT_IPV4_TCP:
2421                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2422                          MLX5_L3_PROT_TYPE_IPV4);
2423                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2424                          MLX5_L4_PROT_TYPE_TCP);
2425                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2426                          MLX5_HASH_IP_L4PORTS);
2427                 break;
2428
2429         case MLX5E_TT_IPV6_TCP:
2430                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2431                          MLX5_L3_PROT_TYPE_IPV6);
2432                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2433                          MLX5_L4_PROT_TYPE_TCP);
2434                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2435                          MLX5_HASH_IP_L4PORTS);
2436                 break;
2437
2438         case MLX5E_TT_IPV4_UDP:
2439                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2440                          MLX5_L3_PROT_TYPE_IPV4);
2441                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2442                          MLX5_L4_PROT_TYPE_UDP);
2443                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2444                          MLX5_HASH_IP_L4PORTS);
2445                 break;
2446
2447         case MLX5E_TT_IPV6_UDP:
2448                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2449                          MLX5_L3_PROT_TYPE_IPV6);
2450                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2451                          MLX5_L4_PROT_TYPE_UDP);
2452                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2453                          MLX5_HASH_IP_L4PORTS);
2454                 break;
2455
2456         case MLX5E_TT_IPV4_IPSEC_AH:
2457                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2458                          MLX5_L3_PROT_TYPE_IPV4);
2459                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2460                          MLX5_HASH_IP_IPSEC_SPI);
2461                 break;
2462
2463         case MLX5E_TT_IPV6_IPSEC_AH:
2464                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2465                          MLX5_L3_PROT_TYPE_IPV6);
2466                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2467                          MLX5_HASH_IP_IPSEC_SPI);
2468                 break;
2469
2470         case MLX5E_TT_IPV4_IPSEC_ESP:
2471                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2472                          MLX5_L3_PROT_TYPE_IPV4);
2473                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2474                          MLX5_HASH_IP_IPSEC_SPI);
2475                 break;
2476
2477         case MLX5E_TT_IPV6_IPSEC_ESP:
2478                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2479                          MLX5_L3_PROT_TYPE_IPV6);
2480                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2481                          MLX5_HASH_IP_IPSEC_SPI);
2482                 break;
2483
2484         case MLX5E_TT_IPV4:
2485                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2486                          MLX5_L3_PROT_TYPE_IPV4);
2487                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2488                          MLX5_HASH_IP);
2489                 break;
2490
2491         case MLX5E_TT_IPV6:
2492                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2493                          MLX5_L3_PROT_TYPE_IPV6);
2494                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2495                          MLX5_HASH_IP);
2496                 break;
2497         default:
2498                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2499         }
2500 }
2501
2502 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2503 {
2504         struct mlx5_core_dev *mdev = priv->mdev;
2505
2506         void *in;
2507         void *tirc;
2508         int inlen;
2509         int err;
2510         int tt;
2511         int ix;
2512
2513         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2514         in = kvzalloc(inlen, GFP_KERNEL);
2515         if (!in)
2516                 return -ENOMEM;
2517
2518         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2519         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2520
2521         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2522
2523         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2524                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2525                                            inlen);
2526                 if (err)
2527                         goto free_in;
2528         }
2529
2530         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2531                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2532                                            in, inlen);
2533                 if (err)
2534                         goto free_in;
2535         }
2536
2537 free_in:
2538         kvfree(in);
2539
2540         return err;
2541 }
2542
2543 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2544                                             enum mlx5e_traffic_types tt,
2545                                             u32 *tirc)
2546 {
2547         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2548
2549         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2550
2551         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2552         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2553         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2554
2555         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2556 }
2557
2558 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2559                          struct mlx5e_params *params, u16 mtu)
2560 {
2561         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2562         int err;
2563
2564         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2565         if (err)
2566                 return err;
2567
2568         /* Update vport context MTU */
2569         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2570         return 0;
2571 }
2572
2573 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2574                             struct mlx5e_params *params, u16 *mtu)
2575 {
2576         u16 hw_mtu = 0;
2577         int err;
2578
2579         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2580         if (err || !hw_mtu) /* fallback to port oper mtu */
2581                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2582
2583         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2584 }
2585
2586 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2587 {
2588         struct mlx5e_params *params = &priv->channels.params;
2589         struct net_device *netdev = priv->netdev;
2590         struct mlx5_core_dev *mdev = priv->mdev;
2591         u16 mtu;
2592         int err;
2593
2594         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2595         if (err)
2596                 return err;
2597
2598         mlx5e_query_mtu(mdev, params, &mtu);
2599         if (mtu != params->sw_mtu)
2600                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2601                             __func__, mtu, params->sw_mtu);
2602
2603         params->sw_mtu = mtu;
2604         return 0;
2605 }
2606
2607 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2608 {
2609         struct mlx5e_priv *priv = netdev_priv(netdev);
2610         int nch = priv->channels.params.num_channels;
2611         int ntc = priv->channels.params.num_tc;
2612         int tc;
2613
2614         netdev_reset_tc(netdev);
2615
2616         if (ntc == 1)
2617                 return;
2618
2619         netdev_set_num_tc(netdev, ntc);
2620
2621         /* Map netdev TCs to offset 0
2622          * We have our own UP to TXQ mapping for QoS
2623          */
2624         for (tc = 0; tc < ntc; tc++)
2625                 netdev_set_tc_queue(netdev, tc, nch, 0);
2626 }
2627
2628 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2629 {
2630         struct mlx5e_channel *c;
2631         struct mlx5e_txqsq *sq;
2632         int i, tc;
2633
2634         for (i = 0; i < priv->channels.num; i++)
2635                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2636                         priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2637
2638         for (i = 0; i < priv->channels.num; i++) {
2639                 c = priv->channels.c[i];
2640                 for (tc = 0; tc < c->num_tc; tc++) {
2641                         sq = &c->sq[tc];
2642                         priv->txq2sq[sq->txq_ix] = sq;
2643                 }
2644         }
2645 }
2646
2647 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2648 {
2649         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2650         struct net_device *netdev = priv->netdev;
2651
2652         mlx5e_netdev_set_tcs(netdev);
2653         netif_set_real_num_tx_queues(netdev, num_txqs);
2654         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2655
2656         mlx5e_build_channels_tx_maps(priv);
2657         mlx5e_activate_channels(&priv->channels);
2658         netif_tx_start_all_queues(priv->netdev);
2659
2660         if (MLX5_VPORT_MANAGER(priv->mdev))
2661                 mlx5e_add_sqs_fwd_rules(priv);
2662
2663         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2664         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2665 }
2666
2667 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2668 {
2669         mlx5e_redirect_rqts_to_drop(priv);
2670
2671         if (MLX5_VPORT_MANAGER(priv->mdev))
2672                 mlx5e_remove_sqs_fwd_rules(priv);
2673
2674         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2675          * polling for inactive tx queues.
2676          */
2677         netif_tx_stop_all_queues(priv->netdev);
2678         netif_tx_disable(priv->netdev);
2679         mlx5e_deactivate_channels(&priv->channels);
2680 }
2681
2682 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2683                                 struct mlx5e_channels *new_chs,
2684                                 mlx5e_fp_hw_modify hw_modify)
2685 {
2686         struct net_device *netdev = priv->netdev;
2687         int new_num_txqs;
2688         int carrier_ok;
2689         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2690
2691         carrier_ok = netif_carrier_ok(netdev);
2692         netif_carrier_off(netdev);
2693
2694         if (new_num_txqs < netdev->real_num_tx_queues)
2695                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2696
2697         mlx5e_deactivate_priv_channels(priv);
2698         mlx5e_close_channels(&priv->channels);
2699
2700         priv->channels = *new_chs;
2701
2702         /* New channels are ready to roll, modify HW settings if needed */
2703         if (hw_modify)
2704                 hw_modify(priv);
2705
2706         mlx5e_refresh_tirs(priv, false);
2707         mlx5e_activate_priv_channels(priv);
2708
2709         /* return carrier back if needed */
2710         if (carrier_ok)
2711                 netif_carrier_on(netdev);
2712 }
2713
2714 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2715 {
2716         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2717         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2718 }
2719
2720 int mlx5e_open_locked(struct net_device *netdev)
2721 {
2722         struct mlx5e_priv *priv = netdev_priv(netdev);
2723         int err;
2724
2725         set_bit(MLX5E_STATE_OPENED, &priv->state);
2726
2727         err = mlx5e_open_channels(priv, &priv->channels);
2728         if (err)
2729                 goto err_clear_state_opened_flag;
2730
2731         mlx5e_refresh_tirs(priv, false);
2732         mlx5e_activate_priv_channels(priv);
2733         if (priv->profile->update_carrier)
2734                 priv->profile->update_carrier(priv);
2735
2736         if (priv->profile->update_stats)
2737                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2738
2739         return 0;
2740
2741 err_clear_state_opened_flag:
2742         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2743         return err;
2744 }
2745
2746 int mlx5e_open(struct net_device *netdev)
2747 {
2748         struct mlx5e_priv *priv = netdev_priv(netdev);
2749         int err;
2750
2751         mutex_lock(&priv->state_lock);
2752         err = mlx5e_open_locked(netdev);
2753         if (!err)
2754                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2755         mutex_unlock(&priv->state_lock);
2756
2757         if (mlx5e_vxlan_allowed(priv->mdev))
2758                 udp_tunnel_get_rx_info(netdev);
2759
2760         return err;
2761 }
2762
2763 int mlx5e_close_locked(struct net_device *netdev)
2764 {
2765         struct mlx5e_priv *priv = netdev_priv(netdev);
2766
2767         /* May already be CLOSED in case a previous configuration operation
2768          * (e.g RX/TX queue size change) that involves close&open failed.
2769          */
2770         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2771                 return 0;
2772
2773         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2774
2775         netif_carrier_off(priv->netdev);
2776         mlx5e_deactivate_priv_channels(priv);
2777         mlx5e_close_channels(&priv->channels);
2778
2779         return 0;
2780 }
2781
2782 int mlx5e_close(struct net_device *netdev)
2783 {
2784         struct mlx5e_priv *priv = netdev_priv(netdev);
2785         int err;
2786
2787         if (!netif_device_present(netdev))
2788                 return -ENODEV;
2789
2790         mutex_lock(&priv->state_lock);
2791         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2792         err = mlx5e_close_locked(netdev);
2793         mutex_unlock(&priv->state_lock);
2794
2795         return err;
2796 }
2797
2798 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2799                                struct mlx5e_rq *rq,
2800                                struct mlx5e_rq_param *param)
2801 {
2802         void *rqc = param->rqc;
2803         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2804         int err;
2805
2806         param->wq.db_numa_node = param->wq.buf_numa_node;
2807
2808         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2809                                 &rq->wq_ctrl);
2810         if (err)
2811                 return err;
2812
2813         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2814         xdp_rxq_info_unused(&rq->xdp_rxq);
2815
2816         rq->mdev = mdev;
2817
2818         return 0;
2819 }
2820
2821 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2822                                struct mlx5e_cq *cq,
2823                                struct mlx5e_cq_param *param)
2824 {
2825         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2826         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
2827
2828         return mlx5e_alloc_cq_common(mdev, param, cq);
2829 }
2830
2831 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2832                               struct mlx5e_rq *drop_rq)
2833 {
2834         struct mlx5_core_dev *mdev = priv->mdev;
2835         struct mlx5e_cq_param cq_param = {};
2836         struct mlx5e_rq_param rq_param = {};
2837         struct mlx5e_cq *cq = &drop_rq->cq;
2838         int err;
2839
2840         mlx5e_build_drop_rq_param(priv, &rq_param);
2841
2842         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2843         if (err)
2844                 return err;
2845
2846         err = mlx5e_create_cq(cq, &cq_param);
2847         if (err)
2848                 goto err_free_cq;
2849
2850         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2851         if (err)
2852                 goto err_destroy_cq;
2853
2854         err = mlx5e_create_rq(drop_rq, &rq_param);
2855         if (err)
2856                 goto err_free_rq;
2857
2858         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2859         if (err)
2860                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2861
2862         return 0;
2863
2864 err_free_rq:
2865         mlx5e_free_rq(drop_rq);
2866
2867 err_destroy_cq:
2868         mlx5e_destroy_cq(cq);
2869
2870 err_free_cq:
2871         mlx5e_free_cq(cq);
2872
2873         return err;
2874 }
2875
2876 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2877 {
2878         mlx5e_destroy_rq(drop_rq);
2879         mlx5e_free_rq(drop_rq);
2880         mlx5e_destroy_cq(&drop_rq->cq);
2881         mlx5e_free_cq(&drop_rq->cq);
2882 }
2883
2884 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2885                      u32 underlay_qpn, u32 *tisn)
2886 {
2887         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2888         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2889
2890         MLX5_SET(tisc, tisc, prio, tc << 1);
2891         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2892         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2893
2894         if (mlx5_lag_is_lacp_owner(mdev))
2895                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2896
2897         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2898 }
2899
2900 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2901 {
2902         mlx5_core_destroy_tis(mdev, tisn);
2903 }
2904
2905 int mlx5e_create_tises(struct mlx5e_priv *priv)
2906 {
2907         int err;
2908         int tc;
2909
2910         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2911                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2912                 if (err)
2913                         goto err_close_tises;
2914         }
2915
2916         return 0;
2917
2918 err_close_tises:
2919         for (tc--; tc >= 0; tc--)
2920                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2921
2922         return err;
2923 }
2924
2925 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2926 {
2927         int tc;
2928
2929         for (tc = 0; tc < priv->profile->max_tc; tc++)
2930                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2931 }
2932
2933 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2934                                       enum mlx5e_traffic_types tt,
2935                                       u32 *tirc)
2936 {
2937         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2938
2939         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2940
2941         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2942         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2943         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2944 }
2945
2946 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2947 {
2948         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2949
2950         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2951
2952         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2953         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2954         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2955 }
2956
2957 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2958 {
2959         struct mlx5e_tir *tir;
2960         void *tirc;
2961         int inlen;
2962         int i = 0;
2963         int err;
2964         u32 *in;
2965         int tt;
2966
2967         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2968         in = kvzalloc(inlen, GFP_KERNEL);
2969         if (!in)
2970                 return -ENOMEM;
2971
2972         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2973                 memset(in, 0, inlen);
2974                 tir = &priv->indir_tir[tt];
2975                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2976                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2977                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2978                 if (err) {
2979                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2980                         goto err_destroy_inner_tirs;
2981                 }
2982         }
2983
2984         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2985                 goto out;
2986
2987         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2988                 memset(in, 0, inlen);
2989                 tir = &priv->inner_indir_tir[i];
2990                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2991                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2992                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2993                 if (err) {
2994                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2995                         goto err_destroy_inner_tirs;
2996                 }
2997         }
2998
2999 out:
3000         kvfree(in);
3001
3002         return 0;
3003
3004 err_destroy_inner_tirs:
3005         for (i--; i >= 0; i--)
3006                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3007
3008         for (tt--; tt >= 0; tt--)
3009                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3010
3011         kvfree(in);
3012
3013         return err;
3014 }
3015
3016 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3017 {
3018         int nch = priv->profile->max_nch(priv->mdev);
3019         struct mlx5e_tir *tir;
3020         void *tirc;
3021         int inlen;
3022         int err;
3023         u32 *in;
3024         int ix;
3025
3026         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3027         in = kvzalloc(inlen, GFP_KERNEL);
3028         if (!in)
3029                 return -ENOMEM;
3030
3031         for (ix = 0; ix < nch; ix++) {
3032                 memset(in, 0, inlen);
3033                 tir = &priv->direct_tir[ix];
3034                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3035                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3036                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3037                 if (err)
3038                         goto err_destroy_ch_tirs;
3039         }
3040
3041         kvfree(in);
3042
3043         return 0;
3044
3045 err_destroy_ch_tirs:
3046         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3047         for (ix--; ix >= 0; ix--)
3048                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3049
3050         kvfree(in);
3051
3052         return err;
3053 }
3054
3055 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3056 {
3057         int i;
3058
3059         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3060                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3061
3062         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3063                 return;
3064
3065         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3066                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3067 }
3068
3069 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3070 {
3071         int nch = priv->profile->max_nch(priv->mdev);
3072         int i;
3073
3074         for (i = 0; i < nch; i++)
3075                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3076 }
3077
3078 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3079 {
3080         int err = 0;
3081         int i;
3082
3083         for (i = 0; i < chs->num; i++) {
3084                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3085                 if (err)
3086                         return err;
3087         }
3088
3089         return 0;
3090 }
3091
3092 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3093 {
3094         int err = 0;
3095         int i;
3096
3097         for (i = 0; i < chs->num; i++) {
3098                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3099                 if (err)
3100                         return err;
3101         }
3102
3103         return 0;
3104 }
3105
3106 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3107                                  struct tc_mqprio_qopt *mqprio)
3108 {
3109         struct mlx5e_priv *priv = netdev_priv(netdev);
3110         struct mlx5e_channels new_channels = {};
3111         u8 tc = mqprio->num_tc;
3112         int err = 0;
3113
3114         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3115
3116         if (tc && tc != MLX5E_MAX_NUM_TC)
3117                 return -EINVAL;
3118
3119         mutex_lock(&priv->state_lock);
3120
3121         new_channels.params = priv->channels.params;
3122         new_channels.params.num_tc = tc ? tc : 1;
3123
3124         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3125                 priv->channels.params = new_channels.params;
3126                 goto out;
3127         }
3128
3129         err = mlx5e_open_channels(priv, &new_channels);
3130         if (err)
3131                 goto out;
3132
3133         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3134 out:
3135         mutex_unlock(&priv->state_lock);
3136         return err;
3137 }
3138
3139 #ifdef CONFIG_MLX5_ESWITCH
3140 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3141                                      struct tc_cls_flower_offload *cls_flower)
3142 {
3143         switch (cls_flower->command) {
3144         case TC_CLSFLOWER_REPLACE:
3145                 return mlx5e_configure_flower(priv, cls_flower);
3146         case TC_CLSFLOWER_DESTROY:
3147                 return mlx5e_delete_flower(priv, cls_flower);
3148         case TC_CLSFLOWER_STATS:
3149                 return mlx5e_stats_flower(priv, cls_flower);
3150         default:
3151                 return -EOPNOTSUPP;
3152         }
3153 }
3154
3155 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3156                             void *cb_priv)
3157 {
3158         struct mlx5e_priv *priv = cb_priv;
3159
3160         if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3161                 return -EOPNOTSUPP;
3162
3163         switch (type) {
3164         case TC_SETUP_CLSFLOWER:
3165                 return mlx5e_setup_tc_cls_flower(priv, type_data);
3166         default:
3167                 return -EOPNOTSUPP;
3168         }
3169 }
3170
3171 static int mlx5e_setup_tc_block(struct net_device *dev,
3172                                 struct tc_block_offload *f)
3173 {
3174         struct mlx5e_priv *priv = netdev_priv(dev);
3175
3176         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3177                 return -EOPNOTSUPP;
3178
3179         switch (f->command) {
3180         case TC_BLOCK_BIND:
3181                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3182                                              priv, priv);
3183         case TC_BLOCK_UNBIND:
3184                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3185                                         priv);
3186                 return 0;
3187         default:
3188                 return -EOPNOTSUPP;
3189         }
3190 }
3191 #endif
3192
3193 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3194                           void *type_data)
3195 {
3196         switch (type) {
3197 #ifdef CONFIG_MLX5_ESWITCH
3198         case TC_SETUP_BLOCK:
3199                 return mlx5e_setup_tc_block(dev, type_data);
3200 #endif
3201         case TC_SETUP_QDISC_MQPRIO:
3202                 return mlx5e_setup_tc_mqprio(dev, type_data);
3203         default:
3204                 return -EOPNOTSUPP;
3205         }
3206 }
3207
3208 static void
3209 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3210 {
3211         struct mlx5e_priv *priv = netdev_priv(dev);
3212         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3213         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3214         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3215
3216         if (mlx5e_is_uplink_rep(priv)) {
3217                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3218                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3219                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3220                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3221         } else {
3222                 stats->rx_packets = sstats->rx_packets;
3223                 stats->rx_bytes   = sstats->rx_bytes;
3224                 stats->tx_packets = sstats->tx_packets;
3225                 stats->tx_bytes   = sstats->tx_bytes;
3226                 stats->tx_dropped = sstats->tx_queue_dropped;
3227         }
3228
3229         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3230
3231         stats->rx_length_errors =
3232                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3233                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3234                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3235         stats->rx_crc_errors =
3236                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3237         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3238         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3239         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3240                            stats->rx_frame_errors;
3241         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3242
3243         /* vport multicast also counts packets that are dropped due to steering
3244          * or rx out of buffer
3245          */
3246         stats->multicast =
3247                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3248 }
3249
3250 static void mlx5e_set_rx_mode(struct net_device *dev)
3251 {
3252         struct mlx5e_priv *priv = netdev_priv(dev);
3253
3254         queue_work(priv->wq, &priv->set_rx_mode_work);
3255 }
3256
3257 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3258 {
3259         struct mlx5e_priv *priv = netdev_priv(netdev);
3260         struct sockaddr *saddr = addr;
3261
3262         if (!is_valid_ether_addr(saddr->sa_data))
3263                 return -EADDRNOTAVAIL;
3264
3265         netif_addr_lock_bh(netdev);
3266         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3267         netif_addr_unlock_bh(netdev);
3268
3269         queue_work(priv->wq, &priv->set_rx_mode_work);
3270
3271         return 0;
3272 }
3273
3274 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3275         do {                                            \
3276                 if (enable)                             \
3277                         *features |= feature;           \
3278                 else                                    \
3279                         *features &= ~feature;          \
3280         } while (0)
3281
3282 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3283
3284 static int set_feature_lro(struct net_device *netdev, bool enable)
3285 {
3286         struct mlx5e_priv *priv = netdev_priv(netdev);
3287         struct mlx5_core_dev *mdev = priv->mdev;
3288         struct mlx5e_channels new_channels = {};
3289         struct mlx5e_params *old_params;
3290         int err = 0;
3291         bool reset;
3292
3293         mutex_lock(&priv->state_lock);
3294
3295         old_params = &priv->channels.params;
3296         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3297
3298         new_channels.params = *old_params;
3299         new_channels.params.lro_en = enable;
3300
3301         if (old_params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) {
3302                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3303                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3304                         reset = false;
3305         }
3306
3307         if (!reset) {
3308                 *old_params = new_channels.params;
3309                 err = mlx5e_modify_tirs_lro(priv);
3310                 goto out;
3311         }
3312
3313         err = mlx5e_open_channels(priv, &new_channels);
3314         if (err)
3315                 goto out;
3316
3317         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3318 out:
3319         mutex_unlock(&priv->state_lock);
3320         return err;
3321 }
3322
3323 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3324 {
3325         struct mlx5e_priv *priv = netdev_priv(netdev);
3326
3327         if (enable)
3328                 mlx5e_enable_cvlan_filter(priv);
3329         else
3330                 mlx5e_disable_cvlan_filter(priv);
3331
3332         return 0;
3333 }
3334
3335 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3336 {
3337         struct mlx5e_priv *priv = netdev_priv(netdev);
3338
3339         if (!enable && mlx5e_tc_num_filters(priv)) {
3340                 netdev_err(netdev,
3341                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3342                 return -EINVAL;
3343         }
3344
3345         return 0;
3346 }
3347
3348 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3349 {
3350         struct mlx5e_priv *priv = netdev_priv(netdev);
3351         struct mlx5_core_dev *mdev = priv->mdev;
3352
3353         return mlx5_set_port_fcs(mdev, !enable);
3354 }
3355
3356 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3357 {
3358         struct mlx5e_priv *priv = netdev_priv(netdev);
3359         int err;
3360
3361         mutex_lock(&priv->state_lock);
3362
3363         priv->channels.params.scatter_fcs_en = enable;
3364         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3365         if (err)
3366                 priv->channels.params.scatter_fcs_en = !enable;
3367
3368         mutex_unlock(&priv->state_lock);
3369
3370         return err;
3371 }
3372
3373 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3374 {
3375         struct mlx5e_priv *priv = netdev_priv(netdev);
3376         int err = 0;
3377
3378         mutex_lock(&priv->state_lock);
3379
3380         priv->channels.params.vlan_strip_disable = !enable;
3381         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3382                 goto unlock;
3383
3384         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3385         if (err)
3386                 priv->channels.params.vlan_strip_disable = enable;
3387
3388 unlock:
3389         mutex_unlock(&priv->state_lock);
3390
3391         return err;
3392 }
3393
3394 #ifdef CONFIG_RFS_ACCEL
3395 static int set_feature_arfs(struct net_device *netdev, bool enable)
3396 {
3397         struct mlx5e_priv *priv = netdev_priv(netdev);
3398         int err;
3399
3400         if (enable)
3401                 err = mlx5e_arfs_enable(priv);
3402         else
3403                 err = mlx5e_arfs_disable(priv);
3404
3405         return err;
3406 }
3407 #endif
3408
3409 static int mlx5e_handle_feature(struct net_device *netdev,
3410                                 netdev_features_t *features,
3411                                 netdev_features_t wanted_features,
3412                                 netdev_features_t feature,
3413                                 mlx5e_feature_handler feature_handler)
3414 {
3415         netdev_features_t changes = wanted_features ^ netdev->features;
3416         bool enable = !!(wanted_features & feature);
3417         int err;
3418
3419         if (!(changes & feature))
3420                 return 0;
3421
3422         err = feature_handler(netdev, enable);
3423         if (err) {
3424                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3425                            enable ? "Enable" : "Disable", &feature, err);
3426                 return err;
3427         }
3428
3429         MLX5E_SET_FEATURE(features, feature, enable);
3430         return 0;
3431 }
3432
3433 static int mlx5e_set_features(struct net_device *netdev,
3434                               netdev_features_t features)
3435 {
3436         netdev_features_t oper_features = netdev->features;
3437         int err = 0;
3438
3439 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3440         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3441
3442         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3443         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3444                                     set_feature_cvlan_filter);
3445         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3446         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3447         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3448         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3449 #ifdef CONFIG_RFS_ACCEL
3450         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3451 #endif
3452
3453         if (err) {
3454                 netdev->features = oper_features;
3455                 return -EINVAL;
3456         }
3457
3458         return 0;
3459 }
3460
3461 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3462                                             netdev_features_t features)
3463 {
3464         struct mlx5e_priv *priv = netdev_priv(netdev);
3465
3466         mutex_lock(&priv->state_lock);
3467         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3468                 /* HW strips the outer C-tag header, this is a problem
3469                  * for S-tag traffic.
3470                  */
3471                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3472                 if (!priv->channels.params.vlan_strip_disable)
3473                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3474         }
3475         mutex_unlock(&priv->state_lock);
3476
3477         return features;
3478 }
3479
3480 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3481 {
3482         struct mlx5e_priv *priv = netdev_priv(netdev);
3483         struct mlx5e_channels new_channels = {};
3484         struct mlx5e_params *params;
3485         int err = 0;
3486         bool reset;
3487
3488         mutex_lock(&priv->state_lock);
3489
3490         params = &priv->channels.params;
3491
3492         reset = !params->lro_en;
3493         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3494
3495         new_channels.params = *params;
3496         new_channels.params.sw_mtu = new_mtu;
3497
3498         if (params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) {
3499                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3500                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3501
3502                 reset = reset && (ppw_old != ppw_new);
3503         }
3504
3505         if (!reset) {
3506                 params->sw_mtu = new_mtu;
3507                 mlx5e_set_dev_port_mtu(priv);
3508                 netdev->mtu = params->sw_mtu;
3509                 goto out;
3510         }
3511
3512         err = mlx5e_open_channels(priv, &new_channels);
3513         if (err)
3514                 goto out;
3515
3516         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3517         netdev->mtu = new_channels.params.sw_mtu;
3518
3519 out:
3520         mutex_unlock(&priv->state_lock);
3521         return err;
3522 }
3523
3524 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3525 {
3526         struct hwtstamp_config config;
3527         int err;
3528
3529         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3530                 return -EOPNOTSUPP;
3531
3532         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3533                 return -EFAULT;
3534
3535         /* TX HW timestamp */
3536         switch (config.tx_type) {
3537         case HWTSTAMP_TX_OFF:
3538         case HWTSTAMP_TX_ON:
3539                 break;
3540         default:
3541                 return -ERANGE;
3542         }
3543
3544         mutex_lock(&priv->state_lock);
3545         /* RX HW timestamp */
3546         switch (config.rx_filter) {
3547         case HWTSTAMP_FILTER_NONE:
3548                 /* Reset CQE compression to Admin default */
3549                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3550                 break;
3551         case HWTSTAMP_FILTER_ALL:
3552         case HWTSTAMP_FILTER_SOME:
3553         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3554         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3555         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3556         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3557         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3558         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3559         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3560         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3561         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3562         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3563         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3564         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3565         case HWTSTAMP_FILTER_NTP_ALL:
3566                 /* Disable CQE compression */
3567                 netdev_warn(priv->netdev, "Disabling cqe compression");
3568                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3569                 if (err) {
3570                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3571                         mutex_unlock(&priv->state_lock);
3572                         return err;
3573                 }
3574                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3575                 break;
3576         default:
3577                 mutex_unlock(&priv->state_lock);
3578                 return -ERANGE;
3579         }
3580
3581         memcpy(&priv->tstamp, &config, sizeof(config));
3582         mutex_unlock(&priv->state_lock);
3583
3584         return copy_to_user(ifr->ifr_data, &config,
3585                             sizeof(config)) ? -EFAULT : 0;
3586 }
3587
3588 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3589 {
3590         struct hwtstamp_config *cfg = &priv->tstamp;
3591
3592         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3593                 return -EOPNOTSUPP;
3594
3595         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3596 }
3597
3598 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3599 {
3600         struct mlx5e_priv *priv = netdev_priv(dev);
3601
3602         switch (cmd) {
3603         case SIOCSHWTSTAMP:
3604                 return mlx5e_hwstamp_set(priv, ifr);
3605         case SIOCGHWTSTAMP:
3606                 return mlx5e_hwstamp_get(priv, ifr);
3607         default:
3608                 return -EOPNOTSUPP;
3609         }
3610 }
3611
3612 #ifdef CONFIG_MLX5_ESWITCH
3613 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3614 {
3615         struct mlx5e_priv *priv = netdev_priv(dev);
3616         struct mlx5_core_dev *mdev = priv->mdev;
3617
3618         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3619 }
3620
3621 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3622                              __be16 vlan_proto)
3623 {
3624         struct mlx5e_priv *priv = netdev_priv(dev);
3625         struct mlx5_core_dev *mdev = priv->mdev;
3626
3627         if (vlan_proto != htons(ETH_P_8021Q))
3628                 return -EPROTONOSUPPORT;
3629
3630         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3631                                            vlan, qos);
3632 }
3633
3634 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3635 {
3636         struct mlx5e_priv *priv = netdev_priv(dev);
3637         struct mlx5_core_dev *mdev = priv->mdev;
3638
3639         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3640 }
3641
3642 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3643 {
3644         struct mlx5e_priv *priv = netdev_priv(dev);
3645         struct mlx5_core_dev *mdev = priv->mdev;
3646
3647         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3648 }
3649
3650 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3651                              int max_tx_rate)
3652 {
3653         struct mlx5e_priv *priv = netdev_priv(dev);
3654         struct mlx5_core_dev *mdev = priv->mdev;
3655
3656         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3657                                            max_tx_rate, min_tx_rate);
3658 }
3659
3660 static int mlx5_vport_link2ifla(u8 esw_link)
3661 {
3662         switch (esw_link) {
3663         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3664                 return IFLA_VF_LINK_STATE_DISABLE;
3665         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3666                 return IFLA_VF_LINK_STATE_ENABLE;
3667         }
3668         return IFLA_VF_LINK_STATE_AUTO;
3669 }
3670
3671 static int mlx5_ifla_link2vport(u8 ifla_link)
3672 {
3673         switch (ifla_link) {
3674         case IFLA_VF_LINK_STATE_DISABLE:
3675                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3676         case IFLA_VF_LINK_STATE_ENABLE:
3677                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3678         }
3679         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3680 }
3681
3682 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3683                                    int link_state)
3684 {
3685         struct mlx5e_priv *priv = netdev_priv(dev);
3686         struct mlx5_core_dev *mdev = priv->mdev;
3687
3688         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3689                                             mlx5_ifla_link2vport(link_state));
3690 }
3691
3692 static int mlx5e_get_vf_config(struct net_device *dev,
3693                                int vf, struct ifla_vf_info *ivi)
3694 {
3695         struct mlx5e_priv *priv = netdev_priv(dev);
3696         struct mlx5_core_dev *mdev = priv->mdev;
3697         int err;
3698
3699         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3700         if (err)
3701                 return err;
3702         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3703         return 0;
3704 }
3705
3706 static int mlx5e_get_vf_stats(struct net_device *dev,
3707                               int vf, struct ifla_vf_stats *vf_stats)
3708 {
3709         struct mlx5e_priv *priv = netdev_priv(dev);
3710         struct mlx5_core_dev *mdev = priv->mdev;
3711
3712         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3713                                             vf_stats);
3714 }
3715 #endif
3716
3717 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3718                                  struct udp_tunnel_info *ti)
3719 {
3720         struct mlx5e_priv *priv = netdev_priv(netdev);
3721
3722         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3723                 return;
3724
3725         if (!mlx5e_vxlan_allowed(priv->mdev))
3726                 return;
3727
3728         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3729 }
3730
3731 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3732                                  struct udp_tunnel_info *ti)
3733 {
3734         struct mlx5e_priv *priv = netdev_priv(netdev);
3735
3736         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3737                 return;
3738
3739         if (!mlx5e_vxlan_allowed(priv->mdev))
3740                 return;
3741
3742         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3743 }
3744
3745 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3746                                                      struct sk_buff *skb,
3747                                                      netdev_features_t features)
3748 {
3749         unsigned int offset = 0;
3750         struct udphdr *udph;
3751         u8 proto;
3752         u16 port;
3753
3754         switch (vlan_get_protocol(skb)) {
3755         case htons(ETH_P_IP):
3756                 proto = ip_hdr(skb)->protocol;
3757                 break;
3758         case htons(ETH_P_IPV6):
3759                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3760                 break;
3761         default:
3762                 goto out;
3763         }
3764
3765         switch (proto) {
3766         case IPPROTO_GRE:
3767                 return features;
3768         case IPPROTO_UDP:
3769                 udph = udp_hdr(skb);
3770                 port = be16_to_cpu(udph->dest);
3771
3772                 /* Verify if UDP port is being offloaded by HW */
3773                 if (mlx5e_vxlan_lookup_port(priv, port))
3774                         return features;
3775         }
3776
3777 out:
3778         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3779         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3780 }
3781
3782 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3783                                               struct net_device *netdev,
3784                                               netdev_features_t features)
3785 {
3786         struct mlx5e_priv *priv = netdev_priv(netdev);
3787
3788         features = vlan_features_check(skb, features);
3789         features = vxlan_features_check(skb, features);
3790
3791 #ifdef CONFIG_MLX5_EN_IPSEC
3792         if (mlx5e_ipsec_feature_check(skb, netdev, features))
3793                 return features;
3794 #endif
3795
3796         /* Validate if the tunneled packet is being offloaded by HW */
3797         if (skb->encapsulation &&
3798             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3799                 return mlx5e_tunnel_features_check(priv, skb, features);
3800
3801         return features;
3802 }
3803
3804 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
3805                                         struct mlx5e_txqsq *sq)
3806 {
3807         struct mlx5_eq *eq = sq->cq.mcq.eq;
3808         u32 eqe_count;
3809
3810         netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
3811                    eq->eqn, eq->cons_index, eq->irqn);
3812
3813         eqe_count = mlx5_eq_poll_irq_disabled(eq);
3814         if (!eqe_count)
3815                 return false;
3816
3817         netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
3818         sq->channel->stats.eq_rearm++;
3819         return true;
3820 }
3821
3822 static void mlx5e_tx_timeout_work(struct work_struct *work)
3823 {
3824         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
3825                                                tx_timeout_work);
3826         struct net_device *dev = priv->netdev;
3827         bool reopen_channels = false;
3828         int i, err;
3829
3830         rtnl_lock();
3831         mutex_lock(&priv->state_lock);
3832
3833         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3834                 goto unlock;
3835
3836         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3837                 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
3838                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3839
3840                 if (!netif_xmit_stopped(dev_queue))
3841                         continue;
3842
3843                 netdev_err(dev,
3844                            "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
3845                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
3846                            jiffies_to_usecs(jiffies - dev_queue->trans_start));
3847
3848                 /* If we recover a lost interrupt, most likely TX timeout will
3849                  * be resolved, skip reopening channels
3850                  */
3851                 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
3852                         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3853                         reopen_channels = true;
3854                 }
3855         }
3856
3857         if (!reopen_channels)
3858                 goto unlock;
3859
3860         mlx5e_close_locked(dev);
3861         err = mlx5e_open_locked(dev);
3862         if (err)
3863                 netdev_err(priv->netdev,
3864                            "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
3865                            err);
3866
3867 unlock:
3868         mutex_unlock(&priv->state_lock);
3869         rtnl_unlock();
3870 }
3871
3872 static void mlx5e_tx_timeout(struct net_device *dev)
3873 {
3874         struct mlx5e_priv *priv = netdev_priv(dev);
3875
3876         netdev_err(dev, "TX timeout detected\n");
3877         queue_work(priv->wq, &priv->tx_timeout_work);
3878 }
3879
3880 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3881 {
3882         struct mlx5e_priv *priv = netdev_priv(netdev);
3883         struct bpf_prog *old_prog;
3884         int err = 0;
3885         bool reset, was_opened;
3886         int i;
3887
3888         mutex_lock(&priv->state_lock);
3889
3890         if ((netdev->features & NETIF_F_LRO) && prog) {
3891                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3892                 err = -EINVAL;
3893                 goto unlock;
3894         }
3895
3896         if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3897                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3898                 err = -EINVAL;
3899                 goto unlock;
3900         }
3901
3902         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3903         /* no need for full reset when exchanging programs */
3904         reset = (!priv->channels.params.xdp_prog || !prog);
3905
3906         if (was_opened && reset)
3907                 mlx5e_close_locked(netdev);
3908         if (was_opened && !reset) {
3909                 /* num_channels is invariant here, so we can take the
3910                  * batched reference right upfront.
3911                  */
3912                 prog = bpf_prog_add(prog, priv->channels.num);
3913                 if (IS_ERR(prog)) {
3914                         err = PTR_ERR(prog);
3915                         goto unlock;
3916                 }
3917         }
3918
3919         /* exchange programs, extra prog reference we got from caller
3920          * as long as we don't fail from this point onwards.
3921          */
3922         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3923         if (old_prog)
3924                 bpf_prog_put(old_prog);
3925
3926         if (reset) /* change RQ type according to priv->xdp_prog */
3927                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
3928
3929         if (was_opened && reset)
3930                 mlx5e_open_locked(netdev);
3931
3932         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3933                 goto unlock;
3934
3935         /* exchanging programs w/o reset, we update ref counts on behalf
3936          * of the channels RQs here.
3937          */
3938         for (i = 0; i < priv->channels.num; i++) {
3939                 struct mlx5e_channel *c = priv->channels.c[i];
3940
3941                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3942                 napi_synchronize(&c->napi);
3943                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3944
3945                 old_prog = xchg(&c->rq.xdp_prog, prog);
3946
3947                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3948                 /* napi_schedule in case we have missed anything */
3949                 napi_schedule(&c->napi);
3950
3951                 if (old_prog)
3952                         bpf_prog_put(old_prog);
3953         }
3954
3955 unlock:
3956         mutex_unlock(&priv->state_lock);
3957         return err;
3958 }
3959
3960 static u32 mlx5e_xdp_query(struct net_device *dev)
3961 {
3962         struct mlx5e_priv *priv = netdev_priv(dev);
3963         const struct bpf_prog *xdp_prog;
3964         u32 prog_id = 0;
3965
3966         mutex_lock(&priv->state_lock);
3967         xdp_prog = priv->channels.params.xdp_prog;
3968         if (xdp_prog)
3969                 prog_id = xdp_prog->aux->id;
3970         mutex_unlock(&priv->state_lock);
3971
3972         return prog_id;
3973 }
3974
3975 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3976 {
3977         switch (xdp->command) {
3978         case XDP_SETUP_PROG:
3979                 return mlx5e_xdp_set(dev, xdp->prog);
3980         case XDP_QUERY_PROG:
3981                 xdp->prog_id = mlx5e_xdp_query(dev);
3982                 xdp->prog_attached = !!xdp->prog_id;
3983                 return 0;
3984         default:
3985                 return -EINVAL;
3986         }
3987 }
3988
3989 #ifdef CONFIG_NET_POLL_CONTROLLER
3990 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3991  * reenabling interrupts.
3992  */
3993 static void mlx5e_netpoll(struct net_device *dev)
3994 {
3995         struct mlx5e_priv *priv = netdev_priv(dev);
3996         struct mlx5e_channels *chs = &priv->channels;
3997
3998         int i;
3999
4000         for (i = 0; i < chs->num; i++)
4001                 napi_schedule(&chs->c[i]->napi);
4002 }
4003 #endif
4004
4005 static const struct net_device_ops mlx5e_netdev_ops = {
4006         .ndo_open                = mlx5e_open,
4007         .ndo_stop                = mlx5e_close,
4008         .ndo_start_xmit          = mlx5e_xmit,
4009         .ndo_setup_tc            = mlx5e_setup_tc,
4010         .ndo_select_queue        = mlx5e_select_queue,
4011         .ndo_get_stats64         = mlx5e_get_stats,
4012         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4013         .ndo_set_mac_address     = mlx5e_set_mac,
4014         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4015         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4016         .ndo_set_features        = mlx5e_set_features,
4017         .ndo_fix_features        = mlx5e_fix_features,
4018         .ndo_change_mtu          = mlx5e_change_mtu,
4019         .ndo_do_ioctl            = mlx5e_ioctl,
4020         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4021         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4022         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4023         .ndo_features_check      = mlx5e_features_check,
4024 #ifdef CONFIG_RFS_ACCEL
4025         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4026 #endif
4027         .ndo_tx_timeout          = mlx5e_tx_timeout,
4028         .ndo_bpf                 = mlx5e_xdp,
4029 #ifdef CONFIG_NET_POLL_CONTROLLER
4030         .ndo_poll_controller     = mlx5e_netpoll,
4031 #endif
4032 #ifdef CONFIG_MLX5_ESWITCH
4033         /* SRIOV E-Switch NDOs */
4034         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4035         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4036         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4037         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4038         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4039         .ndo_get_vf_config       = mlx5e_get_vf_config,
4040         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4041         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4042         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4043         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4044 #endif
4045 };
4046
4047 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4048 {
4049         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4050                 return -EOPNOTSUPP;
4051         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4052             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4053             !MLX5_CAP_ETH(mdev, csum_cap) ||
4054             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4055             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4056             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4057             MLX5_CAP_FLOWTABLE(mdev,
4058                                flow_table_properties_nic_receive.max_ft_level)
4059                                < 3) {
4060                 mlx5_core_warn(mdev,
4061                                "Not creating net device, some required device capabilities are missing\n");
4062                 return -EOPNOTSUPP;
4063         }
4064         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4065                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4066         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4067                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4068
4069         return 0;
4070 }
4071
4072 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4073                                    int num_channels)
4074 {
4075         int i;
4076
4077         for (i = 0; i < len; i++)
4078                 indirection_rqt[i] = i % num_channels;
4079 }
4080
4081 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4082 {
4083         u32 link_speed = 0;
4084         u32 pci_bw = 0;
4085
4086         mlx5e_get_max_linkspeed(mdev, &link_speed);
4087         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4088         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4089                            link_speed, pci_bw);
4090
4091 #define MLX5E_SLOW_PCI_RATIO (2)
4092
4093         return link_speed && pci_bw &&
4094                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4095 }
4096
4097 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4098 {
4099         struct net_dim_cq_moder moder;
4100
4101         moder.cq_period_mode = cq_period_mode;
4102         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4103         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4104         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4105                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4106
4107         return moder;
4108 }
4109
4110 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4111 {
4112         struct net_dim_cq_moder moder;
4113
4114         moder.cq_period_mode = cq_period_mode;
4115         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4116         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4117         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4118                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4119
4120         return moder;
4121 }
4122
4123 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4124 {
4125         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4126                 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4127                 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4128 }
4129
4130 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4131 {
4132         if (params->tx_dim_enabled) {
4133                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4134
4135                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4136         } else {
4137                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4138         }
4139
4140         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4141                         params->tx_cq_moderation.cq_period_mode ==
4142                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4143 }
4144
4145 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4146 {
4147         if (params->rx_dim_enabled) {
4148                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4149
4150                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4151         } else {
4152                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4153         }
4154
4155         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4156                         params->rx_cq_moderation.cq_period_mode ==
4157                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4158 }
4159
4160 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4161 {
4162         int i;
4163
4164         /* The supported periods are organized in ascending order */
4165         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4166                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4167                         break;
4168
4169         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4170 }
4171
4172 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4173                             struct mlx5e_params *params,
4174                             u16 max_channels, u16 mtu)
4175 {
4176         u8 rx_cq_period_mode;
4177
4178         params->sw_mtu = mtu;
4179         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4180         params->num_channels = max_channels;
4181         params->num_tc       = 1;
4182
4183         /* SQ */
4184         params->log_sq_size = is_kdump_kernel() ?
4185                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4186                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4187
4188         /* set CQE compression */
4189         params->rx_cqe_compress_def = false;
4190         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4191             MLX5_CAP_GEN(mdev, vport_group_manager))
4192                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4193
4194         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4195
4196         /* RQ */
4197         if (mlx5e_striding_rq_possible(mdev, params))
4198                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ,
4199                                 !slow_pci_heuristic(mdev));
4200         mlx5e_set_rq_type(mdev, params);
4201         mlx5e_init_rq_type_params(mdev, params);
4202
4203         /* HW LRO */
4204
4205         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4206         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4207                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4208                         params->lro_en = !slow_pci_heuristic(mdev);
4209         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4210
4211         /* CQ moderation params */
4212         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4213                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4214                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4215         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4216         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4217         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4218         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4219
4220         /* TX inline */
4221         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4222
4223         /* RSS */
4224         params->rss_hfunc = ETH_RSS_HASH_XOR;
4225         netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4226         mlx5e_build_default_indir_rqt(params->indirection_rqt,
4227                                       MLX5E_INDIR_RQT_SIZE, max_channels);
4228 }
4229
4230 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4231                                         struct net_device *netdev,
4232                                         const struct mlx5e_profile *profile,
4233                                         void *ppriv)
4234 {
4235         struct mlx5e_priv *priv = netdev_priv(netdev);
4236
4237         priv->mdev        = mdev;
4238         priv->netdev      = netdev;
4239         priv->profile     = profile;
4240         priv->ppriv       = ppriv;
4241         priv->msglevel    = MLX5E_MSG_LEVEL;
4242
4243         mlx5e_build_nic_params(mdev, &priv->channels.params,
4244                                profile->max_nch(mdev), netdev->mtu);
4245
4246         mutex_init(&priv->state_lock);
4247
4248         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4249         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4250         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4251         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4252
4253         mlx5e_timestamp_init(priv);
4254 }
4255
4256 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4257 {
4258         struct mlx5e_priv *priv = netdev_priv(netdev);
4259
4260         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4261         if (is_zero_ether_addr(netdev->dev_addr) &&
4262             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4263                 eth_hw_addr_random(netdev);
4264                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4265         }
4266 }
4267
4268 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4269 static const struct switchdev_ops mlx5e_switchdev_ops = {
4270         .switchdev_port_attr_get        = mlx5e_attr_get,
4271 };
4272 #endif
4273
4274 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4275 {
4276         struct mlx5e_priv *priv = netdev_priv(netdev);
4277         struct mlx5_core_dev *mdev = priv->mdev;
4278         bool fcs_supported;
4279         bool fcs_enabled;
4280
4281         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4282
4283         netdev->netdev_ops = &mlx5e_netdev_ops;
4284
4285 #ifdef CONFIG_MLX5_CORE_EN_DCB
4286         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4287                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4288 #endif
4289
4290         netdev->watchdog_timeo    = 15 * HZ;
4291
4292         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4293
4294         netdev->vlan_features    |= NETIF_F_SG;
4295         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4296         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4297         netdev->vlan_features    |= NETIF_F_GRO;
4298         netdev->vlan_features    |= NETIF_F_TSO;
4299         netdev->vlan_features    |= NETIF_F_TSO6;
4300         netdev->vlan_features    |= NETIF_F_RXCSUM;
4301         netdev->vlan_features    |= NETIF_F_RXHASH;
4302
4303         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4304         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4305
4306         if (!!MLX5_CAP_ETH(mdev, lro_cap))
4307                 netdev->vlan_features    |= NETIF_F_LRO;
4308
4309         netdev->hw_features       = netdev->vlan_features;
4310         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4311         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4312         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4313         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4314
4315         if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4316                 netdev->hw_features     |= NETIF_F_GSO_PARTIAL;
4317                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4318                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4319                 netdev->hw_enc_features |= NETIF_F_TSO;
4320                 netdev->hw_enc_features |= NETIF_F_TSO6;
4321                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4322         }
4323
4324         if (mlx5e_vxlan_allowed(mdev)) {
4325                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4326                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4327                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4328                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4329                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4330         }
4331
4332         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4333                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4334                                            NETIF_F_GSO_GRE_CSUM;
4335                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4336                                            NETIF_F_GSO_GRE_CSUM;
4337                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4338                                                 NETIF_F_GSO_GRE_CSUM;
4339         }
4340
4341         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4342
4343         if (fcs_supported)
4344                 netdev->hw_features |= NETIF_F_RXALL;
4345
4346         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4347                 netdev->hw_features |= NETIF_F_RXFCS;
4348
4349         netdev->features          = netdev->hw_features;
4350         if (!priv->channels.params.lro_en)
4351                 netdev->features  &= ~NETIF_F_LRO;
4352
4353         if (fcs_enabled)
4354                 netdev->features  &= ~NETIF_F_RXALL;
4355
4356         if (!priv->channels.params.scatter_fcs_en)
4357                 netdev->features  &= ~NETIF_F_RXFCS;
4358
4359 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4360         if (FT_CAP(flow_modify_en) &&
4361             FT_CAP(modify_root) &&
4362             FT_CAP(identified_miss_table_mode) &&
4363             FT_CAP(flow_table_modify)) {
4364                 netdev->hw_features      |= NETIF_F_HW_TC;
4365 #ifdef CONFIG_RFS_ACCEL
4366                 netdev->hw_features      |= NETIF_F_NTUPLE;
4367 #endif
4368         }
4369
4370         netdev->features         |= NETIF_F_HIGHDMA;
4371         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4372
4373         netdev->priv_flags       |= IFF_UNICAST_FLT;
4374
4375         mlx5e_set_netdev_dev_addr(netdev);
4376
4377 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4378         if (MLX5_VPORT_MANAGER(mdev))
4379                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4380 #endif
4381
4382         mlx5e_ipsec_build_netdev(priv);
4383         mlx5e_tls_build_netdev(priv);
4384 }
4385
4386 static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4387 {
4388         struct mlx5_core_dev *mdev = priv->mdev;
4389         int err;
4390
4391         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4392         if (err) {
4393                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4394                 priv->q_counter = 0;
4395         }
4396
4397         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4398         if (err) {
4399                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4400                 priv->drop_rq_q_counter = 0;
4401         }
4402 }
4403
4404 static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4405 {
4406         if (priv->q_counter)
4407                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4408
4409         if (priv->drop_rq_q_counter)
4410                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4411 }
4412
4413 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4414                            struct net_device *netdev,
4415                            const struct mlx5e_profile *profile,
4416                            void *ppriv)
4417 {
4418         struct mlx5e_priv *priv = netdev_priv(netdev);
4419         int err;
4420
4421         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4422         err = mlx5e_ipsec_init(priv);
4423         if (err)
4424                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4425         err = mlx5e_tls_init(priv);
4426         if (err)
4427                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4428         mlx5e_build_nic_netdev(netdev);
4429         mlx5e_vxlan_init(priv);
4430 }
4431
4432 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4433 {
4434         mlx5e_tls_cleanup(priv);
4435         mlx5e_ipsec_cleanup(priv);
4436         mlx5e_vxlan_cleanup(priv);
4437 }
4438
4439 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4440 {
4441         struct mlx5_core_dev *mdev = priv->mdev;
4442         int err;
4443
4444         err = mlx5e_create_indirect_rqt(priv);
4445         if (err)
4446                 return err;
4447
4448         err = mlx5e_create_direct_rqts(priv);
4449         if (err)
4450                 goto err_destroy_indirect_rqts;
4451
4452         err = mlx5e_create_indirect_tirs(priv);
4453         if (err)
4454                 goto err_destroy_direct_rqts;
4455
4456         err = mlx5e_create_direct_tirs(priv);
4457         if (err)
4458                 goto err_destroy_indirect_tirs;
4459
4460         err = mlx5e_create_flow_steering(priv);
4461         if (err) {
4462                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4463                 goto err_destroy_direct_tirs;
4464         }
4465
4466         err = mlx5e_tc_init(priv);
4467         if (err)
4468                 goto err_destroy_flow_steering;
4469
4470         return 0;
4471
4472 err_destroy_flow_steering:
4473         mlx5e_destroy_flow_steering(priv);
4474 err_destroy_direct_tirs:
4475         mlx5e_destroy_direct_tirs(priv);
4476 err_destroy_indirect_tirs:
4477         mlx5e_destroy_indirect_tirs(priv);
4478 err_destroy_direct_rqts:
4479         mlx5e_destroy_direct_rqts(priv);
4480 err_destroy_indirect_rqts:
4481         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4482         return err;
4483 }
4484
4485 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4486 {
4487         mlx5e_tc_cleanup(priv);
4488         mlx5e_destroy_flow_steering(priv);
4489         mlx5e_destroy_direct_tirs(priv);
4490         mlx5e_destroy_indirect_tirs(priv);
4491         mlx5e_destroy_direct_rqts(priv);
4492         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4493 }
4494
4495 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4496 {
4497         int err;
4498
4499         err = mlx5e_create_tises(priv);
4500         if (err) {
4501                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4502                 return err;
4503         }
4504
4505 #ifdef CONFIG_MLX5_CORE_EN_DCB
4506         mlx5e_dcbnl_initialize(priv);
4507 #endif
4508         return 0;
4509 }
4510
4511 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4512 {
4513         struct net_device *netdev = priv->netdev;
4514         struct mlx5_core_dev *mdev = priv->mdev;
4515         u16 max_mtu;
4516
4517         mlx5e_init_l2_addr(priv);
4518
4519         /* Marking the link as currently not needed by the Driver */
4520         if (!netif_running(netdev))
4521                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4522
4523         /* MTU range: 68 - hw-specific max */
4524         netdev->min_mtu = ETH_MIN_MTU;
4525         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4526         netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4527         mlx5e_set_dev_port_mtu(priv);
4528
4529         mlx5_lag_add(mdev, netdev);
4530
4531         mlx5e_enable_async_events(priv);
4532
4533         if (MLX5_VPORT_MANAGER(priv->mdev))
4534                 mlx5e_register_vport_reps(priv);
4535
4536         if (netdev->reg_state != NETREG_REGISTERED)
4537                 return;
4538 #ifdef CONFIG_MLX5_CORE_EN_DCB
4539         mlx5e_dcbnl_init_app(priv);
4540 #endif
4541
4542         queue_work(priv->wq, &priv->set_rx_mode_work);
4543
4544         rtnl_lock();
4545         if (netif_running(netdev))
4546                 mlx5e_open(netdev);
4547         netif_device_attach(netdev);
4548         rtnl_unlock();
4549 }
4550
4551 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4552 {
4553         struct mlx5_core_dev *mdev = priv->mdev;
4554
4555 #ifdef CONFIG_MLX5_CORE_EN_DCB
4556         if (priv->netdev->reg_state == NETREG_REGISTERED)
4557                 mlx5e_dcbnl_delete_app(priv);
4558 #endif
4559
4560         rtnl_lock();
4561         if (netif_running(priv->netdev))
4562                 mlx5e_close(priv->netdev);
4563         netif_device_detach(priv->netdev);
4564         rtnl_unlock();
4565
4566         queue_work(priv->wq, &priv->set_rx_mode_work);
4567
4568         if (MLX5_VPORT_MANAGER(priv->mdev))
4569                 mlx5e_unregister_vport_reps(priv);
4570
4571         mlx5e_disable_async_events(priv);
4572         mlx5_lag_remove(mdev);
4573 }
4574
4575 static const struct mlx5e_profile mlx5e_nic_profile = {
4576         .init              = mlx5e_nic_init,
4577         .cleanup           = mlx5e_nic_cleanup,
4578         .init_rx           = mlx5e_init_nic_rx,
4579         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4580         .init_tx           = mlx5e_init_nic_tx,
4581         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4582         .enable            = mlx5e_nic_enable,
4583         .disable           = mlx5e_nic_disable,
4584         .update_stats      = mlx5e_update_ndo_stats,
4585         .max_nch           = mlx5e_get_max_num_channels,
4586         .update_carrier    = mlx5e_update_carrier,
4587         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4588         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4589         .max_tc            = MLX5E_MAX_NUM_TC,
4590 };
4591
4592 /* mlx5e generic netdev management API (move to en_common.c) */
4593
4594 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4595                                        const struct mlx5e_profile *profile,
4596                                        void *ppriv)
4597 {
4598         int nch = profile->max_nch(mdev);
4599         struct net_device *netdev;
4600         struct mlx5e_priv *priv;
4601
4602         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4603                                     nch * profile->max_tc,
4604                                     nch);
4605         if (!netdev) {
4606                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4607                 return NULL;
4608         }
4609
4610 #ifdef CONFIG_RFS_ACCEL
4611         netdev->rx_cpu_rmap = mdev->rmap;
4612 #endif
4613
4614         profile->init(mdev, netdev, profile, ppriv);
4615
4616         netif_carrier_off(netdev);
4617
4618         priv = netdev_priv(netdev);
4619
4620         priv->wq = create_singlethread_workqueue("mlx5e");
4621         if (!priv->wq)
4622                 goto err_cleanup_nic;
4623
4624         return netdev;
4625
4626 err_cleanup_nic:
4627         if (profile->cleanup)
4628                 profile->cleanup(priv);
4629         free_netdev(netdev);
4630
4631         return NULL;
4632 }
4633
4634 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4635 {
4636         struct mlx5_core_dev *mdev = priv->mdev;
4637         const struct mlx5e_profile *profile;
4638         int err;
4639
4640         profile = priv->profile;
4641         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4642
4643         err = profile->init_tx(priv);
4644         if (err)
4645                 goto out;
4646
4647         mlx5e_create_q_counters(priv);
4648
4649         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4650         if (err) {
4651                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4652                 goto err_destroy_q_counters;
4653         }
4654
4655         err = profile->init_rx(priv);
4656         if (err)
4657                 goto err_close_drop_rq;
4658
4659         if (profile->enable)
4660                 profile->enable(priv);
4661
4662         return 0;
4663
4664 err_close_drop_rq:
4665         mlx5e_close_drop_rq(&priv->drop_rq);
4666
4667 err_destroy_q_counters:
4668         mlx5e_destroy_q_counters(priv);
4669         profile->cleanup_tx(priv);
4670
4671 out:
4672         return err;
4673 }
4674
4675 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4676 {
4677         const struct mlx5e_profile *profile = priv->profile;
4678
4679         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4680
4681         if (profile->disable)
4682                 profile->disable(priv);
4683         flush_workqueue(priv->wq);
4684
4685         profile->cleanup_rx(priv);
4686         mlx5e_close_drop_rq(&priv->drop_rq);
4687         mlx5e_destroy_q_counters(priv);
4688         profile->cleanup_tx(priv);
4689         cancel_delayed_work_sync(&priv->update_stats_work);
4690 }
4691
4692 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4693 {
4694         const struct mlx5e_profile *profile = priv->profile;
4695         struct net_device *netdev = priv->netdev;
4696
4697         destroy_workqueue(priv->wq);
4698         if (profile->cleanup)
4699                 profile->cleanup(priv);
4700         free_netdev(netdev);
4701 }
4702
4703 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4704  * hardware contexts and to connect it to the current netdev.
4705  */
4706 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4707 {
4708         struct mlx5e_priv *priv = vpriv;
4709         struct net_device *netdev = priv->netdev;
4710         int err;
4711
4712         if (netif_device_present(netdev))
4713                 return 0;
4714
4715         err = mlx5e_create_mdev_resources(mdev);
4716         if (err)
4717                 return err;
4718
4719         err = mlx5e_attach_netdev(priv);
4720         if (err) {
4721                 mlx5e_destroy_mdev_resources(mdev);
4722                 return err;
4723         }
4724
4725         return 0;
4726 }
4727
4728 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4729 {
4730         struct mlx5e_priv *priv = vpriv;
4731         struct net_device *netdev = priv->netdev;
4732
4733         if (!netif_device_present(netdev))
4734                 return;
4735
4736         mlx5e_detach_netdev(priv);
4737         mlx5e_destroy_mdev_resources(mdev);
4738 }
4739
4740 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4741 {
4742         struct net_device *netdev;
4743         void *rpriv = NULL;
4744         void *priv;
4745         int err;
4746
4747         err = mlx5e_check_required_hca_cap(mdev);
4748         if (err)
4749                 return NULL;
4750
4751 #ifdef CONFIG_MLX5_ESWITCH
4752         if (MLX5_VPORT_MANAGER(mdev)) {
4753                 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4754                 if (!rpriv) {
4755                         mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4756                         return NULL;
4757                 }
4758         }
4759 #endif
4760
4761         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4762         if (!netdev) {
4763                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4764                 goto err_free_rpriv;
4765         }
4766
4767         priv = netdev_priv(netdev);
4768
4769         err = mlx5e_attach(mdev, priv);
4770         if (err) {
4771                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4772                 goto err_destroy_netdev;
4773         }
4774
4775         err = register_netdev(netdev);
4776         if (err) {
4777                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4778                 goto err_detach;
4779         }
4780
4781 #ifdef CONFIG_MLX5_CORE_EN_DCB
4782         mlx5e_dcbnl_init_app(priv);
4783 #endif
4784         return priv;
4785
4786 err_detach:
4787         mlx5e_detach(mdev, priv);
4788 err_destroy_netdev:
4789         mlx5e_destroy_netdev(priv);
4790 err_free_rpriv:
4791         kfree(rpriv);
4792         return NULL;
4793 }
4794
4795 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4796 {
4797         struct mlx5e_priv *priv = vpriv;
4798         void *ppriv = priv->ppriv;
4799
4800 #ifdef CONFIG_MLX5_CORE_EN_DCB
4801         mlx5e_dcbnl_delete_app(priv);
4802 #endif
4803         unregister_netdev(priv->netdev);
4804         mlx5e_detach(mdev, vpriv);
4805         mlx5e_destroy_netdev(priv);
4806         kfree(ppriv);
4807 }
4808
4809 static void *mlx5e_get_netdev(void *vpriv)
4810 {
4811         struct mlx5e_priv *priv = vpriv;
4812
4813         return priv->netdev;
4814 }
4815
4816 static struct mlx5_interface mlx5e_interface = {
4817         .add       = mlx5e_add,
4818         .remove    = mlx5e_remove,
4819         .attach    = mlx5e_attach,
4820         .detach    = mlx5e_detach,
4821         .event     = mlx5e_async_event,
4822         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
4823         .get_dev   = mlx5e_get_netdev,
4824 };
4825
4826 void mlx5e_init(void)
4827 {
4828         mlx5e_ipsec_build_inverse_table();
4829         mlx5e_build_ptys2ethtool_map();
4830         mlx5_register_interface(&mlx5e_interface);
4831 }
4832
4833 void mlx5e_cleanup(void)
4834 {
4835         mlx5_unregister_interface(&mlx5e_interface);
4836 }