drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 enum {
  43         MLX5_EN_QP_FLUSH_TIMEOUT_MS     = 5000,
  44         MLX5_EN_QP_FLUSH_MSLEEP_QUANT   = 20,
  45         MLX5_EN_QP_FLUSH_MAX_ITER       = MLX5_EN_QP_FLUSH_TIMEOUT_MS /
  46                                           MLX5_EN_QP_FLUSH_MSLEEP_QUANT,
  47 };
  48
  49 struct mlx5e_rq_param {
  50         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  51         struct mlx5_wq_param    wq;
  52         bool                    am_enabled;
  53 };
  54
  55 struct mlx5e_sq_param {
  56         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  57         struct mlx5_wq_param       wq;
  58         u16                        max_inline;
  59         u8                         min_inline_mode;
  60         bool                       icosq;
  61 };
  62
  63 struct mlx5e_cq_param {
  64         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  65         struct mlx5_wq_param       wq;
  66         u16                        eq_ix;
  67         u8                         cq_period_mode;
  68 };
  69
  70 struct mlx5e_channel_param {
  71         struct mlx5e_rq_param      rq;
  72         struct mlx5e_sq_param      sq;
  73         struct mlx5e_sq_param      icosq;
  74         struct mlx5e_cq_param      rx_cq;
  75         struct mlx5e_cq_param      tx_cq;
  76         struct mlx5e_cq_param      icosq_cq;
  77 };
  78
  79 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  80 {
  81         struct mlx5_core_dev *mdev = priv->mdev;
  82         u8 port_state;
  83
  84         port_state = mlx5_query_vport_state(mdev,
  85                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  86
  87         if (port_state == VPORT_STATE_UP) {
  88                 netdev_info(priv->netdev, "Link up\n");
  89                 netif_carrier_on(priv->netdev);
  90         } else {
  91                 netdev_info(priv->netdev, "Link down\n");
  92                 netif_carrier_off(priv->netdev);
  93         }
  94 }
  95
  96 static void mlx5e_update_carrier_work(struct work_struct *work)
  97 {
  98         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  99                                                update_carrier_work);
 100
 101         mutex_lock(&priv->state_lock);
 102         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 103                 mlx5e_update_carrier(priv);
 104         mutex_unlock(&priv->state_lock);
 105 }
 106
 107 static void mlx5e_tx_timeout_work(struct work_struct *work)
 108 {
 109         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 110                                                tx_timeout_work);
 111         int err;
 112
 113         rtnl_lock();
 114         mutex_lock(&priv->state_lock);
 115         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 116                 goto unlock;
 117         mlx5e_close_locked(priv->netdev);
 118         err = mlx5e_open_locked(priv->netdev);
 119         if (err)
 120                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 121                            err);
 122 unlock:
 123         mutex_unlock(&priv->state_lock);
 124         rtnl_unlock();
 125 }
 126
 127 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 128 {
 129         struct mlx5e_sw_stats *s = &priv->stats.sw;
 130         struct mlx5e_rq_stats *rq_stats;
 131         struct mlx5e_sq_stats *sq_stats;
 132         u64 tx_offload_none = 0;
 133         int i, j;
 134
 135         memset(s, 0, sizeof(*s));
 136         for (i = 0; i < priv->params.num_channels; i++) {
 137                 rq_stats = &priv->channel[i]->rq.stats;
 138
 139                 s->rx_packets   += rq_stats->packets;
 140                 s->rx_bytes     += rq_stats->bytes;
 141                 s->rx_lro_packets += rq_stats->lro_packets;
 142                 s->rx_lro_bytes += rq_stats->lro_bytes;
 143                 s->rx_csum_none += rq_stats->csum_none;
 144                 s->rx_csum_complete += rq_stats->csum_complete;
 145                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 146                 s->rx_wqe_err   += rq_stats->wqe_err;
 147                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 148                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 149                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 150                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 151                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 152
 153                 for (j = 0; j < priv->params.num_tc; j++) {
 154                         sq_stats = &priv->channel[i]->sq[j].stats;
 155
 156                         s->tx_packets           += sq_stats->packets;
 157                         s->tx_bytes             += sq_stats->bytes;
 158                         s->tx_tso_packets       += sq_stats->tso_packets;
 159                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 160                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 161                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 162                         s->tx_queue_stopped     += sq_stats->stopped;
 163                         s->tx_queue_wake        += sq_stats->wake;
 164                         s->tx_queue_dropped     += sq_stats->dropped;
 165                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 166                         tx_offload_none         += sq_stats->csum_none;
 167                 }
 168         }
 169
 170         /* Update calculated offload counters */
 171         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 172         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 173
 174         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 175                                 priv->stats.pport.phy_counters,
 176                                 counter_set.phys_layer_cntrs.link_down_events);
 177 }
 178
 179 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 180 {
 181         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 182         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 183         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 184         struct mlx5_core_dev *mdev = priv->mdev;
 185
 186         MLX5_SET(query_vport_counter_in, in, opcode,
 187                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 188         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 189         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 190
 191         memset(out, 0, outlen);
 192         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 193 }
 194
 195 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 196 {
 197         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 198         struct mlx5_core_dev *mdev = priv->mdev;
 199         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 200         int prio;
 201         void *out;
 202         u32 *in;
 203
 204         in = mlx5_vzalloc(sz);
 205         if (!in)
 206                 goto free_out;
 207
 208         MLX5_SET(ppcnt_reg, in, local_port, 1);
 209
 210         out = pstats->IEEE_802_3_counters;
 211         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 212         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 213
 214         out = pstats->RFC_2863_counters;
 215         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 216         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 217
 218         out = pstats->RFC_2819_counters;
 219         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 220         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 221
 222         out = pstats->phy_counters;
 223         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 224         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 225
 226         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 227         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 228                 out = pstats->per_prio_counters[prio];
 229                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 230                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 231                                      MLX5_REG_PPCNT, 0, 0);
 232         }
 233
 234 free_out:
 235         kvfree(in);
 236 }
 237
 238 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 239 {
 240         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 241
 242         if (!priv->q_counter)
 243                 return;
 244
 245         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 246                                       &qcnt->rx_out_of_buffer);
 247 }
 248
 249 void mlx5e_update_stats(struct mlx5e_priv *priv)
 250 {
 251         mlx5e_update_q_counter(priv);
 252         mlx5e_update_vport_counters(priv);
 253         mlx5e_update_pport_counters(priv);
 254         mlx5e_update_sw_counters(priv);
 255 }
 256
 257 void mlx5e_update_stats_work(struct work_struct *work)
 258 {
 259         struct delayed_work *dwork = to_delayed_work(work);
 260         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 261                                                update_stats_work);
 262         mutex_lock(&priv->state_lock);
 263         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 264                 priv->profile->update_stats(priv);
 265                 queue_delayed_work(priv->wq, dwork,
 266                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 267         }
 268         mutex_unlock(&priv->state_lock);
 269 }
 270
 271 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 272                               enum mlx5_dev_event event, unsigned long param)
 273 {
 274         struct mlx5e_priv *priv = vpriv;
 275
 276         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 277                 return;
 278
 279         switch (event) {
 280         case MLX5_DEV_EVENT_PORT_UP:
 281         case MLX5_DEV_EVENT_PORT_DOWN:
 282                 queue_work(priv->wq, &priv->update_carrier_work);
 283                 break;
 284
 285         default:
 286                 break;
 287         }
 288 }
 289
 290 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 291 {
 292         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 293 }
 294
 295 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 296 {
 297         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 298         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 299 }
 300
 301 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 302 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 303
 304 static int mlx5e_create_rq(struct mlx5e_channel *c,
 305                            struct mlx5e_rq_param *param,
 306                            struct mlx5e_rq *rq)
 307 {
 308         struct mlx5e_priv *priv = c->priv;
 309         struct mlx5_core_dev *mdev = priv->mdev;
 310         void *rqc = param->rqc;
 311         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 312         u32 byte_count;
 313         int wq_sz;
 314         int err;
 315         int i;
 316
 317         param->wq.db_numa_node = cpu_to_node(c->cpu);
 318
 319         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 320                                 &rq->wq_ctrl);
 321         if (err)
 322                 return err;
 323
 324         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 325
 326         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 327
 328         switch (priv->params.rq_wq_type) {
 329         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 330                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 331                                             GFP_KERNEL, cpu_to_node(c->cpu));
 332                 if (!rq->wqe_info) {
 333                         err = -ENOMEM;
 334                         goto err_rq_wq_destroy;
 335                 }
 336                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 337                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 338                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 339
 340                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 341                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 342                 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 343                 byte_count = rq->wqe_sz;
 344                 break;
 345         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 346                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 347                                        cpu_to_node(c->cpu));
 348                 if (!rq->skb) {
 349                         err = -ENOMEM;
 350                         goto err_rq_wq_destroy;
 351                 }
 352                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 353                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 354                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 355
 356                 rq->wqe_sz = (priv->params.lro_en) ?
 357                                 priv->params.lro_wqe_sz :
 358                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 359                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 360                 byte_count = rq->wqe_sz;
 361                 byte_count |= MLX5_HW_START_PADDING;
 362         }
 363
 364         for (i = 0; i < wq_sz; i++) {
 365                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 366
 367                 wqe->data.byte_count = cpu_to_be32(byte_count);
 368         }
 369
 370         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 371         rq->am.mode = priv->params.rx_cq_period_mode;
 372
 373         rq->wq_type = priv->params.rq_wq_type;
 374         rq->pdev    = c->pdev;
 375         rq->netdev  = c->netdev;
 376         rq->tstamp  = &priv->tstamp;
 377         rq->channel = c;
 378         rq->ix      = c->ix;
 379         rq->priv    = c->priv;
 380         rq->mkey_be = c->mkey_be;
 381         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 382
 383         return 0;
 384
 385 err_rq_wq_destroy:
 386         mlx5_wq_destroy(&rq->wq_ctrl);
 387
 388         return err;
 389 }
 390
 391 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 392 {
 393         switch (rq->wq_type) {
 394         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 395                 kfree(rq->wqe_info);
 396                 break;
 397         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 398                 kfree(rq->skb);
 399         }
 400
 401         mlx5_wq_destroy(&rq->wq_ctrl);
 402 }
 403
 404 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 405 {
 406         struct mlx5e_priv *priv = rq->priv;
 407         struct mlx5_core_dev *mdev = priv->mdev;
 408
 409         void *in;
 410         void *rqc;
 411         void *wq;
 412         int inlen;
 413         int err;
 414
 415         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 416                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 417         in = mlx5_vzalloc(inlen);
 418         if (!in)
 419                 return -ENOMEM;
 420
 421         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 422         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 423
 424         memcpy(rqc, param->rqc, sizeof(param->rqc));
 425
 426         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 427         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 428         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 429         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 430         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 431                                                 MLX5_ADAPTER_PAGE_SHIFT);
 432         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 433
 434         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 435                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 436
 437         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 438
 439         kvfree(in);
 440
 441         return err;
 442 }
 443
 444 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 445                                  int next_state)
 446 {
 447         struct mlx5e_channel *c = rq->channel;
 448         struct mlx5e_priv *priv = c->priv;
 449         struct mlx5_core_dev *mdev = priv->mdev;
 450
 451         void *in;
 452         void *rqc;
 453         int inlen;
 454         int err;
 455
 456         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 457         in = mlx5_vzalloc(inlen);
 458         if (!in)
 459                 return -ENOMEM;
 460
 461         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 462
 463         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 464         MLX5_SET(rqc, rqc, state, next_state);
 465
 466         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 467
 468         kvfree(in);
 469
 470         return err;
 471 }
 472
 473 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 474 {
 475         struct mlx5e_channel *c = rq->channel;
 476         struct mlx5e_priv *priv = c->priv;
 477         struct mlx5_core_dev *mdev = priv->mdev;
 478
 479         void *in;
 480         void *rqc;
 481         int inlen;
 482         int err;
 483
 484         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 485         in = mlx5_vzalloc(inlen);
 486         if (!in)
 487                 return -ENOMEM;
 488
 489         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 490
 491         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 492         MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
 493         MLX5_SET(rqc, rqc, vsd, vsd);
 494         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 495
 496         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 497
 498         kvfree(in);
 499
 500         return err;
 501 }
 502
 503 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 504 {
 505         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 506 }
 507
 508 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 509 {
 510         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 511         struct mlx5e_channel *c = rq->channel;
 512         struct mlx5e_priv *priv = c->priv;
 513         struct mlx5_wq_ll *wq = &rq->wq;
 514
 515         while (time_before(jiffies, exp_time)) {
 516                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 517                         return 0;
 518
 519                 msleep(20);
 520         }
 521
 522         return -ETIMEDOUT;
 523 }
 524
 525 static int mlx5e_open_rq(struct mlx5e_channel *c,
 526                          struct mlx5e_rq_param *param,
 527                          struct mlx5e_rq *rq)
 528 {
 529         struct mlx5e_sq *sq = &c->icosq;
 530         u16 pi = sq->pc & sq->wq.sz_m1;
 531         int err;
 532
 533         err = mlx5e_create_rq(c, param, rq);
 534         if (err)
 535                 return err;
 536
 537         err = mlx5e_enable_rq(rq, param);
 538         if (err)
 539                 goto err_destroy_rq;
 540
 541         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 542         if (err)
 543                 goto err_disable_rq;
 544
 545         if (param->am_enabled)
 546                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 547
 548         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 549
 550         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 551         sq->ico_wqe_info[pi].num_wqebbs = 1;
 552         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 553
 554         return 0;
 555
 556 err_disable_rq:
 557         mlx5e_disable_rq(rq);
 558 err_destroy_rq:
 559         mlx5e_destroy_rq(rq);
 560
 561         return err;
 562 }
 563
 564 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 565 {
 566         int tout = 0;
 567         int err;
 568
 569         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 570         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 571
 572         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 573         while (!mlx5_wq_ll_is_empty(&rq->wq) && !err &&
 574                tout++ < MLX5_EN_QP_FLUSH_MAX_ITER)
 575                 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
 576
 577         if (err || tout == MLX5_EN_QP_FLUSH_MAX_ITER)
 578                 set_bit(MLX5E_RQ_STATE_FLUSH_TIMEOUT, &rq->state);
 579
 580         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 581         napi_synchronize(&rq->channel->napi);
 582
 583         cancel_work_sync(&rq->am.work);
 584
 585         mlx5e_disable_rq(rq);
 586         mlx5e_free_rx_descs(rq);
 587         mlx5e_destroy_rq(rq);
 588 }
 589
 590 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 591 {
 592         kfree(sq->wqe_info);
 593         kfree(sq->dma_fifo);
 594         kfree(sq->skb);
 595 }
 596
 597 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 598 {
 599         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 600         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 601
 602         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 603         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 604                                     numa);
 605         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 606                                     numa);
 607
 608         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 609                 mlx5e_free_sq_db(sq);
 610                 return -ENOMEM;
 611         }
 612
 613         sq->dma_fifo_mask = df_sz - 1;
 614
 615         return 0;
 616 }
 617
 618 static int mlx5e_create_sq(struct mlx5e_channel *c,
 619                            int tc,
 620                            struct mlx5e_sq_param *param,
 621                            struct mlx5e_sq *sq)
 622 {
 623         struct mlx5e_priv *priv = c->priv;
 624         struct mlx5_core_dev *mdev = priv->mdev;
 625
 626         void *sqc = param->sqc;
 627         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 628         int err;
 629
 630         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 631         if (err)
 632                 return err;
 633
 634         param->wq.db_numa_node = cpu_to_node(c->cpu);
 635
 636         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 637                                  &sq->wq_ctrl);
 638         if (err)
 639                 goto err_unmap_free_uar;
 640
 641         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 642         if (sq->uar.bf_map) {
 643                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 644                 sq->uar_map = sq->uar.bf_map;
 645         } else {
 646                 sq->uar_map = sq->uar.map;
 647         }
 648         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 649         sq->max_inline  = param->max_inline;
 650         sq->min_inline_mode =
 651                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
 652                 param->min_inline_mode : 0;
 653
 654         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 655         if (err)
 656                 goto err_sq_wq_destroy;
 657
 658         if (param->icosq) {
 659                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 660
 661                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 662                                                 wq_sz,
 663                                                 GFP_KERNEL,
 664                                                 cpu_to_node(c->cpu));
 665                 if (!sq->ico_wqe_info) {
 666                         err = -ENOMEM;
 667                         goto err_free_sq_db;
 668                 }
 669         } else {
 670                 int txq_ix;
 671
 672                 txq_ix = c->ix + tc * priv->params.num_channels;
 673                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 674                 priv->txq_to_sq_map[txq_ix] = sq;
 675         }
 676
 677         sq->pdev      = c->pdev;
 678         sq->tstamp    = &priv->tstamp;
 679         sq->mkey_be   = c->mkey_be;
 680         sq->channel   = c;
 681         sq->tc        = tc;
 682         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 683         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 684
 685         return 0;
 686
 687 err_free_sq_db:
 688         mlx5e_free_sq_db(sq);
 689
 690 err_sq_wq_destroy:
 691         mlx5_wq_destroy(&sq->wq_ctrl);
 692
 693 err_unmap_free_uar:
 694         mlx5_unmap_free_uar(mdev, &sq->uar);
 695
 696         return err;
 697 }
 698
 699 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 700 {
 701         struct mlx5e_channel *c = sq->channel;
 702         struct mlx5e_priv *priv = c->priv;
 703
 704         kfree(sq->ico_wqe_info);
 705         mlx5e_free_sq_db(sq);
 706         mlx5_wq_destroy(&sq->wq_ctrl);
 707         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 708 }
 709
 710 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 711 {
 712         struct mlx5e_channel *c = sq->channel;
 713         struct mlx5e_priv *priv = c->priv;
 714         struct mlx5_core_dev *mdev = priv->mdev;
 715
 716         void *in;
 717         void *sqc;
 718         void *wq;
 719         int inlen;
 720         int err;
 721
 722         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 723                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 724         in = mlx5_vzalloc(inlen);
 725         if (!in)
 726                 return -ENOMEM;
 727
 728         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 729         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 730
 731         memcpy(sqc, param->sqc, sizeof(param->sqc));
 732
 733         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 734         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 735         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
 736         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 737         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 738         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 739
 740         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 741         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 742         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 743                                           MLX5_ADAPTER_PAGE_SHIFT);
 744         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 745
 746         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 747                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 748
 749         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 750
 751         kvfree(in);
 752
 753         return err;
 754 }
 755
 756 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
 757                            int next_state, bool update_rl, int rl_index)
 758 {
 759         struct mlx5e_channel *c = sq->channel;
 760         struct mlx5e_priv *priv = c->priv;
 761         struct mlx5_core_dev *mdev = priv->mdev;
 762
 763         void *in;
 764         void *sqc;
 765         int inlen;
 766         int err;
 767
 768         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 769         in = mlx5_vzalloc(inlen);
 770         if (!in)
 771                 return -ENOMEM;
 772
 773         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 774
 775         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 776         MLX5_SET(sqc, sqc, state, next_state);
 777         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
 778                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
 779                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
 780         }
 781
 782         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 783
 784         kvfree(in);
 785
 786         return err;
 787 }
 788
 789 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 790 {
 791         struct mlx5e_channel *c = sq->channel;
 792         struct mlx5e_priv *priv = c->priv;
 793         struct mlx5_core_dev *mdev = priv->mdev;
 794
 795         mlx5_core_destroy_sq(mdev, sq->sqn);
 796         if (sq->rate_limit)
 797                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
 798 }
 799
 800 static int mlx5e_open_sq(struct mlx5e_channel *c,
 801                          int tc,
 802                          struct mlx5e_sq_param *param,
 803                          struct mlx5e_sq *sq)
 804 {
 805         int err;
 806
 807         err = mlx5e_create_sq(c, tc, param, sq);
 808         if (err)
 809                 return err;
 810
 811         err = mlx5e_enable_sq(sq, param);
 812         if (err)
 813                 goto err_destroy_sq;
 814
 815         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
 816                               false, 0);
 817         if (err)
 818                 goto err_disable_sq;
 819
 820         if (sq->txq) {
 821                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 822                 netdev_tx_reset_queue(sq->txq);
 823                 netif_tx_start_queue(sq->txq);
 824         }
 825
 826         return 0;
 827
 828 err_disable_sq:
 829         mlx5e_disable_sq(sq);
 830 err_destroy_sq:
 831         mlx5e_destroy_sq(sq);
 832
 833         return err;
 834 }
 835
 836 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 837 {
 838         __netif_tx_lock_bh(txq);
 839         netif_tx_stop_queue(txq);
 840         __netif_tx_unlock_bh(txq);
 841 }
 842
 843 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 844 {
 845         int tout = 0;
 846         int err;
 847
 848         if (sq->txq) {
 849                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 850                 /* prevent netif_tx_wake_queue */
 851                 napi_synchronize(&sq->channel->napi);
 852                 netif_tx_disable_queue(sq->txq);
 853
 854                 /* ensure hw is notified of all pending wqes */
 855                 if (mlx5e_sq_has_room_for(sq, 1))
 856                         mlx5e_send_nop(sq, true);
 857
 858                 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
 859                                       MLX5_SQC_STATE_ERR, false, 0);
 860                 if (err)
 861                         set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
 862         }
 863
 864         /* wait till sq is empty, unless a TX timeout occurred on this SQ */
 865         while (sq->cc != sq->pc &&
 866                !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) {
 867                 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
 868                 if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER)
 869                         set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
 870         }
 871
 872         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 873         napi_synchronize(&sq->channel->napi);
 874
 875         mlx5e_free_tx_descs(sq);
 876         mlx5e_disable_sq(sq);
 877         mlx5e_destroy_sq(sq);
 878 }
 879
 880 static int mlx5e_create_cq(struct mlx5e_channel *c,
 881                            struct mlx5e_cq_param *param,
 882                            struct mlx5e_cq *cq)
 883 {
 884         struct mlx5e_priv *priv = c->priv;
 885         struct mlx5_core_dev *mdev = priv->mdev;
 886         struct mlx5_core_cq *mcq = &cq->mcq;
 887         int eqn_not_used;
 888         unsigned int irqn;
 889         int err;
 890         u32 i;
 891
 892         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 893         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 894         param->eq_ix   = c->ix;
 895
 896         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 897                                &cq->wq_ctrl);
 898         if (err)
 899                 return err;
 900
 901         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 902
 903         cq->napi        = &c->napi;
 904
 905         mcq->cqe_sz     = 64;
 906         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 907         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 908         *mcq->set_ci_db = 0;
 909         *mcq->arm_db    = 0;
 910         mcq->vector     = param->eq_ix;
 911         mcq->comp       = mlx5e_completion_event;
 912         mcq->event      = mlx5e_cq_error_event;
 913         mcq->irqn       = irqn;
 914         mcq->uar        = &mdev->mlx5e_res.cq_uar;
 915
 916         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 917                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 918
 919                 cqe->op_own = 0xf1;
 920         }
 921
 922         cq->channel = c;
 923         cq->priv = priv;
 924
 925         return 0;
 926 }
 927
 928 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 929 {
 930         mlx5_wq_destroy(&cq->wq_ctrl);
 931 }
 932
 933 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 934 {
 935         struct mlx5e_priv *priv = cq->priv;
 936         struct mlx5_core_dev *mdev = priv->mdev;
 937         struct mlx5_core_cq *mcq = &cq->mcq;
 938
 939         void *in;
 940         void *cqc;
 941         int inlen;
 942         unsigned int irqn_not_used;
 943         int eqn;
 944         int err;
 945
 946         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 947                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 948         in = mlx5_vzalloc(inlen);
 949         if (!in)
 950                 return -ENOMEM;
 951
 952         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 953
 954         memcpy(cqc, param->cqc, sizeof(param->cqc));
 955
 956         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 957                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 958
 959         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 960
 961         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
 962         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 963         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 964         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 965                                             MLX5_ADAPTER_PAGE_SHIFT);
 966         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 967
 968         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 969
 970         kvfree(in);
 971
 972         if (err)
 973                 return err;
 974
 975         mlx5e_cq_arm(cq);
 976
 977         return 0;
 978 }
 979
 980 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 981 {
 982         struct mlx5e_priv *priv = cq->priv;
 983         struct mlx5_core_dev *mdev = priv->mdev;
 984
 985         mlx5_core_destroy_cq(mdev, &cq->mcq);
 986 }
 987
 988 static int mlx5e_open_cq(struct mlx5e_channel *c,
 989                          struct mlx5e_cq_param *param,
 990                          struct mlx5e_cq *cq,
 991                          struct mlx5e_cq_moder moderation)
 992 {
 993         int err;
 994         struct mlx5e_priv *priv = c->priv;
 995         struct mlx5_core_dev *mdev = priv->mdev;
 996
 997         err = mlx5e_create_cq(c, param, cq);
 998         if (err)
 999                 return err;
1000
1001         err = mlx5e_enable_cq(cq, param);
1002         if (err)
1003                 goto err_destroy_cq;
1004
1005         if (MLX5_CAP_GEN(mdev, cq_moderation))
1006                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1007                                                moderation.usec,
1008                                                moderation.pkts);
1009         return 0;
1010
1011 err_destroy_cq:
1012         mlx5e_destroy_cq(cq);
1013
1014         return err;
1015 }
1016
1017 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1018 {
1019         mlx5e_disable_cq(cq);
1020         mlx5e_destroy_cq(cq);
1021 }
1022
1023 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1024 {
1025         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1026 }
1027
1028 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1029                              struct mlx5e_channel_param *cparam)
1030 {
1031         struct mlx5e_priv *priv = c->priv;
1032         int err;
1033         int tc;
1034
1035         for (tc = 0; tc < c->num_tc; tc++) {
1036                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1037                                     priv->params.tx_cq_moderation);
1038                 if (err)
1039                         goto err_close_tx_cqs;
1040         }
1041
1042         return 0;
1043
1044 err_close_tx_cqs:
1045         for (tc--; tc >= 0; tc--)
1046                 mlx5e_close_cq(&c->sq[tc].cq);
1047
1048         return err;
1049 }
1050
1051 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1052 {
1053         int tc;
1054
1055         for (tc = 0; tc < c->num_tc; tc++)
1056                 mlx5e_close_cq(&c->sq[tc].cq);
1057 }
1058
1059 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1060                           struct mlx5e_channel_param *cparam)
1061 {
1062         int err;
1063         int tc;
1064
1065         for (tc = 0; tc < c->num_tc; tc++) {
1066                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1067                 if (err)
1068                         goto err_close_sqs;
1069         }
1070
1071         return 0;
1072
1073 err_close_sqs:
1074         for (tc--; tc >= 0; tc--)
1075                 mlx5e_close_sq(&c->sq[tc]);
1076
1077         return err;
1078 }
1079
1080 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1081 {
1082         int tc;
1083
1084         for (tc = 0; tc < c->num_tc; tc++)
1085                 mlx5e_close_sq(&c->sq[tc]);
1086 }
1087
1088 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1089 {
1090         int i;
1091
1092         for (i = 0; i < priv->profile->max_tc; i++)
1093                 priv->channeltc_to_txq_map[ix][i] =
1094                         ix + i * priv->params.num_channels;
1095 }
1096
1097 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1098                                 struct mlx5e_sq *sq, u32 rate)
1099 {
1100         struct mlx5e_priv *priv = netdev_priv(dev);
1101         struct mlx5_core_dev *mdev = priv->mdev;
1102         u16 rl_index = 0;
1103         int err;
1104
1105         if (rate == sq->rate_limit)
1106                 /* nothing to do */
1107                 return 0;
1108
1109         if (sq->rate_limit)
1110                 /* remove current rl index to free space to next ones */
1111                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1112
1113         sq->rate_limit = 0;
1114
1115         if (rate) {
1116                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1117                 if (err) {
1118                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1119                                    rate, err);
1120                         return err;
1121                 }
1122         }
1123
1124         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1125                               MLX5_SQC_STATE_RDY, true, rl_index);
1126         if (err) {
1127                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1128                            rate, err);
1129                 /* remove the rate from the table */
1130                 if (rate)
1131                         mlx5_rl_remove_rate(mdev, rate);
1132                 return err;
1133         }
1134
1135         sq->rate_limit = rate;
1136         return 0;
1137 }
1138
1139 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1140 {
1141         struct mlx5e_priv *priv = netdev_priv(dev);
1142         struct mlx5_core_dev *mdev = priv->mdev;
1143         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1144         int err = 0;
1145
1146         if (!mlx5_rl_is_supported(mdev)) {
1147                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1148                 return -EINVAL;
1149         }
1150
1151         /* rate is given in Mb/sec, HW config is in Kb/sec */
1152         rate = rate << 10;
1153
1154         /* Check whether rate in valid range, 0 is always valid */
1155         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1156                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1157                 return -ERANGE;
1158         }
1159
1160         mutex_lock(&priv->state_lock);
1161         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1162                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1163         if (!err)
1164                 priv->tx_rates[index] = rate;
1165         mutex_unlock(&priv->state_lock);
1166
1167         return err;
1168 }
1169
1170 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1171                               struct mlx5e_channel_param *cparam,
1172                               struct mlx5e_channel **cp)
1173 {
1174         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1175         struct net_device *netdev = priv->netdev;
1176         struct mlx5e_cq_moder rx_cq_profile;
1177         int cpu = mlx5e_get_cpu(priv, ix);
1178         struct mlx5e_channel *c;
1179         struct mlx5e_sq *sq;
1180         int err;
1181         int i;
1182
1183         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1184         if (!c)
1185                 return -ENOMEM;
1186
1187         c->priv     = priv;
1188         c->ix       = ix;
1189         c->cpu      = cpu;
1190         c->pdev     = &priv->mdev->pdev->dev;
1191         c->netdev   = priv->netdev;
1192         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1193         c->num_tc   = priv->params.num_tc;
1194
1195         if (priv->params.rx_am_enabled)
1196                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1197         else
1198                 rx_cq_profile = priv->params.rx_cq_moderation;
1199
1200         mlx5e_build_channeltc_to_txq_map(priv, ix);
1201
1202         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1203
1204         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1205         if (err)
1206                 goto err_napi_del;
1207
1208         err = mlx5e_open_tx_cqs(c, cparam);
1209         if (err)
1210                 goto err_close_icosq_cq;
1211
1212         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1213                             rx_cq_profile);
1214         if (err)
1215                 goto err_close_tx_cqs;
1216
1217         napi_enable(&c->napi);
1218
1219         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1220         if (err)
1221                 goto err_disable_napi;
1222
1223         err = mlx5e_open_sqs(c, cparam);
1224         if (err)
1225                 goto err_close_icosq;
1226
1227         for (i = 0; i < priv->params.num_tc; i++) {
1228                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1229
1230                 if (priv->tx_rates[txq_ix]) {
1231                         sq = priv->txq_to_sq_map[txq_ix];
1232                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1233                                              priv->tx_rates[txq_ix]);
1234                 }
1235         }
1236
1237         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1238         if (err)
1239                 goto err_close_sqs;
1240
1241         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1242         *cp = c;
1243
1244         return 0;
1245
1246 err_close_sqs:
1247         mlx5e_close_sqs(c);
1248
1249 err_close_icosq:
1250         mlx5e_close_sq(&c->icosq);
1251
1252 err_disable_napi:
1253         napi_disable(&c->napi);
1254         mlx5e_close_cq(&c->rq.cq);
1255
1256 err_close_tx_cqs:
1257         mlx5e_close_tx_cqs(c);
1258
1259 err_close_icosq_cq:
1260         mlx5e_close_cq(&c->icosq.cq);
1261
1262 err_napi_del:
1263         netif_napi_del(&c->napi);
1264         napi_hash_del(&c->napi);
1265         kfree(c);
1266
1267         return err;
1268 }
1269
1270 static void mlx5e_close_channel(struct mlx5e_channel *c)
1271 {
1272         mlx5e_close_rq(&c->rq);
1273         mlx5e_close_sqs(c);
1274         mlx5e_close_sq(&c->icosq);
1275         napi_disable(&c->napi);
1276         mlx5e_close_cq(&c->rq.cq);
1277         mlx5e_close_tx_cqs(c);
1278         mlx5e_close_cq(&c->icosq.cq);
1279         netif_napi_del(&c->napi);
1280
1281         napi_hash_del(&c->napi);
1282         synchronize_rcu();
1283
1284         kfree(c);
1285 }
1286
1287 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1288                                  struct mlx5e_rq_param *param)
1289 {
1290         void *rqc = param->rqc;
1291         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1292
1293         switch (priv->params.rq_wq_type) {
1294         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1295                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1296                          priv->params.mpwqe_log_num_strides - 9);
1297                 MLX5_SET(wq, wq, log_wqe_stride_size,
1298                          priv->params.mpwqe_log_stride_sz - 6);
1299                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1300                 break;
1301         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1302                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1303         }
1304
1305         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1306         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1307         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1308         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1309         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1310
1311         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1312         param->wq.linear = 1;
1313
1314         param->am_enabled = priv->params.rx_am_enabled;
1315 }
1316
1317 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1318 {
1319         void *rqc = param->rqc;
1320         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1321
1322         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1323         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1324 }
1325
1326 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1327                                         struct mlx5e_sq_param *param)
1328 {
1329         void *sqc = param->sqc;
1330         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1331
1332         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1333         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1334
1335         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1336 }
1337
1338 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1339                                  struct mlx5e_sq_param *param)
1340 {
1341         void *sqc = param->sqc;
1342         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1343
1344         mlx5e_build_sq_param_common(priv, param);
1345         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1346
1347         param->max_inline = priv->params.tx_max_inline;
1348         param->min_inline_mode = priv->params.tx_min_inline_mode;
1349 }
1350
1351 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1352                                         struct mlx5e_cq_param *param)
1353 {
1354         void *cqc = param->cqc;
1355
1356         MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1357 }
1358
1359 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1360                                     struct mlx5e_cq_param *param)
1361 {
1362         void *cqc = param->cqc;
1363         u8 log_cq_size;
1364
1365         switch (priv->params.rq_wq_type) {
1366         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1367                 log_cq_size = priv->params.log_rq_size +
1368                         priv->params.mpwqe_log_num_strides;
1369                 break;
1370         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1371                 log_cq_size = priv->params.log_rq_size;
1372         }
1373
1374         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1375         if (priv->params.rx_cqe_compress) {
1376                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1377                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1378         }
1379
1380         mlx5e_build_common_cq_param(priv, param);
1381
1382         param->cq_period_mode = priv->params.rx_cq_period_mode;
1383 }
1384
1385 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1386                                     struct mlx5e_cq_param *param)
1387 {
1388         void *cqc = param->cqc;
1389
1390         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1391
1392         mlx5e_build_common_cq_param(priv, param);
1393
1394         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1395 }
1396
1397 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1398                                      struct mlx5e_cq_param *param,
1399                                      u8 log_wq_size)
1400 {
1401         void *cqc = param->cqc;
1402
1403         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1404
1405         mlx5e_build_common_cq_param(priv, param);
1406
1407         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1408 }
1409
1410 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1411                                     struct mlx5e_sq_param *param,
1412                                     u8 log_wq_size)
1413 {
1414         void *sqc = param->sqc;
1415         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1416
1417         mlx5e_build_sq_param_common(priv, param);
1418
1419         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1420         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1421
1422         param->icosq = true;
1423 }
1424
1425 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1426 {
1427         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1428
1429         mlx5e_build_rq_param(priv, &cparam->rq);
1430         mlx5e_build_sq_param(priv, &cparam->sq);
1431         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1432         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1433         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1434         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1435 }
1436
1437 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1438 {
1439         struct mlx5e_channel_param *cparam;
1440         int nch = priv->params.num_channels;
1441         int err = -ENOMEM;
1442         int i;
1443         int j;
1444
1445         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1446                                 GFP_KERNEL);
1447
1448         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1449                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1450
1451         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1452
1453         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1454                 goto err_free_txq_to_sq_map;
1455
1456         mlx5e_build_channel_param(priv, cparam);
1457
1458         for (i = 0; i < nch; i++) {
1459                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1460                 if (err)
1461                         goto err_close_channels;
1462         }
1463
1464         for (j = 0; j < nch; j++) {
1465                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1466                 if (err)
1467                         goto err_close_channels;
1468         }
1469
1470         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1471          * polling for inactive tx queues.
1472          */
1473         netif_tx_start_all_queues(priv->netdev);
1474
1475         kfree(cparam);
1476         return 0;
1477
1478 err_close_channels:
1479         for (i--; i >= 0; i--)
1480                 mlx5e_close_channel(priv->channel[i]);
1481
1482 err_free_txq_to_sq_map:
1483         kfree(priv->txq_to_sq_map);
1484         kfree(priv->channel);
1485         kfree(cparam);
1486
1487         return err;
1488 }
1489
1490 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1491 {
1492         int i;
1493
1494         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1495          * polling for inactive tx queues.
1496          */
1497         netif_tx_stop_all_queues(priv->netdev);
1498         netif_tx_disable(priv->netdev);
1499
1500         for (i = 0; i < priv->params.num_channels; i++)
1501                 mlx5e_close_channel(priv->channel[i]);
1502
1503         kfree(priv->txq_to_sq_map);
1504         kfree(priv->channel);
1505 }
1506
1507 static int mlx5e_rx_hash_fn(int hfunc)
1508 {
1509         return (hfunc == ETH_RSS_HASH_TOP) ?
1510                MLX5_RX_HASH_FN_TOEPLITZ :
1511                MLX5_RX_HASH_FN_INVERTED_XOR8;
1512 }
1513
1514 static int mlx5e_bits_invert(unsigned long a, int size)
1515 {
1516         int inv = 0;
1517         int i;
1518
1519         for (i = 0; i < size; i++)
1520                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1521
1522         return inv;
1523 }
1524
1525 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1526 {
1527         int i;
1528
1529         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1530                 int ix = i;
1531                 u32 rqn;
1532
1533                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1534                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1535
1536                 ix = priv->params.indirection_rqt[ix];
1537                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1538                                 priv->channel[ix]->rq.rqn :
1539                                 priv->drop_rq.rqn;
1540                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1541         }
1542 }
1543
1544 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1545                                       int ix)
1546 {
1547         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1548                         priv->channel[ix]->rq.rqn :
1549                         priv->drop_rq.rqn;
1550
1551         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1552 }
1553
1554 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1555                             int ix, struct mlx5e_rqt *rqt)
1556 {
1557         struct mlx5_core_dev *mdev = priv->mdev;
1558         void *rqtc;
1559         int inlen;
1560         int err;
1561         u32 *in;
1562
1563         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1564         in = mlx5_vzalloc(inlen);
1565         if (!in)
1566                 return -ENOMEM;
1567
1568         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1569
1570         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1571         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1572
1573         if (sz > 1) /* RSS */
1574                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1575         else
1576                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1577
1578         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1579         if (!err)
1580                 rqt->enabled = true;
1581
1582         kvfree(in);
1583         return err;
1584 }
1585
1586 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1587 {
1588         rqt->enabled = false;
1589         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1590 }
1591
1592 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1593 {
1594         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1595
1596         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1597 }
1598
1599 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1600 {
1601         struct mlx5e_rqt *rqt;
1602         int err;
1603         int ix;
1604
1605         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1606                 rqt = &priv->direct_tir[ix].rqt;
1607                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1608                 if (err)
1609                         goto err_destroy_rqts;
1610         }
1611
1612         return 0;
1613
1614 err_destroy_rqts:
1615         for (ix--; ix >= 0; ix--)
1616                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1617
1618         return err;
1619 }
1620
1621 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1622 {
1623         struct mlx5_core_dev *mdev = priv->mdev;
1624         void *rqtc;
1625         int inlen;
1626         u32 *in;
1627         int err;
1628
1629         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1630         in = mlx5_vzalloc(inlen);
1631         if (!in)
1632                 return -ENOMEM;
1633
1634         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1635
1636         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1637         if (sz > 1) /* RSS */
1638                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1639         else
1640                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1641
1642         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1643
1644         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1645
1646         kvfree(in);
1647
1648         return err;
1649 }
1650
1651 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1652 {
1653         u32 rqtn;
1654         int ix;
1655
1656         if (priv->indir_rqt.enabled) {
1657                 rqtn = priv->indir_rqt.rqtn;
1658                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1659         }
1660
1661         for (ix = 0; ix < priv->params.num_channels; ix++) {
1662                 if (!priv->direct_tir[ix].rqt.enabled)
1663                         continue;
1664                 rqtn = priv->direct_tir[ix].rqt.rqtn;
1665                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1666         }
1667 }
1668
1669 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1670 {
1671         if (!priv->params.lro_en)
1672                 return;
1673
1674 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1675
1676         MLX5_SET(tirc, tirc, lro_enable_mask,
1677                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1678                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1679         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1680                  (priv->params.lro_wqe_sz -
1681                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1682         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1683                  MLX5_CAP_ETH(priv->mdev,
1684                               lro_timer_supported_periods[2]));
1685 }
1686
1687 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1688 {
1689         MLX5_SET(tirc, tirc, rx_hash_fn,
1690                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1691         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1692                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1693                                              rx_hash_toeplitz_key);
1694                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1695                                                rx_hash_toeplitz_key);
1696
1697                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1698                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1699         }
1700 }
1701
1702 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1703 {
1704         struct mlx5_core_dev *mdev = priv->mdev;
1705
1706         void *in;
1707         void *tirc;
1708         int inlen;
1709         int err;
1710         int tt;
1711         int ix;
1712
1713         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1714         in = mlx5_vzalloc(inlen);
1715         if (!in)
1716                 return -ENOMEM;
1717
1718         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1719         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1720
1721         mlx5e_build_tir_ctx_lro(tirc, priv);
1722
1723         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1724                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1725                                            inlen);
1726                 if (err)
1727                         goto free_in;
1728         }
1729
1730         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1731                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1732                                            in, inlen);
1733                 if (err)
1734                         goto free_in;
1735         }
1736
1737 free_in:
1738         kvfree(in);
1739
1740         return err;
1741 }
1742
1743 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1744 {
1745         struct mlx5_core_dev *mdev = priv->mdev;
1746         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1747         int err;
1748
1749         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1750         if (err)
1751                 return err;
1752
1753         /* Update vport context MTU */
1754         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1755         return 0;
1756 }
1757
1758 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1759 {
1760         struct mlx5_core_dev *mdev = priv->mdev;
1761         u16 hw_mtu = 0;
1762         int err;
1763
1764         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1765         if (err || !hw_mtu) /* fallback to port oper mtu */
1766                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1767
1768         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1769 }
1770
1771 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1772 {
1773         struct mlx5e_priv *priv = netdev_priv(netdev);
1774         u16 mtu;
1775         int err;
1776
1777         err = mlx5e_set_mtu(priv, netdev->mtu);
1778         if (err)
1779                 return err;
1780
1781         mlx5e_query_mtu(priv, &mtu);
1782         if (mtu != netdev->mtu)
1783                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1784                             __func__, mtu, netdev->mtu);
1785
1786         netdev->mtu = mtu;
1787         return 0;
1788 }
1789
1790 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1791 {
1792         struct mlx5e_priv *priv = netdev_priv(netdev);
1793         int nch = priv->params.num_channels;
1794         int ntc = priv->params.num_tc;
1795         int tc;
1796
1797         netdev_reset_tc(netdev);
1798
1799         if (ntc == 1)
1800                 return;
1801
1802         netdev_set_num_tc(netdev, ntc);
1803
1804         /* Map netdev TCs to offset 0
1805          * We have our own UP to TXQ mapping for QoS
1806          */
1807         for (tc = 0; tc < ntc; tc++)
1808                 netdev_set_tc_queue(netdev, tc, nch, 0);
1809 }
1810
1811 int mlx5e_open_locked(struct net_device *netdev)
1812 {
1813         struct mlx5e_priv *priv = netdev_priv(netdev);
1814         struct mlx5_core_dev *mdev = priv->mdev;
1815         int num_txqs;
1816         int err;
1817
1818         set_bit(MLX5E_STATE_OPENED, &priv->state);
1819
1820         mlx5e_netdev_set_tcs(netdev);
1821
1822         num_txqs = priv->params.num_channels * priv->params.num_tc;
1823         netif_set_real_num_tx_queues(netdev, num_txqs);
1824         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1825
1826         err = mlx5e_set_dev_port_mtu(netdev);
1827         if (err)
1828                 goto err_clear_state_opened_flag;
1829
1830         err = mlx5e_open_channels(priv);
1831         if (err) {
1832                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1833                            __func__, err);
1834                 goto err_clear_state_opened_flag;
1835         }
1836
1837         err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
1838         if (err) {
1839                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1840                            __func__, err);
1841                 goto err_close_channels;
1842         }
1843
1844         mlx5e_redirect_rqts(priv);
1845         mlx5e_update_carrier(priv);
1846         mlx5e_timestamp_init(priv);
1847 #ifdef CONFIG_RFS_ACCEL
1848         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1849 #endif
1850         if (priv->profile->update_stats)
1851                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1852
1853         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
1854                 err = mlx5e_add_sqs_fwd_rules(priv);
1855                 if (err)
1856                         goto err_close_channels;
1857         }
1858         return 0;
1859
1860 err_close_channels:
1861         mlx5e_close_channels(priv);
1862 err_clear_state_opened_flag:
1863         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1864         return err;
1865 }
1866
1867 int mlx5e_open(struct net_device *netdev)
1868 {
1869         struct mlx5e_priv *priv = netdev_priv(netdev);
1870         int err;
1871
1872         mutex_lock(&priv->state_lock);
1873         err = mlx5e_open_locked(netdev);
1874         mutex_unlock(&priv->state_lock);
1875
1876         return err;
1877 }
1878
1879 int mlx5e_close_locked(struct net_device *netdev)
1880 {
1881         struct mlx5e_priv *priv = netdev_priv(netdev);
1882         struct mlx5_core_dev *mdev = priv->mdev;
1883
1884         /* May already be CLOSED in case a previous configuration operation
1885          * (e.g RX/TX queue size change) that involves close&open failed.
1886          */
1887         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1888                 return 0;
1889
1890         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1891
1892         if (MLX5_CAP_GEN(mdev, vport_group_manager))
1893                 mlx5e_remove_sqs_fwd_rules(priv);
1894
1895         mlx5e_timestamp_cleanup(priv);
1896         netif_carrier_off(priv->netdev);
1897         mlx5e_redirect_rqts(priv);
1898         mlx5e_close_channels(priv);
1899
1900         return 0;
1901 }
1902
1903 int mlx5e_close(struct net_device *netdev)
1904 {
1905         struct mlx5e_priv *priv = netdev_priv(netdev);
1906         int err;
1907
1908         mutex_lock(&priv->state_lock);
1909         err = mlx5e_close_locked(netdev);
1910         mutex_unlock(&priv->state_lock);
1911
1912         return err;
1913 }
1914
1915 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1916                                 struct mlx5e_rq *rq,
1917                                 struct mlx5e_rq_param *param)
1918 {
1919         struct mlx5_core_dev *mdev = priv->mdev;
1920         void *rqc = param->rqc;
1921         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1922         int err;
1923
1924         param->wq.db_numa_node = param->wq.buf_numa_node;
1925
1926         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1927                                 &rq->wq_ctrl);
1928         if (err)
1929                 return err;
1930
1931         rq->priv = priv;
1932
1933         return 0;
1934 }
1935
1936 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1937                                 struct mlx5e_cq *cq,
1938                                 struct mlx5e_cq_param *param)
1939 {
1940         struct mlx5_core_dev *mdev = priv->mdev;
1941         struct mlx5_core_cq *mcq = &cq->mcq;
1942         int eqn_not_used;
1943         unsigned int irqn;
1944         int err;
1945
1946         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1947                                &cq->wq_ctrl);
1948         if (err)
1949                 return err;
1950
1951         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1952
1953         mcq->cqe_sz     = 64;
1954         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1955         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1956         *mcq->set_ci_db = 0;
1957         *mcq->arm_db    = 0;
1958         mcq->vector     = param->eq_ix;
1959         mcq->comp       = mlx5e_completion_event;
1960         mcq->event      = mlx5e_cq_error_event;
1961         mcq->irqn       = irqn;
1962         mcq->uar        = &mdev->mlx5e_res.cq_uar;
1963
1964         cq->priv = priv;
1965
1966         return 0;
1967 }
1968
1969 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1970 {
1971         struct mlx5e_cq_param cq_param;
1972         struct mlx5e_rq_param rq_param;
1973         struct mlx5e_rq *rq = &priv->drop_rq;
1974         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1975         int err;
1976
1977         memset(&cq_param, 0, sizeof(cq_param));
1978         memset(&rq_param, 0, sizeof(rq_param));
1979         mlx5e_build_drop_rq_param(&rq_param);
1980
1981         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1982         if (err)
1983                 return err;
1984
1985         err = mlx5e_enable_cq(cq, &cq_param);
1986         if (err)
1987                 goto err_destroy_cq;
1988
1989         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1990         if (err)
1991                 goto err_disable_cq;
1992
1993         err = mlx5e_enable_rq(rq, &rq_param);
1994         if (err)
1995                 goto err_destroy_rq;
1996
1997         return 0;
1998
1999 err_destroy_rq:
2000         mlx5e_destroy_rq(&priv->drop_rq);
2001
2002 err_disable_cq:
2003         mlx5e_disable_cq(&priv->drop_rq.cq);
2004
2005 err_destroy_cq:
2006         mlx5e_destroy_cq(&priv->drop_rq.cq);
2007
2008         return err;
2009 }
2010
2011 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2012 {
2013         mlx5e_disable_rq(&priv->drop_rq);
2014         mlx5e_destroy_rq(&priv->drop_rq);
2015         mlx5e_disable_cq(&priv->drop_rq.cq);
2016         mlx5e_destroy_cq(&priv->drop_rq.cq);
2017 }
2018
2019 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2020 {
2021         struct mlx5_core_dev *mdev = priv->mdev;
2022         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2023         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2024
2025         MLX5_SET(tisc, tisc, prio, tc << 1);
2026         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2027         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2028 }
2029
2030 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2031 {
2032         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2033 }
2034
2035 int mlx5e_create_tises(struct mlx5e_priv *priv)
2036 {
2037         int err;
2038         int tc;
2039
2040         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2041                 err = mlx5e_create_tis(priv, tc);
2042                 if (err)
2043                         goto err_close_tises;
2044         }
2045
2046         return 0;
2047
2048 err_close_tises:
2049         for (tc--; tc >= 0; tc--)
2050                 mlx5e_destroy_tis(priv, tc);
2051
2052         return err;
2053 }
2054
2055 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2056 {
2057         int tc;
2058
2059         for (tc = 0; tc < priv->profile->max_tc; tc++)
2060                 mlx5e_destroy_tis(priv, tc);
2061 }
2062
2063 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2064                                       enum mlx5e_traffic_types tt)
2065 {
2066         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2067
2068         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2069
2070 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2071                                  MLX5_HASH_FIELD_SEL_DST_IP)
2072
2073 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2074                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2075                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2076                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2077
2078 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2079                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2080                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2081
2082         mlx5e_build_tir_ctx_lro(tirc, priv);
2083
2084         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2085         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2086         mlx5e_build_tir_ctx_hash(tirc, priv);
2087
2088         switch (tt) {
2089         case MLX5E_TT_IPV4_TCP:
2090                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2091                          MLX5_L3_PROT_TYPE_IPV4);
2092                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2093                          MLX5_L4_PROT_TYPE_TCP);
2094                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2095                          MLX5_HASH_IP_L4PORTS);
2096                 break;
2097
2098         case MLX5E_TT_IPV6_TCP:
2099                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2100                          MLX5_L3_PROT_TYPE_IPV6);
2101                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2102                          MLX5_L4_PROT_TYPE_TCP);
2103                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2104                          MLX5_HASH_IP_L4PORTS);
2105                 break;
2106
2107         case MLX5E_TT_IPV4_UDP:
2108                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2109                          MLX5_L3_PROT_TYPE_IPV4);
2110                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2111                          MLX5_L4_PROT_TYPE_UDP);
2112                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2113                          MLX5_HASH_IP_L4PORTS);
2114                 break;
2115
2116         case MLX5E_TT_IPV6_UDP:
2117                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2118                          MLX5_L3_PROT_TYPE_IPV6);
2119                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2120                          MLX5_L4_PROT_TYPE_UDP);
2121                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2122                          MLX5_HASH_IP_L4PORTS);
2123                 break;
2124
2125         case MLX5E_TT_IPV4_IPSEC_AH:
2126                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2127                          MLX5_L3_PROT_TYPE_IPV4);
2128                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2129                          MLX5_HASH_IP_IPSEC_SPI);
2130                 break;
2131
2132         case MLX5E_TT_IPV6_IPSEC_AH:
2133                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2134                          MLX5_L3_PROT_TYPE_IPV6);
2135                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2136                          MLX5_HASH_IP_IPSEC_SPI);
2137                 break;
2138
2139         case MLX5E_TT_IPV4_IPSEC_ESP:
2140                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2141                          MLX5_L3_PROT_TYPE_IPV4);
2142                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2143                          MLX5_HASH_IP_IPSEC_SPI);
2144                 break;
2145
2146         case MLX5E_TT_IPV6_IPSEC_ESP:
2147                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2148                          MLX5_L3_PROT_TYPE_IPV6);
2149                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2150                          MLX5_HASH_IP_IPSEC_SPI);
2151                 break;
2152
2153         case MLX5E_TT_IPV4:
2154                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2155                          MLX5_L3_PROT_TYPE_IPV4);
2156                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2157                          MLX5_HASH_IP);
2158                 break;
2159
2160         case MLX5E_TT_IPV6:
2161                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2162                          MLX5_L3_PROT_TYPE_IPV6);
2163                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2164                          MLX5_HASH_IP);
2165                 break;
2166         default:
2167                 WARN_ONCE(true,
2168                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2169         }
2170 }
2171
2172 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2173                                        u32 rqtn)
2174 {
2175         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2176
2177         mlx5e_build_tir_ctx_lro(tirc, priv);
2178
2179         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2180         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2181         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2182 }
2183
2184 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2185 {
2186         struct mlx5e_tir *tir;
2187         void *tirc;
2188         int inlen;
2189         int err;
2190         u32 *in;
2191         int tt;
2192
2193         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2194         in = mlx5_vzalloc(inlen);
2195         if (!in)
2196                 return -ENOMEM;
2197
2198         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2199                 memset(in, 0, inlen);
2200                 tir = &priv->indir_tir[tt];
2201                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2202                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2203                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2204                 if (err)
2205                         goto err_destroy_tirs;
2206         }
2207
2208         kvfree(in);
2209
2210         return 0;
2211
2212 err_destroy_tirs:
2213         for (tt--; tt >= 0; tt--)
2214                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2215
2216         kvfree(in);
2217
2218         return err;
2219 }
2220
2221 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2222 {
2223         int nch = priv->profile->max_nch(priv->mdev);
2224         struct mlx5e_tir *tir;
2225         void *tirc;
2226         int inlen;
2227         int err;
2228         u32 *in;
2229         int ix;
2230
2231         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2232         in = mlx5_vzalloc(inlen);
2233         if (!in)
2234                 return -ENOMEM;
2235
2236         for (ix = 0; ix < nch; ix++) {
2237                 memset(in, 0, inlen);
2238                 tir = &priv->direct_tir[ix];
2239                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2240                 mlx5e_build_direct_tir_ctx(priv, tirc,
2241                                            priv->direct_tir[ix].rqt.rqtn);
2242                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2243                 if (err)
2244                         goto err_destroy_ch_tirs;
2245         }
2246
2247         kvfree(in);
2248
2249         return 0;
2250
2251 err_destroy_ch_tirs:
2252         for (ix--; ix >= 0; ix--)
2253                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2254
2255         kvfree(in);
2256
2257         return err;
2258 }
2259
2260 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2261 {
2262         int i;
2263
2264         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2265                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2266 }
2267
2268 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2269 {
2270         int nch = priv->profile->max_nch(priv->mdev);
2271         int i;
2272
2273         for (i = 0; i < nch; i++)
2274                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2275 }
2276
2277 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2278 {
2279         int err = 0;
2280         int i;
2281
2282         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2283                 return 0;
2284
2285         for (i = 0; i < priv->params.num_channels; i++) {
2286                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2287                 if (err)
2288                         return err;
2289         }
2290
2291         return 0;
2292 }
2293
2294 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2295 {
2296         struct mlx5e_priv *priv = netdev_priv(netdev);
2297         bool was_opened;
2298         int err = 0;
2299
2300         if (tc && tc != MLX5E_MAX_NUM_TC)
2301                 return -EINVAL;
2302
2303         mutex_lock(&priv->state_lock);
2304
2305         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2306         if (was_opened)
2307                 mlx5e_close_locked(priv->netdev);
2308
2309         priv->params.num_tc = tc ? tc : 1;
2310
2311         if (was_opened)
2312                 err = mlx5e_open_locked(priv->netdev);
2313
2314         mutex_unlock(&priv->state_lock);
2315
2316         return err;
2317 }
2318
2319 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2320                               __be16 proto, struct tc_to_netdev *tc)
2321 {
2322         struct mlx5e_priv *priv = netdev_priv(dev);
2323
2324         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2325                 goto mqprio;
2326
2327         switch (tc->type) {
2328         case TC_SETUP_CLSFLOWER:
2329                 switch (tc->cls_flower->command) {
2330                 case TC_CLSFLOWER_REPLACE:
2331                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2332                 case TC_CLSFLOWER_DESTROY:
2333                         return mlx5e_delete_flower(priv, tc->cls_flower);
2334                 case TC_CLSFLOWER_STATS:
2335                         return mlx5e_stats_flower(priv, tc->cls_flower);
2336                 }
2337         default:
2338                 return -EOPNOTSUPP;
2339         }
2340
2341 mqprio:
2342         if (tc->type != TC_SETUP_MQPRIO)
2343                 return -EINVAL;
2344
2345         return mlx5e_setup_tc(dev, tc->tc);
2346 }
2347
2348 struct rtnl_link_stats64 *
2349 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2350 {
2351         struct mlx5e_priv *priv = netdev_priv(dev);
2352         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2353         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2354         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2355
2356         stats->rx_packets = sstats->rx_packets;
2357         stats->rx_bytes   = sstats->rx_bytes;
2358         stats->tx_packets = sstats->tx_packets;
2359         stats->tx_bytes   = sstats->tx_bytes;
2360
2361         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2362         stats->tx_dropped = sstats->tx_queue_dropped;
2363
2364         stats->rx_length_errors =
2365                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2366                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2367                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2368         stats->rx_crc_errors =
2369                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2370         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2371         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2372         stats->tx_carrier_errors =
2373                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2374         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2375                            stats->rx_frame_errors;
2376         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2377
2378         /* vport multicast also counts packets that are dropped due to steering
2379          * or rx out of buffer
2380          */
2381         stats->multicast =
2382                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2383
2384         return stats;
2385 }
2386
2387 static void mlx5e_set_rx_mode(struct net_device *dev)
2388 {
2389         struct mlx5e_priv *priv = netdev_priv(dev);
2390
2391         queue_work(priv->wq, &priv->set_rx_mode_work);
2392 }
2393
2394 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2395 {
2396         struct mlx5e_priv *priv = netdev_priv(netdev);
2397         struct sockaddr *saddr = addr;
2398
2399         if (!is_valid_ether_addr(saddr->sa_data))
2400                 return -EADDRNOTAVAIL;
2401
2402         netif_addr_lock_bh(netdev);
2403         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2404         netif_addr_unlock_bh(netdev);
2405
2406         queue_work(priv->wq, &priv->set_rx_mode_work);
2407
2408         return 0;
2409 }
2410
2411 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2412         do {                                            \
2413                 if (enable)                             \
2414                         netdev->features |= feature;    \
2415                 else                                    \
2416                         netdev->features &= ~feature;   \
2417         } while (0)
2418
2419 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2420
2421 static int set_feature_lro(struct net_device *netdev, bool enable)
2422 {
2423         struct mlx5e_priv *priv = netdev_priv(netdev);
2424         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2425         int err;
2426
2427         mutex_lock(&priv->state_lock);
2428
2429         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2430                 mlx5e_close_locked(priv->netdev);
2431
2432         priv->params.lro_en = enable;
2433         err = mlx5e_modify_tirs_lro(priv);
2434         if (err) {
2435                 netdev_err(netdev, "lro modify failed, %d\n", err);
2436                 priv->params.lro_en = !enable;
2437         }
2438
2439         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2440                 mlx5e_open_locked(priv->netdev);
2441
2442         mutex_unlock(&priv->state_lock);
2443
2444         return err;
2445 }
2446
2447 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2448 {
2449         struct mlx5e_priv *priv = netdev_priv(netdev);
2450
2451         if (enable)
2452                 mlx5e_enable_vlan_filter(priv);
2453         else
2454                 mlx5e_disable_vlan_filter(priv);
2455
2456         return 0;
2457 }
2458
2459 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2460 {
2461         struct mlx5e_priv *priv = netdev_priv(netdev);
2462
2463         if (!enable && mlx5e_tc_num_filters(priv)) {
2464                 netdev_err(netdev,
2465                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2466                 return -EINVAL;
2467         }
2468
2469         return 0;
2470 }
2471
2472 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2473 {
2474         struct mlx5e_priv *priv = netdev_priv(netdev);
2475         struct mlx5_core_dev *mdev = priv->mdev;
2476
2477         return mlx5_set_port_fcs(mdev, !enable);
2478 }
2479
2480 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2481 {
2482         struct mlx5e_priv *priv = netdev_priv(netdev);
2483         int err;
2484
2485         mutex_lock(&priv->state_lock);
2486
2487         priv->params.vlan_strip_disable = !enable;
2488         err = mlx5e_modify_rqs_vsd(priv, !enable);
2489         if (err)
2490                 priv->params.vlan_strip_disable = enable;
2491
2492         mutex_unlock(&priv->state_lock);
2493
2494         return err;
2495 }
2496
2497 #ifdef CONFIG_RFS_ACCEL
2498 static int set_feature_arfs(struct net_device *netdev, bool enable)
2499 {
2500         struct mlx5e_priv *priv = netdev_priv(netdev);
2501         int err;
2502
2503         if (enable)
2504                 err = mlx5e_arfs_enable(priv);
2505         else
2506                 err = mlx5e_arfs_disable(priv);
2507
2508         return err;
2509 }
2510 #endif
2511
2512 static int mlx5e_handle_feature(struct net_device *netdev,
2513                                 netdev_features_t wanted_features,
2514                                 netdev_features_t feature,
2515                                 mlx5e_feature_handler feature_handler)
2516 {
2517         netdev_features_t changes = wanted_features ^ netdev->features;
2518         bool enable = !!(wanted_features & feature);
2519         int err;
2520
2521         if (!(changes & feature))
2522                 return 0;
2523
2524         err = feature_handler(netdev, enable);
2525         if (err) {
2526                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2527                            enable ? "Enable" : "Disable", feature, err);
2528                 return err;
2529         }
2530
2531         MLX5E_SET_FEATURE(netdev, feature, enable);
2532         return 0;
2533 }
2534
2535 static int mlx5e_set_features(struct net_device *netdev,
2536                               netdev_features_t features)
2537 {
2538         int err;
2539
2540         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2541                                     set_feature_lro);
2542         err |= mlx5e_handle_feature(netdev, features,
2543                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2544                                     set_feature_vlan_filter);
2545         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2546                                     set_feature_tc_num_filters);
2547         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2548                                     set_feature_rx_all);
2549         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2550                                     set_feature_rx_vlan);
2551 #ifdef CONFIG_RFS_ACCEL
2552         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2553                                     set_feature_arfs);
2554 #endif
2555
2556         return err ? -EINVAL : 0;
2557 }
2558
2559 #define MXL5_HW_MIN_MTU 64
2560 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2561
2562 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2563 {
2564         struct mlx5e_priv *priv = netdev_priv(netdev);
2565         struct mlx5_core_dev *mdev = priv->mdev;
2566         bool was_opened;
2567         u16 max_mtu;
2568         u16 min_mtu;
2569         int err = 0;
2570
2571         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2572
2573         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2574         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2575
2576         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2577                 netdev_err(netdev,
2578                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2579                            __func__, new_mtu, min_mtu, max_mtu);
2580                 return -EINVAL;
2581         }
2582
2583         mutex_lock(&priv->state_lock);
2584
2585         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2586         if (was_opened)
2587                 mlx5e_close_locked(netdev);
2588
2589         netdev->mtu = new_mtu;
2590
2591         if (was_opened)
2592                 err = mlx5e_open_locked(netdev);
2593
2594         mutex_unlock(&priv->state_lock);
2595
2596         return err;
2597 }
2598
2599 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2600 {
2601         switch (cmd) {
2602         case SIOCSHWTSTAMP:
2603                 return mlx5e_hwstamp_set(dev, ifr);
2604         case SIOCGHWTSTAMP:
2605                 return mlx5e_hwstamp_get(dev, ifr);
2606         default:
2607                 return -EOPNOTSUPP;
2608         }
2609 }
2610
2611 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2612 {
2613         struct mlx5e_priv *priv = netdev_priv(dev);
2614         struct mlx5_core_dev *mdev = priv->mdev;
2615
2616         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2617 }
2618
2619 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2620 {
2621         struct mlx5e_priv *priv = netdev_priv(dev);
2622         struct mlx5_core_dev *mdev = priv->mdev;
2623
2624         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2625                                            vlan, qos);
2626 }
2627
2628 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2629 {
2630         struct mlx5e_priv *priv = netdev_priv(dev);
2631         struct mlx5_core_dev *mdev = priv->mdev;
2632
2633         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2634 }
2635
2636 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2637 {
2638         struct mlx5e_priv *priv = netdev_priv(dev);
2639         struct mlx5_core_dev *mdev = priv->mdev;
2640
2641         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2642 }
2643 static int mlx5_vport_link2ifla(u8 esw_link)
2644 {
2645         switch (esw_link) {
2646         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2647                 return IFLA_VF_LINK_STATE_DISABLE;
2648         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2649                 return IFLA_VF_LINK_STATE_ENABLE;
2650         }
2651         return IFLA_VF_LINK_STATE_AUTO;
2652 }
2653
2654 static int mlx5_ifla_link2vport(u8 ifla_link)
2655 {
2656         switch (ifla_link) {
2657         case IFLA_VF_LINK_STATE_DISABLE:
2658                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2659         case IFLA_VF_LINK_STATE_ENABLE:
2660                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2661         }
2662         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2663 }
2664
2665 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2666                                    int link_state)
2667 {
2668         struct mlx5e_priv *priv = netdev_priv(dev);
2669         struct mlx5_core_dev *mdev = priv->mdev;
2670
2671         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2672                                             mlx5_ifla_link2vport(link_state));
2673 }
2674
2675 static int mlx5e_get_vf_config(struct net_device *dev,
2676                                int vf, struct ifla_vf_info *ivi)
2677 {
2678         struct mlx5e_priv *priv = netdev_priv(dev);
2679         struct mlx5_core_dev *mdev = priv->mdev;
2680         int err;
2681
2682         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2683         if (err)
2684                 return err;
2685         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2686         return 0;
2687 }
2688
2689 static int mlx5e_get_vf_stats(struct net_device *dev,
2690                               int vf, struct ifla_vf_stats *vf_stats)
2691 {
2692         struct mlx5e_priv *priv = netdev_priv(dev);
2693         struct mlx5_core_dev *mdev = priv->mdev;
2694
2695         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2696                                             vf_stats);
2697 }
2698
2699 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2700                                  struct udp_tunnel_info *ti)
2701 {
2702         struct mlx5e_priv *priv = netdev_priv(netdev);
2703
2704         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2705                 return;
2706
2707         if (!mlx5e_vxlan_allowed(priv->mdev))
2708                 return;
2709
2710         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
2711 }
2712
2713 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2714                                  struct udp_tunnel_info *ti)
2715 {
2716         struct mlx5e_priv *priv = netdev_priv(netdev);
2717
2718         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2719                 return;
2720
2721         if (!mlx5e_vxlan_allowed(priv->mdev))
2722                 return;
2723
2724         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
2725 }
2726
2727 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2728                                                     struct sk_buff *skb,
2729                                                     netdev_features_t features)
2730 {
2731         struct udphdr *udph;
2732         u16 proto;
2733         u16 port = 0;
2734
2735         switch (vlan_get_protocol(skb)) {
2736         case htons(ETH_P_IP):
2737                 proto = ip_hdr(skb)->protocol;
2738                 break;
2739         case htons(ETH_P_IPV6):
2740                 proto = ipv6_hdr(skb)->nexthdr;
2741                 break;
2742         default:
2743                 goto out;
2744         }
2745
2746         if (proto == IPPROTO_UDP) {
2747                 udph = udp_hdr(skb);
2748                 port = be16_to_cpu(udph->dest);
2749         }
2750
2751         /* Verify if UDP port is being offloaded by HW */
2752         if (port && mlx5e_vxlan_lookup_port(priv, port))
2753                 return features;
2754
2755 out:
2756         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2757         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2758 }
2759
2760 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2761                                               struct net_device *netdev,
2762                                               netdev_features_t features)
2763 {
2764         struct mlx5e_priv *priv = netdev_priv(netdev);
2765
2766         features = vlan_features_check(skb, features);
2767         features = vxlan_features_check(skb, features);
2768
2769         /* Validate if the tunneled packet is being offloaded by HW */
2770         if (skb->encapsulation &&
2771             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2772                 return mlx5e_vxlan_features_check(priv, skb, features);
2773
2774         return features;
2775 }
2776
2777 static void mlx5e_tx_timeout(struct net_device *dev)
2778 {
2779         struct mlx5e_priv *priv = netdev_priv(dev);
2780         bool sched_work = false;
2781         int i;
2782
2783         netdev_err(dev, "TX timeout detected\n");
2784
2785         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2786                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2787
2788                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
2789                         continue;
2790                 sched_work = true;
2791                 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
2792                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2793                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2794         }
2795
2796         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2797                 schedule_work(&priv->tx_timeout_work);
2798 }
2799
2800 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2801         .ndo_open                = mlx5e_open,
2802         .ndo_stop                = mlx5e_close,
2803         .ndo_start_xmit          = mlx5e_xmit,
2804         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2805         .ndo_select_queue        = mlx5e_select_queue,
2806         .ndo_get_stats64         = mlx5e_get_stats,
2807         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2808         .ndo_set_mac_address     = mlx5e_set_mac,
2809         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2810         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2811         .ndo_set_features        = mlx5e_set_features,
2812         .ndo_change_mtu          = mlx5e_change_mtu,
2813         .ndo_do_ioctl            = mlx5e_ioctl,
2814         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2815 #ifdef CONFIG_RFS_ACCEL
2816         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2817 #endif
2818         .ndo_tx_timeout          = mlx5e_tx_timeout,
2819 };
2820
2821 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2822         .ndo_open                = mlx5e_open,
2823         .ndo_stop                = mlx5e_close,
2824         .ndo_start_xmit          = mlx5e_xmit,
2825         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2826         .ndo_select_queue        = mlx5e_select_queue,
2827         .ndo_get_stats64         = mlx5e_get_stats,
2828         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2829         .ndo_set_mac_address     = mlx5e_set_mac,
2830         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2831         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2832         .ndo_set_features        = mlx5e_set_features,
2833         .ndo_change_mtu          = mlx5e_change_mtu,
2834         .ndo_do_ioctl            = mlx5e_ioctl,
2835         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
2836         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
2837         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2838         .ndo_features_check      = mlx5e_features_check,
2839 #ifdef CONFIG_RFS_ACCEL
2840         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2841 #endif
2842         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2843         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2844         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2845         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
2846         .ndo_get_vf_config       = mlx5e_get_vf_config,
2847         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2848         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2849         .ndo_tx_timeout          = mlx5e_tx_timeout,
2850 };
2851
2852 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2853 {
2854         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2855                 return -ENOTSUPP;
2856         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2857             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2858             !MLX5_CAP_ETH(mdev, csum_cap) ||
2859             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2860             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2861             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2862             MLX5_CAP_FLOWTABLE(mdev,
2863                                flow_table_properties_nic_receive.max_ft_level)
2864                                < 3) {
2865                 mlx5_core_warn(mdev,
2866                                "Not creating net device, some required device capabilities are missing\n");
2867                 return -ENOTSUPP;
2868         }
2869         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2870                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2871         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2872                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2873
2874         return 0;
2875 }
2876
2877 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2878 {
2879         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2880
2881         return bf_buf_size -
2882                sizeof(struct mlx5e_tx_wqe) +
2883                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2884 }
2885
2886 #ifdef CONFIG_MLX5_CORE_EN_DCB
2887 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2888 {
2889         int i;
2890
2891         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2892         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2893                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2894                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2895                 priv->params.ets.prio_tc[i] = i;
2896         }
2897
2898         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2899         priv->params.ets.prio_tc[0] = 1;
2900         priv->params.ets.prio_tc[1] = 0;
2901 }
2902 #endif
2903
2904 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2905                                    u32 *indirection_rqt, int len,
2906                                    int num_channels)
2907 {
2908         int node = mdev->priv.numa_node;
2909         int node_num_of_cores;
2910         int i;
2911
2912         if (node == -1)
2913                 node = first_online_node;
2914
2915         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2916
2917         if (node_num_of_cores)
2918                 num_channels = min_t(int, num_channels, node_num_of_cores);
2919
2920         for (i = 0; i < len; i++)
2921                 indirection_rqt[i] = i % num_channels;
2922 }
2923
2924 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2925 {
2926         return MLX5_CAP_GEN(mdev, striding_rq) &&
2927                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2928                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2929 }
2930
2931 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2932 {
2933         enum pcie_link_width width;
2934         enum pci_bus_speed speed;
2935         int err = 0;
2936
2937         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2938         if (err)
2939                 return err;
2940
2941         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2942                 return -EINVAL;
2943
2944         switch (speed) {
2945         case PCIE_SPEED_2_5GT:
2946                 *pci_bw = 2500 * width;
2947                 break;
2948         case PCIE_SPEED_5_0GT:
2949                 *pci_bw = 5000 * width;
2950                 break;
2951         case PCIE_SPEED_8_0GT:
2952                 *pci_bw = 8000 * width;
2953                 break;
2954         default:
2955                 return -EINVAL;
2956         }
2957
2958         return 0;
2959 }
2960
2961 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2962 {
2963         return (link_speed && pci_bw &&
2964                 (pci_bw < 40000) && (pci_bw < link_speed));
2965 }
2966
2967 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
2968 {
2969         params->rx_cq_period_mode = cq_period_mode;
2970
2971         params->rx_cq_moderation.pkts =
2972                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2973         params->rx_cq_moderation.usec =
2974                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2975
2976         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
2977                 params->rx_cq_moderation.usec =
2978                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
2979 }
2980
2981 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
2982                                    u8 *min_inline_mode)
2983 {
2984         switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
2985         case MLX5E_INLINE_MODE_L2:
2986                 *min_inline_mode = MLX5_INLINE_MODE_L2;
2987                 break;
2988         case MLX5E_INLINE_MODE_VPORT_CONTEXT:
2989                 mlx5_query_nic_vport_min_inline(mdev,
2990                                                 min_inline_mode);
2991                 break;
2992         case MLX5_INLINE_MODE_NOT_REQUIRED:
2993                 *min_inline_mode = MLX5_INLINE_MODE_NONE;
2994                 break;
2995         }
2996 }
2997
2998 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
2999                                         struct net_device *netdev,
3000                                         const struct mlx5e_profile *profile,
3001                                         void *ppriv)
3002 {
3003         struct mlx5e_priv *priv = netdev_priv(netdev);
3004         u32 link_speed = 0;
3005         u32 pci_bw = 0;
3006         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3007                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3008                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3009
3010         priv->params.log_sq_size           =
3011                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3012         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
3013                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
3014                 MLX5_WQ_TYPE_LINKED_LIST;
3015
3016         /* set CQE compression */
3017         priv->params.rx_cqe_compress_admin = false;
3018         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3019             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3020                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3021                 mlx5e_get_pci_bw(mdev, &pci_bw);
3022                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3023                               link_speed, pci_bw);
3024                 priv->params.rx_cqe_compress_admin =
3025                         cqe_compress_heuristic(link_speed, pci_bw);
3026         }
3027
3028         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3029
3030         switch (priv->params.rq_wq_type) {
3031         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
3032                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
3033                 priv->params.mpwqe_log_stride_sz =
3034                         priv->params.rx_cqe_compress ?
3035                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
3036                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
3037                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
3038                         priv->params.mpwqe_log_stride_sz;
3039                 priv->params.lro_en = true;
3040                 break;
3041         default: /* MLX5_WQ_TYPE_LINKED_LIST */
3042                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3043         }
3044
3045         mlx5_core_info(mdev,
3046                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
3047                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
3048                        BIT(priv->params.log_rq_size),
3049                        BIT(priv->params.mpwqe_log_stride_sz),
3050                        priv->params.rx_cqe_compress_admin);
3051
3052         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
3053                                             BIT(priv->params.log_rq_size));
3054
3055         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3056         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3057
3058         priv->params.tx_cq_moderation.usec =
3059                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3060         priv->params.tx_cq_moderation.pkts =
3061                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3062         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3063         mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3064         priv->params.num_tc                = 1;
3065         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3066
3067         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3068                             sizeof(priv->params.toeplitz_hash_key));
3069
3070         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3071                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3072
3073         priv->params.lro_wqe_sz            =
3074                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3075
3076         /* Initialize pflags */
3077         MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3078                             priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3079
3080         priv->mdev                         = mdev;
3081         priv->netdev                       = netdev;
3082         priv->params.num_channels          = profile->max_nch(mdev);
3083         priv->profile                      = profile;
3084         priv->ppriv                        = ppriv;
3085
3086 #ifdef CONFIG_MLX5_CORE_EN_DCB
3087         mlx5e_ets_init(priv);
3088 #endif
3089
3090         mutex_init(&priv->state_lock);
3091
3092         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3093         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3094         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3095         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3096 }
3097
3098 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3099 {
3100         struct mlx5e_priv *priv = netdev_priv(netdev);
3101
3102         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3103         if (is_zero_ether_addr(netdev->dev_addr) &&
3104             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3105                 eth_hw_addr_random(netdev);
3106                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3107         }
3108 }
3109
3110 static const struct switchdev_ops mlx5e_switchdev_ops = {
3111         .switchdev_port_attr_get        = mlx5e_attr_get,
3112 };
3113
3114 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3115 {
3116         struct mlx5e_priv *priv = netdev_priv(netdev);
3117         struct mlx5_core_dev *mdev = priv->mdev;
3118         bool fcs_supported;
3119         bool fcs_enabled;
3120
3121         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3122
3123         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3124                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3125 #ifdef CONFIG_MLX5_CORE_EN_DCB
3126                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3127 #endif
3128         } else {
3129                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3130         }
3131
3132         netdev->watchdog_timeo    = 15 * HZ;
3133
3134         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3135
3136         netdev->vlan_features    |= NETIF_F_SG;
3137         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3138         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3139         netdev->vlan_features    |= NETIF_F_GRO;
3140         netdev->vlan_features    |= NETIF_F_TSO;
3141         netdev->vlan_features    |= NETIF_F_TSO6;
3142         netdev->vlan_features    |= NETIF_F_RXCSUM;
3143         netdev->vlan_features    |= NETIF_F_RXHASH;
3144
3145         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3146                 netdev->vlan_features    |= NETIF_F_LRO;
3147
3148         netdev->hw_features       = netdev->vlan_features;
3149         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3150         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3151         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3152
3153         if (mlx5e_vxlan_allowed(mdev)) {
3154                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3155                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3156                                            NETIF_F_GSO_PARTIAL;
3157                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3158                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3159                 netdev->hw_enc_features |= NETIF_F_TSO;
3160                 netdev->hw_enc_features |= NETIF_F_TSO6;
3161                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3162                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3163                                            NETIF_F_GSO_PARTIAL;
3164                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3165         }
3166
3167         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3168
3169         if (fcs_supported)
3170                 netdev->hw_features |= NETIF_F_RXALL;
3171
3172         netdev->features          = netdev->hw_features;
3173         if (!priv->params.lro_en)
3174                 netdev->features  &= ~NETIF_F_LRO;
3175
3176         if (fcs_enabled)
3177                 netdev->features  &= ~NETIF_F_RXALL;
3178
3179 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3180         if (FT_CAP(flow_modify_en) &&
3181             FT_CAP(modify_root) &&
3182             FT_CAP(identified_miss_table_mode) &&
3183             FT_CAP(flow_table_modify)) {
3184                 netdev->hw_features      |= NETIF_F_HW_TC;
3185 #ifdef CONFIG_RFS_ACCEL
3186                 netdev->hw_features      |= NETIF_F_NTUPLE;
3187 #endif
3188         }
3189
3190         netdev->features         |= NETIF_F_HIGHDMA;
3191
3192         netdev->priv_flags       |= IFF_UNICAST_FLT;
3193
3194         mlx5e_set_netdev_dev_addr(netdev);
3195
3196 #ifdef CONFIG_NET_SWITCHDEV
3197         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3198                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3199 #endif
3200 }
3201
3202 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3203 {
3204         struct mlx5_core_dev *mdev = priv->mdev;
3205         int err;
3206
3207         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3208         if (err) {
3209                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3210                 priv->q_counter = 0;
3211         }
3212 }
3213
3214 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3215 {
3216         if (!priv->q_counter)
3217                 return;
3218
3219         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3220 }
3221
3222 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3223 {
3224         struct mlx5_core_dev *mdev = priv->mdev;
3225         u64 npages = priv->profile->max_nch(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
3226         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3227         void *mkc;
3228         u32 *in;
3229         int err;
3230
3231         in = mlx5_vzalloc(inlen);
3232         if (!in)
3233                 return -ENOMEM;
3234
3235         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3236
3237         MLX5_SET(mkc, mkc, free, 1);
3238         MLX5_SET(mkc, mkc, umr_en, 1);
3239         MLX5_SET(mkc, mkc, lw, 1);
3240         MLX5_SET(mkc, mkc, lr, 1);
3241         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
3242
3243         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3244         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3245         MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3246         MLX5_SET(mkc, mkc, translations_octword_size,
3247                  mlx5e_get_mtt_octw(npages));
3248         MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
3249
3250         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
3251
3252         kvfree(in);
3253         return err;
3254 }
3255
3256 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3257                            struct net_device *netdev,
3258                            const struct mlx5e_profile *profile,
3259                            void *ppriv)
3260 {
3261         struct mlx5e_priv *priv = netdev_priv(netdev);
3262
3263         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3264         mlx5e_build_nic_netdev(netdev);
3265         mlx5e_vxlan_init(priv);
3266 }
3267
3268 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3269 {
3270         struct mlx5_core_dev *mdev = priv->mdev;
3271         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3272
3273         mlx5e_vxlan_cleanup(priv);
3274
3275         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3276                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3277 }
3278
3279 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3280 {
3281         struct mlx5_core_dev *mdev = priv->mdev;
3282         int err;
3283         int i;
3284
3285         err = mlx5e_create_indirect_rqts(priv);
3286         if (err) {
3287                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3288                 return err;
3289         }
3290
3291         err = mlx5e_create_direct_rqts(priv);
3292         if (err) {
3293                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3294                 goto err_destroy_indirect_rqts;
3295         }
3296
3297         err = mlx5e_create_indirect_tirs(priv);
3298         if (err) {
3299                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3300                 goto err_destroy_direct_rqts;
3301         }
3302
3303         err = mlx5e_create_direct_tirs(priv);
3304         if (err) {
3305                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3306                 goto err_destroy_indirect_tirs;
3307         }
3308
3309         err = mlx5e_create_flow_steering(priv);
3310         if (err) {
3311                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3312                 goto err_destroy_direct_tirs;
3313         }
3314
3315         err = mlx5e_tc_init(priv);
3316         if (err)
3317                 goto err_destroy_flow_steering;
3318
3319         return 0;
3320
3321 err_destroy_flow_steering:
3322         mlx5e_destroy_flow_steering(priv);
3323 err_destroy_direct_tirs:
3324         mlx5e_destroy_direct_tirs(priv);
3325 err_destroy_indirect_tirs:
3326         mlx5e_destroy_indirect_tirs(priv);
3327 err_destroy_direct_rqts:
3328         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3329                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3330 err_destroy_indirect_rqts:
3331         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3332         return err;
3333 }
3334
3335 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3336 {
3337         int i;
3338
3339         mlx5e_tc_cleanup(priv);
3340         mlx5e_destroy_flow_steering(priv);
3341         mlx5e_destroy_direct_tirs(priv);
3342         mlx5e_destroy_indirect_tirs(priv);
3343         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3344                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3345         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3346 }
3347
3348 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3349 {
3350         int err;
3351
3352         err = mlx5e_create_tises(priv);
3353         if (err) {
3354                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3355                 return err;
3356         }
3357
3358 #ifdef CONFIG_MLX5_CORE_EN_DCB
3359         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3360 #endif
3361         return 0;
3362 }
3363
3364 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3365 {
3366         struct net_device *netdev = priv->netdev;
3367         struct mlx5_core_dev *mdev = priv->mdev;
3368         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3369         struct mlx5_eswitch_rep rep;
3370
3371         if (mlx5e_vxlan_allowed(mdev)) {
3372                 rtnl_lock();
3373                 udp_tunnel_get_rx_info(netdev);
3374                 rtnl_unlock();
3375         }
3376
3377         mlx5e_enable_async_events(priv);
3378         queue_work(priv->wq, &priv->set_rx_mode_work);
3379
3380         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3381                 rep.load = mlx5e_nic_rep_load;
3382                 rep.unload = mlx5e_nic_rep_unload;
3383                 rep.vport = 0;
3384                 rep.priv_data = priv;
3385                 mlx5_eswitch_register_vport_rep(esw, &rep);
3386         }
3387 }
3388
3389 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3390 {
3391         queue_work(priv->wq, &priv->set_rx_mode_work);
3392         mlx5e_disable_async_events(priv);
3393 }
3394
3395 static const struct mlx5e_profile mlx5e_nic_profile = {
3396         .init              = mlx5e_nic_init,
3397         .cleanup           = mlx5e_nic_cleanup,
3398         .init_rx           = mlx5e_init_nic_rx,
3399         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3400         .init_tx           = mlx5e_init_nic_tx,
3401         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3402         .enable            = mlx5e_nic_enable,
3403         .disable           = mlx5e_nic_disable,
3404         .update_stats      = mlx5e_update_stats,
3405         .max_nch           = mlx5e_get_max_num_channels,
3406         .max_tc            = MLX5E_MAX_NUM_TC,
3407 };
3408
3409 void *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3410                           const struct mlx5e_profile *profile, void *ppriv)
3411 {
3412         struct net_device *netdev;
3413         struct mlx5e_priv *priv;
3414         int nch = profile->max_nch(mdev);
3415         int err;
3416
3417         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3418                                     nch * profile->max_tc,
3419                                     nch);
3420         if (!netdev) {
3421                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3422                 return NULL;
3423         }
3424
3425         profile->init(mdev, netdev, profile, ppriv);
3426
3427         netif_carrier_off(netdev);
3428
3429         priv = netdev_priv(netdev);
3430
3431         priv->wq = create_singlethread_workqueue("mlx5e");
3432         if (!priv->wq)
3433                 goto err_free_netdev;
3434
3435         err = mlx5e_create_umr_mkey(priv);
3436         if (err) {
3437                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3438                 goto err_destroy_wq;
3439         }
3440
3441         err = profile->init_tx(priv);
3442         if (err)
3443                 goto err_destroy_umr_mkey;
3444
3445         err = mlx5e_open_drop_rq(priv);
3446         if (err) {
3447                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3448                 goto err_cleanup_tx;
3449         }
3450
3451         err = profile->init_rx(priv);
3452         if (err)
3453                 goto err_close_drop_rq;
3454
3455         mlx5e_create_q_counter(priv);
3456
3457         mlx5e_init_l2_addr(priv);
3458
3459         err = register_netdev(netdev);
3460         if (err) {
3461                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3462                 goto err_dealloc_q_counters;
3463         }
3464
3465         if (profile->enable)
3466                 profile->enable(priv);
3467
3468         return priv;
3469
3470 err_dealloc_q_counters:
3471         mlx5e_destroy_q_counter(priv);
3472         profile->cleanup_rx(priv);
3473
3474 err_close_drop_rq:
3475         mlx5e_close_drop_rq(priv);
3476
3477 err_cleanup_tx:
3478         profile->cleanup_tx(priv);
3479
3480 err_destroy_umr_mkey:
3481         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3482
3483 err_destroy_wq:
3484         destroy_workqueue(priv->wq);
3485
3486 err_free_netdev:
3487         free_netdev(netdev);
3488
3489         return NULL;
3490 }
3491
3492 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3493 {
3494         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3495         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3496         int vport;
3497
3498         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3499                 return;
3500
3501         for (vport = 1; vport < total_vfs; vport++) {
3502                 struct mlx5_eswitch_rep rep;
3503
3504                 rep.load = mlx5e_vport_rep_load;
3505                 rep.unload = mlx5e_vport_rep_unload;
3506                 rep.vport = vport;
3507                 mlx5_eswitch_register_vport_rep(esw, &rep);
3508         }
3509 }
3510
3511 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3512 {
3513         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3514         void *ppriv = NULL;
3515         void *ret;
3516
3517         if (mlx5e_check_required_hca_cap(mdev))
3518                 return NULL;
3519
3520         if (mlx5e_create_mdev_resources(mdev))
3521                 return NULL;
3522
3523         mlx5e_register_vport_rep(mdev);
3524
3525         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3526                 ppriv = &esw->offloads.vport_reps[0];
3527
3528         ret = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
3529         if (!ret) {
3530                 mlx5e_destroy_mdev_resources(mdev);
3531                 return NULL;
3532         }
3533         return ret;
3534 }
3535
3536 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
3537 {
3538         const struct mlx5e_profile *profile = priv->profile;
3539         struct net_device *netdev = priv->netdev;
3540
3541         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3542         if (profile->disable)
3543                 profile->disable(priv);
3544
3545         flush_workqueue(priv->wq);
3546         if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3547                 netif_device_detach(netdev);
3548                 mlx5e_close(netdev);
3549         } else {
3550                 unregister_netdev(netdev);
3551         }
3552
3553         mlx5e_destroy_q_counter(priv);
3554         profile->cleanup_rx(priv);
3555         mlx5e_close_drop_rq(priv);
3556         profile->cleanup_tx(priv);
3557         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3558         cancel_delayed_work_sync(&priv->update_stats_work);
3559         destroy_workqueue(priv->wq);
3560         if (profile->cleanup)
3561                 profile->cleanup(priv);
3562
3563         if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3564                 free_netdev(netdev);
3565 }
3566
3567 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3568 {
3569         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3570         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3571         struct mlx5e_priv *priv = vpriv;
3572         int vport;
3573
3574         mlx5e_destroy_netdev(mdev, priv);
3575
3576         for (vport = 1; vport < total_vfs; vport++)
3577                 mlx5_eswitch_unregister_vport_rep(esw, vport);
3578
3579         mlx5e_destroy_mdev_resources(mdev);
3580 }
3581
3582 static void *mlx5e_get_netdev(void *vpriv)
3583 {
3584         struct mlx5e_priv *priv = vpriv;
3585
3586         return priv->netdev;
3587 }
3588
3589 static struct mlx5_interface mlx5e_interface = {
3590         .add       = mlx5e_add,
3591         .remove    = mlx5e_remove,
3592         .event     = mlx5e_async_event,
3593         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3594         .get_dev   = mlx5e_get_netdev,
3595 };
3596
3597 void mlx5e_init(void)
3598 {
3599         mlx5e_build_ptys2ethtool_map();
3600         mlx5_register_interface(&mlx5e_interface);
3601 }
3602
3603 void mlx5e_cleanup(void)
3604 {
3605         mlx5_unregister_interface(&mlx5e_interface);
3606 }