drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include "en.h"
  39 #include "en_tc.h"
  40 #include "eswitch.h"
  41 #include "vxlan.h"
  42
  43 struct mlx5e_rq_param {
  44         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  45         struct mlx5_wq_param    wq;
  46         bool                    am_enabled;
  47 };
  48
  49 struct mlx5e_sq_param {
  50         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  51         struct mlx5_wq_param       wq;
  52         u16                        max_inline;
  53         u8                         min_inline_mode;
  54         enum mlx5e_sq_type         type;
  55 };
  56
  57 struct mlx5e_cq_param {
  58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  59         struct mlx5_wq_param       wq;
  60         u16                        eq_ix;
  61         u8                         cq_period_mode;
  62 };
  63
  64 struct mlx5e_channel_param {
  65         struct mlx5e_rq_param      rq;
  66         struct mlx5e_sq_param      sq;
  67         struct mlx5e_sq_param      xdp_sq;
  68         struct mlx5e_sq_param      icosq;
  69         struct mlx5e_cq_param      rx_cq;
  70         struct mlx5e_cq_param      tx_cq;
  71         struct mlx5e_cq_param      icosq_cq;
  72 };
  73
  74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  75 {
  76         return MLX5_CAP_GEN(mdev, striding_rq) &&
  77                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  78                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  79 }
  80
  81 static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
  82 {
  83         priv->params.rq_wq_type = rq_type;
  84         switch (priv->params.rq_wq_type) {
  85         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
  86                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
  87                 priv->params.mpwqe_log_stride_sz =
  88                         MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
  89                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
  90                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
  91                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
  92                         priv->params.mpwqe_log_stride_sz;
  93                 break;
  94         default: /* MLX5_WQ_TYPE_LINKED_LIST */
  95                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  96         }
  97         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
  98                                                BIT(priv->params.log_rq_size));
  99
 100         mlx5_core_info(priv->mdev,
 101                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 102                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 103                        BIT(priv->params.log_rq_size),
 104                        BIT(priv->params.mpwqe_log_stride_sz),
 105                        MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS));
 106 }
 107
 108 static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
 109 {
 110         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
 111                     !priv->xdp_prog ?
 112                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 113                     MLX5_WQ_TYPE_LINKED_LIST;
 114         mlx5e_set_rq_type_params(priv, rq_type);
 115 }
 116
 117 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 118 {
 119         struct mlx5_core_dev *mdev = priv->mdev;
 120         u8 port_state;
 121
 122         port_state = mlx5_query_vport_state(mdev,
 123                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 124
 125         if (port_state == VPORT_STATE_UP) {
 126                 netdev_info(priv->netdev, "Link up\n");
 127                 netif_carrier_on(priv->netdev);
 128         } else {
 129                 netdev_info(priv->netdev, "Link down\n");
 130                 netif_carrier_off(priv->netdev);
 131         }
 132 }
 133
 134 static void mlx5e_update_carrier_work(struct work_struct *work)
 135 {
 136         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 137                                                update_carrier_work);
 138
 139         mutex_lock(&priv->state_lock);
 140         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 141                 mlx5e_update_carrier(priv);
 142         mutex_unlock(&priv->state_lock);
 143 }
 144
 145 static void mlx5e_tx_timeout_work(struct work_struct *work)
 146 {
 147         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 148                                                tx_timeout_work);
 149         int err;
 150
 151         rtnl_lock();
 152         mutex_lock(&priv->state_lock);
 153         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 154                 goto unlock;
 155         mlx5e_close_locked(priv->netdev);
 156         err = mlx5e_open_locked(priv->netdev);
 157         if (err)
 158                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 159                            err);
 160 unlock:
 161         mutex_unlock(&priv->state_lock);
 162         rtnl_unlock();
 163 }
 164
 165 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 166 {
 167         struct mlx5e_sw_stats *s = &priv->stats.sw;
 168         struct mlx5e_rq_stats *rq_stats;
 169         struct mlx5e_sq_stats *sq_stats;
 170         u64 tx_offload_none = 0;
 171         int i, j;
 172
 173         memset(s, 0, sizeof(*s));
 174         for (i = 0; i < priv->params.num_channels; i++) {
 175                 rq_stats = &priv->channel[i]->rq.stats;
 176
 177                 s->rx_packets   += rq_stats->packets;
 178                 s->rx_bytes     += rq_stats->bytes;
 179                 s->rx_lro_packets += rq_stats->lro_packets;
 180                 s->rx_lro_bytes += rq_stats->lro_bytes;
 181                 s->rx_csum_none += rq_stats->csum_none;
 182                 s->rx_csum_complete += rq_stats->csum_complete;
 183                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 184                 s->rx_xdp_drop += rq_stats->xdp_drop;
 185                 s->rx_xdp_tx += rq_stats->xdp_tx;
 186                 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
 187                 s->rx_wqe_err   += rq_stats->wqe_err;
 188                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 189                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 190                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 191                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 192                 s->rx_cache_reuse += rq_stats->cache_reuse;
 193                 s->rx_cache_full  += rq_stats->cache_full;
 194                 s->rx_cache_empty += rq_stats->cache_empty;
 195                 s->rx_cache_busy  += rq_stats->cache_busy;
 196
 197                 for (j = 0; j < priv->params.num_tc; j++) {
 198                         sq_stats = &priv->channel[i]->sq[j].stats;
 199
 200                         s->tx_packets           += sq_stats->packets;
 201                         s->tx_bytes             += sq_stats->bytes;
 202                         s->tx_tso_packets       += sq_stats->tso_packets;
 203                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 204                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 205                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 206                         s->tx_queue_stopped     += sq_stats->stopped;
 207                         s->tx_queue_wake        += sq_stats->wake;
 208                         s->tx_queue_dropped     += sq_stats->dropped;
 209                         s->tx_xmit_more         += sq_stats->xmit_more;
 210                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 211                         tx_offload_none         += sq_stats->csum_none;
 212                 }
 213         }
 214
 215         /* Update calculated offload counters */
 216         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 217         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 218
 219         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 220                                 priv->stats.pport.phy_counters,
 221                                 counter_set.phys_layer_cntrs.link_down_events);
 222 }
 223
 224 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 225 {
 226         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 227         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 228         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 229         struct mlx5_core_dev *mdev = priv->mdev;
 230
 231         MLX5_SET(query_vport_counter_in, in, opcode,
 232                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 233         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 234         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 235
 236         memset(out, 0, outlen);
 237         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 238 }
 239
 240 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 241 {
 242         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 243         struct mlx5_core_dev *mdev = priv->mdev;
 244         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 245         int prio;
 246         void *out;
 247         u32 *in;
 248
 249         in = mlx5_vzalloc(sz);
 250         if (!in)
 251                 goto free_out;
 252
 253         MLX5_SET(ppcnt_reg, in, local_port, 1);
 254
 255         out = pstats->IEEE_802_3_counters;
 256         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 257         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 258
 259         out = pstats->RFC_2863_counters;
 260         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 261         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 262
 263         out = pstats->RFC_2819_counters;
 264         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 265         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 266
 267         out = pstats->phy_counters;
 268         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 269         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 270
 271         if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
 272                 out = pstats->phy_statistical_counters;
 273                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
 274                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 275         }
 276
 277         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 278         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 279                 out = pstats->per_prio_counters[prio];
 280                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 281                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 282                                      MLX5_REG_PPCNT, 0, 0);
 283         }
 284
 285 free_out:
 286         kvfree(in);
 287 }
 288
 289 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 290 {
 291         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 292
 293         if (!priv->q_counter)
 294                 return;
 295
 296         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 297                                       &qcnt->rx_out_of_buffer);
 298 }
 299
 300 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 301 {
 302         struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
 303         struct mlx5_core_dev *mdev = priv->mdev;
 304         int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 305         void *out;
 306         u32 *in;
 307
 308         if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
 309                 return;
 310
 311         in = mlx5_vzalloc(sz);
 312         if (!in)
 313                 return;
 314
 315         out = pcie_stats->pcie_perf_counters;
 316         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 317         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 318
 319         kvfree(in);
 320 }
 321
 322 void mlx5e_update_stats(struct mlx5e_priv *priv)
 323 {
 324         mlx5e_update_q_counter(priv);
 325         mlx5e_update_vport_counters(priv);
 326         mlx5e_update_pport_counters(priv);
 327         mlx5e_update_sw_counters(priv);
 328         mlx5e_update_pcie_counters(priv);
 329 }
 330
 331 void mlx5e_update_stats_work(struct work_struct *work)
 332 {
 333         struct delayed_work *dwork = to_delayed_work(work);
 334         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 335                                                update_stats_work);
 336         mutex_lock(&priv->state_lock);
 337         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 338                 priv->profile->update_stats(priv);
 339                 queue_delayed_work(priv->wq, dwork,
 340                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 341         }
 342         mutex_unlock(&priv->state_lock);
 343 }
 344
 345 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 346                               enum mlx5_dev_event event, unsigned long param)
 347 {
 348         struct mlx5e_priv *priv = vpriv;
 349         struct ptp_clock_event ptp_event;
 350         struct mlx5_eqe *eqe = NULL;
 351
 352         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 353                 return;
 354
 355         switch (event) {
 356         case MLX5_DEV_EVENT_PORT_UP:
 357         case MLX5_DEV_EVENT_PORT_DOWN:
 358                 queue_work(priv->wq, &priv->update_carrier_work);
 359                 break;
 360         case MLX5_DEV_EVENT_PPS:
 361                 eqe = (struct mlx5_eqe *)param;
 362                 ptp_event.type = PTP_CLOCK_EXTTS;
 363                 ptp_event.index = eqe->data.pps.pin;
 364                 ptp_event.timestamp =
 365                         timecounter_cyc2time(&priv->tstamp.clock,
 366                                              be64_to_cpu(eqe->data.pps.time_stamp));
 367                 mlx5e_pps_event_handler(vpriv, &ptp_event);
 368                 break;
 369         default:
 370                 break;
 371         }
 372 }
 373
 374 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 375 {
 376         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 377 }
 378
 379 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 380 {
 381         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 382         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 383 }
 384
 385 static inline int mlx5e_get_wqe_mtt_sz(void)
 386 {
 387         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 388          * To avoid copying garbage after the mtt array, we allocate
 389          * a little more.
 390          */
 391         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 392                      MLX5_UMR_MTT_ALIGNMENT);
 393 }
 394
 395 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
 396                                        struct mlx5e_umr_wqe *wqe, u16 ix)
 397 {
 398         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 399         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 400         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 401         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 402         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 403         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 404
 405         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 406                                       ds_cnt);
 407         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 408         cseg->imm       = rq->mkey_be;
 409
 410         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 411         ucseg->xlt_octowords =
 412                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 413         ucseg->bsf_octowords =
 414                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 415         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 416
 417         dseg->lkey = sq->mkey_be;
 418         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 419 }
 420
 421 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 422                                      struct mlx5e_channel *c)
 423 {
 424         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 425         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 426         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
 427         int i;
 428
 429         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 430                                       GFP_KERNEL, cpu_to_node(c->cpu));
 431         if (!rq->mpwqe.info)
 432                 goto err_out;
 433
 434         /* We allocate more than mtt_sz as we will align the pointer */
 435         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
 436                                         cpu_to_node(c->cpu));
 437         if (unlikely(!rq->mpwqe.mtt_no_align))
 438                 goto err_free_wqe_info;
 439
 440         for (i = 0; i < wq_sz; i++) {
 441                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 442
 443                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
 444                                         MLX5_UMR_ALIGN);
 445                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
 446                                                   PCI_DMA_TODEVICE);
 447                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
 448                         goto err_unmap_mtts;
 449
 450                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 451         }
 452
 453         return 0;
 454
 455 err_unmap_mtts:
 456         while (--i >= 0) {
 457                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 458
 459                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
 460                                  PCI_DMA_TODEVICE);
 461         }
 462         kfree(rq->mpwqe.mtt_no_align);
 463 err_free_wqe_info:
 464         kfree(rq->mpwqe.info);
 465
 466 err_out:
 467         return -ENOMEM;
 468 }
 469
 470 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
 471 {
 472         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 473         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 474         int i;
 475
 476         for (i = 0; i < wq_sz; i++) {
 477                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 478
 479                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
 480                                  PCI_DMA_TODEVICE);
 481         }
 482         kfree(rq->mpwqe.mtt_no_align);
 483         kfree(rq->mpwqe.info);
 484 }
 485
 486 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv,
 487                                  u64 npages, u8 page_shift,
 488                                  struct mlx5_core_mkey *umr_mkey)
 489 {
 490         struct mlx5_core_dev *mdev = priv->mdev;
 491         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 492         void *mkc;
 493         u32 *in;
 494         int err;
 495
 496         if (!MLX5E_VALID_NUM_MTTS(npages))
 497                 return -EINVAL;
 498
 499         in = mlx5_vzalloc(inlen);
 500         if (!in)
 501                 return -ENOMEM;
 502
 503         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 504
 505         MLX5_SET(mkc, mkc, free, 1);
 506         MLX5_SET(mkc, mkc, umr_en, 1);
 507         MLX5_SET(mkc, mkc, lw, 1);
 508         MLX5_SET(mkc, mkc, lr, 1);
 509         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
 510
 511         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 512         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 513         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 514         MLX5_SET(mkc, mkc, translations_octword_size,
 515                  MLX5_MTT_OCTW(npages));
 516         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 517
 518         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 519
 520         kvfree(in);
 521         return err;
 522 }
 523
 524 static int mlx5e_create_rq_umr_mkey(struct mlx5e_rq *rq)
 525 {
 526         struct mlx5e_priv *priv = rq->priv;
 527         u64 num_mtts = MLX5E_REQUIRED_MTTS(BIT(priv->params.log_rq_size));
 528
 529         return mlx5e_create_umr_mkey(priv, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 530 }
 531
 532 static int mlx5e_create_rq(struct mlx5e_channel *c,
 533                            struct mlx5e_rq_param *param,
 534                            struct mlx5e_rq *rq)
 535 {
 536         struct mlx5e_priv *priv = c->priv;
 537         struct mlx5_core_dev *mdev = priv->mdev;
 538         void *rqc = param->rqc;
 539         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 540         u32 byte_count;
 541         u32 frag_sz;
 542         int npages;
 543         int wq_sz;
 544         int err;
 545         int i;
 546
 547         param->wq.db_numa_node = cpu_to_node(c->cpu);
 548
 549         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 550                                 &rq->wq_ctrl);
 551         if (err)
 552                 return err;
 553
 554         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 555
 556         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 557
 558         rq->wq_type = priv->params.rq_wq_type;
 559         rq->pdev    = c->pdev;
 560         rq->netdev  = c->netdev;
 561         rq->tstamp  = &priv->tstamp;
 562         rq->channel = c;
 563         rq->ix      = c->ix;
 564         rq->priv    = c->priv;
 565
 566         rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
 567         if (IS_ERR(rq->xdp_prog)) {
 568                 err = PTR_ERR(rq->xdp_prog);
 569                 rq->xdp_prog = NULL;
 570                 goto err_rq_wq_destroy;
 571         }
 572
 573         if (rq->xdp_prog) {
 574                 rq->buff.map_dir = DMA_BIDIRECTIONAL;
 575                 rq->rx_headroom = XDP_PACKET_HEADROOM;
 576         } else {
 577                 rq->buff.map_dir = DMA_FROM_DEVICE;
 578                 rq->rx_headroom = MLX5_RX_HEADROOM;
 579         }
 580
 581         switch (priv->params.rq_wq_type) {
 582         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 583                 if (mlx5e_is_vf_vport_rep(priv)) {
 584                         err = -EINVAL;
 585                         goto err_rq_wq_destroy;
 586                 }
 587
 588                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 589                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 590                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 591
 592                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 593                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 594
 595                 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 596                 byte_count = rq->buff.wqe_sz;
 597
 598                 err = mlx5e_create_rq_umr_mkey(rq);
 599                 if (err)
 600                         goto err_rq_wq_destroy;
 601                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 602
 603                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 604                 if (err)
 605                         goto err_destroy_umr_mkey;
 606                 break;
 607         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 608                 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
 609                                             GFP_KERNEL, cpu_to_node(c->cpu));
 610                 if (!rq->dma_info) {
 611                         err = -ENOMEM;
 612                         goto err_rq_wq_destroy;
 613                 }
 614
 615                 if (mlx5e_is_vf_vport_rep(priv))
 616                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
 617                 else
 618                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 619
 620                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 621                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 622
 623                 rq->buff.wqe_sz = (priv->params.lro_en) ?
 624                                 priv->params.lro_wqe_sz :
 625                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 626                 byte_count = rq->buff.wqe_sz;
 627
 628                 /* calc the required page order */
 629                 frag_sz = rq->rx_headroom +
 630                           byte_count /* packet data */ +
 631                           SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 632                 frag_sz = SKB_DATA_ALIGN(frag_sz);
 633
 634                 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
 635                 rq->buff.page_order = order_base_2(npages);
 636
 637                 byte_count |= MLX5_HW_START_PADDING;
 638                 rq->mkey_be = c->mkey_be;
 639         }
 640
 641         for (i = 0; i < wq_sz; i++) {
 642                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 643
 644                 wqe->data.byte_count = cpu_to_be32(byte_count);
 645                 wqe->data.lkey = rq->mkey_be;
 646         }
 647
 648         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 649         rq->am.mode = priv->params.rx_cq_period_mode;
 650
 651         rq->page_cache.head = 0;
 652         rq->page_cache.tail = 0;
 653
 654         return 0;
 655
 656 err_destroy_umr_mkey:
 657         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 658
 659 err_rq_wq_destroy:
 660         if (rq->xdp_prog)
 661                 bpf_prog_put(rq->xdp_prog);
 662         mlx5_wq_destroy(&rq->wq_ctrl);
 663
 664         return err;
 665 }
 666
 667 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 668 {
 669         int i;
 670
 671         if (rq->xdp_prog)
 672                 bpf_prog_put(rq->xdp_prog);
 673
 674         switch (rq->wq_type) {
 675         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 676                 mlx5e_rq_free_mpwqe_info(rq);
 677                 mlx5_core_destroy_mkey(rq->priv->mdev, &rq->umr_mkey);
 678                 break;
 679         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 680                 kfree(rq->dma_info);
 681         }
 682
 683         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 684              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 685                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 686
 687                 mlx5e_page_release(rq, dma_info, false);
 688         }
 689         mlx5_wq_destroy(&rq->wq_ctrl);
 690 }
 691
 692 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 693 {
 694         struct mlx5e_priv *priv = rq->priv;
 695         struct mlx5_core_dev *mdev = priv->mdev;
 696
 697         void *in;
 698         void *rqc;
 699         void *wq;
 700         int inlen;
 701         int err;
 702
 703         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 704                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 705         in = mlx5_vzalloc(inlen);
 706         if (!in)
 707                 return -ENOMEM;
 708
 709         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 710         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 711
 712         memcpy(rqc, param->rqc, sizeof(param->rqc));
 713
 714         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 715         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 716         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 717         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 718                                                 MLX5_ADAPTER_PAGE_SHIFT);
 719         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 720
 721         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 722                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 723
 724         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 725
 726         kvfree(in);
 727
 728         return err;
 729 }
 730
 731 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 732                                  int next_state)
 733 {
 734         struct mlx5e_channel *c = rq->channel;
 735         struct mlx5e_priv *priv = c->priv;
 736         struct mlx5_core_dev *mdev = priv->mdev;
 737
 738         void *in;
 739         void *rqc;
 740         int inlen;
 741         int err;
 742
 743         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 744         in = mlx5_vzalloc(inlen);
 745         if (!in)
 746                 return -ENOMEM;
 747
 748         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 749
 750         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 751         MLX5_SET(rqc, rqc, state, next_state);
 752
 753         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 754
 755         kvfree(in);
 756
 757         return err;
 758 }
 759
 760 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 761 {
 762         struct mlx5e_channel *c = rq->channel;
 763         struct mlx5e_priv *priv = c->priv;
 764         struct mlx5_core_dev *mdev = priv->mdev;
 765
 766         void *in;
 767         void *rqc;
 768         int inlen;
 769         int err;
 770
 771         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 772         in = mlx5_vzalloc(inlen);
 773         if (!in)
 774                 return -ENOMEM;
 775
 776         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 777
 778         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 779         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 780                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 781         MLX5_SET(rqc, rqc, vsd, vsd);
 782         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 783
 784         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 785
 786         kvfree(in);
 787
 788         return err;
 789 }
 790
 791 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 792 {
 793         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 794 }
 795
 796 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 797 {
 798         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 799         struct mlx5e_channel *c = rq->channel;
 800         struct mlx5e_priv *priv = c->priv;
 801         struct mlx5_wq_ll *wq = &rq->wq;
 802
 803         while (time_before(jiffies, exp_time)) {
 804                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 805                         return 0;
 806
 807                 msleep(20);
 808         }
 809
 810         return -ETIMEDOUT;
 811 }
 812
 813 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 814 {
 815         struct mlx5_wq_ll *wq = &rq->wq;
 816         struct mlx5e_rx_wqe *wqe;
 817         __be16 wqe_ix_be;
 818         u16 wqe_ix;
 819
 820         /* UMR WQE (if in progress) is always at wq->head */
 821         if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 822                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 823
 824         while (!mlx5_wq_ll_is_empty(wq)) {
 825                 wqe_ix_be = *wq->tail_next;
 826                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 827                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 828                 rq->dealloc_wqe(rq, wqe_ix);
 829                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 830                                &wqe->next.next_wqe_index);
 831         }
 832 }
 833
 834 static int mlx5e_open_rq(struct mlx5e_channel *c,
 835                          struct mlx5e_rq_param *param,
 836                          struct mlx5e_rq *rq)
 837 {
 838         struct mlx5e_sq *sq = &c->icosq;
 839         u16 pi = sq->pc & sq->wq.sz_m1;
 840         int err;
 841
 842         err = mlx5e_create_rq(c, param, rq);
 843         if (err)
 844                 return err;
 845
 846         err = mlx5e_enable_rq(rq, param);
 847         if (err)
 848                 goto err_destroy_rq;
 849
 850         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 851         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 852         if (err)
 853                 goto err_disable_rq;
 854
 855         if (param->am_enabled)
 856                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 857
 858         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 859         sq->db.ico_wqe[pi].num_wqebbs = 1;
 860         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 861
 862         return 0;
 863
 864 err_disable_rq:
 865         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 866         mlx5e_disable_rq(rq);
 867 err_destroy_rq:
 868         mlx5e_destroy_rq(rq);
 869
 870         return err;
 871 }
 872
 873 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 874 {
 875         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 876         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 877         cancel_work_sync(&rq->am.work);
 878
 879         mlx5e_disable_rq(rq);
 880         mlx5e_free_rx_descs(rq);
 881         mlx5e_destroy_rq(rq);
 882 }
 883
 884 static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
 885 {
 886         kfree(sq->db.xdp.di);
 887         kfree(sq->db.xdp.wqe_info);
 888 }
 889
 890 static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
 891 {
 892         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 893
 894         sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
 895                                      GFP_KERNEL, numa);
 896         sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
 897                                            GFP_KERNEL, numa);
 898         if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
 899                 mlx5e_free_sq_xdp_db(sq);
 900                 return -ENOMEM;
 901         }
 902
 903         return 0;
 904 }
 905
 906 static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
 907 {
 908         kfree(sq->db.ico_wqe);
 909 }
 910
 911 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
 912 {
 913         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 914
 915         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 916                                       GFP_KERNEL, numa);
 917         if (!sq->db.ico_wqe)
 918                 return -ENOMEM;
 919
 920         return 0;
 921 }
 922
 923 static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
 924 {
 925         kfree(sq->db.txq.wqe_info);
 926         kfree(sq->db.txq.dma_fifo);
 927         kfree(sq->db.txq.skb);
 928 }
 929
 930 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
 931 {
 932         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 933         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 934
 935         sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
 936                                       GFP_KERNEL, numa);
 937         sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
 938                                            GFP_KERNEL, numa);
 939         sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
 940                                            GFP_KERNEL, numa);
 941         if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
 942                 mlx5e_free_sq_txq_db(sq);
 943                 return -ENOMEM;
 944         }
 945
 946         sq->dma_fifo_mask = df_sz - 1;
 947
 948         return 0;
 949 }
 950
 951 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 952 {
 953         switch (sq->type) {
 954         case MLX5E_SQ_TXQ:
 955                 mlx5e_free_sq_txq_db(sq);
 956                 break;
 957         case MLX5E_SQ_ICO:
 958                 mlx5e_free_sq_ico_db(sq);
 959                 break;
 960         case MLX5E_SQ_XDP:
 961                 mlx5e_free_sq_xdp_db(sq);
 962                 break;
 963         }
 964 }
 965
 966 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 967 {
 968         switch (sq->type) {
 969         case MLX5E_SQ_TXQ:
 970                 return mlx5e_alloc_sq_txq_db(sq, numa);
 971         case MLX5E_SQ_ICO:
 972                 return mlx5e_alloc_sq_ico_db(sq, numa);
 973         case MLX5E_SQ_XDP:
 974                 return mlx5e_alloc_sq_xdp_db(sq, numa);
 975         }
 976
 977         return 0;
 978 }
 979
 980 static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
 981 {
 982         switch (sq_type) {
 983         case MLX5E_SQ_ICO:
 984                 return MLX5E_ICOSQ_MAX_WQEBBS;
 985         case MLX5E_SQ_XDP:
 986                 return MLX5E_XDP_TX_WQEBBS;
 987         }
 988         return MLX5_SEND_WQE_MAX_WQEBBS;
 989 }
 990
 991 static int mlx5e_create_sq(struct mlx5e_channel *c,
 992                            int tc,
 993                            struct mlx5e_sq_param *param,
 994                            struct mlx5e_sq *sq)
 995 {
 996         struct mlx5e_priv *priv = c->priv;
 997         struct mlx5_core_dev *mdev = priv->mdev;
 998
 999         void *sqc = param->sqc;
1000         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1001         int err;
1002
1003         sq->type      = param->type;
1004         sq->pdev      = c->pdev;
1005         sq->tstamp    = &priv->tstamp;
1006         sq->mkey_be   = c->mkey_be;
1007         sq->channel   = c;
1008         sq->tc        = tc;
1009
1010         err = mlx5_alloc_bfreg(mdev, &sq->bfreg, MLX5_CAP_GEN(mdev, bf), false);
1011         if (err)
1012                 return err;
1013
1014         param->wq.db_numa_node = cpu_to_node(c->cpu);
1015
1016         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1017                                  &sq->wq_ctrl);
1018         if (err)
1019                 goto err_unmap_free_uar;
1020
1021         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
1022         if (sq->bfreg.wc)
1023                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
1024
1025         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1026         sq->max_inline  = param->max_inline;
1027         sq->min_inline_mode =
1028                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT ?
1029                 param->min_inline_mode : 0;
1030
1031         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
1032         if (err)
1033                 goto err_sq_wq_destroy;
1034
1035         if (sq->type == MLX5E_SQ_TXQ) {
1036                 int txq_ix;
1037
1038                 txq_ix = c->ix + tc * priv->params.num_channels;
1039                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
1040                 priv->txq_to_sq_map[txq_ix] = sq;
1041         }
1042
1043         sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
1044         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
1045
1046         return 0;
1047
1048 err_sq_wq_destroy:
1049         mlx5_wq_destroy(&sq->wq_ctrl);
1050
1051 err_unmap_free_uar:
1052         mlx5_free_bfreg(mdev, &sq->bfreg);
1053
1054         return err;
1055 }
1056
1057 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
1058 {
1059         struct mlx5e_channel *c = sq->channel;
1060         struct mlx5e_priv *priv = c->priv;
1061
1062         mlx5e_free_sq_db(sq);
1063         mlx5_wq_destroy(&sq->wq_ctrl);
1064         mlx5_free_bfreg(priv->mdev, &sq->bfreg);
1065 }
1066
1067 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1068 {
1069         struct mlx5e_channel *c = sq->channel;
1070         struct mlx5e_priv *priv = c->priv;
1071         struct mlx5_core_dev *mdev = priv->mdev;
1072
1073         void *in;
1074         void *sqc;
1075         void *wq;
1076         int inlen;
1077         int err;
1078
1079         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1080                 sizeof(u64) * sq->wq_ctrl.buf.npages;
1081         in = mlx5_vzalloc(inlen);
1082         if (!in)
1083                 return -ENOMEM;
1084
1085         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1086         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1087
1088         memcpy(sqc, param->sqc, sizeof(param->sqc));
1089
1090         MLX5_SET(sqc,  sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1091                                        0 : priv->tisn[sq->tc]);
1092         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
1093         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
1094         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
1095         MLX5_SET(sqc,  sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
1096
1097         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1098         MLX5_SET(wq,   wq, uar_page,      sq->bfreg.index);
1099         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
1100                                           MLX5_ADAPTER_PAGE_SHIFT);
1101         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
1102
1103         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1104                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1105
1106         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1107
1108         kvfree(in);
1109
1110         return err;
1111 }
1112
1113 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1114                            int next_state, bool update_rl, int rl_index)
1115 {
1116         struct mlx5e_channel *c = sq->channel;
1117         struct mlx5e_priv *priv = c->priv;
1118         struct mlx5_core_dev *mdev = priv->mdev;
1119
1120         void *in;
1121         void *sqc;
1122         int inlen;
1123         int err;
1124
1125         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1126         in = mlx5_vzalloc(inlen);
1127         if (!in)
1128                 return -ENOMEM;
1129
1130         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1131
1132         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1133         MLX5_SET(sqc, sqc, state, next_state);
1134         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1135                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1136                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
1137         }
1138
1139         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
1140
1141         kvfree(in);
1142
1143         return err;
1144 }
1145
1146 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1147 {
1148         struct mlx5e_channel *c = sq->channel;
1149         struct mlx5e_priv *priv = c->priv;
1150         struct mlx5_core_dev *mdev = priv->mdev;
1151
1152         mlx5_core_destroy_sq(mdev, sq->sqn);
1153         if (sq->rate_limit)
1154                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1155 }
1156
1157 static int mlx5e_open_sq(struct mlx5e_channel *c,
1158                          int tc,
1159                          struct mlx5e_sq_param *param,
1160                          struct mlx5e_sq *sq)
1161 {
1162         int err;
1163
1164         err = mlx5e_create_sq(c, tc, param, sq);
1165         if (err)
1166                 return err;
1167
1168         err = mlx5e_enable_sq(sq, param);
1169         if (err)
1170                 goto err_destroy_sq;
1171
1172         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1173         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1174                               false, 0);
1175         if (err)
1176                 goto err_disable_sq;
1177
1178         if (sq->txq) {
1179                 netdev_tx_reset_queue(sq->txq);
1180                 netif_tx_start_queue(sq->txq);
1181         }
1182
1183         return 0;
1184
1185 err_disable_sq:
1186         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1187         mlx5e_disable_sq(sq);
1188 err_destroy_sq:
1189         mlx5e_destroy_sq(sq);
1190
1191         return err;
1192 }
1193
1194 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1195 {
1196         __netif_tx_lock_bh(txq);
1197         netif_tx_stop_queue(txq);
1198         __netif_tx_unlock_bh(txq);
1199 }
1200
1201 static void mlx5e_close_sq(struct mlx5e_sq *sq)
1202 {
1203         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1204         /* prevent netif_tx_wake_queue */
1205         napi_synchronize(&sq->channel->napi);
1206
1207         if (sq->txq) {
1208                 netif_tx_disable_queue(sq->txq);
1209
1210                 /* last doorbell out, godspeed .. */
1211                 if (mlx5e_sq_has_room_for(sq, 1)) {
1212                         sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1213                         mlx5e_send_nop(sq, true);
1214                 }
1215         }
1216
1217         mlx5e_disable_sq(sq);
1218         mlx5e_free_sq_descs(sq);
1219         mlx5e_destroy_sq(sq);
1220 }
1221
1222 static int mlx5e_create_cq(struct mlx5e_channel *c,
1223                            struct mlx5e_cq_param *param,
1224                            struct mlx5e_cq *cq)
1225 {
1226         struct mlx5e_priv *priv = c->priv;
1227         struct mlx5_core_dev *mdev = priv->mdev;
1228         struct mlx5_core_cq *mcq = &cq->mcq;
1229         int eqn_not_used;
1230         unsigned int irqn;
1231         int err;
1232         u32 i;
1233
1234         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1235         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1236         param->eq_ix   = c->ix;
1237
1238         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1239                                &cq->wq_ctrl);
1240         if (err)
1241                 return err;
1242
1243         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1244
1245         cq->napi        = &c->napi;
1246
1247         mcq->cqe_sz     = 64;
1248         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1249         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1250         *mcq->set_ci_db = 0;
1251         *mcq->arm_db    = 0;
1252         mcq->vector     = param->eq_ix;
1253         mcq->comp       = mlx5e_completion_event;
1254         mcq->event      = mlx5e_cq_error_event;
1255         mcq->irqn       = irqn;
1256
1257         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1258                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1259
1260                 cqe->op_own = 0xf1;
1261         }
1262
1263         cq->channel = c;
1264         cq->priv = priv;
1265
1266         return 0;
1267 }
1268
1269 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1270 {
1271         mlx5_cqwq_destroy(&cq->wq_ctrl);
1272 }
1273
1274 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1275 {
1276         struct mlx5e_priv *priv = cq->priv;
1277         struct mlx5_core_dev *mdev = priv->mdev;
1278         struct mlx5_core_cq *mcq = &cq->mcq;
1279
1280         void *in;
1281         void *cqc;
1282         int inlen;
1283         unsigned int irqn_not_used;
1284         int eqn;
1285         int err;
1286
1287         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1288                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1289         in = mlx5_vzalloc(inlen);
1290         if (!in)
1291                 return -ENOMEM;
1292
1293         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1294
1295         memcpy(cqc, param->cqc, sizeof(param->cqc));
1296
1297         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1298                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1299
1300         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1301
1302         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1303         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1304         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1305         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1306                                             MLX5_ADAPTER_PAGE_SHIFT);
1307         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1308
1309         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1310
1311         kvfree(in);
1312
1313         if (err)
1314                 return err;
1315
1316         mlx5e_cq_arm(cq);
1317
1318         return 0;
1319 }
1320
1321 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1322 {
1323         struct mlx5e_priv *priv = cq->priv;
1324         struct mlx5_core_dev *mdev = priv->mdev;
1325
1326         mlx5_core_destroy_cq(mdev, &cq->mcq);
1327 }
1328
1329 static int mlx5e_open_cq(struct mlx5e_channel *c,
1330                          struct mlx5e_cq_param *param,
1331                          struct mlx5e_cq *cq,
1332                          struct mlx5e_cq_moder moderation)
1333 {
1334         int err;
1335         struct mlx5e_priv *priv = c->priv;
1336         struct mlx5_core_dev *mdev = priv->mdev;
1337
1338         err = mlx5e_create_cq(c, param, cq);
1339         if (err)
1340                 return err;
1341
1342         err = mlx5e_enable_cq(cq, param);
1343         if (err)
1344                 goto err_destroy_cq;
1345
1346         if (MLX5_CAP_GEN(mdev, cq_moderation))
1347                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1348                                                moderation.usec,
1349                                                moderation.pkts);
1350         return 0;
1351
1352 err_destroy_cq:
1353         mlx5e_destroy_cq(cq);
1354
1355         return err;
1356 }
1357
1358 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1359 {
1360         mlx5e_disable_cq(cq);
1361         mlx5e_destroy_cq(cq);
1362 }
1363
1364 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1365 {
1366         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1367 }
1368
1369 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1370                              struct mlx5e_channel_param *cparam)
1371 {
1372         struct mlx5e_priv *priv = c->priv;
1373         int err;
1374         int tc;
1375
1376         for (tc = 0; tc < c->num_tc; tc++) {
1377                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1378                                     priv->params.tx_cq_moderation);
1379                 if (err)
1380                         goto err_close_tx_cqs;
1381         }
1382
1383         return 0;
1384
1385 err_close_tx_cqs:
1386         for (tc--; tc >= 0; tc--)
1387                 mlx5e_close_cq(&c->sq[tc].cq);
1388
1389         return err;
1390 }
1391
1392 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1393 {
1394         int tc;
1395
1396         for (tc = 0; tc < c->num_tc; tc++)
1397                 mlx5e_close_cq(&c->sq[tc].cq);
1398 }
1399
1400 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1401                           struct mlx5e_channel_param *cparam)
1402 {
1403         int err;
1404         int tc;
1405
1406         for (tc = 0; tc < c->num_tc; tc++) {
1407                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1408                 if (err)
1409                         goto err_close_sqs;
1410         }
1411
1412         return 0;
1413
1414 err_close_sqs:
1415         for (tc--; tc >= 0; tc--)
1416                 mlx5e_close_sq(&c->sq[tc]);
1417
1418         return err;
1419 }
1420
1421 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1422 {
1423         int tc;
1424
1425         for (tc = 0; tc < c->num_tc; tc++)
1426                 mlx5e_close_sq(&c->sq[tc]);
1427 }
1428
1429 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1430 {
1431         int i;
1432
1433         for (i = 0; i < priv->profile->max_tc; i++)
1434                 priv->channeltc_to_txq_map[ix][i] =
1435                         ix + i * priv->params.num_channels;
1436 }
1437
1438 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1439                                 struct mlx5e_sq *sq, u32 rate)
1440 {
1441         struct mlx5e_priv *priv = netdev_priv(dev);
1442         struct mlx5_core_dev *mdev = priv->mdev;
1443         u16 rl_index = 0;
1444         int err;
1445
1446         if (rate == sq->rate_limit)
1447                 /* nothing to do */
1448                 return 0;
1449
1450         if (sq->rate_limit)
1451                 /* remove current rl index to free space to next ones */
1452                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1453
1454         sq->rate_limit = 0;
1455
1456         if (rate) {
1457                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1458                 if (err) {
1459                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1460                                    rate, err);
1461                         return err;
1462                 }
1463         }
1464
1465         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1466                               MLX5_SQC_STATE_RDY, true, rl_index);
1467         if (err) {
1468                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1469                            rate, err);
1470                 /* remove the rate from the table */
1471                 if (rate)
1472                         mlx5_rl_remove_rate(mdev, rate);
1473                 return err;
1474         }
1475
1476         sq->rate_limit = rate;
1477         return 0;
1478 }
1479
1480 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1481 {
1482         struct mlx5e_priv *priv = netdev_priv(dev);
1483         struct mlx5_core_dev *mdev = priv->mdev;
1484         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1485         int err = 0;
1486
1487         if (!mlx5_rl_is_supported(mdev)) {
1488                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1489                 return -EINVAL;
1490         }
1491
1492         /* rate is given in Mb/sec, HW config is in Kb/sec */
1493         rate = rate << 10;
1494
1495         /* Check whether rate in valid range, 0 is always valid */
1496         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1497                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1498                 return -ERANGE;
1499         }
1500
1501         mutex_lock(&priv->state_lock);
1502         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1503                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1504         if (!err)
1505                 priv->tx_rates[index] = rate;
1506         mutex_unlock(&priv->state_lock);
1507
1508         return err;
1509 }
1510
1511 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1512                               struct mlx5e_channel_param *cparam,
1513                               struct mlx5e_channel **cp)
1514 {
1515         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1516         struct net_device *netdev = priv->netdev;
1517         struct mlx5e_cq_moder rx_cq_profile;
1518         int cpu = mlx5e_get_cpu(priv, ix);
1519         struct mlx5e_channel *c;
1520         struct mlx5e_sq *sq;
1521         int err;
1522         int i;
1523
1524         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1525         if (!c)
1526                 return -ENOMEM;
1527
1528         c->priv     = priv;
1529         c->ix       = ix;
1530         c->cpu      = cpu;
1531         c->pdev     = &priv->mdev->pdev->dev;
1532         c->netdev   = priv->netdev;
1533         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1534         c->num_tc   = priv->params.num_tc;
1535         c->xdp      = !!priv->xdp_prog;
1536
1537         if (priv->params.rx_am_enabled)
1538                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1539         else
1540                 rx_cq_profile = priv->params.rx_cq_moderation;
1541
1542         mlx5e_build_channeltc_to_txq_map(priv, ix);
1543
1544         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1545
1546         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1547         if (err)
1548                 goto err_napi_del;
1549
1550         err = mlx5e_open_tx_cqs(c, cparam);
1551         if (err)
1552                 goto err_close_icosq_cq;
1553
1554         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1555                             rx_cq_profile);
1556         if (err)
1557                 goto err_close_tx_cqs;
1558
1559         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1560         err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1561                                      priv->params.tx_cq_moderation) : 0;
1562         if (err)
1563                 goto err_close_rx_cq;
1564
1565         napi_enable(&c->napi);
1566
1567         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1568         if (err)
1569                 goto err_disable_napi;
1570
1571         err = mlx5e_open_sqs(c, cparam);
1572         if (err)
1573                 goto err_close_icosq;
1574
1575         for (i = 0; i < priv->params.num_tc; i++) {
1576                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1577
1578                 if (priv->tx_rates[txq_ix]) {
1579                         sq = priv->txq_to_sq_map[txq_ix];
1580                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1581                                              priv->tx_rates[txq_ix]);
1582                 }
1583         }
1584
1585         err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1586         if (err)
1587                 goto err_close_sqs;
1588
1589         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1590         if (err)
1591                 goto err_close_xdp_sq;
1592
1593         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1594         *cp = c;
1595
1596         return 0;
1597 err_close_xdp_sq:
1598         if (c->xdp)
1599                 mlx5e_close_sq(&c->xdp_sq);
1600
1601 err_close_sqs:
1602         mlx5e_close_sqs(c);
1603
1604 err_close_icosq:
1605         mlx5e_close_sq(&c->icosq);
1606
1607 err_disable_napi:
1608         napi_disable(&c->napi);
1609         if (c->xdp)
1610                 mlx5e_close_cq(&c->xdp_sq.cq);
1611
1612 err_close_rx_cq:
1613         mlx5e_close_cq(&c->rq.cq);
1614
1615 err_close_tx_cqs:
1616         mlx5e_close_tx_cqs(c);
1617
1618 err_close_icosq_cq:
1619         mlx5e_close_cq(&c->icosq.cq);
1620
1621 err_napi_del:
1622         netif_napi_del(&c->napi);
1623         kfree(c);
1624
1625         return err;
1626 }
1627
1628 static void mlx5e_close_channel(struct mlx5e_channel *c)
1629 {
1630         mlx5e_close_rq(&c->rq);
1631         if (c->xdp)
1632                 mlx5e_close_sq(&c->xdp_sq);
1633         mlx5e_close_sqs(c);
1634         mlx5e_close_sq(&c->icosq);
1635         napi_disable(&c->napi);
1636         if (c->xdp)
1637                 mlx5e_close_cq(&c->xdp_sq.cq);
1638         mlx5e_close_cq(&c->rq.cq);
1639         mlx5e_close_tx_cqs(c);
1640         mlx5e_close_cq(&c->icosq.cq);
1641         netif_napi_del(&c->napi);
1642
1643         kfree(c);
1644 }
1645
1646 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1647                                  struct mlx5e_rq_param *param)
1648 {
1649         void *rqc = param->rqc;
1650         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1651
1652         switch (priv->params.rq_wq_type) {
1653         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1654                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1655                          priv->params.mpwqe_log_num_strides - 9);
1656                 MLX5_SET(wq, wq, log_wqe_stride_size,
1657                          priv->params.mpwqe_log_stride_sz - 6);
1658                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1659                 break;
1660         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1661                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1662         }
1663
1664         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1665         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1666         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1667         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1668         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1669
1670         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1671         param->wq.linear = 1;
1672
1673         param->am_enabled = priv->params.rx_am_enabled;
1674 }
1675
1676 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1677 {
1678         void *rqc = param->rqc;
1679         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1680
1681         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1682         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1683 }
1684
1685 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1686                                         struct mlx5e_sq_param *param)
1687 {
1688         void *sqc = param->sqc;
1689         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1690
1691         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1692         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1693
1694         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1695 }
1696
1697 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1698                                  struct mlx5e_sq_param *param)
1699 {
1700         void *sqc = param->sqc;
1701         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1702
1703         mlx5e_build_sq_param_common(priv, param);
1704         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1705
1706         param->max_inline = priv->params.tx_max_inline;
1707         param->min_inline_mode = priv->params.tx_min_inline_mode;
1708         param->type = MLX5E_SQ_TXQ;
1709 }
1710
1711 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1712                                         struct mlx5e_cq_param *param)
1713 {
1714         void *cqc = param->cqc;
1715
1716         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1717 }
1718
1719 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1720                                     struct mlx5e_cq_param *param)
1721 {
1722         void *cqc = param->cqc;
1723         u8 log_cq_size;
1724
1725         switch (priv->params.rq_wq_type) {
1726         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1727                 log_cq_size = priv->params.log_rq_size +
1728                         priv->params.mpwqe_log_num_strides;
1729                 break;
1730         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1731                 log_cq_size = priv->params.log_rq_size;
1732         }
1733
1734         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1735         if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1736                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1737                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1738         }
1739
1740         mlx5e_build_common_cq_param(priv, param);
1741
1742         param->cq_period_mode = priv->params.rx_cq_period_mode;
1743 }
1744
1745 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1746                                     struct mlx5e_cq_param *param)
1747 {
1748         void *cqc = param->cqc;
1749
1750         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1751
1752         mlx5e_build_common_cq_param(priv, param);
1753
1754         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1755 }
1756
1757 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1758                                      struct mlx5e_cq_param *param,
1759                                      u8 log_wq_size)
1760 {
1761         void *cqc = param->cqc;
1762
1763         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1764
1765         mlx5e_build_common_cq_param(priv, param);
1766
1767         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1768 }
1769
1770 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1771                                     struct mlx5e_sq_param *param,
1772                                     u8 log_wq_size)
1773 {
1774         void *sqc = param->sqc;
1775         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1776
1777         mlx5e_build_sq_param_common(priv, param);
1778
1779         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1780         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1781
1782         param->type = MLX5E_SQ_ICO;
1783 }
1784
1785 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1786                                     struct mlx5e_sq_param *param)
1787 {
1788         void *sqc = param->sqc;
1789         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1790
1791         mlx5e_build_sq_param_common(priv, param);
1792         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1793
1794         param->max_inline = priv->params.tx_max_inline;
1795         /* FOR XDP SQs will support only L2 inline mode */
1796         param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1797         param->type = MLX5E_SQ_XDP;
1798 }
1799
1800 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1801 {
1802         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1803
1804         mlx5e_build_rq_param(priv, &cparam->rq);
1805         mlx5e_build_sq_param(priv, &cparam->sq);
1806         mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
1807         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1808         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1809         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1810         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1811 }
1812
1813 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1814 {
1815         struct mlx5e_channel_param *cparam;
1816         int nch = priv->params.num_channels;
1817         int err = -ENOMEM;
1818         int i;
1819         int j;
1820
1821         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1822                                 GFP_KERNEL);
1823
1824         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1825                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1826
1827         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1828
1829         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1830                 goto err_free_txq_to_sq_map;
1831
1832         mlx5e_build_channel_param(priv, cparam);
1833
1834         for (i = 0; i < nch; i++) {
1835                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1836                 if (err)
1837                         goto err_close_channels;
1838         }
1839
1840         for (j = 0; j < nch; j++) {
1841                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1842                 if (err)
1843                         goto err_close_channels;
1844         }
1845
1846         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1847          * polling for inactive tx queues.
1848          */
1849         netif_tx_start_all_queues(priv->netdev);
1850
1851         kfree(cparam);
1852         return 0;
1853
1854 err_close_channels:
1855         for (i--; i >= 0; i--)
1856                 mlx5e_close_channel(priv->channel[i]);
1857
1858 err_free_txq_to_sq_map:
1859         kfree(priv->txq_to_sq_map);
1860         kfree(priv->channel);
1861         kfree(cparam);
1862
1863         return err;
1864 }
1865
1866 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1867 {
1868         int i;
1869
1870         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1871          * polling for inactive tx queues.
1872          */
1873         netif_tx_stop_all_queues(priv->netdev);
1874         netif_tx_disable(priv->netdev);
1875
1876         for (i = 0; i < priv->params.num_channels; i++)
1877                 mlx5e_close_channel(priv->channel[i]);
1878
1879         kfree(priv->txq_to_sq_map);
1880         kfree(priv->channel);
1881 }
1882
1883 static int mlx5e_rx_hash_fn(int hfunc)
1884 {
1885         return (hfunc == ETH_RSS_HASH_TOP) ?
1886                MLX5_RX_HASH_FN_TOEPLITZ :
1887                MLX5_RX_HASH_FN_INVERTED_XOR8;
1888 }
1889
1890 static int mlx5e_bits_invert(unsigned long a, int size)
1891 {
1892         int inv = 0;
1893         int i;
1894
1895         for (i = 0; i < size; i++)
1896                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1897
1898         return inv;
1899 }
1900
1901 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1902 {
1903         int i;
1904
1905         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1906                 int ix = i;
1907                 u32 rqn;
1908
1909                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1910                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1911
1912                 ix = priv->params.indirection_rqt[ix];
1913                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1914                                 priv->channel[ix]->rq.rqn :
1915                                 priv->drop_rq.rqn;
1916                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1917         }
1918 }
1919
1920 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1921                                       int ix)
1922 {
1923         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1924                         priv->channel[ix]->rq.rqn :
1925                         priv->drop_rq.rqn;
1926
1927         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1928 }
1929
1930 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1931                             int ix, struct mlx5e_rqt *rqt)
1932 {
1933         struct mlx5_core_dev *mdev = priv->mdev;
1934         void *rqtc;
1935         int inlen;
1936         int err;
1937         u32 *in;
1938
1939         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1940         in = mlx5_vzalloc(inlen);
1941         if (!in)
1942                 return -ENOMEM;
1943
1944         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1945
1946         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1947         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1948
1949         if (sz > 1) /* RSS */
1950                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1951         else
1952                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1953
1954         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1955         if (!err)
1956                 rqt->enabled = true;
1957
1958         kvfree(in);
1959         return err;
1960 }
1961
1962 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1963 {
1964         rqt->enabled = false;
1965         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1966 }
1967
1968 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1969 {
1970         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1971
1972         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1973 }
1974
1975 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1976 {
1977         struct mlx5e_rqt *rqt;
1978         int err;
1979         int ix;
1980
1981         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1982                 rqt = &priv->direct_tir[ix].rqt;
1983                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1984                 if (err)
1985                         goto err_destroy_rqts;
1986         }
1987
1988         return 0;
1989
1990 err_destroy_rqts:
1991         for (ix--; ix >= 0; ix--)
1992                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1993
1994         return err;
1995 }
1996
1997 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1998 {
1999         struct mlx5_core_dev *mdev = priv->mdev;
2000         void *rqtc;
2001         int inlen;
2002         u32 *in;
2003         int err;
2004
2005         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2006         in = mlx5_vzalloc(inlen);
2007         if (!in)
2008                 return -ENOMEM;
2009
2010         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2011
2012         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2013         if (sz > 1) /* RSS */
2014                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
2015         else
2016                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2017
2018         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2019
2020         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2021
2022         kvfree(in);
2023
2024         return err;
2025 }
2026
2027 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
2028 {
2029         u32 rqtn;
2030         int ix;
2031
2032         if (priv->indir_rqt.enabled) {
2033                 rqtn = priv->indir_rqt.rqtn;
2034                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
2035         }
2036
2037         for (ix = 0; ix < priv->params.num_channels; ix++) {
2038                 if (!priv->direct_tir[ix].rqt.enabled)
2039                         continue;
2040                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2041                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
2042         }
2043 }
2044
2045 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
2046 {
2047         if (!priv->params.lro_en)
2048                 return;
2049
2050 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2051
2052         MLX5_SET(tirc, tirc, lro_enable_mask,
2053                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2054                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2055         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2056                  (priv->params.lro_wqe_sz -
2057                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2058         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
2059 }
2060
2061 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
2062 {
2063         MLX5_SET(tirc, tirc, rx_hash_fn,
2064                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
2065         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
2066                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2067                                              rx_hash_toeplitz_key);
2068                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2069                                                rx_hash_toeplitz_key);
2070
2071                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2072                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2073         }
2074 }
2075
2076 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2077 {
2078         struct mlx5_core_dev *mdev = priv->mdev;
2079
2080         void *in;
2081         void *tirc;
2082         int inlen;
2083         int err;
2084         int tt;
2085         int ix;
2086
2087         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2088         in = mlx5_vzalloc(inlen);
2089         if (!in)
2090                 return -ENOMEM;
2091
2092         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2093         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2094
2095         mlx5e_build_tir_ctx_lro(tirc, priv);
2096
2097         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2098                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2099                                            inlen);
2100                 if (err)
2101                         goto free_in;
2102         }
2103
2104         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2105                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2106                                            in, inlen);
2107                 if (err)
2108                         goto free_in;
2109         }
2110
2111 free_in:
2112         kvfree(in);
2113
2114         return err;
2115 }
2116
2117 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2118 {
2119         struct mlx5_core_dev *mdev = priv->mdev;
2120         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2121         int err;
2122
2123         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2124         if (err)
2125                 return err;
2126
2127         /* Update vport context MTU */
2128         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2129         return 0;
2130 }
2131
2132 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2133 {
2134         struct mlx5_core_dev *mdev = priv->mdev;
2135         u16 hw_mtu = 0;
2136         int err;
2137
2138         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2139         if (err || !hw_mtu) /* fallback to port oper mtu */
2140                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2141
2142         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2143 }
2144
2145 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2146 {
2147         struct mlx5e_priv *priv = netdev_priv(netdev);
2148         u16 mtu;
2149         int err;
2150
2151         err = mlx5e_set_mtu(priv, netdev->mtu);
2152         if (err)
2153                 return err;
2154
2155         mlx5e_query_mtu(priv, &mtu);
2156         if (mtu != netdev->mtu)
2157                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2158                             __func__, mtu, netdev->mtu);
2159
2160         netdev->mtu = mtu;
2161         return 0;
2162 }
2163
2164 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2165 {
2166         struct mlx5e_priv *priv = netdev_priv(netdev);
2167         int nch = priv->params.num_channels;
2168         int ntc = priv->params.num_tc;
2169         int tc;
2170
2171         netdev_reset_tc(netdev);
2172
2173         if (ntc == 1)
2174                 return;
2175
2176         netdev_set_num_tc(netdev, ntc);
2177
2178         /* Map netdev TCs to offset 0
2179          * We have our own UP to TXQ mapping for QoS
2180          */
2181         for (tc = 0; tc < ntc; tc++)
2182                 netdev_set_tc_queue(netdev, tc, nch, 0);
2183 }
2184
2185 int mlx5e_open_locked(struct net_device *netdev)
2186 {
2187         struct mlx5e_priv *priv = netdev_priv(netdev);
2188         struct mlx5_core_dev *mdev = priv->mdev;
2189         int num_txqs;
2190         int err;
2191
2192         set_bit(MLX5E_STATE_OPENED, &priv->state);
2193
2194         mlx5e_netdev_set_tcs(netdev);
2195
2196         num_txqs = priv->params.num_channels * priv->params.num_tc;
2197         netif_set_real_num_tx_queues(netdev, num_txqs);
2198         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2199
2200         err = mlx5e_open_channels(priv);
2201         if (err) {
2202                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2203                            __func__, err);
2204                 goto err_clear_state_opened_flag;
2205         }
2206
2207         err = mlx5e_refresh_tirs_self_loopback(priv->mdev, false);
2208         if (err) {
2209                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2210                            __func__, err);
2211                 goto err_close_channels;
2212         }
2213
2214         mlx5e_redirect_rqts(priv);
2215         mlx5e_update_carrier(priv);
2216         mlx5e_timestamp_init(priv);
2217 #ifdef CONFIG_RFS_ACCEL
2218         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2219 #endif
2220         if (priv->profile->update_stats)
2221                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2222
2223         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2224                 err = mlx5e_add_sqs_fwd_rules(priv);
2225                 if (err)
2226                         goto err_close_channels;
2227         }
2228         return 0;
2229
2230 err_close_channels:
2231         mlx5e_close_channels(priv);
2232 err_clear_state_opened_flag:
2233         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2234         return err;
2235 }
2236
2237 int mlx5e_open(struct net_device *netdev)
2238 {
2239         struct mlx5e_priv *priv = netdev_priv(netdev);
2240         int err;
2241
2242         mutex_lock(&priv->state_lock);
2243         err = mlx5e_open_locked(netdev);
2244         mutex_unlock(&priv->state_lock);
2245
2246         return err;
2247 }
2248
2249 int mlx5e_close_locked(struct net_device *netdev)
2250 {
2251         struct mlx5e_priv *priv = netdev_priv(netdev);
2252         struct mlx5_core_dev *mdev = priv->mdev;
2253
2254         /* May already be CLOSED in case a previous configuration operation
2255          * (e.g RX/TX queue size change) that involves close&open failed.
2256          */
2257         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2258                 return 0;
2259
2260         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2261
2262         if (MLX5_CAP_GEN(mdev, vport_group_manager))
2263                 mlx5e_remove_sqs_fwd_rules(priv);
2264
2265         mlx5e_timestamp_cleanup(priv);
2266         netif_carrier_off(priv->netdev);
2267         mlx5e_redirect_rqts(priv);
2268         mlx5e_close_channels(priv);
2269
2270         return 0;
2271 }
2272
2273 int mlx5e_close(struct net_device *netdev)
2274 {
2275         struct mlx5e_priv *priv = netdev_priv(netdev);
2276         int err;
2277
2278         if (!netif_device_present(netdev))
2279                 return -ENODEV;
2280
2281         mutex_lock(&priv->state_lock);
2282         err = mlx5e_close_locked(netdev);
2283         mutex_unlock(&priv->state_lock);
2284
2285         return err;
2286 }
2287
2288 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2289                                 struct mlx5e_rq *rq,
2290                                 struct mlx5e_rq_param *param)
2291 {
2292         struct mlx5_core_dev *mdev = priv->mdev;
2293         void *rqc = param->rqc;
2294         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2295         int err;
2296
2297         param->wq.db_numa_node = param->wq.buf_numa_node;
2298
2299         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2300                                 &rq->wq_ctrl);
2301         if (err)
2302                 return err;
2303
2304         rq->priv = priv;
2305
2306         return 0;
2307 }
2308
2309 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2310                                 struct mlx5e_cq *cq,
2311                                 struct mlx5e_cq_param *param)
2312 {
2313         struct mlx5_core_dev *mdev = priv->mdev;
2314         struct mlx5_core_cq *mcq = &cq->mcq;
2315         int eqn_not_used;
2316         unsigned int irqn;
2317         int err;
2318
2319         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2320                                &cq->wq_ctrl);
2321         if (err)
2322                 return err;
2323
2324         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2325
2326         mcq->cqe_sz     = 64;
2327         mcq->set_ci_db  = cq->wq_ctrl.db.db;
2328         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
2329         *mcq->set_ci_db = 0;
2330         *mcq->arm_db    = 0;
2331         mcq->vector     = param->eq_ix;
2332         mcq->comp       = mlx5e_completion_event;
2333         mcq->event      = mlx5e_cq_error_event;
2334         mcq->irqn       = irqn;
2335
2336         cq->priv = priv;
2337
2338         return 0;
2339 }
2340
2341 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2342 {
2343         struct mlx5e_cq_param cq_param;
2344         struct mlx5e_rq_param rq_param;
2345         struct mlx5e_rq *rq = &priv->drop_rq;
2346         struct mlx5e_cq *cq = &priv->drop_rq.cq;
2347         int err;
2348
2349         memset(&cq_param, 0, sizeof(cq_param));
2350         memset(&rq_param, 0, sizeof(rq_param));
2351         mlx5e_build_drop_rq_param(&rq_param);
2352
2353         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2354         if (err)
2355                 return err;
2356
2357         err = mlx5e_enable_cq(cq, &cq_param);
2358         if (err)
2359                 goto err_destroy_cq;
2360
2361         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2362         if (err)
2363                 goto err_disable_cq;
2364
2365         err = mlx5e_enable_rq(rq, &rq_param);
2366         if (err)
2367                 goto err_destroy_rq;
2368
2369         return 0;
2370
2371 err_destroy_rq:
2372         mlx5e_destroy_rq(&priv->drop_rq);
2373
2374 err_disable_cq:
2375         mlx5e_disable_cq(&priv->drop_rq.cq);
2376
2377 err_destroy_cq:
2378         mlx5e_destroy_cq(&priv->drop_rq.cq);
2379
2380         return err;
2381 }
2382
2383 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2384 {
2385         mlx5e_disable_rq(&priv->drop_rq);
2386         mlx5e_destroy_rq(&priv->drop_rq);
2387         mlx5e_disable_cq(&priv->drop_rq.cq);
2388         mlx5e_destroy_cq(&priv->drop_rq.cq);
2389 }
2390
2391 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2392 {
2393         struct mlx5_core_dev *mdev = priv->mdev;
2394         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2395         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2396
2397         MLX5_SET(tisc, tisc, prio, tc << 1);
2398         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2399
2400         if (mlx5_lag_is_lacp_owner(mdev))
2401                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2402
2403         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2404 }
2405
2406 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2407 {
2408         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2409 }
2410
2411 int mlx5e_create_tises(struct mlx5e_priv *priv)
2412 {
2413         int err;
2414         int tc;
2415
2416         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2417                 err = mlx5e_create_tis(priv, tc);
2418                 if (err)
2419                         goto err_close_tises;
2420         }
2421
2422         return 0;
2423
2424 err_close_tises:
2425         for (tc--; tc >= 0; tc--)
2426                 mlx5e_destroy_tis(priv, tc);
2427
2428         return err;
2429 }
2430
2431 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2432 {
2433         int tc;
2434
2435         for (tc = 0; tc < priv->profile->max_tc; tc++)
2436                 mlx5e_destroy_tis(priv, tc);
2437 }
2438
2439 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2440                                       enum mlx5e_traffic_types tt)
2441 {
2442         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2443
2444         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2445
2446 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2447                                  MLX5_HASH_FIELD_SEL_DST_IP)
2448
2449 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2450                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2451                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2452                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2453
2454 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2455                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2456                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2457
2458         mlx5e_build_tir_ctx_lro(tirc, priv);
2459
2460         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2461         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2462         mlx5e_build_tir_ctx_hash(tirc, priv);
2463
2464         switch (tt) {
2465         case MLX5E_TT_IPV4_TCP:
2466                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2467                          MLX5_L3_PROT_TYPE_IPV4);
2468                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2469                          MLX5_L4_PROT_TYPE_TCP);
2470                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2471                          MLX5_HASH_IP_L4PORTS);
2472                 break;
2473
2474         case MLX5E_TT_IPV6_TCP:
2475                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2476                          MLX5_L3_PROT_TYPE_IPV6);
2477                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2478                          MLX5_L4_PROT_TYPE_TCP);
2479                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2480                          MLX5_HASH_IP_L4PORTS);
2481                 break;
2482
2483         case MLX5E_TT_IPV4_UDP:
2484                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2485                          MLX5_L3_PROT_TYPE_IPV4);
2486                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2487                          MLX5_L4_PROT_TYPE_UDP);
2488                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2489                          MLX5_HASH_IP_L4PORTS);
2490                 break;
2491
2492         case MLX5E_TT_IPV6_UDP:
2493                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2494                          MLX5_L3_PROT_TYPE_IPV6);
2495                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2496                          MLX5_L4_PROT_TYPE_UDP);
2497                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2498                          MLX5_HASH_IP_L4PORTS);
2499                 break;
2500
2501         case MLX5E_TT_IPV4_IPSEC_AH:
2502                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2503                          MLX5_L3_PROT_TYPE_IPV4);
2504                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2505                          MLX5_HASH_IP_IPSEC_SPI);
2506                 break;
2507
2508         case MLX5E_TT_IPV6_IPSEC_AH:
2509                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2510                          MLX5_L3_PROT_TYPE_IPV6);
2511                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2512                          MLX5_HASH_IP_IPSEC_SPI);
2513                 break;
2514
2515         case MLX5E_TT_IPV4_IPSEC_ESP:
2516                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2517                          MLX5_L3_PROT_TYPE_IPV4);
2518                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2519                          MLX5_HASH_IP_IPSEC_SPI);
2520                 break;
2521
2522         case MLX5E_TT_IPV6_IPSEC_ESP:
2523                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2524                          MLX5_L3_PROT_TYPE_IPV6);
2525                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2526                          MLX5_HASH_IP_IPSEC_SPI);
2527                 break;
2528
2529         case MLX5E_TT_IPV4:
2530                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2531                          MLX5_L3_PROT_TYPE_IPV4);
2532                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2533                          MLX5_HASH_IP);
2534                 break;
2535
2536         case MLX5E_TT_IPV6:
2537                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2538                          MLX5_L3_PROT_TYPE_IPV6);
2539                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2540                          MLX5_HASH_IP);
2541                 break;
2542         default:
2543                 WARN_ONCE(true,
2544                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2545         }
2546 }
2547
2548 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2549                                        u32 rqtn)
2550 {
2551         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2552
2553         mlx5e_build_tir_ctx_lro(tirc, priv);
2554
2555         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2556         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2557         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2558 }
2559
2560 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2561 {
2562         struct mlx5e_tir *tir;
2563         void *tirc;
2564         int inlen;
2565         int err;
2566         u32 *in;
2567         int tt;
2568
2569         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2570         in = mlx5_vzalloc(inlen);
2571         if (!in)
2572                 return -ENOMEM;
2573
2574         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2575                 memset(in, 0, inlen);
2576                 tir = &priv->indir_tir[tt];
2577                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2578                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2579                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2580                 if (err)
2581                         goto err_destroy_tirs;
2582         }
2583
2584         kvfree(in);
2585
2586         return 0;
2587
2588 err_destroy_tirs:
2589         for (tt--; tt >= 0; tt--)
2590                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2591
2592         kvfree(in);
2593
2594         return err;
2595 }
2596
2597 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2598 {
2599         int nch = priv->profile->max_nch(priv->mdev);
2600         struct mlx5e_tir *tir;
2601         void *tirc;
2602         int inlen;
2603         int err;
2604         u32 *in;
2605         int ix;
2606
2607         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2608         in = mlx5_vzalloc(inlen);
2609         if (!in)
2610                 return -ENOMEM;
2611
2612         for (ix = 0; ix < nch; ix++) {
2613                 memset(in, 0, inlen);
2614                 tir = &priv->direct_tir[ix];
2615                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2616                 mlx5e_build_direct_tir_ctx(priv, tirc,
2617                                            priv->direct_tir[ix].rqt.rqtn);
2618                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2619                 if (err)
2620                         goto err_destroy_ch_tirs;
2621         }
2622
2623         kvfree(in);
2624
2625         return 0;
2626
2627 err_destroy_ch_tirs:
2628         for (ix--; ix >= 0; ix--)
2629                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2630
2631         kvfree(in);
2632
2633         return err;
2634 }
2635
2636 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2637 {
2638         int i;
2639
2640         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2641                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2642 }
2643
2644 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2645 {
2646         int nch = priv->profile->max_nch(priv->mdev);
2647         int i;
2648
2649         for (i = 0; i < nch; i++)
2650                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2651 }
2652
2653 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2654 {
2655         int err = 0;
2656         int i;
2657
2658         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2659                 return 0;
2660
2661         for (i = 0; i < priv->params.num_channels; i++) {
2662                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2663                 if (err)
2664                         return err;
2665         }
2666
2667         return 0;
2668 }
2669
2670 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2671 {
2672         struct mlx5e_priv *priv = netdev_priv(netdev);
2673         bool was_opened;
2674         int err = 0;
2675
2676         if (tc && tc != MLX5E_MAX_NUM_TC)
2677                 return -EINVAL;
2678
2679         mutex_lock(&priv->state_lock);
2680
2681         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2682         if (was_opened)
2683                 mlx5e_close_locked(priv->netdev);
2684
2685         priv->params.num_tc = tc ? tc : 1;
2686
2687         if (was_opened)
2688                 err = mlx5e_open_locked(priv->netdev);
2689
2690         mutex_unlock(&priv->state_lock);
2691
2692         return err;
2693 }
2694
2695 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2696                               __be16 proto, struct tc_to_netdev *tc)
2697 {
2698         struct mlx5e_priv *priv = netdev_priv(dev);
2699
2700         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2701                 goto mqprio;
2702
2703         switch (tc->type) {
2704         case TC_SETUP_CLSFLOWER:
2705                 switch (tc->cls_flower->command) {
2706                 case TC_CLSFLOWER_REPLACE:
2707                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2708                 case TC_CLSFLOWER_DESTROY:
2709                         return mlx5e_delete_flower(priv, tc->cls_flower);
2710                 case TC_CLSFLOWER_STATS:
2711                         return mlx5e_stats_flower(priv, tc->cls_flower);
2712                 }
2713         default:
2714                 return -EOPNOTSUPP;
2715         }
2716
2717 mqprio:
2718         if (tc->type != TC_SETUP_MQPRIO)
2719                 return -EINVAL;
2720
2721         return mlx5e_setup_tc(dev, tc->tc);
2722 }
2723
2724 static void
2725 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2726 {
2727         struct mlx5e_priv *priv = netdev_priv(dev);
2728         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2729         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2730         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2731
2732         if (mlx5e_is_uplink_rep(priv)) {
2733                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2734                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
2735                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2736                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2737         } else {
2738                 stats->rx_packets = sstats->rx_packets;
2739                 stats->rx_bytes   = sstats->rx_bytes;
2740                 stats->tx_packets = sstats->tx_packets;
2741                 stats->tx_bytes   = sstats->tx_bytes;
2742                 stats->tx_dropped = sstats->tx_queue_dropped;
2743         }
2744
2745         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2746
2747         stats->rx_length_errors =
2748                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2749                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2750                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2751         stats->rx_crc_errors =
2752                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2753         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2754         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2755         stats->tx_carrier_errors =
2756                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2757         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2758                            stats->rx_frame_errors;
2759         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2760
2761         /* vport multicast also counts packets that are dropped due to steering
2762          * or rx out of buffer
2763          */
2764         stats->multicast =
2765                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2766
2767 }
2768
2769 static void mlx5e_set_rx_mode(struct net_device *dev)
2770 {
2771         struct mlx5e_priv *priv = netdev_priv(dev);
2772
2773         queue_work(priv->wq, &priv->set_rx_mode_work);
2774 }
2775
2776 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2777 {
2778         struct mlx5e_priv *priv = netdev_priv(netdev);
2779         struct sockaddr *saddr = addr;
2780
2781         if (!is_valid_ether_addr(saddr->sa_data))
2782                 return -EADDRNOTAVAIL;
2783
2784         netif_addr_lock_bh(netdev);
2785         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2786         netif_addr_unlock_bh(netdev);
2787
2788         queue_work(priv->wq, &priv->set_rx_mode_work);
2789
2790         return 0;
2791 }
2792
2793 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2794         do {                                            \
2795                 if (enable)                             \
2796                         netdev->features |= feature;    \
2797                 else                                    \
2798                         netdev->features &= ~feature;   \
2799         } while (0)
2800
2801 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2802
2803 static int set_feature_lro(struct net_device *netdev, bool enable)
2804 {
2805         struct mlx5e_priv *priv = netdev_priv(netdev);
2806         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2807         int err;
2808
2809         mutex_lock(&priv->state_lock);
2810
2811         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2812                 mlx5e_close_locked(priv->netdev);
2813
2814         priv->params.lro_en = enable;
2815         err = mlx5e_modify_tirs_lro(priv);
2816         if (err) {
2817                 netdev_err(netdev, "lro modify failed, %d\n", err);
2818                 priv->params.lro_en = !enable;
2819         }
2820
2821         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2822                 mlx5e_open_locked(priv->netdev);
2823
2824         mutex_unlock(&priv->state_lock);
2825
2826         return err;
2827 }
2828
2829 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2830 {
2831         struct mlx5e_priv *priv = netdev_priv(netdev);
2832
2833         if (enable)
2834                 mlx5e_enable_vlan_filter(priv);
2835         else
2836                 mlx5e_disable_vlan_filter(priv);
2837
2838         return 0;
2839 }
2840
2841 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2842 {
2843         struct mlx5e_priv *priv = netdev_priv(netdev);
2844
2845         if (!enable && mlx5e_tc_num_filters(priv)) {
2846                 netdev_err(netdev,
2847                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2848                 return -EINVAL;
2849         }
2850
2851         return 0;
2852 }
2853
2854 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2855 {
2856         struct mlx5e_priv *priv = netdev_priv(netdev);
2857         struct mlx5_core_dev *mdev = priv->mdev;
2858
2859         return mlx5_set_port_fcs(mdev, !enable);
2860 }
2861
2862 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2863 {
2864         struct mlx5e_priv *priv = netdev_priv(netdev);
2865         int err;
2866
2867         mutex_lock(&priv->state_lock);
2868
2869         priv->params.vlan_strip_disable = !enable;
2870         err = mlx5e_modify_rqs_vsd(priv, !enable);
2871         if (err)
2872                 priv->params.vlan_strip_disable = enable;
2873
2874         mutex_unlock(&priv->state_lock);
2875
2876         return err;
2877 }
2878
2879 #ifdef CONFIG_RFS_ACCEL
2880 static int set_feature_arfs(struct net_device *netdev, bool enable)
2881 {
2882         struct mlx5e_priv *priv = netdev_priv(netdev);
2883         int err;
2884
2885         if (enable)
2886                 err = mlx5e_arfs_enable(priv);
2887         else
2888                 err = mlx5e_arfs_disable(priv);
2889
2890         return err;
2891 }
2892 #endif
2893
2894 static int mlx5e_handle_feature(struct net_device *netdev,
2895                                 netdev_features_t wanted_features,
2896                                 netdev_features_t feature,
2897                                 mlx5e_feature_handler feature_handler)
2898 {
2899         netdev_features_t changes = wanted_features ^ netdev->features;
2900         bool enable = !!(wanted_features & feature);
2901         int err;
2902
2903         if (!(changes & feature))
2904                 return 0;
2905
2906         err = feature_handler(netdev, enable);
2907         if (err) {
2908                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2909                            enable ? "Enable" : "Disable", feature, err);
2910                 return err;
2911         }
2912
2913         MLX5E_SET_FEATURE(netdev, feature, enable);
2914         return 0;
2915 }
2916
2917 static int mlx5e_set_features(struct net_device *netdev,
2918                               netdev_features_t features)
2919 {
2920         int err;
2921
2922         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2923                                     set_feature_lro);
2924         err |= mlx5e_handle_feature(netdev, features,
2925                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2926                                     set_feature_vlan_filter);
2927         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2928                                     set_feature_tc_num_filters);
2929         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2930                                     set_feature_rx_all);
2931         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2932                                     set_feature_rx_vlan);
2933 #ifdef CONFIG_RFS_ACCEL
2934         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2935                                     set_feature_arfs);
2936 #endif
2937
2938         return err ? -EINVAL : 0;
2939 }
2940
2941 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2942 {
2943         struct mlx5e_priv *priv = netdev_priv(netdev);
2944         bool was_opened;
2945         int err = 0;
2946         bool reset;
2947
2948         mutex_lock(&priv->state_lock);
2949
2950         reset = !priv->params.lro_en &&
2951                 (priv->params.rq_wq_type !=
2952                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2953
2954         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2955         if (was_opened && reset)
2956                 mlx5e_close_locked(netdev);
2957
2958         netdev->mtu = new_mtu;
2959         mlx5e_set_dev_port_mtu(netdev);
2960
2961         if (was_opened && reset)
2962                 err = mlx5e_open_locked(netdev);
2963
2964         mutex_unlock(&priv->state_lock);
2965
2966         return err;
2967 }
2968
2969 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2970 {
2971         switch (cmd) {
2972         case SIOCSHWTSTAMP:
2973                 return mlx5e_hwstamp_set(dev, ifr);
2974         case SIOCGHWTSTAMP:
2975                 return mlx5e_hwstamp_get(dev, ifr);
2976         default:
2977                 return -EOPNOTSUPP;
2978         }
2979 }
2980
2981 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2982 {
2983         struct mlx5e_priv *priv = netdev_priv(dev);
2984         struct mlx5_core_dev *mdev = priv->mdev;
2985
2986         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2987 }
2988
2989 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2990                              __be16 vlan_proto)
2991 {
2992         struct mlx5e_priv *priv = netdev_priv(dev);
2993         struct mlx5_core_dev *mdev = priv->mdev;
2994
2995         if (vlan_proto != htons(ETH_P_8021Q))
2996                 return -EPROTONOSUPPORT;
2997
2998         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2999                                            vlan, qos);
3000 }
3001
3002 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3003 {
3004         struct mlx5e_priv *priv = netdev_priv(dev);
3005         struct mlx5_core_dev *mdev = priv->mdev;
3006
3007         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3008 }
3009
3010 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3011 {
3012         struct mlx5e_priv *priv = netdev_priv(dev);
3013         struct mlx5_core_dev *mdev = priv->mdev;
3014
3015         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3016 }
3017
3018 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3019                              int max_tx_rate)
3020 {
3021         struct mlx5e_priv *priv = netdev_priv(dev);
3022         struct mlx5_core_dev *mdev = priv->mdev;
3023
3024         if (min_tx_rate)
3025                 return -EOPNOTSUPP;
3026
3027         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3028                                            max_tx_rate);
3029 }
3030
3031 static int mlx5_vport_link2ifla(u8 esw_link)
3032 {
3033         switch (esw_link) {
3034         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3035                 return IFLA_VF_LINK_STATE_DISABLE;
3036         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3037                 return IFLA_VF_LINK_STATE_ENABLE;
3038         }
3039         return IFLA_VF_LINK_STATE_AUTO;
3040 }
3041
3042 static int mlx5_ifla_link2vport(u8 ifla_link)
3043 {
3044         switch (ifla_link) {
3045         case IFLA_VF_LINK_STATE_DISABLE:
3046                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3047         case IFLA_VF_LINK_STATE_ENABLE:
3048                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3049         }
3050         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3051 }
3052
3053 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3054                                    int link_state)
3055 {
3056         struct mlx5e_priv *priv = netdev_priv(dev);
3057         struct mlx5_core_dev *mdev = priv->mdev;
3058
3059         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3060                                             mlx5_ifla_link2vport(link_state));
3061 }
3062
3063 static int mlx5e_get_vf_config(struct net_device *dev,
3064                                int vf, struct ifla_vf_info *ivi)
3065 {
3066         struct mlx5e_priv *priv = netdev_priv(dev);
3067         struct mlx5_core_dev *mdev = priv->mdev;
3068         int err;
3069
3070         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3071         if (err)
3072                 return err;
3073         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3074         return 0;
3075 }
3076
3077 static int mlx5e_get_vf_stats(struct net_device *dev,
3078                               int vf, struct ifla_vf_stats *vf_stats)
3079 {
3080         struct mlx5e_priv *priv = netdev_priv(dev);
3081         struct mlx5_core_dev *mdev = priv->mdev;
3082
3083         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3084                                             vf_stats);
3085 }
3086
3087 void mlx5e_add_vxlan_port(struct net_device *netdev,
3088                           struct udp_tunnel_info *ti)
3089 {
3090         struct mlx5e_priv *priv = netdev_priv(netdev);
3091
3092         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3093                 return;
3094
3095         if (!mlx5e_vxlan_allowed(priv->mdev))
3096                 return;
3097
3098         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3099 }
3100
3101 void mlx5e_del_vxlan_port(struct net_device *netdev,
3102                           struct udp_tunnel_info *ti)
3103 {
3104         struct mlx5e_priv *priv = netdev_priv(netdev);
3105
3106         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3107                 return;
3108
3109         if (!mlx5e_vxlan_allowed(priv->mdev))
3110                 return;
3111
3112         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3113 }
3114
3115 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3116                                                     struct sk_buff *skb,
3117                                                     netdev_features_t features)
3118 {
3119         struct udphdr *udph;
3120         u16 proto;
3121         u16 port = 0;
3122
3123         switch (vlan_get_protocol(skb)) {
3124         case htons(ETH_P_IP):
3125                 proto = ip_hdr(skb)->protocol;
3126                 break;
3127         case htons(ETH_P_IPV6):
3128                 proto = ipv6_hdr(skb)->nexthdr;
3129                 break;
3130         default:
3131                 goto out;
3132         }
3133
3134         if (proto == IPPROTO_UDP) {
3135                 udph = udp_hdr(skb);
3136                 port = be16_to_cpu(udph->dest);
3137         }
3138
3139         /* Verify if UDP port is being offloaded by HW */
3140         if (port && mlx5e_vxlan_lookup_port(priv, port))
3141                 return features;
3142
3143 out:
3144         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3145         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3146 }
3147
3148 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3149                                               struct net_device *netdev,
3150                                               netdev_features_t features)
3151 {
3152         struct mlx5e_priv *priv = netdev_priv(netdev);
3153
3154         features = vlan_features_check(skb, features);
3155         features = vxlan_features_check(skb, features);
3156
3157         /* Validate if the tunneled packet is being offloaded by HW */
3158         if (skb->encapsulation &&
3159             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3160                 return mlx5e_vxlan_features_check(priv, skb, features);
3161
3162         return features;
3163 }
3164
3165 static void mlx5e_tx_timeout(struct net_device *dev)
3166 {
3167         struct mlx5e_priv *priv = netdev_priv(dev);
3168         bool sched_work = false;
3169         int i;
3170
3171         netdev_err(dev, "TX timeout detected\n");
3172
3173         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3174                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3175
3176                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3177                         continue;
3178                 sched_work = true;
3179                 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3180                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3181                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3182         }
3183
3184         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3185                 schedule_work(&priv->tx_timeout_work);
3186 }
3187
3188 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3189 {
3190         struct mlx5e_priv *priv = netdev_priv(netdev);
3191         struct bpf_prog *old_prog;
3192         int err = 0;
3193         bool reset, was_opened;
3194         int i;
3195
3196         mutex_lock(&priv->state_lock);
3197
3198         if ((netdev->features & NETIF_F_LRO) && prog) {
3199                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3200                 err = -EINVAL;
3201                 goto unlock;
3202         }
3203
3204         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3205         /* no need for full reset when exchanging programs */
3206         reset = (!priv->xdp_prog || !prog);
3207
3208         if (was_opened && reset)
3209                 mlx5e_close_locked(netdev);
3210         if (was_opened && !reset) {
3211                 /* num_channels is invariant here, so we can take the
3212                  * batched reference right upfront.
3213                  */
3214                 prog = bpf_prog_add(prog, priv->params.num_channels);
3215                 if (IS_ERR(prog)) {
3216                         err = PTR_ERR(prog);
3217                         goto unlock;
3218                 }
3219         }
3220
3221         /* exchange programs, extra prog reference we got from caller
3222          * as long as we don't fail from this point onwards.
3223          */
3224         old_prog = xchg(&priv->xdp_prog, prog);
3225         if (old_prog)
3226                 bpf_prog_put(old_prog);
3227
3228         if (reset) /* change RQ type according to priv->xdp_prog */
3229                 mlx5e_set_rq_priv_params(priv);
3230
3231         if (was_opened && reset)
3232                 mlx5e_open_locked(netdev);
3233
3234         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3235                 goto unlock;
3236
3237         /* exchanging programs w/o reset, we update ref counts on behalf
3238          * of the channels RQs here.
3239          */
3240         for (i = 0; i < priv->params.num_channels; i++) {
3241                 struct mlx5e_channel *c = priv->channel[i];
3242
3243                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3244                 napi_synchronize(&c->napi);
3245                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3246
3247                 old_prog = xchg(&c->rq.xdp_prog, prog);
3248
3249                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3250                 /* napi_schedule in case we have missed anything */
3251                 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3252                 napi_schedule(&c->napi);
3253
3254                 if (old_prog)
3255                         bpf_prog_put(old_prog);
3256         }
3257
3258 unlock:
3259         mutex_unlock(&priv->state_lock);
3260         return err;
3261 }
3262
3263 static bool mlx5e_xdp_attached(struct net_device *dev)
3264 {
3265         struct mlx5e_priv *priv = netdev_priv(dev);
3266
3267         return !!priv->xdp_prog;
3268 }
3269
3270 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3271 {
3272         switch (xdp->command) {
3273         case XDP_SETUP_PROG:
3274                 return mlx5e_xdp_set(dev, xdp->prog);
3275         case XDP_QUERY_PROG:
3276                 xdp->prog_attached = mlx5e_xdp_attached(dev);
3277                 return 0;
3278         default:
3279                 return -EINVAL;
3280         }
3281 }
3282
3283 #ifdef CONFIG_NET_POLL_CONTROLLER
3284 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3285  * reenabling interrupts.
3286  */
3287 static void mlx5e_netpoll(struct net_device *dev)
3288 {
3289         struct mlx5e_priv *priv = netdev_priv(dev);
3290         int i;
3291
3292         for (i = 0; i < priv->params.num_channels; i++)
3293                 napi_schedule(&priv->channel[i]->napi);
3294 }
3295 #endif
3296
3297 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3298         .ndo_open                = mlx5e_open,
3299         .ndo_stop                = mlx5e_close,
3300         .ndo_start_xmit          = mlx5e_xmit,
3301         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3302         .ndo_select_queue        = mlx5e_select_queue,
3303         .ndo_get_stats64         = mlx5e_get_stats,
3304         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3305         .ndo_set_mac_address     = mlx5e_set_mac,
3306         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3307         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3308         .ndo_set_features        = mlx5e_set_features,
3309         .ndo_change_mtu          = mlx5e_change_mtu,
3310         .ndo_do_ioctl            = mlx5e_ioctl,
3311         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3312 #ifdef CONFIG_RFS_ACCEL
3313         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3314 #endif
3315         .ndo_tx_timeout          = mlx5e_tx_timeout,
3316         .ndo_xdp                 = mlx5e_xdp,
3317 #ifdef CONFIG_NET_POLL_CONTROLLER
3318         .ndo_poll_controller     = mlx5e_netpoll,
3319 #endif
3320 };
3321
3322 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3323         .ndo_open                = mlx5e_open,
3324         .ndo_stop                = mlx5e_close,
3325         .ndo_start_xmit          = mlx5e_xmit,
3326         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3327         .ndo_select_queue        = mlx5e_select_queue,
3328         .ndo_get_stats64         = mlx5e_get_stats,
3329         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3330         .ndo_set_mac_address     = mlx5e_set_mac,
3331         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3332         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3333         .ndo_set_features        = mlx5e_set_features,
3334         .ndo_change_mtu          = mlx5e_change_mtu,
3335         .ndo_do_ioctl            = mlx5e_ioctl,
3336         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
3337         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
3338         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3339         .ndo_features_check      = mlx5e_features_check,
3340 #ifdef CONFIG_RFS_ACCEL
3341         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3342 #endif
3343         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
3344         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
3345         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
3346         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
3347         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
3348         .ndo_get_vf_config       = mlx5e_get_vf_config,
3349         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
3350         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
3351         .ndo_tx_timeout          = mlx5e_tx_timeout,
3352         .ndo_xdp                 = mlx5e_xdp,
3353 #ifdef CONFIG_NET_POLL_CONTROLLER
3354         .ndo_poll_controller     = mlx5e_netpoll,
3355 #endif
3356         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
3357         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
3358 };
3359
3360 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3361 {
3362         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3363                 return -ENOTSUPP;
3364         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3365             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3366             !MLX5_CAP_ETH(mdev, csum_cap) ||
3367             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3368             !MLX5_CAP_ETH(mdev, vlan_cap) ||
3369             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3370             MLX5_CAP_FLOWTABLE(mdev,
3371                                flow_table_properties_nic_receive.max_ft_level)
3372                                < 3) {
3373                 mlx5_core_warn(mdev,
3374                                "Not creating net device, some required device capabilities are missing\n");
3375                 return -ENOTSUPP;
3376         }
3377         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3378                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3379         if (!MLX5_CAP_GEN(mdev, cq_moderation))
3380                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3381
3382         return 0;
3383 }
3384
3385 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3386 {
3387         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3388
3389         return bf_buf_size -
3390                sizeof(struct mlx5e_tx_wqe) +
3391                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3392 }
3393
3394 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3395                                    u32 *indirection_rqt, int len,
3396                                    int num_channels)
3397 {
3398         int node = mdev->priv.numa_node;
3399         int node_num_of_cores;
3400         int i;
3401
3402         if (node == -1)
3403                 node = first_online_node;
3404
3405         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3406
3407         if (node_num_of_cores)
3408                 num_channels = min_t(int, num_channels, node_num_of_cores);
3409
3410         for (i = 0; i < len; i++)
3411                 indirection_rqt[i] = i % num_channels;
3412 }
3413
3414 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3415 {
3416         enum pcie_link_width width;
3417         enum pci_bus_speed speed;
3418         int err = 0;
3419
3420         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3421         if (err)
3422                 return err;
3423
3424         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3425                 return -EINVAL;
3426
3427         switch (speed) {
3428         case PCIE_SPEED_2_5GT:
3429                 *pci_bw = 2500 * width;
3430                 break;
3431         case PCIE_SPEED_5_0GT:
3432                 *pci_bw = 5000 * width;
3433                 break;
3434         case PCIE_SPEED_8_0GT:
3435                 *pci_bw = 8000 * width;
3436                 break;
3437         default:
3438                 return -EINVAL;
3439         }
3440
3441         return 0;
3442 }
3443
3444 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3445 {
3446         return (link_speed && pci_bw &&
3447                 (pci_bw < 40000) && (pci_bw < link_speed));
3448 }
3449
3450 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3451 {
3452         params->rx_cq_period_mode = cq_period_mode;
3453
3454         params->rx_cq_moderation.pkts =
3455                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3456         params->rx_cq_moderation.usec =
3457                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3458
3459         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3460                 params->rx_cq_moderation.usec =
3461                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3462 }
3463
3464 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3465                                    u8 *min_inline_mode)
3466 {
3467         switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
3468         case MLX5_CAP_INLINE_MODE_L2:
3469                 *min_inline_mode = MLX5_INLINE_MODE_L2;
3470                 break;
3471         case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3472                 mlx5_query_nic_vport_min_inline(mdev, 0, min_inline_mode);
3473                 break;
3474         case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
3475                 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3476                 break;
3477         }
3478 }
3479
3480 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3481 {
3482         int i;
3483
3484         /* The supported periods are organized in ascending order */
3485         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3486                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3487                         break;
3488
3489         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3490 }
3491
3492 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3493                                         struct net_device *netdev,
3494                                         const struct mlx5e_profile *profile,
3495                                         void *ppriv)
3496 {
3497         struct mlx5e_priv *priv = netdev_priv(netdev);
3498         u32 link_speed = 0;
3499         u32 pci_bw = 0;
3500         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3501                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3502                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3503
3504         priv->mdev                         = mdev;
3505         priv->netdev                       = netdev;
3506         priv->params.num_channels          = profile->max_nch(mdev);
3507         priv->profile                      = profile;
3508         priv->ppriv                        = ppriv;
3509
3510         priv->params.lro_timeout =
3511                 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3512
3513         priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3514
3515         /* set CQE compression */
3516         priv->params.rx_cqe_compress_def = false;
3517         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3518             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3519                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3520                 mlx5e_get_pci_bw(mdev, &pci_bw);
3521                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3522                               link_speed, pci_bw);
3523                 priv->params.rx_cqe_compress_def =
3524                         cqe_compress_heuristic(link_speed, pci_bw);
3525         }
3526
3527         mlx5e_set_rq_priv_params(priv);
3528         if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3529                 priv->params.lro_en = true;
3530
3531         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3532         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3533
3534         priv->params.tx_cq_moderation.usec =
3535                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3536         priv->params.tx_cq_moderation.pkts =
3537                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3538         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3539         mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3540         priv->params.num_tc                = 1;
3541         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3542
3543         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3544                             sizeof(priv->params.toeplitz_hash_key));
3545
3546         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3547                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3548
3549         priv->params.lro_wqe_sz =
3550                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3551                 /* Extra room needed for build_skb */
3552                 MLX5_RX_HEADROOM -
3553                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3554
3555         /* Initialize pflags */
3556         MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3557                         priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3558         MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, priv->params.rx_cqe_compress_def);
3559
3560         mutex_init(&priv->state_lock);
3561
3562         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3563         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3564         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3565         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3566 }
3567
3568 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3569 {
3570         struct mlx5e_priv *priv = netdev_priv(netdev);
3571
3572         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3573         if (is_zero_ether_addr(netdev->dev_addr) &&
3574             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3575                 eth_hw_addr_random(netdev);
3576                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3577         }
3578 }
3579
3580 static const struct switchdev_ops mlx5e_switchdev_ops = {
3581         .switchdev_port_attr_get        = mlx5e_attr_get,
3582 };
3583
3584 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3585 {
3586         struct mlx5e_priv *priv = netdev_priv(netdev);
3587         struct mlx5_core_dev *mdev = priv->mdev;
3588         bool fcs_supported;
3589         bool fcs_enabled;
3590
3591         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3592
3593         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3594                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3595 #ifdef CONFIG_MLX5_CORE_EN_DCB
3596                 if (MLX5_CAP_GEN(mdev, qos))
3597                         netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3598 #endif
3599         } else {
3600                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3601         }
3602
3603         netdev->watchdog_timeo    = 15 * HZ;
3604
3605         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3606
3607         netdev->vlan_features    |= NETIF_F_SG;
3608         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3609         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3610         netdev->vlan_features    |= NETIF_F_GRO;
3611         netdev->vlan_features    |= NETIF_F_TSO;
3612         netdev->vlan_features    |= NETIF_F_TSO6;
3613         netdev->vlan_features    |= NETIF_F_RXCSUM;
3614         netdev->vlan_features    |= NETIF_F_RXHASH;
3615
3616         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3617                 netdev->vlan_features    |= NETIF_F_LRO;
3618
3619         netdev->hw_features       = netdev->vlan_features;
3620         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3621         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3622         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3623
3624         if (mlx5e_vxlan_allowed(mdev)) {
3625                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3626                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3627                                            NETIF_F_GSO_PARTIAL;
3628                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3629                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3630                 netdev->hw_enc_features |= NETIF_F_TSO;
3631                 netdev->hw_enc_features |= NETIF_F_TSO6;
3632                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3633                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3634                                            NETIF_F_GSO_PARTIAL;
3635                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3636         }
3637
3638         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3639
3640         if (fcs_supported)
3641                 netdev->hw_features |= NETIF_F_RXALL;
3642
3643         netdev->features          = netdev->hw_features;
3644         if (!priv->params.lro_en)
3645                 netdev->features  &= ~NETIF_F_LRO;
3646
3647         if (fcs_enabled)
3648                 netdev->features  &= ~NETIF_F_RXALL;
3649
3650 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3651         if (FT_CAP(flow_modify_en) &&
3652             FT_CAP(modify_root) &&
3653             FT_CAP(identified_miss_table_mode) &&
3654             FT_CAP(flow_table_modify)) {
3655                 netdev->hw_features      |= NETIF_F_HW_TC;
3656 #ifdef CONFIG_RFS_ACCEL
3657                 netdev->hw_features      |= NETIF_F_NTUPLE;
3658 #endif
3659         }
3660
3661         netdev->features         |= NETIF_F_HIGHDMA;
3662
3663         netdev->priv_flags       |= IFF_UNICAST_FLT;
3664
3665         mlx5e_set_netdev_dev_addr(netdev);
3666
3667 #ifdef CONFIG_NET_SWITCHDEV
3668         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3669                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3670 #endif
3671 }
3672
3673 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3674 {
3675         struct mlx5_core_dev *mdev = priv->mdev;
3676         int err;
3677
3678         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3679         if (err) {
3680                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3681                 priv->q_counter = 0;
3682         }
3683 }
3684
3685 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3686 {
3687         if (!priv->q_counter)
3688                 return;
3689
3690         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3691 }
3692
3693 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3694                            struct net_device *netdev,
3695                            const struct mlx5e_profile *profile,
3696                            void *ppriv)
3697 {
3698         struct mlx5e_priv *priv = netdev_priv(netdev);
3699
3700         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3701         mlx5e_build_nic_netdev(netdev);
3702         mlx5e_vxlan_init(priv);
3703 }
3704
3705 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3706 {
3707         mlx5e_vxlan_cleanup(priv);
3708
3709         if (priv->xdp_prog)
3710                 bpf_prog_put(priv->xdp_prog);
3711 }
3712
3713 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3714 {
3715         struct mlx5_core_dev *mdev = priv->mdev;
3716         int err;
3717         int i;
3718
3719         err = mlx5e_create_indirect_rqts(priv);
3720         if (err) {
3721                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3722                 return err;
3723         }
3724
3725         err = mlx5e_create_direct_rqts(priv);
3726         if (err) {
3727                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3728                 goto err_destroy_indirect_rqts;
3729         }
3730
3731         err = mlx5e_create_indirect_tirs(priv);
3732         if (err) {
3733                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3734                 goto err_destroy_direct_rqts;
3735         }
3736
3737         err = mlx5e_create_direct_tirs(priv);
3738         if (err) {
3739                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3740                 goto err_destroy_indirect_tirs;
3741         }
3742
3743         err = mlx5e_create_flow_steering(priv);
3744         if (err) {
3745                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3746                 goto err_destroy_direct_tirs;
3747         }
3748
3749         err = mlx5e_tc_init(priv);
3750         if (err)
3751                 goto err_destroy_flow_steering;
3752
3753         return 0;
3754
3755 err_destroy_flow_steering:
3756         mlx5e_destroy_flow_steering(priv);
3757 err_destroy_direct_tirs:
3758         mlx5e_destroy_direct_tirs(priv);
3759 err_destroy_indirect_tirs:
3760         mlx5e_destroy_indirect_tirs(priv);
3761 err_destroy_direct_rqts:
3762         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3763                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3764 err_destroy_indirect_rqts:
3765         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3766         return err;
3767 }
3768
3769 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3770 {
3771         int i;
3772
3773         mlx5e_tc_cleanup(priv);
3774         mlx5e_destroy_flow_steering(priv);
3775         mlx5e_destroy_direct_tirs(priv);
3776         mlx5e_destroy_indirect_tirs(priv);
3777         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3778                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3779         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3780 }
3781
3782 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3783 {
3784         int err;
3785
3786         err = mlx5e_create_tises(priv);
3787         if (err) {
3788                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3789                 return err;
3790         }
3791
3792 #ifdef CONFIG_MLX5_CORE_EN_DCB
3793         mlx5e_dcbnl_initialize(priv);
3794 #endif
3795         return 0;
3796 }
3797
3798 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3799 {
3800         struct net_device *netdev = priv->netdev;
3801         struct mlx5_core_dev *mdev = priv->mdev;
3802         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3803         struct mlx5_eswitch_rep rep;
3804
3805         mlx5_lag_add(mdev, netdev);
3806
3807         mlx5e_enable_async_events(priv);
3808
3809         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3810                 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3811                 rep.load = mlx5e_nic_rep_load;
3812                 rep.unload = mlx5e_nic_rep_unload;
3813                 rep.vport = FDB_UPLINK_VPORT;
3814                 rep.netdev = netdev;
3815                 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
3816         }
3817
3818         if (netdev->reg_state != NETREG_REGISTERED)
3819                 return;
3820
3821         /* Device already registered: sync netdev system state */
3822         if (mlx5e_vxlan_allowed(mdev)) {
3823                 rtnl_lock();
3824                 udp_tunnel_get_rx_info(netdev);
3825                 rtnl_unlock();
3826         }
3827
3828         queue_work(priv->wq, &priv->set_rx_mode_work);
3829 }
3830
3831 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3832 {
3833         struct mlx5_core_dev *mdev = priv->mdev;
3834         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3835
3836         queue_work(priv->wq, &priv->set_rx_mode_work);
3837         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3838                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3839         mlx5e_disable_async_events(priv);
3840         mlx5_lag_remove(mdev);
3841 }
3842
3843 static const struct mlx5e_profile mlx5e_nic_profile = {
3844         .init              = mlx5e_nic_init,
3845         .cleanup           = mlx5e_nic_cleanup,
3846         .init_rx           = mlx5e_init_nic_rx,
3847         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3848         .init_tx           = mlx5e_init_nic_tx,
3849         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3850         .enable            = mlx5e_nic_enable,
3851         .disable           = mlx5e_nic_disable,
3852         .update_stats      = mlx5e_update_stats,
3853         .max_nch           = mlx5e_get_max_num_channels,
3854         .max_tc            = MLX5E_MAX_NUM_TC,
3855 };
3856
3857 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3858                                        const struct mlx5e_profile *profile,
3859                                        void *ppriv)
3860 {
3861         int nch = profile->max_nch(mdev);
3862         struct net_device *netdev;
3863         struct mlx5e_priv *priv;
3864
3865         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3866                                     nch * profile->max_tc,
3867                                     nch);
3868         if (!netdev) {
3869                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3870                 return NULL;
3871         }
3872
3873         profile->init(mdev, netdev, profile, ppriv);
3874
3875         netif_carrier_off(netdev);
3876
3877         priv = netdev_priv(netdev);
3878
3879         priv->wq = create_singlethread_workqueue("mlx5e");
3880         if (!priv->wq)
3881                 goto err_cleanup_nic;
3882
3883         return netdev;
3884
3885 err_cleanup_nic:
3886         profile->cleanup(priv);
3887         free_netdev(netdev);
3888
3889         return NULL;
3890 }
3891
3892 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3893 {
3894         const struct mlx5e_profile *profile;
3895         struct mlx5e_priv *priv;
3896         u16 max_mtu;
3897         int err;
3898
3899         priv = netdev_priv(netdev);
3900         profile = priv->profile;
3901         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
3902
3903         err = profile->init_tx(priv);
3904         if (err)
3905                 goto out;
3906
3907         err = mlx5e_open_drop_rq(priv);
3908         if (err) {
3909                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3910                 goto err_cleanup_tx;
3911         }
3912
3913         err = profile->init_rx(priv);
3914         if (err)
3915                 goto err_close_drop_rq;
3916
3917         mlx5e_create_q_counter(priv);
3918
3919         mlx5e_init_l2_addr(priv);
3920
3921         /* MTU range: 68 - hw-specific max */
3922         netdev->min_mtu = ETH_MIN_MTU;
3923         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
3924         netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
3925
3926         mlx5e_set_dev_port_mtu(netdev);
3927
3928         if (profile->enable)
3929                 profile->enable(priv);
3930
3931         rtnl_lock();
3932         if (netif_running(netdev))
3933                 mlx5e_open(netdev);
3934         netif_device_attach(netdev);
3935         rtnl_unlock();
3936
3937         return 0;
3938
3939 err_close_drop_rq:
3940         mlx5e_close_drop_rq(priv);
3941
3942 err_cleanup_tx:
3943         profile->cleanup_tx(priv);
3944
3945 out:
3946         return err;
3947 }
3948
3949 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3950 {
3951         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3952         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3953         int vport;
3954         u8 mac[ETH_ALEN];
3955
3956         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3957                 return;
3958
3959         mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3960
3961         for (vport = 1; vport < total_vfs; vport++) {
3962                 struct mlx5_eswitch_rep rep;
3963
3964                 rep.load = mlx5e_vport_rep_load;
3965                 rep.unload = mlx5e_vport_rep_unload;
3966                 rep.vport = vport;
3967                 ether_addr_copy(rep.hw_id, mac);
3968                 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
3969         }
3970 }
3971
3972 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3973 {
3974         struct mlx5e_priv *priv = netdev_priv(netdev);
3975         const struct mlx5e_profile *profile = priv->profile;
3976
3977         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3978
3979         rtnl_lock();
3980         if (netif_running(netdev))
3981                 mlx5e_close(netdev);
3982         netif_device_detach(netdev);
3983         rtnl_unlock();
3984
3985         if (profile->disable)
3986                 profile->disable(priv);
3987         flush_workqueue(priv->wq);
3988
3989         mlx5e_destroy_q_counter(priv);
3990         profile->cleanup_rx(priv);
3991         mlx5e_close_drop_rq(priv);
3992         profile->cleanup_tx(priv);
3993         cancel_delayed_work_sync(&priv->update_stats_work);
3994 }
3995
3996 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3997  * hardware contexts and to connect it to the current netdev.
3998  */
3999 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4000 {
4001         struct mlx5e_priv *priv = vpriv;
4002         struct net_device *netdev = priv->netdev;
4003         int err;
4004
4005         if (netif_device_present(netdev))
4006                 return 0;
4007
4008         err = mlx5e_create_mdev_resources(mdev);
4009         if (err)
4010                 return err;
4011
4012         err = mlx5e_attach_netdev(mdev, netdev);
4013         if (err) {
4014                 mlx5e_destroy_mdev_resources(mdev);
4015                 return err;
4016         }
4017
4018         return 0;
4019 }
4020
4021 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4022 {
4023         struct mlx5e_priv *priv = vpriv;
4024         struct net_device *netdev = priv->netdev;
4025
4026         if (!netif_device_present(netdev))
4027                 return;
4028
4029         mlx5e_detach_netdev(mdev, netdev);
4030         mlx5e_destroy_mdev_resources(mdev);
4031 }
4032
4033 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4034 {
4035         struct mlx5_eswitch *esw = mdev->priv.eswitch;
4036         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4037         void *ppriv = NULL;
4038         void *priv;
4039         int vport;
4040         int err;
4041         struct net_device *netdev;
4042
4043         err = mlx5e_check_required_hca_cap(mdev);
4044         if (err)
4045                 return NULL;
4046
4047         mlx5e_register_vport_rep(mdev);
4048
4049         if (MLX5_CAP_GEN(mdev, vport_group_manager))
4050                 ppriv = &esw->offloads.vport_reps[0];
4051
4052         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4053         if (!netdev) {
4054                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4055                 goto err_unregister_reps;
4056         }
4057
4058         priv = netdev_priv(netdev);
4059
4060         err = mlx5e_attach(mdev, priv);
4061         if (err) {
4062                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4063                 goto err_destroy_netdev;
4064         }
4065
4066         err = register_netdev(netdev);
4067         if (err) {
4068                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4069                 goto err_detach;
4070         }
4071
4072         return priv;
4073
4074 err_detach:
4075         mlx5e_detach(mdev, priv);
4076
4077 err_destroy_netdev:
4078         mlx5e_destroy_netdev(mdev, priv);
4079
4080 err_unregister_reps:
4081         for (vport = 1; vport < total_vfs; vport++)
4082                 mlx5_eswitch_unregister_vport_rep(esw, vport);
4083
4084         return NULL;
4085 }
4086
4087 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
4088 {
4089         const struct mlx5e_profile *profile = priv->profile;
4090         struct net_device *netdev = priv->netdev;
4091
4092         destroy_workqueue(priv->wq);
4093         if (profile->cleanup)
4094                 profile->cleanup(priv);
4095         free_netdev(netdev);
4096 }
4097
4098 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4099 {
4100         struct mlx5_eswitch *esw = mdev->priv.eswitch;
4101         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4102         struct mlx5e_priv *priv = vpriv;
4103         int vport;
4104
4105         for (vport = 1; vport < total_vfs; vport++)
4106                 mlx5_eswitch_unregister_vport_rep(esw, vport);
4107
4108         unregister_netdev(priv->netdev);
4109         mlx5e_detach(mdev, vpriv);
4110         mlx5e_destroy_netdev(mdev, priv);
4111 }
4112
4113 static void *mlx5e_get_netdev(void *vpriv)
4114 {
4115         struct mlx5e_priv *priv = vpriv;
4116
4117         return priv->netdev;
4118 }
4119
4120 static struct mlx5_interface mlx5e_interface = {
4121         .add       = mlx5e_add,
4122         .remove    = mlx5e_remove,
4123         .attach    = mlx5e_attach,
4124         .detach    = mlx5e_detach,
4125         .event     = mlx5e_async_event,
4126         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
4127         .get_dev   = mlx5e_get_netdev,
4128 };
4129
4130 void mlx5e_init(void)
4131 {
4132         mlx5e_build_ptys2ethtool_map();
4133         mlx5_register_interface(&mlx5e_interface);
4134 }
4135
4136 void mlx5e_cleanup(void)
4137 {
4138         mlx5_unregister_interface(&mlx5e_interface);
4139 }