2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
42 struct mlx5e_rq_param {
43 u32 rqc[MLX5_ST_SZ_DW(rqc)];
44 struct mlx5_wq_param wq;
47 struct mlx5e_sq_param {
48 u32 sqc[MLX5_ST_SZ_DW(sqc)];
49 struct mlx5_wq_param wq;
54 struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
60 struct mlx5e_channel_param {
61 struct mlx5e_rq_param rq;
62 struct mlx5e_sq_param sq;
63 struct mlx5e_sq_param icosq;
64 struct mlx5e_cq_param rx_cq;
65 struct mlx5e_cq_param tx_cq;
66 struct mlx5e_cq_param icosq_cq;
69 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
71 struct mlx5_core_dev *mdev = priv->mdev;
74 port_state = mlx5_query_vport_state(mdev,
75 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
77 if (port_state == VPORT_STATE_UP)
78 netif_carrier_on(priv->netdev);
80 netif_carrier_off(priv->netdev);
83 static void mlx5e_update_carrier_work(struct work_struct *work)
85 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
88 mutex_lock(&priv->state_lock);
89 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
90 mlx5e_update_carrier(priv);
91 mutex_unlock(&priv->state_lock);
94 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
96 struct mlx5e_sw_stats *s = &priv->stats.sw;
97 struct mlx5e_rq_stats *rq_stats;
98 struct mlx5e_sq_stats *sq_stats;
99 u64 tx_offload_none = 0;
102 memset(s, 0, sizeof(*s));
103 for (i = 0; i < priv->params.num_channels; i++) {
104 rq_stats = &priv->channel[i]->rq.stats;
106 s->rx_packets += rq_stats->packets;
107 s->rx_bytes += rq_stats->bytes;
108 s->lro_packets += rq_stats->lro_packets;
109 s->lro_bytes += rq_stats->lro_bytes;
110 s->rx_csum_none += rq_stats->csum_none;
111 s->rx_csum_sw += rq_stats->csum_sw;
112 s->rx_wqe_err += rq_stats->wqe_err;
113 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
114 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
115 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
117 for (j = 0; j < priv->params.num_tc; j++) {
118 sq_stats = &priv->channel[i]->sq[j].stats;
120 s->tx_packets += sq_stats->packets;
121 s->tx_bytes += sq_stats->bytes;
122 s->tso_packets += sq_stats->tso_packets;
123 s->tso_bytes += sq_stats->tso_bytes;
124 s->tso_inner_packets += sq_stats->tso_inner_packets;
125 s->tso_inner_bytes += sq_stats->tso_inner_bytes;
126 s->tx_queue_stopped += sq_stats->stopped;
127 s->tx_queue_wake += sq_stats->wake;
128 s->tx_queue_dropped += sq_stats->dropped;
129 s->tx_csum_inner += sq_stats->csum_offload_inner;
130 tx_offload_none += sq_stats->csum_offload_none;
134 /* Update calculated offload counters */
135 s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
136 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
139 s->link_down_events = MLX5_GET(ppcnt_reg,
140 priv->stats.pport.phy_counters,
141 counter_set.phys_layer_cntrs.link_down_events);
144 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
146 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
147 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
148 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
149 struct mlx5_core_dev *mdev = priv->mdev;
151 memset(in, 0, sizeof(in));
153 MLX5_SET(query_vport_counter_in, in, opcode,
154 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
155 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
156 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
158 memset(out, 0, outlen);
160 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
163 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
165 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
166 struct mlx5_core_dev *mdev = priv->mdev;
167 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
172 in = mlx5_vzalloc(sz);
176 MLX5_SET(ppcnt_reg, in, local_port, 1);
178 out = pstats->IEEE_802_3_counters;
179 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
180 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
182 out = pstats->RFC_2863_counters;
183 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
184 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
186 out = pstats->RFC_2819_counters;
187 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
188 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
190 out = pstats->phy_counters;
191 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
192 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
194 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
195 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
196 out = pstats->per_prio_counters[prio];
197 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
198 mlx5_core_access_reg(mdev, in, sz, out, sz,
199 MLX5_REG_PPCNT, 0, 0);
206 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
208 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
210 if (!priv->q_counter)
213 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
214 &qcnt->rx_out_of_buffer);
217 void mlx5e_update_stats(struct mlx5e_priv *priv)
219 mlx5e_update_q_counter(priv);
220 mlx5e_update_vport_counters(priv);
221 mlx5e_update_pport_counters(priv);
222 mlx5e_update_sw_counters(priv);
225 static void mlx5e_update_stats_work(struct work_struct *work)
227 struct delayed_work *dwork = to_delayed_work(work);
228 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
230 mutex_lock(&priv->state_lock);
231 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
232 mlx5e_update_stats(priv);
233 schedule_delayed_work(dwork,
235 MLX5E_UPDATE_STATS_INTERVAL));
237 mutex_unlock(&priv->state_lock);
240 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
241 enum mlx5_dev_event event, unsigned long param)
243 struct mlx5e_priv *priv = vpriv;
245 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
249 case MLX5_DEV_EVENT_PORT_UP:
250 case MLX5_DEV_EVENT_PORT_DOWN:
251 schedule_work(&priv->update_carrier_work);
259 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
261 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
264 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
266 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
267 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
270 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
271 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
273 static int mlx5e_create_rq(struct mlx5e_channel *c,
274 struct mlx5e_rq_param *param,
277 struct mlx5e_priv *priv = c->priv;
278 struct mlx5_core_dev *mdev = priv->mdev;
279 void *rqc = param->rqc;
280 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
286 param->wq.db_numa_node = cpu_to_node(c->cpu);
288 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
293 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
295 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
297 switch (priv->params.rq_wq_type) {
298 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
299 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
300 GFP_KERNEL, cpu_to_node(c->cpu));
303 goto err_rq_wq_destroy;
305 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
306 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
308 rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE;
309 byte_count = rq->wqe_sz;
311 default: /* MLX5_WQ_TYPE_LINKED_LIST */
312 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
313 cpu_to_node(c->cpu));
316 goto err_rq_wq_destroy;
318 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
319 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
321 rq->wqe_sz = (priv->params.lro_en) ?
322 priv->params.lro_wqe_sz :
323 MLX5E_SW2HW_MTU(priv->netdev->mtu);
324 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
325 byte_count = rq->wqe_sz;
326 byte_count |= MLX5_HW_START_PADDING;
329 for (i = 0; i < wq_sz; i++) {
330 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
332 wqe->data.byte_count = cpu_to_be32(byte_count);
335 rq->wq_type = priv->params.rq_wq_type;
337 rq->netdev = c->netdev;
338 rq->tstamp = &priv->tstamp;
342 rq->mkey_be = c->mkey_be;
343 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
348 mlx5_wq_destroy(&rq->wq_ctrl);
353 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
355 switch (rq->wq_type) {
356 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
359 default: /* MLX5_WQ_TYPE_LINKED_LIST */
363 mlx5_wq_destroy(&rq->wq_ctrl);
366 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
368 struct mlx5e_priv *priv = rq->priv;
369 struct mlx5_core_dev *mdev = priv->mdev;
377 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
378 sizeof(u64) * rq->wq_ctrl.buf.npages;
379 in = mlx5_vzalloc(inlen);
383 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
384 wq = MLX5_ADDR_OF(rqc, rqc, wq);
386 memcpy(rqc, param->rqc, sizeof(param->rqc));
388 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
389 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
390 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
391 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
392 MLX5_ADAPTER_PAGE_SHIFT);
393 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
395 mlx5_fill_page_array(&rq->wq_ctrl.buf,
396 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
398 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
405 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
407 struct mlx5e_channel *c = rq->channel;
408 struct mlx5e_priv *priv = c->priv;
409 struct mlx5_core_dev *mdev = priv->mdev;
416 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
417 in = mlx5_vzalloc(inlen);
421 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
423 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
424 MLX5_SET(rqc, rqc, state, next_state);
426 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
433 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
435 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
438 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
440 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
441 struct mlx5e_channel *c = rq->channel;
442 struct mlx5e_priv *priv = c->priv;
443 struct mlx5_wq_ll *wq = &rq->wq;
445 while (time_before(jiffies, exp_time)) {
446 if (wq->cur_sz >= priv->params.min_rx_wqes)
455 static int mlx5e_open_rq(struct mlx5e_channel *c,
456 struct mlx5e_rq_param *param,
459 struct mlx5e_sq *sq = &c->icosq;
460 u16 pi = sq->pc & sq->wq.sz_m1;
463 err = mlx5e_create_rq(c, param, rq);
467 err = mlx5e_enable_rq(rq, param);
471 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
475 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
477 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
478 sq->ico_wqe_info[pi].num_wqebbs = 1;
479 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
484 mlx5e_disable_rq(rq);
486 mlx5e_destroy_rq(rq);
491 static void mlx5e_close_rq(struct mlx5e_rq *rq)
493 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
494 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
496 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
497 while (!mlx5_wq_ll_is_empty(&rq->wq))
500 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
501 napi_synchronize(&rq->channel->napi);
503 mlx5e_disable_rq(rq);
504 mlx5e_destroy_rq(rq);
507 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
514 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
516 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
517 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
519 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
520 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
522 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
525 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
526 mlx5e_free_sq_db(sq);
530 sq->dma_fifo_mask = df_sz - 1;
535 static int mlx5e_create_sq(struct mlx5e_channel *c,
537 struct mlx5e_sq_param *param,
540 struct mlx5e_priv *priv = c->priv;
541 struct mlx5_core_dev *mdev = priv->mdev;
543 void *sqc = param->sqc;
544 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
547 err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
551 param->wq.db_numa_node = cpu_to_node(c->cpu);
553 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
556 goto err_unmap_free_uar;
558 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
559 if (sq->uar.bf_map) {
560 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
561 sq->uar_map = sq->uar.bf_map;
563 sq->uar_map = sq->uar.map;
565 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
566 sq->max_inline = param->max_inline;
568 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
570 goto err_sq_wq_destroy;
573 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
575 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
578 cpu_to_node(c->cpu));
579 if (!sq->ico_wqe_info) {
586 txq_ix = c->ix + tc * priv->params.num_channels;
587 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
588 priv->txq_to_sq_map[txq_ix] = sq;
592 sq->tstamp = &priv->tstamp;
593 sq->mkey_be = c->mkey_be;
596 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
597 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
602 mlx5e_free_sq_db(sq);
605 mlx5_wq_destroy(&sq->wq_ctrl);
608 mlx5_unmap_free_uar(mdev, &sq->uar);
613 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
615 struct mlx5e_channel *c = sq->channel;
616 struct mlx5e_priv *priv = c->priv;
618 kfree(sq->ico_wqe_info);
619 mlx5e_free_sq_db(sq);
620 mlx5_wq_destroy(&sq->wq_ctrl);
621 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
624 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
626 struct mlx5e_channel *c = sq->channel;
627 struct mlx5e_priv *priv = c->priv;
628 struct mlx5_core_dev *mdev = priv->mdev;
636 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
637 sizeof(u64) * sq->wq_ctrl.buf.npages;
638 in = mlx5_vzalloc(inlen);
642 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
643 wq = MLX5_ADDR_OF(sqc, sqc, wq);
645 memcpy(sqc, param->sqc, sizeof(param->sqc));
647 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
648 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
649 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
650 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
651 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
653 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
654 MLX5_SET(wq, wq, uar_page, sq->uar.index);
655 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
656 MLX5_ADAPTER_PAGE_SHIFT);
657 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
659 mlx5_fill_page_array(&sq->wq_ctrl.buf,
660 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
662 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
669 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
671 struct mlx5e_channel *c = sq->channel;
672 struct mlx5e_priv *priv = c->priv;
673 struct mlx5_core_dev *mdev = priv->mdev;
680 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
681 in = mlx5_vzalloc(inlen);
685 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
687 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
688 MLX5_SET(sqc, sqc, state, next_state);
690 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
697 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
699 struct mlx5e_channel *c = sq->channel;
700 struct mlx5e_priv *priv = c->priv;
701 struct mlx5_core_dev *mdev = priv->mdev;
703 mlx5_core_destroy_sq(mdev, sq->sqn);
706 static int mlx5e_open_sq(struct mlx5e_channel *c,
708 struct mlx5e_sq_param *param,
713 err = mlx5e_create_sq(c, tc, param, sq);
717 err = mlx5e_enable_sq(sq, param);
721 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
726 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
727 netdev_tx_reset_queue(sq->txq);
728 netif_tx_start_queue(sq->txq);
734 mlx5e_disable_sq(sq);
736 mlx5e_destroy_sq(sq);
741 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
743 __netif_tx_lock_bh(txq);
744 netif_tx_stop_queue(txq);
745 __netif_tx_unlock_bh(txq);
748 static void mlx5e_close_sq(struct mlx5e_sq *sq)
751 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
752 /* prevent netif_tx_wake_queue */
753 napi_synchronize(&sq->channel->napi);
754 netif_tx_disable_queue(sq->txq);
756 /* ensure hw is notified of all pending wqes */
757 if (mlx5e_sq_has_room_for(sq, 1))
758 mlx5e_send_nop(sq, true);
760 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
763 while (sq->cc != sq->pc) /* wait till sq is empty */
766 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
767 napi_synchronize(&sq->channel->napi);
769 mlx5e_disable_sq(sq);
770 mlx5e_destroy_sq(sq);
773 static int mlx5e_create_cq(struct mlx5e_channel *c,
774 struct mlx5e_cq_param *param,
777 struct mlx5e_priv *priv = c->priv;
778 struct mlx5_core_dev *mdev = priv->mdev;
779 struct mlx5_core_cq *mcq = &cq->mcq;
785 param->wq.buf_numa_node = cpu_to_node(c->cpu);
786 param->wq.db_numa_node = cpu_to_node(c->cpu);
787 param->eq_ix = c->ix;
789 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
794 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
799 mcq->set_ci_db = cq->wq_ctrl.db.db;
800 mcq->arm_db = cq->wq_ctrl.db.db + 1;
803 mcq->vector = param->eq_ix;
804 mcq->comp = mlx5e_completion_event;
805 mcq->event = mlx5e_cq_error_event;
807 mcq->uar = &priv->cq_uar;
809 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
810 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
821 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
823 mlx5_wq_destroy(&cq->wq_ctrl);
826 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
828 struct mlx5e_priv *priv = cq->priv;
829 struct mlx5_core_dev *mdev = priv->mdev;
830 struct mlx5_core_cq *mcq = &cq->mcq;
835 unsigned int irqn_not_used;
839 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
840 sizeof(u64) * cq->wq_ctrl.buf.npages;
841 in = mlx5_vzalloc(inlen);
845 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
847 memcpy(cqc, param->cqc, sizeof(param->cqc));
849 mlx5_fill_page_array(&cq->wq_ctrl.buf,
850 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
852 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
854 MLX5_SET(cqc, cqc, c_eqn, eqn);
855 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
856 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
857 MLX5_ADAPTER_PAGE_SHIFT);
858 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
860 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
872 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
874 struct mlx5e_priv *priv = cq->priv;
875 struct mlx5_core_dev *mdev = priv->mdev;
877 mlx5_core_destroy_cq(mdev, &cq->mcq);
880 static int mlx5e_open_cq(struct mlx5e_channel *c,
881 struct mlx5e_cq_param *param,
883 u16 moderation_usecs,
884 u16 moderation_frames)
887 struct mlx5e_priv *priv = c->priv;
888 struct mlx5_core_dev *mdev = priv->mdev;
890 err = mlx5e_create_cq(c, param, cq);
894 err = mlx5e_enable_cq(cq, param);
898 if (MLX5_CAP_GEN(mdev, cq_moderation))
899 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
905 mlx5e_destroy_cq(cq);
910 static void mlx5e_close_cq(struct mlx5e_cq *cq)
912 mlx5e_disable_cq(cq);
913 mlx5e_destroy_cq(cq);
916 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
918 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
921 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
922 struct mlx5e_channel_param *cparam)
924 struct mlx5e_priv *priv = c->priv;
928 for (tc = 0; tc < c->num_tc; tc++) {
929 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
930 priv->params.tx_cq_moderation_usec,
931 priv->params.tx_cq_moderation_pkts);
933 goto err_close_tx_cqs;
939 for (tc--; tc >= 0; tc--)
940 mlx5e_close_cq(&c->sq[tc].cq);
945 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
949 for (tc = 0; tc < c->num_tc; tc++)
950 mlx5e_close_cq(&c->sq[tc].cq);
953 static int mlx5e_open_sqs(struct mlx5e_channel *c,
954 struct mlx5e_channel_param *cparam)
959 for (tc = 0; tc < c->num_tc; tc++) {
960 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
968 for (tc--; tc >= 0; tc--)
969 mlx5e_close_sq(&c->sq[tc]);
974 static void mlx5e_close_sqs(struct mlx5e_channel *c)
978 for (tc = 0; tc < c->num_tc; tc++)
979 mlx5e_close_sq(&c->sq[tc]);
982 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
986 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
987 priv->channeltc_to_txq_map[ix][i] =
988 ix + i * priv->params.num_channels;
991 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
992 struct mlx5e_channel_param *cparam,
993 struct mlx5e_channel **cp)
995 struct net_device *netdev = priv->netdev;
996 int cpu = mlx5e_get_cpu(priv, ix);
997 struct mlx5e_channel *c;
1000 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1007 c->pdev = &priv->mdev->pdev->dev;
1008 c->netdev = priv->netdev;
1009 c->mkey_be = cpu_to_be32(priv->mkey.key);
1010 c->num_tc = priv->params.num_tc;
1012 mlx5e_build_channeltc_to_txq_map(priv, ix);
1014 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1016 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1020 err = mlx5e_open_tx_cqs(c, cparam);
1022 goto err_close_icosq_cq;
1024 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1025 priv->params.rx_cq_moderation_usec,
1026 priv->params.rx_cq_moderation_pkts);
1028 goto err_close_tx_cqs;
1030 napi_enable(&c->napi);
1032 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1034 goto err_disable_napi;
1036 err = mlx5e_open_sqs(c, cparam);
1038 goto err_close_icosq;
1040 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1044 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1053 mlx5e_close_sq(&c->icosq);
1056 napi_disable(&c->napi);
1057 mlx5e_close_cq(&c->rq.cq);
1060 mlx5e_close_tx_cqs(c);
1063 mlx5e_close_cq(&c->icosq.cq);
1066 netif_napi_del(&c->napi);
1067 napi_hash_del(&c->napi);
1073 static void mlx5e_close_channel(struct mlx5e_channel *c)
1075 mlx5e_close_rq(&c->rq);
1077 mlx5e_close_sq(&c->icosq);
1078 napi_disable(&c->napi);
1079 mlx5e_close_cq(&c->rq.cq);
1080 mlx5e_close_tx_cqs(c);
1081 mlx5e_close_cq(&c->icosq.cq);
1082 netif_napi_del(&c->napi);
1084 napi_hash_del(&c->napi);
1090 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1091 struct mlx5e_rq_param *param)
1093 void *rqc = param->rqc;
1094 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1096 switch (priv->params.rq_wq_type) {
1097 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1098 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1099 MLX5_MPWRQ_LOG_NUM_STRIDES - 9);
1100 MLX5_SET(wq, wq, log_wqe_stride_size,
1101 MLX5_MPWRQ_LOG_STRIDE_SIZE - 6);
1102 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1104 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1105 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1108 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1109 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1110 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1111 MLX5_SET(wq, wq, pd, priv->pdn);
1112 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1114 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1115 param->wq.linear = 1;
1118 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1120 void *rqc = param->rqc;
1121 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1123 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1124 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1127 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1128 struct mlx5e_sq_param *param)
1130 void *sqc = param->sqc;
1131 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1133 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1134 MLX5_SET(wq, wq, pd, priv->pdn);
1136 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1139 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1140 struct mlx5e_sq_param *param)
1142 void *sqc = param->sqc;
1143 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1145 mlx5e_build_sq_param_common(priv, param);
1146 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1148 param->max_inline = priv->params.tx_max_inline;
1151 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1152 struct mlx5e_cq_param *param)
1154 void *cqc = param->cqc;
1156 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1159 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1160 struct mlx5e_cq_param *param)
1162 void *cqc = param->cqc;
1165 switch (priv->params.rq_wq_type) {
1166 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1167 log_cq_size = priv->params.log_rq_size +
1168 MLX5_MPWRQ_LOG_NUM_STRIDES;
1170 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1171 log_cq_size = priv->params.log_rq_size;
1174 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1176 mlx5e_build_common_cq_param(priv, param);
1179 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1180 struct mlx5e_cq_param *param)
1182 void *cqc = param->cqc;
1184 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1186 mlx5e_build_common_cq_param(priv, param);
1189 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1190 struct mlx5e_cq_param *param,
1193 void *cqc = param->cqc;
1195 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1197 mlx5e_build_common_cq_param(priv, param);
1200 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1201 struct mlx5e_sq_param *param,
1204 void *sqc = param->sqc;
1205 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1207 mlx5e_build_sq_param_common(priv, param);
1209 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1210 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1212 param->icosq = true;
1215 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1216 struct mlx5e_channel_param *cparam)
1218 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1220 memset(cparam, 0, sizeof(*cparam));
1222 mlx5e_build_rq_param(priv, &cparam->rq);
1223 mlx5e_build_sq_param(priv, &cparam->sq);
1224 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1225 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1226 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1227 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1230 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1232 struct mlx5e_channel_param cparam;
1233 int nch = priv->params.num_channels;
1238 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1241 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1242 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1244 if (!priv->channel || !priv->txq_to_sq_map)
1245 goto err_free_txq_to_sq_map;
1247 mlx5e_build_channel_param(priv, &cparam);
1248 for (i = 0; i < nch; i++) {
1249 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1251 goto err_close_channels;
1254 for (j = 0; j < nch; j++) {
1255 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1257 goto err_close_channels;
1263 for (i--; i >= 0; i--)
1264 mlx5e_close_channel(priv->channel[i]);
1266 err_free_txq_to_sq_map:
1267 kfree(priv->txq_to_sq_map);
1268 kfree(priv->channel);
1273 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1277 for (i = 0; i < priv->params.num_channels; i++)
1278 mlx5e_close_channel(priv->channel[i]);
1280 kfree(priv->txq_to_sq_map);
1281 kfree(priv->channel);
1284 static int mlx5e_rx_hash_fn(int hfunc)
1286 return (hfunc == ETH_RSS_HASH_TOP) ?
1287 MLX5_RX_HASH_FN_TOEPLITZ :
1288 MLX5_RX_HASH_FN_INVERTED_XOR8;
1291 static int mlx5e_bits_invert(unsigned long a, int size)
1296 for (i = 0; i < size; i++)
1297 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1302 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1306 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1309 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1310 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1312 ix = priv->params.indirection_rqt[ix];
1313 MLX5_SET(rqtc, rqtc, rq_num[i],
1314 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1315 priv->channel[ix]->rq.rqn :
1320 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1321 enum mlx5e_rqt_ix rqt_ix)
1325 case MLX5E_INDIRECTION_RQT:
1326 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1330 default: /* MLX5E_SINGLE_RQ_RQT */
1331 MLX5_SET(rqtc, rqtc, rq_num[0],
1332 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1333 priv->channel[0]->rq.rqn :
1340 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1342 struct mlx5_core_dev *mdev = priv->mdev;
1349 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1351 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1352 in = mlx5_vzalloc(inlen);
1356 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1358 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1359 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1361 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1363 err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1370 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1372 struct mlx5_core_dev *mdev = priv->mdev;
1379 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1381 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1382 in = mlx5_vzalloc(inlen);
1386 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1388 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1390 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1392 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1394 err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1401 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1403 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1406 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1408 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1409 mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1412 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1414 if (!priv->params.lro_en)
1417 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1419 MLX5_SET(tirc, tirc, lro_enable_mask,
1420 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1421 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1422 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1423 (priv->params.lro_wqe_sz -
1424 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1425 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1426 MLX5_CAP_ETH(priv->mdev,
1427 lro_timer_supported_periods[2]));
1430 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1432 MLX5_SET(tirc, tirc, rx_hash_fn,
1433 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1434 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1435 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1436 rx_hash_toeplitz_key);
1437 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1438 rx_hash_toeplitz_key);
1440 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1441 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1445 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1447 struct mlx5_core_dev *mdev = priv->mdev;
1455 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1456 in = mlx5_vzalloc(inlen);
1460 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1461 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1463 mlx5e_build_tir_ctx_lro(tirc, priv);
1465 for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1466 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1476 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1483 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1484 in = mlx5_vzalloc(inlen);
1488 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1490 err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1497 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1502 for (i = 0; i < MLX5E_NUM_TT; i++) {
1503 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1512 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1514 struct mlx5e_priv *priv = netdev_priv(netdev);
1515 struct mlx5_core_dev *mdev = priv->mdev;
1519 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1523 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1525 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1526 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1527 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1529 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1533 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1535 struct mlx5e_priv *priv = netdev_priv(netdev);
1536 int nch = priv->params.num_channels;
1537 int ntc = priv->params.num_tc;
1540 netdev_reset_tc(netdev);
1545 netdev_set_num_tc(netdev, ntc);
1547 for (tc = 0; tc < ntc; tc++)
1548 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1551 int mlx5e_open_locked(struct net_device *netdev)
1553 struct mlx5e_priv *priv = netdev_priv(netdev);
1557 set_bit(MLX5E_STATE_OPENED, &priv->state);
1559 mlx5e_netdev_set_tcs(netdev);
1561 num_txqs = priv->params.num_channels * priv->params.num_tc;
1562 netif_set_real_num_tx_queues(netdev, num_txqs);
1563 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1565 err = mlx5e_set_dev_port_mtu(netdev);
1567 goto err_clear_state_opened_flag;
1569 err = mlx5e_open_channels(priv);
1571 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1573 goto err_clear_state_opened_flag;
1576 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1578 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1580 goto err_close_channels;
1583 mlx5e_redirect_rqts(priv);
1584 mlx5e_update_carrier(priv);
1585 mlx5e_timestamp_init(priv);
1587 schedule_delayed_work(&priv->update_stats_work, 0);
1592 mlx5e_close_channels(priv);
1593 err_clear_state_opened_flag:
1594 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1598 static int mlx5e_open(struct net_device *netdev)
1600 struct mlx5e_priv *priv = netdev_priv(netdev);
1603 mutex_lock(&priv->state_lock);
1604 err = mlx5e_open_locked(netdev);
1605 mutex_unlock(&priv->state_lock);
1610 int mlx5e_close_locked(struct net_device *netdev)
1612 struct mlx5e_priv *priv = netdev_priv(netdev);
1614 /* May already be CLOSED in case a previous configuration operation
1615 * (e.g RX/TX queue size change) that involves close&open failed.
1617 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1620 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1622 mlx5e_timestamp_cleanup(priv);
1623 netif_carrier_off(priv->netdev);
1624 mlx5e_redirect_rqts(priv);
1625 mlx5e_close_channels(priv);
1630 static int mlx5e_close(struct net_device *netdev)
1632 struct mlx5e_priv *priv = netdev_priv(netdev);
1635 mutex_lock(&priv->state_lock);
1636 err = mlx5e_close_locked(netdev);
1637 mutex_unlock(&priv->state_lock);
1642 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1643 struct mlx5e_rq *rq,
1644 struct mlx5e_rq_param *param)
1646 struct mlx5_core_dev *mdev = priv->mdev;
1647 void *rqc = param->rqc;
1648 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1651 param->wq.db_numa_node = param->wq.buf_numa_node;
1653 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1663 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1664 struct mlx5e_cq *cq,
1665 struct mlx5e_cq_param *param)
1667 struct mlx5_core_dev *mdev = priv->mdev;
1668 struct mlx5_core_cq *mcq = &cq->mcq;
1673 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1678 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1681 mcq->set_ci_db = cq->wq_ctrl.db.db;
1682 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1683 *mcq->set_ci_db = 0;
1685 mcq->vector = param->eq_ix;
1686 mcq->comp = mlx5e_completion_event;
1687 mcq->event = mlx5e_cq_error_event;
1689 mcq->uar = &priv->cq_uar;
1696 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1698 struct mlx5e_cq_param cq_param;
1699 struct mlx5e_rq_param rq_param;
1700 struct mlx5e_rq *rq = &priv->drop_rq;
1701 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1704 memset(&cq_param, 0, sizeof(cq_param));
1705 memset(&rq_param, 0, sizeof(rq_param));
1706 mlx5e_build_drop_rq_param(&rq_param);
1708 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1712 err = mlx5e_enable_cq(cq, &cq_param);
1714 goto err_destroy_cq;
1716 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1718 goto err_disable_cq;
1720 err = mlx5e_enable_rq(rq, &rq_param);
1722 goto err_destroy_rq;
1727 mlx5e_destroy_rq(&priv->drop_rq);
1730 mlx5e_disable_cq(&priv->drop_rq.cq);
1733 mlx5e_destroy_cq(&priv->drop_rq.cq);
1738 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1740 mlx5e_disable_rq(&priv->drop_rq);
1741 mlx5e_destroy_rq(&priv->drop_rq);
1742 mlx5e_disable_cq(&priv->drop_rq.cq);
1743 mlx5e_destroy_cq(&priv->drop_rq.cq);
1746 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1748 struct mlx5_core_dev *mdev = priv->mdev;
1749 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1750 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1752 memset(in, 0, sizeof(in));
1754 MLX5_SET(tisc, tisc, prio, tc << 1);
1755 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1757 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1760 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1762 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1765 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1770 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1771 err = mlx5e_create_tis(priv, tc);
1773 goto err_close_tises;
1779 for (tc--; tc >= 0; tc--)
1780 mlx5e_destroy_tis(priv, tc);
1785 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1789 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1790 mlx5e_destroy_tis(priv, tc);
1793 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1795 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1797 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1799 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1800 MLX5_HASH_FIELD_SEL_DST_IP)
1802 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1803 MLX5_HASH_FIELD_SEL_DST_IP |\
1804 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1805 MLX5_HASH_FIELD_SEL_L4_DPORT)
1807 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1808 MLX5_HASH_FIELD_SEL_DST_IP |\
1809 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1811 mlx5e_build_tir_ctx_lro(tirc, priv);
1813 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1817 MLX5_SET(tirc, tirc, indirect_table,
1818 priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1819 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1822 MLX5_SET(tirc, tirc, indirect_table,
1823 priv->rqtn[MLX5E_INDIRECTION_RQT]);
1824 mlx5e_build_tir_ctx_hash(tirc, priv);
1829 case MLX5E_TT_IPV4_TCP:
1830 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1831 MLX5_L3_PROT_TYPE_IPV4);
1832 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1833 MLX5_L4_PROT_TYPE_TCP);
1834 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1835 MLX5_HASH_IP_L4PORTS);
1838 case MLX5E_TT_IPV6_TCP:
1839 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1840 MLX5_L3_PROT_TYPE_IPV6);
1841 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1842 MLX5_L4_PROT_TYPE_TCP);
1843 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1844 MLX5_HASH_IP_L4PORTS);
1847 case MLX5E_TT_IPV4_UDP:
1848 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1849 MLX5_L3_PROT_TYPE_IPV4);
1850 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1851 MLX5_L4_PROT_TYPE_UDP);
1852 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1853 MLX5_HASH_IP_L4PORTS);
1856 case MLX5E_TT_IPV6_UDP:
1857 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1858 MLX5_L3_PROT_TYPE_IPV6);
1859 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1860 MLX5_L4_PROT_TYPE_UDP);
1861 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1862 MLX5_HASH_IP_L4PORTS);
1865 case MLX5E_TT_IPV4_IPSEC_AH:
1866 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1867 MLX5_L3_PROT_TYPE_IPV4);
1868 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1869 MLX5_HASH_IP_IPSEC_SPI);
1872 case MLX5E_TT_IPV6_IPSEC_AH:
1873 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1874 MLX5_L3_PROT_TYPE_IPV6);
1875 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1876 MLX5_HASH_IP_IPSEC_SPI);
1879 case MLX5E_TT_IPV4_IPSEC_ESP:
1880 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1881 MLX5_L3_PROT_TYPE_IPV4);
1882 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1883 MLX5_HASH_IP_IPSEC_SPI);
1886 case MLX5E_TT_IPV6_IPSEC_ESP:
1887 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1888 MLX5_L3_PROT_TYPE_IPV6);
1889 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1890 MLX5_HASH_IP_IPSEC_SPI);
1894 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1895 MLX5_L3_PROT_TYPE_IPV4);
1896 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1901 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1902 MLX5_L3_PROT_TYPE_IPV6);
1903 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1909 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1911 struct mlx5_core_dev *mdev = priv->mdev;
1917 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1918 in = mlx5_vzalloc(inlen);
1922 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1924 mlx5e_build_tir_ctx(priv, tirc, tt);
1926 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1933 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1935 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1938 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1943 for (i = 0; i < MLX5E_NUM_TT; i++) {
1944 err = mlx5e_create_tir(priv, i);
1946 goto err_destroy_tirs;
1952 for (i--; i >= 0; i--)
1953 mlx5e_destroy_tir(priv, i);
1958 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1962 for (i = 0; i < MLX5E_NUM_TT; i++)
1963 mlx5e_destroy_tir(priv, i);
1966 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1968 struct mlx5e_priv *priv = netdev_priv(netdev);
1972 if (tc && tc != MLX5E_MAX_NUM_TC)
1975 mutex_lock(&priv->state_lock);
1977 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1979 mlx5e_close_locked(priv->netdev);
1981 priv->params.num_tc = tc ? tc : 1;
1984 err = mlx5e_open_locked(priv->netdev);
1986 mutex_unlock(&priv->state_lock);
1991 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1992 __be16 proto, struct tc_to_netdev *tc)
1994 struct mlx5e_priv *priv = netdev_priv(dev);
1996 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2000 case TC_SETUP_CLSFLOWER:
2001 switch (tc->cls_flower->command) {
2002 case TC_CLSFLOWER_REPLACE:
2003 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2004 case TC_CLSFLOWER_DESTROY:
2005 return mlx5e_delete_flower(priv, tc->cls_flower);
2012 if (tc->type != TC_SETUP_MQPRIO)
2015 return mlx5e_setup_tc(dev, tc->tc);
2018 static struct rtnl_link_stats64 *
2019 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2021 struct mlx5e_priv *priv = netdev_priv(dev);
2022 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2023 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2024 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2026 stats->rx_packets = sstats->rx_packets;
2027 stats->rx_bytes = sstats->rx_bytes;
2028 stats->tx_packets = sstats->tx_packets;
2029 stats->tx_bytes = sstats->tx_bytes;
2031 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2032 stats->tx_dropped = sstats->tx_queue_dropped;
2034 stats->rx_length_errors =
2035 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2036 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2037 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2038 stats->rx_crc_errors =
2039 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2040 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2041 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2042 stats->tx_carrier_errors =
2043 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2044 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2045 stats->rx_frame_errors;
2046 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2048 /* vport multicast also counts packets that are dropped due to steering
2049 * or rx out of buffer
2052 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2057 static void mlx5e_set_rx_mode(struct net_device *dev)
2059 struct mlx5e_priv *priv = netdev_priv(dev);
2061 schedule_work(&priv->set_rx_mode_work);
2064 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2066 struct mlx5e_priv *priv = netdev_priv(netdev);
2067 struct sockaddr *saddr = addr;
2069 if (!is_valid_ether_addr(saddr->sa_data))
2070 return -EADDRNOTAVAIL;
2072 netif_addr_lock_bh(netdev);
2073 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2074 netif_addr_unlock_bh(netdev);
2076 schedule_work(&priv->set_rx_mode_work);
2081 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2084 netdev->features |= feature; \
2086 netdev->features &= ~feature; \
2089 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2091 static int set_feature_lro(struct net_device *netdev, bool enable)
2093 struct mlx5e_priv *priv = netdev_priv(netdev);
2094 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2097 mutex_lock(&priv->state_lock);
2099 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2100 mlx5e_close_locked(priv->netdev);
2102 priv->params.lro_en = enable;
2103 err = mlx5e_modify_tirs_lro(priv);
2105 netdev_err(netdev, "lro modify failed, %d\n", err);
2106 priv->params.lro_en = !enable;
2109 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2110 mlx5e_open_locked(priv->netdev);
2112 mutex_unlock(&priv->state_lock);
2117 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2119 struct mlx5e_priv *priv = netdev_priv(netdev);
2122 mlx5e_enable_vlan_filter(priv);
2124 mlx5e_disable_vlan_filter(priv);
2129 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2131 struct mlx5e_priv *priv = netdev_priv(netdev);
2133 if (!enable && mlx5e_tc_num_filters(priv)) {
2135 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2142 static int mlx5e_handle_feature(struct net_device *netdev,
2143 netdev_features_t wanted_features,
2144 netdev_features_t feature,
2145 mlx5e_feature_handler feature_handler)
2147 netdev_features_t changes = wanted_features ^ netdev->features;
2148 bool enable = !!(wanted_features & feature);
2151 if (!(changes & feature))
2154 err = feature_handler(netdev, enable);
2156 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2157 enable ? "Enable" : "Disable", feature, err);
2161 MLX5E_SET_FEATURE(netdev, feature, enable);
2165 static int mlx5e_set_features(struct net_device *netdev,
2166 netdev_features_t features)
2170 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2172 err |= mlx5e_handle_feature(netdev, features,
2173 NETIF_F_HW_VLAN_CTAG_FILTER,
2174 set_feature_vlan_filter);
2175 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2176 set_feature_tc_num_filters);
2178 return err ? -EINVAL : 0;
2181 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2183 struct mlx5e_priv *priv = netdev_priv(netdev);
2184 struct mlx5_core_dev *mdev = priv->mdev;
2189 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2191 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2193 if (new_mtu > max_mtu) {
2195 "%s: Bad MTU (%d) > (%d) Max\n",
2196 __func__, new_mtu, max_mtu);
2200 mutex_lock(&priv->state_lock);
2202 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2204 mlx5e_close_locked(netdev);
2206 netdev->mtu = new_mtu;
2209 err = mlx5e_open_locked(netdev);
2211 mutex_unlock(&priv->state_lock);
2216 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2220 return mlx5e_hwstamp_set(dev, ifr);
2222 return mlx5e_hwstamp_get(dev, ifr);
2228 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2230 struct mlx5e_priv *priv = netdev_priv(dev);
2231 struct mlx5_core_dev *mdev = priv->mdev;
2233 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2236 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2238 struct mlx5e_priv *priv = netdev_priv(dev);
2239 struct mlx5_core_dev *mdev = priv->mdev;
2241 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2245 static int mlx5_vport_link2ifla(u8 esw_link)
2248 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2249 return IFLA_VF_LINK_STATE_DISABLE;
2250 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2251 return IFLA_VF_LINK_STATE_ENABLE;
2253 return IFLA_VF_LINK_STATE_AUTO;
2256 static int mlx5_ifla_link2vport(u8 ifla_link)
2258 switch (ifla_link) {
2259 case IFLA_VF_LINK_STATE_DISABLE:
2260 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2261 case IFLA_VF_LINK_STATE_ENABLE:
2262 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2264 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2267 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2270 struct mlx5e_priv *priv = netdev_priv(dev);
2271 struct mlx5_core_dev *mdev = priv->mdev;
2273 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2274 mlx5_ifla_link2vport(link_state));
2277 static int mlx5e_get_vf_config(struct net_device *dev,
2278 int vf, struct ifla_vf_info *ivi)
2280 struct mlx5e_priv *priv = netdev_priv(dev);
2281 struct mlx5_core_dev *mdev = priv->mdev;
2284 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2287 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2291 static int mlx5e_get_vf_stats(struct net_device *dev,
2292 int vf, struct ifla_vf_stats *vf_stats)
2294 struct mlx5e_priv *priv = netdev_priv(dev);
2295 struct mlx5_core_dev *mdev = priv->mdev;
2297 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2301 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2302 sa_family_t sa_family, __be16 port)
2304 struct mlx5e_priv *priv = netdev_priv(netdev);
2306 if (!mlx5e_vxlan_allowed(priv->mdev))
2309 mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2312 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2313 sa_family_t sa_family, __be16 port)
2315 struct mlx5e_priv *priv = netdev_priv(netdev);
2317 if (!mlx5e_vxlan_allowed(priv->mdev))
2320 mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2323 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2324 struct sk_buff *skb,
2325 netdev_features_t features)
2327 struct udphdr *udph;
2331 switch (vlan_get_protocol(skb)) {
2332 case htons(ETH_P_IP):
2333 proto = ip_hdr(skb)->protocol;
2335 case htons(ETH_P_IPV6):
2336 proto = ipv6_hdr(skb)->nexthdr;
2342 if (proto == IPPROTO_UDP) {
2343 udph = udp_hdr(skb);
2344 port = be16_to_cpu(udph->dest);
2347 /* Verify if UDP port is being offloaded by HW */
2348 if (port && mlx5e_vxlan_lookup_port(priv, port))
2352 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2353 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2356 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2357 struct net_device *netdev,
2358 netdev_features_t features)
2360 struct mlx5e_priv *priv = netdev_priv(netdev);
2362 features = vlan_features_check(skb, features);
2363 features = vxlan_features_check(skb, features);
2365 /* Validate if the tunneled packet is being offloaded by HW */
2366 if (skb->encapsulation &&
2367 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2368 return mlx5e_vxlan_features_check(priv, skb, features);
2373 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2374 .ndo_open = mlx5e_open,
2375 .ndo_stop = mlx5e_close,
2376 .ndo_start_xmit = mlx5e_xmit,
2377 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2378 .ndo_select_queue = mlx5e_select_queue,
2379 .ndo_get_stats64 = mlx5e_get_stats,
2380 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2381 .ndo_set_mac_address = mlx5e_set_mac,
2382 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2383 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2384 .ndo_set_features = mlx5e_set_features,
2385 .ndo_change_mtu = mlx5e_change_mtu,
2386 .ndo_do_ioctl = mlx5e_ioctl,
2389 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2390 .ndo_open = mlx5e_open,
2391 .ndo_stop = mlx5e_close,
2392 .ndo_start_xmit = mlx5e_xmit,
2393 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2394 .ndo_select_queue = mlx5e_select_queue,
2395 .ndo_get_stats64 = mlx5e_get_stats,
2396 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2397 .ndo_set_mac_address = mlx5e_set_mac,
2398 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2399 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2400 .ndo_set_features = mlx5e_set_features,
2401 .ndo_change_mtu = mlx5e_change_mtu,
2402 .ndo_do_ioctl = mlx5e_ioctl,
2403 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2404 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2405 .ndo_features_check = mlx5e_features_check,
2406 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2407 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2408 .ndo_get_vf_config = mlx5e_get_vf_config,
2409 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2410 .ndo_get_vf_stats = mlx5e_get_vf_stats,
2413 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2415 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2417 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2418 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2419 !MLX5_CAP_ETH(mdev, csum_cap) ||
2420 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2421 !MLX5_CAP_ETH(mdev, vlan_cap) ||
2422 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2423 MLX5_CAP_FLOWTABLE(mdev,
2424 flow_table_properties_nic_receive.max_ft_level)
2426 mlx5_core_warn(mdev,
2427 "Not creating net device, some required device capabilities are missing\n");
2430 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2431 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2432 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2433 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2438 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2440 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2442 return bf_buf_size -
2443 sizeof(struct mlx5e_tx_wqe) +
2444 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2447 #ifdef CONFIG_MLX5_CORE_EN_DCB
2448 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2452 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2453 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2454 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2455 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2456 priv->params.ets.prio_tc[i] = i;
2459 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2460 priv->params.ets.prio_tc[0] = 1;
2461 priv->params.ets.prio_tc[1] = 0;
2465 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2466 u32 *indirection_rqt, int len,
2469 int node = mdev->priv.numa_node;
2470 int node_num_of_cores;
2474 node = first_online_node;
2476 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2478 if (node_num_of_cores)
2479 num_channels = min_t(int, num_channels, node_num_of_cores);
2481 for (i = 0; i < len; i++)
2482 indirection_rqt[i] = i % num_channels;
2485 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2487 return MLX5_CAP_GEN(mdev, striding_rq) &&
2488 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2489 MLX5_CAP_ETH(mdev, reg_umr_sq);
2492 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2493 struct net_device *netdev,
2496 struct mlx5e_priv *priv = netdev_priv(netdev);
2498 priv->params.log_sq_size =
2499 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2500 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2501 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2502 MLX5_WQ_TYPE_LINKED_LIST;
2504 switch (priv->params.rq_wq_type) {
2505 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2506 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2507 priv->params.lro_en = true;
2509 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2510 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2513 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2514 BIT(priv->params.log_rq_size));
2515 priv->params.rx_cq_moderation_usec =
2516 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2517 priv->params.rx_cq_moderation_pkts =
2518 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2519 priv->params.tx_cq_moderation_usec =
2520 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2521 priv->params.tx_cq_moderation_pkts =
2522 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2523 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
2524 priv->params.num_tc = 1;
2525 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
2527 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2528 sizeof(priv->params.toeplitz_hash_key));
2530 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2531 MLX5E_INDIR_RQT_SIZE, num_channels);
2533 priv->params.lro_wqe_sz =
2534 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2537 priv->netdev = netdev;
2538 priv->params.num_channels = num_channels;
2540 #ifdef CONFIG_MLX5_CORE_EN_DCB
2541 mlx5e_ets_init(priv);
2544 mutex_init(&priv->state_lock);
2546 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2547 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2548 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2551 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2553 struct mlx5e_priv *priv = netdev_priv(netdev);
2555 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2556 if (is_zero_ether_addr(netdev->dev_addr) &&
2557 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2558 eth_hw_addr_random(netdev);
2559 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2563 static void mlx5e_build_netdev(struct net_device *netdev)
2565 struct mlx5e_priv *priv = netdev_priv(netdev);
2566 struct mlx5_core_dev *mdev = priv->mdev;
2568 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2570 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2571 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2572 #ifdef CONFIG_MLX5_CORE_EN_DCB
2573 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2576 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2579 netdev->watchdog_timeo = 15 * HZ;
2581 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2583 netdev->vlan_features |= NETIF_F_SG;
2584 netdev->vlan_features |= NETIF_F_IP_CSUM;
2585 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2586 netdev->vlan_features |= NETIF_F_GRO;
2587 netdev->vlan_features |= NETIF_F_TSO;
2588 netdev->vlan_features |= NETIF_F_TSO6;
2589 netdev->vlan_features |= NETIF_F_RXCSUM;
2590 netdev->vlan_features |= NETIF_F_RXHASH;
2592 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2593 netdev->vlan_features |= NETIF_F_LRO;
2595 netdev->hw_features = netdev->vlan_features;
2596 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
2597 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2598 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2600 if (mlx5e_vxlan_allowed(mdev)) {
2601 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2602 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2603 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2604 netdev->hw_enc_features |= NETIF_F_TSO;
2605 netdev->hw_enc_features |= NETIF_F_TSO6;
2606 netdev->hw_enc_features |= NETIF_F_RXHASH;
2607 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2610 netdev->features = netdev->hw_features;
2611 if (!priv->params.lro_en)
2612 netdev->features &= ~NETIF_F_LRO;
2614 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2615 if (FT_CAP(flow_modify_en) &&
2616 FT_CAP(modify_root) &&
2617 FT_CAP(identified_miss_table_mode) &&
2618 FT_CAP(flow_table_modify))
2619 priv->netdev->hw_features |= NETIF_F_HW_TC;
2621 netdev->features |= NETIF_F_HIGHDMA;
2623 netdev->priv_flags |= IFF_UNICAST_FLT;
2625 mlx5e_set_netdev_dev_addr(netdev);
2628 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2629 struct mlx5_core_mkey *mkey)
2631 struct mlx5_core_dev *mdev = priv->mdev;
2632 struct mlx5_create_mkey_mbox_in *in;
2635 in = mlx5_vzalloc(sizeof(*in));
2639 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2640 MLX5_PERM_LOCAL_READ |
2641 MLX5_ACCESS_MODE_PA;
2642 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2643 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2645 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2653 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2655 struct mlx5_core_dev *mdev = priv->mdev;
2658 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2660 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2661 priv->q_counter = 0;
2665 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2667 if (!priv->q_counter)
2670 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2673 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2675 struct mlx5_core_dev *mdev = priv->mdev;
2676 struct mlx5_create_mkey_mbox_in *in;
2677 struct mlx5_mkey_seg *mkc;
2678 int inlen = sizeof(*in);
2680 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2683 in = mlx5_vzalloc(inlen);
2688 mkc->status = MLX5_MKEY_STATUS_FREE;
2689 mkc->flags = MLX5_PERM_UMR_EN |
2690 MLX5_PERM_LOCAL_READ |
2691 MLX5_PERM_LOCAL_WRITE |
2692 MLX5_ACCESS_MODE_MTT;
2694 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2695 mkc->flags_pd = cpu_to_be32(priv->pdn);
2696 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
2697 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
2698 mkc->log2_page_size = PAGE_SHIFT;
2700 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
2708 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2710 struct net_device *netdev;
2711 struct mlx5e_priv *priv;
2712 int nch = mlx5e_get_max_num_channels(mdev);
2715 if (mlx5e_check_required_hca_cap(mdev))
2718 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2719 nch * MLX5E_MAX_NUM_TC,
2722 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2726 mlx5e_build_netdev_priv(mdev, netdev, nch);
2727 mlx5e_build_netdev(netdev);
2729 netif_carrier_off(netdev);
2731 priv = netdev_priv(netdev);
2733 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2735 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2736 goto err_free_netdev;
2739 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2741 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2742 goto err_unmap_free_uar;
2745 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2747 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2748 goto err_dealloc_pd;
2751 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2753 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2754 goto err_dealloc_transport_domain;
2757 err = mlx5e_create_umr_mkey(priv);
2759 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
2760 goto err_destroy_mkey;
2763 err = mlx5e_create_tises(priv);
2765 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2766 goto err_destroy_umr_mkey;
2769 err = mlx5e_open_drop_rq(priv);
2771 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2772 goto err_destroy_tises;
2775 err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2777 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2778 goto err_close_drop_rq;
2781 err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2783 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2784 goto err_destroy_rqt_indir;
2787 err = mlx5e_create_tirs(priv);
2789 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2790 goto err_destroy_rqt_single;
2793 err = mlx5e_create_flow_tables(priv);
2795 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2796 goto err_destroy_tirs;
2799 mlx5e_create_q_counter(priv);
2801 mlx5e_init_eth_addr(priv);
2803 mlx5e_vxlan_init(priv);
2805 err = mlx5e_tc_init(priv);
2807 goto err_dealloc_q_counters;
2809 #ifdef CONFIG_MLX5_CORE_EN_DCB
2810 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2813 err = register_netdev(netdev);
2815 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2816 goto err_tc_cleanup;
2819 if (mlx5e_vxlan_allowed(mdev))
2820 vxlan_get_rx_port(netdev);
2822 mlx5e_enable_async_events(priv);
2823 schedule_work(&priv->set_rx_mode_work);
2828 mlx5e_tc_cleanup(priv);
2830 err_dealloc_q_counters:
2831 mlx5e_destroy_q_counter(priv);
2832 mlx5e_destroy_flow_tables(priv);
2835 mlx5e_destroy_tirs(priv);
2837 err_destroy_rqt_single:
2838 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2840 err_destroy_rqt_indir:
2841 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2844 mlx5e_close_drop_rq(priv);
2847 mlx5e_destroy_tises(priv);
2849 err_destroy_umr_mkey:
2850 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
2853 mlx5_core_destroy_mkey(mdev, &priv->mkey);
2855 err_dealloc_transport_domain:
2856 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2859 mlx5_core_dealloc_pd(mdev, priv->pdn);
2862 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2865 free_netdev(netdev);
2870 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2872 struct mlx5e_priv *priv = vpriv;
2873 struct net_device *netdev = priv->netdev;
2875 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2877 schedule_work(&priv->set_rx_mode_work);
2878 mlx5e_disable_async_events(priv);
2879 flush_scheduled_work();
2880 unregister_netdev(netdev);
2881 mlx5e_tc_cleanup(priv);
2882 mlx5e_vxlan_cleanup(priv);
2883 mlx5e_destroy_q_counter(priv);
2884 mlx5e_destroy_flow_tables(priv);
2885 mlx5e_destroy_tirs(priv);
2886 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2887 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2888 mlx5e_close_drop_rq(priv);
2889 mlx5e_destroy_tises(priv);
2890 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
2891 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
2892 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2893 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2894 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2895 free_netdev(netdev);
2898 static void *mlx5e_get_netdev(void *vpriv)
2900 struct mlx5e_priv *priv = vpriv;
2902 return priv->netdev;
2905 static struct mlx5_interface mlx5e_interface = {
2906 .add = mlx5e_create_netdev,
2907 .remove = mlx5e_destroy_netdev,
2908 .event = mlx5e_async_event,
2909 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
2910 .get_dev = mlx5e_get_netdev,
2913 void mlx5e_init(void)
2915 mlx5_register_interface(&mlx5e_interface);
2918 void mlx5e_cleanup(void)
2920 mlx5_unregister_interface(&mlx5e_interface);