2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include <net/page_pool.h>
43 #include "en_accel/ipsec.h"
44 #include "en_accel/ipsec_rxtx.h"
45 #include "en_accel/tls.h"
46 #include "accel/ipsec.h"
47 #include "accel/tls.h"
48 #include "lib/vxlan.h"
49 #include "lib/clock.h"
53 struct mlx5e_rq_param {
54 u32 rqc[MLX5_ST_SZ_DW(rqc)];
55 struct mlx5_wq_param wq;
56 struct mlx5e_rq_frags_info frags_info;
59 struct mlx5e_sq_param {
60 u32 sqc[MLX5_ST_SZ_DW(sqc)];
61 struct mlx5_wq_param wq;
64 struct mlx5e_cq_param {
65 u32 cqc[MLX5_ST_SZ_DW(cqc)];
66 struct mlx5_wq_param wq;
71 struct mlx5e_channel_param {
72 struct mlx5e_rq_param rq;
73 struct mlx5e_sq_param sq;
74 struct mlx5e_sq_param xdp_sq;
75 struct mlx5e_sq_param icosq;
76 struct mlx5e_cq_param rx_cq;
77 struct mlx5e_cq_param tx_cq;
78 struct mlx5e_cq_param icosq_cq;
81 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
83 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
84 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
85 MLX5_CAP_ETH(mdev, reg_umr_sq);
86 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
87 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
92 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
93 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
99 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
101 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
102 u16 linear_rq_headroom = params->xdp_prog ?
103 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
106 linear_rq_headroom += NET_IP_ALIGN;
108 frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
110 if (params->xdp_prog && frag_sz < PAGE_SIZE)
116 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
118 u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
120 return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
123 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
124 struct mlx5e_params *params)
126 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
128 return !params->lro_en && frag_sz <= PAGE_SIZE;
131 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
132 struct mlx5e_params *params)
134 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
135 s8 signed_log_num_strides_param;
138 if (!mlx5e_rx_is_linear_skb(mdev, params))
141 if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
144 log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
145 signed_log_num_strides_param =
146 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
148 return signed_log_num_strides_param >= 0;
151 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
153 if (params->log_rq_mtu_frames <
154 mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
155 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
157 return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
160 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
161 struct mlx5e_params *params)
163 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
164 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
166 return MLX5E_MPWQE_STRIDE_SZ(mdev,
167 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
170 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
171 struct mlx5e_params *params)
173 return MLX5_MPWRQ_LOG_WQE_SZ -
174 mlx5e_mpwqe_get_log_stride_size(mdev, params);
177 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
178 struct mlx5e_params *params)
180 u16 linear_rq_headroom = params->xdp_prog ?
181 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
184 linear_rq_headroom += NET_IP_ALIGN;
186 is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
187 mlx5e_rx_is_linear_skb(mdev, params) :
188 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
190 return is_linear_skb ? linear_rq_headroom : 0;
193 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
194 struct mlx5e_params *params)
196 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
197 params->log_rq_mtu_frames = is_kdump_kernel() ?
198 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
199 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
201 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
202 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
203 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
204 BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
205 BIT(params->log_rq_mtu_frames),
206 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
207 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
210 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
211 struct mlx5e_params *params)
213 return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
214 !MLX5_IPSEC_DEV(mdev) &&
215 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
218 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
220 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
221 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
222 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
226 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
228 struct mlx5_core_dev *mdev = priv->mdev;
231 port_state = mlx5_query_vport_state(mdev,
232 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
235 if (port_state == VPORT_STATE_UP) {
236 netdev_info(priv->netdev, "Link up\n");
237 netif_carrier_on(priv->netdev);
239 netdev_info(priv->netdev, "Link down\n");
240 netif_carrier_off(priv->netdev);
244 static void mlx5e_update_carrier_work(struct work_struct *work)
246 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
247 update_carrier_work);
249 mutex_lock(&priv->state_lock);
250 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
251 if (priv->profile->update_carrier)
252 priv->profile->update_carrier(priv);
253 mutex_unlock(&priv->state_lock);
256 void mlx5e_update_stats(struct mlx5e_priv *priv)
260 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
261 if (mlx5e_stats_grps[i].update_stats)
262 mlx5e_stats_grps[i].update_stats(priv);
265 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
269 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
270 if (mlx5e_stats_grps[i].update_stats_mask &
271 MLX5E_NDO_UPDATE_STATS)
272 mlx5e_stats_grps[i].update_stats(priv);
275 void mlx5e_update_stats_work(struct work_struct *work)
277 struct delayed_work *dwork = to_delayed_work(work);
278 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
281 mutex_lock(&priv->state_lock);
282 priv->profile->update_stats(priv);
283 mutex_unlock(&priv->state_lock);
286 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
287 enum mlx5_dev_event event, unsigned long param)
289 struct mlx5e_priv *priv = vpriv;
291 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
295 case MLX5_DEV_EVENT_PORT_UP:
296 case MLX5_DEV_EVENT_PORT_DOWN:
297 queue_work(priv->wq, &priv->update_carrier_work);
304 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
306 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
309 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
311 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
312 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
315 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
316 struct mlx5e_icosq *sq,
317 struct mlx5e_umr_wqe *wqe)
319 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
320 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
321 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
323 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
325 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
326 cseg->imm = rq->mkey_be;
328 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
329 ucseg->xlt_octowords =
330 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
331 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
334 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
336 switch (rq->wq_type) {
337 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
338 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
340 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
344 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
346 switch (rq->wq_type) {
347 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
348 return rq->mpwqe.wq.cur_sz;
350 return rq->wqe.wq.cur_sz;
354 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
355 struct mlx5e_channel *c)
357 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
359 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
360 sizeof(*rq->mpwqe.info)),
361 GFP_KERNEL, cpu_to_node(c->cpu));
365 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
370 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
371 u64 npages, u8 page_shift,
372 struct mlx5_core_mkey *umr_mkey)
374 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
379 in = kvzalloc(inlen, GFP_KERNEL);
383 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
385 MLX5_SET(mkc, mkc, free, 1);
386 MLX5_SET(mkc, mkc, umr_en, 1);
387 MLX5_SET(mkc, mkc, lw, 1);
388 MLX5_SET(mkc, mkc, lr, 1);
389 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
391 MLX5_SET(mkc, mkc, qpn, 0xffffff);
392 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
393 MLX5_SET64(mkc, mkc, len, npages << page_shift);
394 MLX5_SET(mkc, mkc, translations_octword_size,
395 MLX5_MTT_OCTW(npages));
396 MLX5_SET(mkc, mkc, log_page_size, page_shift);
398 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
404 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
406 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
408 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
411 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
413 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
416 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
418 struct mlx5e_wqe_frag_info next_frag, *prev;
421 next_frag.di = &rq->wqe.di[0];
422 next_frag.offset = 0;
425 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
426 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
427 struct mlx5e_wqe_frag_info *frag =
428 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
431 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
432 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
434 next_frag.offset = 0;
436 prev->last_in_page = true;
441 next_frag.offset += frag_info[f].frag_stride;
447 prev->last_in_page = true;
450 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
451 struct mlx5e_params *params,
454 int len = wq_sz << rq->wqe.info.log_num_frags;
456 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
457 GFP_KERNEL, cpu_to_node(cpu));
461 mlx5e_init_frags_partition(rq);
466 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
471 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
472 struct mlx5e_params *params,
473 struct mlx5e_rq_param *rqp,
476 struct page_pool_params pp_params = { 0 };
477 struct mlx5_core_dev *mdev = c->mdev;
478 void *rqc = rqp->rqc;
479 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
485 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
487 rq->wq_type = params->rq_wq_type;
489 rq->netdev = c->netdev;
490 rq->tstamp = c->tstamp;
491 rq->clock = &mdev->clock;
495 rq->stats = &c->priv->channel_stats[c->ix].rq;
497 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
498 if (IS_ERR(rq->xdp_prog)) {
499 err = PTR_ERR(rq->xdp_prog);
501 goto err_rq_wq_destroy;
504 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
506 goto err_rq_wq_destroy;
508 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
509 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
510 pool_size = 1 << params->log_rq_mtu_frames;
512 switch (rq->wq_type) {
513 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
514 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
519 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
521 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
523 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
525 rq->post_wqes = mlx5e_post_rx_mpwqes;
526 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
528 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
529 #ifdef CONFIG_MLX5_EN_IPSEC
530 if (MLX5_IPSEC_DEV(mdev)) {
532 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
533 goto err_rq_wq_destroy;
536 if (!rq->handle_rx_cqe) {
538 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
539 goto err_rq_wq_destroy;
542 rq->mpwqe.skb_from_cqe_mpwrq =
543 mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
544 mlx5e_skb_from_cqe_mpwrq_linear :
545 mlx5e_skb_from_cqe_mpwrq_nonlinear;
546 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
547 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
549 err = mlx5e_create_rq_umr_mkey(mdev, rq);
551 goto err_rq_wq_destroy;
552 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
554 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
558 default: /* MLX5_WQ_TYPE_CYCLIC */
559 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
564 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
566 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
568 rq->wqe.info = rqp->frags_info;
570 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
571 (wq_sz << rq->wqe.info.log_num_frags)),
572 GFP_KERNEL, cpu_to_node(c->cpu));
573 if (!rq->wqe.frags) {
578 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
581 rq->post_wqes = mlx5e_post_rx_wqes;
582 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
584 #ifdef CONFIG_MLX5_EN_IPSEC
586 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
589 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
590 if (!rq->handle_rx_cqe) {
592 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
596 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
597 mlx5e_skb_from_cqe_linear :
598 mlx5e_skb_from_cqe_nonlinear;
599 rq->mkey_be = c->mkey_be;
602 /* Create a page_pool and register it with rxq */
604 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
605 pp_params.pool_size = pool_size;
606 pp_params.nid = cpu_to_node(c->cpu);
607 pp_params.dev = c->pdev;
608 pp_params.dma_dir = rq->buff.map_dir;
610 /* page_pool can be used even when there is no rq->xdp_prog,
611 * given page_pool does not handle DMA mapping there is no
612 * required state to clear. And page_pool gracefully handle
615 rq->page_pool = page_pool_create(&pp_params);
616 if (IS_ERR(rq->page_pool)) {
617 err = PTR_ERR(rq->page_pool);
618 rq->page_pool = NULL;
621 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
622 MEM_TYPE_PAGE_POOL, rq->page_pool);
626 for (i = 0; i < wq_sz; i++) {
627 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
628 struct mlx5e_rx_wqe_ll *wqe =
629 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
631 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
632 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
634 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
635 wqe->data[0].byte_count = cpu_to_be32(byte_count);
636 wqe->data[0].lkey = rq->mkey_be;
638 struct mlx5e_rx_wqe_cyc *wqe =
639 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
642 for (f = 0; f < rq->wqe.info.num_frags; f++) {
643 u32 frag_size = rq->wqe.info.arr[f].frag_size |
644 MLX5_HW_START_PADDING;
646 wqe->data[f].byte_count = cpu_to_be32(frag_size);
647 wqe->data[f].lkey = rq->mkey_be;
649 /* check if num_frags is not a pow of two */
650 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
651 wqe->data[f].byte_count = 0;
652 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
653 wqe->data[f].addr = 0;
658 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
660 switch (params->rx_cq_moderation.cq_period_mode) {
661 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
662 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
664 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
666 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
669 rq->page_cache.head = 0;
670 rq->page_cache.tail = 0;
675 switch (rq->wq_type) {
676 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
677 kvfree(rq->mpwqe.info);
678 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
680 default: /* MLX5_WQ_TYPE_CYCLIC */
681 kvfree(rq->wqe.frags);
682 mlx5e_free_di_list(rq);
687 bpf_prog_put(rq->xdp_prog);
688 xdp_rxq_info_unreg(&rq->xdp_rxq);
690 page_pool_destroy(rq->page_pool);
691 mlx5_wq_destroy(&rq->wq_ctrl);
696 static void mlx5e_free_rq(struct mlx5e_rq *rq)
701 bpf_prog_put(rq->xdp_prog);
703 xdp_rxq_info_unreg(&rq->xdp_rxq);
705 page_pool_destroy(rq->page_pool);
707 switch (rq->wq_type) {
708 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
709 kvfree(rq->mpwqe.info);
710 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
712 default: /* MLX5_WQ_TYPE_CYCLIC */
713 kvfree(rq->wqe.frags);
714 mlx5e_free_di_list(rq);
717 for (i = rq->page_cache.head; i != rq->page_cache.tail;
718 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
719 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
721 mlx5e_page_release(rq, dma_info, false);
723 mlx5_wq_destroy(&rq->wq_ctrl);
726 static int mlx5e_create_rq(struct mlx5e_rq *rq,
727 struct mlx5e_rq_param *param)
729 struct mlx5_core_dev *mdev = rq->mdev;
737 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
738 sizeof(u64) * rq->wq_ctrl.buf.npages;
739 in = kvzalloc(inlen, GFP_KERNEL);
743 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
744 wq = MLX5_ADDR_OF(rqc, rqc, wq);
746 memcpy(rqc, param->rqc, sizeof(param->rqc));
748 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
749 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
750 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
751 MLX5_ADAPTER_PAGE_SHIFT);
752 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
754 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
755 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
757 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
764 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
767 struct mlx5_core_dev *mdev = rq->mdev;
774 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
775 in = kvzalloc(inlen, GFP_KERNEL);
779 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
781 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
782 MLX5_SET(rqc, rqc, state, next_state);
784 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
791 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
793 struct mlx5e_channel *c = rq->channel;
794 struct mlx5e_priv *priv = c->priv;
795 struct mlx5_core_dev *mdev = priv->mdev;
802 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
803 in = kvzalloc(inlen, GFP_KERNEL);
807 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
809 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
810 MLX5_SET64(modify_rq_in, in, modify_bitmask,
811 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
812 MLX5_SET(rqc, rqc, scatter_fcs, enable);
813 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
815 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
822 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
824 struct mlx5e_channel *c = rq->channel;
825 struct mlx5_core_dev *mdev = c->mdev;
831 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
832 in = kvzalloc(inlen, GFP_KERNEL);
836 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
838 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
839 MLX5_SET64(modify_rq_in, in, modify_bitmask,
840 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
841 MLX5_SET(rqc, rqc, vsd, vsd);
842 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
844 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
851 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
853 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
856 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
858 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
859 struct mlx5e_channel *c = rq->channel;
861 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
864 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
868 } while (time_before(jiffies, exp_time));
870 netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
871 c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
876 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
881 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
882 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
884 /* UMR WQE (if in progress) is always at wq->head */
885 if (rq->mpwqe.umr_in_progress)
886 rq->dealloc_wqe(rq, wq->head);
888 while (!mlx5_wq_ll_is_empty(wq)) {
889 struct mlx5e_rx_wqe_ll *wqe;
891 wqe_ix_be = *wq->tail_next;
892 wqe_ix = be16_to_cpu(wqe_ix_be);
893 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
894 rq->dealloc_wqe(rq, wqe_ix);
895 mlx5_wq_ll_pop(wq, wqe_ix_be,
896 &wqe->next.next_wqe_index);
899 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
901 while (!mlx5_wq_cyc_is_empty(wq)) {
902 wqe_ix = mlx5_wq_cyc_get_tail(wq);
903 rq->dealloc_wqe(rq, wqe_ix);
910 static int mlx5e_open_rq(struct mlx5e_channel *c,
911 struct mlx5e_params *params,
912 struct mlx5e_rq_param *param,
917 err = mlx5e_alloc_rq(c, params, param, rq);
921 err = mlx5e_create_rq(rq, param);
925 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
929 if (params->rx_dim_enabled)
930 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
932 if (params->pflags & MLX5E_PFLAG_RX_NO_CSUM_COMPLETE)
933 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
938 mlx5e_destroy_rq(rq);
945 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
947 struct mlx5e_icosq *sq = &rq->channel->icosq;
948 struct mlx5_wq_cyc *wq = &sq->wq;
949 struct mlx5e_tx_wqe *nopwqe;
951 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
953 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
954 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
955 nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
956 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
959 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
961 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
962 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
965 static void mlx5e_close_rq(struct mlx5e_rq *rq)
967 cancel_work_sync(&rq->dim.work);
968 mlx5e_destroy_rq(rq);
969 mlx5e_free_rx_descs(rq);
973 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
978 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
980 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
982 sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)),
985 mlx5e_free_xdpsq_db(sq);
992 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
993 struct mlx5e_params *params,
994 struct mlx5e_sq_param *param,
995 struct mlx5e_xdpsq *sq,
998 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
999 struct mlx5_core_dev *mdev = c->mdev;
1000 struct mlx5_wq_cyc *wq = &sq->wq;
1004 sq->mkey_be = c->mkey_be;
1006 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1007 sq->min_inline_mode = params->tx_min_inline_mode;
1008 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1009 sq->stats = is_redirect ?
1010 &c->priv->channel_stats[c->ix].xdpsq :
1011 &c->priv->channel_stats[c->ix].rq_xdpsq;
1013 param->wq.db_numa_node = cpu_to_node(c->cpu);
1014 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1017 wq->db = &wq->db[MLX5_SND_DBR];
1019 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1021 goto err_sq_wq_destroy;
1026 mlx5_wq_destroy(&sq->wq_ctrl);
1031 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1033 mlx5e_free_xdpsq_db(sq);
1034 mlx5_wq_destroy(&sq->wq_ctrl);
1037 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1039 kvfree(sq->db.ico_wqe);
1042 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1044 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1046 sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1047 sizeof(*sq->db.ico_wqe)),
1049 if (!sq->db.ico_wqe)
1055 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1056 struct mlx5e_sq_param *param,
1057 struct mlx5e_icosq *sq)
1059 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1060 struct mlx5_core_dev *mdev = c->mdev;
1061 struct mlx5_wq_cyc *wq = &sq->wq;
1065 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1067 param->wq.db_numa_node = cpu_to_node(c->cpu);
1068 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1071 wq->db = &wq->db[MLX5_SND_DBR];
1073 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1075 goto err_sq_wq_destroy;
1080 mlx5_wq_destroy(&sq->wq_ctrl);
1085 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1087 mlx5e_free_icosq_db(sq);
1088 mlx5_wq_destroy(&sq->wq_ctrl);
1091 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1093 kvfree(sq->db.wqe_info);
1094 kvfree(sq->db.dma_fifo);
1097 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1099 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1100 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1102 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1103 sizeof(*sq->db.dma_fifo)),
1105 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1106 sizeof(*sq->db.wqe_info)),
1108 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1109 mlx5e_free_txqsq_db(sq);
1113 sq->dma_fifo_mask = df_sz - 1;
1118 static void mlx5e_sq_recover(struct work_struct *work);
1119 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1121 struct mlx5e_params *params,
1122 struct mlx5e_sq_param *param,
1123 struct mlx5e_txqsq *sq,
1126 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1127 struct mlx5_core_dev *mdev = c->mdev;
1128 struct mlx5_wq_cyc *wq = &sq->wq;
1132 sq->tstamp = c->tstamp;
1133 sq->clock = &mdev->clock;
1134 sq->mkey_be = c->mkey_be;
1136 sq->txq_ix = txq_ix;
1137 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1138 sq->min_inline_mode = params->tx_min_inline_mode;
1139 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1140 INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1141 if (MLX5_IPSEC_DEV(c->priv->mdev))
1142 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1143 if (mlx5_accel_is_tls_device(c->priv->mdev))
1144 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1146 param->wq.db_numa_node = cpu_to_node(c->cpu);
1147 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1150 wq->db = &wq->db[MLX5_SND_DBR];
1152 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1154 goto err_sq_wq_destroy;
1156 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1157 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1162 mlx5_wq_destroy(&sq->wq_ctrl);
1167 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1169 mlx5e_free_txqsq_db(sq);
1170 mlx5_wq_destroy(&sq->wq_ctrl);
1173 struct mlx5e_create_sq_param {
1174 struct mlx5_wq_ctrl *wq_ctrl;
1181 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1182 struct mlx5e_sq_param *param,
1183 struct mlx5e_create_sq_param *csp,
1192 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1193 sizeof(u64) * csp->wq_ctrl->buf.npages;
1194 in = kvzalloc(inlen, GFP_KERNEL);
1198 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1199 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1201 memcpy(sqc, param->sqc, sizeof(param->sqc));
1202 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1203 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1204 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1206 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1207 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1209 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1210 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1212 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1213 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1214 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1215 MLX5_ADAPTER_PAGE_SHIFT);
1216 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1218 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1219 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1221 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1228 struct mlx5e_modify_sq_param {
1235 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1236 struct mlx5e_modify_sq_param *p)
1243 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1244 in = kvzalloc(inlen, GFP_KERNEL);
1248 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1250 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1251 MLX5_SET(sqc, sqc, state, p->next_state);
1252 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1253 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1254 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1257 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1264 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1266 mlx5_core_destroy_sq(mdev, sqn);
1269 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1270 struct mlx5e_sq_param *param,
1271 struct mlx5e_create_sq_param *csp,
1274 struct mlx5e_modify_sq_param msp = {0};
1277 err = mlx5e_create_sq(mdev, param, csp, sqn);
1281 msp.curr_state = MLX5_SQC_STATE_RST;
1282 msp.next_state = MLX5_SQC_STATE_RDY;
1283 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1285 mlx5e_destroy_sq(mdev, *sqn);
1290 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1291 struct mlx5e_txqsq *sq, u32 rate);
1293 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1296 struct mlx5e_params *params,
1297 struct mlx5e_sq_param *param,
1298 struct mlx5e_txqsq *sq,
1301 struct mlx5e_create_sq_param csp = {};
1305 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1311 csp.cqn = sq->cq.mcq.cqn;
1312 csp.wq_ctrl = &sq->wq_ctrl;
1313 csp.min_inline_mode = sq->min_inline_mode;
1314 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1316 goto err_free_txqsq;
1318 tx_rate = c->priv->tx_rates[sq->txq_ix];
1320 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1322 if (params->tx_dim_enabled)
1323 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1328 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1329 mlx5e_free_txqsq(sq);
1334 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1336 WARN_ONCE(sq->cc != sq->pc,
1337 "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1338 sq->sqn, sq->cc, sq->pc);
1340 sq->dma_fifo_cc = 0;
1344 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1346 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1347 clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1348 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1349 netdev_tx_reset_queue(sq->txq);
1350 netif_tx_start_queue(sq->txq);
1353 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1355 __netif_tx_lock_bh(txq);
1356 netif_tx_stop_queue(txq);
1357 __netif_tx_unlock_bh(txq);
1360 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1362 struct mlx5e_channel *c = sq->channel;
1363 struct mlx5_wq_cyc *wq = &sq->wq;
1365 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1366 /* prevent netif_tx_wake_queue */
1367 napi_synchronize(&c->napi);
1369 netif_tx_disable_queue(sq->txq);
1371 /* last doorbell out, godspeed .. */
1372 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1373 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1374 struct mlx5e_tx_wqe *nop;
1376 sq->db.wqe_info[pi].skb = NULL;
1377 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1378 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1382 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1384 struct mlx5e_channel *c = sq->channel;
1385 struct mlx5_core_dev *mdev = c->mdev;
1386 struct mlx5_rate_limit rl = {0};
1388 mlx5e_destroy_sq(mdev, sq->sqn);
1389 if (sq->rate_limit) {
1390 rl.rate = sq->rate_limit;
1391 mlx5_rl_remove_rate(mdev, &rl);
1393 mlx5e_free_txqsq_descs(sq);
1394 mlx5e_free_txqsq(sq);
1397 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1399 unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1401 while (time_before(jiffies, exp_time)) {
1402 if (sq->cc == sq->pc)
1408 netdev_err(sq->channel->netdev,
1409 "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1410 sq->sqn, sq->cc, sq->pc);
1415 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1417 struct mlx5_core_dev *mdev = sq->channel->mdev;
1418 struct net_device *dev = sq->channel->netdev;
1419 struct mlx5e_modify_sq_param msp = {0};
1422 msp.curr_state = curr_state;
1423 msp.next_state = MLX5_SQC_STATE_RST;
1425 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1427 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1431 memset(&msp, 0, sizeof(msp));
1432 msp.curr_state = MLX5_SQC_STATE_RST;
1433 msp.next_state = MLX5_SQC_STATE_RDY;
1435 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1437 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1444 static void mlx5e_sq_recover(struct work_struct *work)
1446 struct mlx5e_txqsq_recover *recover =
1447 container_of(work, struct mlx5e_txqsq_recover,
1449 struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1451 struct mlx5_core_dev *mdev = sq->channel->mdev;
1452 struct net_device *dev = sq->channel->netdev;
1456 err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1458 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1463 if (state != MLX5_RQC_STATE_ERR) {
1464 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1468 netif_tx_disable_queue(sq->txq);
1470 if (mlx5e_wait_for_sq_flush(sq))
1473 /* If the interval between two consecutive recovers per SQ is too
1474 * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1475 * If we reached this state, there is probably a bug that needs to be
1476 * fixed. let's keep the queue close and let tx timeout cleanup.
1478 if (jiffies_to_msecs(jiffies - recover->last_recover) <
1479 MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1480 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1485 /* At this point, no new packets will arrive from the stack as TXQ is
1486 * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1487 * pending WQEs. SQ can safely reset the SQ.
1489 if (mlx5e_sq_to_ready(sq, state))
1492 mlx5e_reset_txqsq_cc_pc(sq);
1493 sq->stats->recover++;
1494 recover->last_recover = jiffies;
1495 mlx5e_activate_txqsq(sq);
1498 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1499 struct mlx5e_params *params,
1500 struct mlx5e_sq_param *param,
1501 struct mlx5e_icosq *sq)
1503 struct mlx5e_create_sq_param csp = {};
1506 err = mlx5e_alloc_icosq(c, param, sq);
1510 csp.cqn = sq->cq.mcq.cqn;
1511 csp.wq_ctrl = &sq->wq_ctrl;
1512 csp.min_inline_mode = params->tx_min_inline_mode;
1513 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1514 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1516 goto err_free_icosq;
1521 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1522 mlx5e_free_icosq(sq);
1527 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1529 struct mlx5e_channel *c = sq->channel;
1531 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1532 napi_synchronize(&c->napi);
1534 mlx5e_destroy_sq(c->mdev, sq->sqn);
1535 mlx5e_free_icosq(sq);
1538 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1539 struct mlx5e_params *params,
1540 struct mlx5e_sq_param *param,
1541 struct mlx5e_xdpsq *sq,
1544 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1545 struct mlx5e_create_sq_param csp = {};
1546 unsigned int inline_hdr_sz = 0;
1550 err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1555 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1556 csp.cqn = sq->cq.mcq.cqn;
1557 csp.wq_ctrl = &sq->wq_ctrl;
1558 csp.min_inline_mode = sq->min_inline_mode;
1560 set_bit(MLX5E_SQ_STATE_REDIRECT, &sq->state);
1561 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1562 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1564 goto err_free_xdpsq;
1566 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1567 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1571 /* Pre initialize fixed WQE fields */
1572 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1573 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1574 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1575 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1576 struct mlx5_wqe_data_seg *dseg;
1578 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1579 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1581 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1582 dseg->lkey = sq->mkey_be;
1588 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1589 mlx5e_free_xdpsq(sq);
1594 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1596 struct mlx5e_channel *c = sq->channel;
1598 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1599 napi_synchronize(&c->napi);
1601 mlx5e_destroy_sq(c->mdev, sq->sqn);
1602 mlx5e_free_xdpsq_descs(sq);
1603 mlx5e_free_xdpsq(sq);
1606 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1607 struct mlx5e_cq_param *param,
1608 struct mlx5e_cq *cq)
1610 struct mlx5_core_cq *mcq = &cq->mcq;
1616 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1621 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1624 mcq->set_ci_db = cq->wq_ctrl.db.db;
1625 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1626 *mcq->set_ci_db = 0;
1628 mcq->vector = param->eq_ix;
1629 mcq->comp = mlx5e_completion_event;
1630 mcq->event = mlx5e_cq_error_event;
1633 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1634 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1644 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1645 struct mlx5e_cq_param *param,
1646 struct mlx5e_cq *cq)
1648 struct mlx5_core_dev *mdev = c->priv->mdev;
1651 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1652 param->wq.db_numa_node = cpu_to_node(c->cpu);
1653 param->eq_ix = c->ix;
1655 err = mlx5e_alloc_cq_common(mdev, param, cq);
1657 cq->napi = &c->napi;
1663 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1665 mlx5_wq_destroy(&cq->wq_ctrl);
1668 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1670 struct mlx5_core_dev *mdev = cq->mdev;
1671 struct mlx5_core_cq *mcq = &cq->mcq;
1676 unsigned int irqn_not_used;
1680 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1681 sizeof(u64) * cq->wq_ctrl.buf.npages;
1682 in = kvzalloc(inlen, GFP_KERNEL);
1686 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1688 memcpy(cqc, param->cqc, sizeof(param->cqc));
1690 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1691 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1693 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1695 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1696 MLX5_SET(cqc, cqc, c_eqn, eqn);
1697 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1698 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1699 MLX5_ADAPTER_PAGE_SHIFT);
1700 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1702 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1714 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1716 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1719 static int mlx5e_open_cq(struct mlx5e_channel *c,
1720 struct net_dim_cq_moder moder,
1721 struct mlx5e_cq_param *param,
1722 struct mlx5e_cq *cq)
1724 struct mlx5_core_dev *mdev = c->mdev;
1727 err = mlx5e_alloc_cq(c, param, cq);
1731 err = mlx5e_create_cq(cq, param);
1735 if (MLX5_CAP_GEN(mdev, cq_moderation))
1736 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1745 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1747 mlx5e_destroy_cq(cq);
1751 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1753 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1756 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1757 struct mlx5e_params *params,
1758 struct mlx5e_channel_param *cparam)
1763 for (tc = 0; tc < c->num_tc; tc++) {
1764 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1765 &cparam->tx_cq, &c->sq[tc].cq);
1767 goto err_close_tx_cqs;
1773 for (tc--; tc >= 0; tc--)
1774 mlx5e_close_cq(&c->sq[tc].cq);
1779 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1783 for (tc = 0; tc < c->num_tc; tc++)
1784 mlx5e_close_cq(&c->sq[tc].cq);
1787 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1788 struct mlx5e_params *params,
1789 struct mlx5e_channel_param *cparam)
1791 struct mlx5e_priv *priv = c->priv;
1792 int err, tc, max_nch = priv->profile->max_nch(priv->mdev);
1794 for (tc = 0; tc < params->num_tc; tc++) {
1795 int txq_ix = c->ix + tc * max_nch;
1797 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1798 params, &cparam->sq, &c->sq[tc], tc);
1806 for (tc--; tc >= 0; tc--)
1807 mlx5e_close_txqsq(&c->sq[tc]);
1812 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1816 for (tc = 0; tc < c->num_tc; tc++)
1817 mlx5e_close_txqsq(&c->sq[tc]);
1820 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1821 struct mlx5e_txqsq *sq, u32 rate)
1823 struct mlx5e_priv *priv = netdev_priv(dev);
1824 struct mlx5_core_dev *mdev = priv->mdev;
1825 struct mlx5e_modify_sq_param msp = {0};
1826 struct mlx5_rate_limit rl = {0};
1830 if (rate == sq->rate_limit)
1834 if (sq->rate_limit) {
1835 rl.rate = sq->rate_limit;
1836 /* remove current rl index to free space to next ones */
1837 mlx5_rl_remove_rate(mdev, &rl);
1844 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1846 netdev_err(dev, "Failed configuring rate %u: %d\n",
1852 msp.curr_state = MLX5_SQC_STATE_RDY;
1853 msp.next_state = MLX5_SQC_STATE_RDY;
1854 msp.rl_index = rl_index;
1855 msp.rl_update = true;
1856 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1858 netdev_err(dev, "Failed configuring rate %u: %d\n",
1860 /* remove the rate from the table */
1862 mlx5_rl_remove_rate(mdev, &rl);
1866 sq->rate_limit = rate;
1870 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1872 struct mlx5e_priv *priv = netdev_priv(dev);
1873 struct mlx5_core_dev *mdev = priv->mdev;
1874 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1877 if (!mlx5_rl_is_supported(mdev)) {
1878 netdev_err(dev, "Rate limiting is not supported on this device\n");
1882 /* rate is given in Mb/sec, HW config is in Kb/sec */
1885 /* Check whether rate in valid range, 0 is always valid */
1886 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1887 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1891 mutex_lock(&priv->state_lock);
1892 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1893 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1895 priv->tx_rates[index] = rate;
1896 mutex_unlock(&priv->state_lock);
1901 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1902 struct mlx5e_params *params,
1903 struct mlx5e_channel_param *cparam,
1904 struct mlx5e_channel **cp)
1906 struct net_dim_cq_moder icocq_moder = {0, 0};
1907 struct net_device *netdev = priv->netdev;
1908 int cpu = mlx5e_get_cpu(priv, ix);
1909 struct mlx5e_channel *c;
1914 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1919 c->mdev = priv->mdev;
1920 c->tstamp = &priv->tstamp;
1923 c->pdev = &priv->mdev->pdev->dev;
1924 c->netdev = priv->netdev;
1925 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1926 c->num_tc = params->num_tc;
1927 c->xdp = !!params->xdp_prog;
1928 c->stats = &priv->channel_stats[ix].ch;
1930 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1931 c->irq_desc = irq_to_desc(irq);
1933 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1935 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1939 err = mlx5e_open_tx_cqs(c, params, cparam);
1941 goto err_close_icosq_cq;
1943 err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1945 goto err_close_tx_cqs;
1947 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1949 goto err_close_xdp_tx_cqs;
1951 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1952 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1953 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1955 goto err_close_rx_cq;
1957 napi_enable(&c->napi);
1959 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1961 goto err_disable_napi;
1963 err = mlx5e_open_sqs(c, params, cparam);
1965 goto err_close_icosq;
1967 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1971 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1973 goto err_close_xdp_sq;
1975 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1984 mlx5e_close_rq(&c->rq);
1988 mlx5e_close_xdpsq(&c->rq.xdpsq);
1994 mlx5e_close_icosq(&c->icosq);
1997 napi_disable(&c->napi);
1999 mlx5e_close_cq(&c->rq.xdpsq.cq);
2002 mlx5e_close_cq(&c->rq.cq);
2004 err_close_xdp_tx_cqs:
2005 mlx5e_close_cq(&c->xdpsq.cq);
2008 mlx5e_close_tx_cqs(c);
2011 mlx5e_close_cq(&c->icosq.cq);
2014 netif_napi_del(&c->napi);
2020 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2024 for (tc = 0; tc < c->num_tc; tc++)
2025 mlx5e_activate_txqsq(&c->sq[tc]);
2026 mlx5e_activate_rq(&c->rq);
2027 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
2030 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2034 mlx5e_deactivate_rq(&c->rq);
2035 for (tc = 0; tc < c->num_tc; tc++)
2036 mlx5e_deactivate_txqsq(&c->sq[tc]);
2039 static void mlx5e_close_channel(struct mlx5e_channel *c)
2041 mlx5e_close_xdpsq(&c->xdpsq);
2042 mlx5e_close_rq(&c->rq);
2044 mlx5e_close_xdpsq(&c->rq.xdpsq);
2046 mlx5e_close_icosq(&c->icosq);
2047 napi_disable(&c->napi);
2049 mlx5e_close_cq(&c->rq.xdpsq.cq);
2050 mlx5e_close_cq(&c->rq.cq);
2051 mlx5e_close_cq(&c->xdpsq.cq);
2052 mlx5e_close_tx_cqs(c);
2053 mlx5e_close_cq(&c->icosq.cq);
2054 netif_napi_del(&c->napi);
2059 #define DEFAULT_FRAG_SIZE (2048)
2061 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2062 struct mlx5e_params *params,
2063 struct mlx5e_rq_frags_info *info)
2065 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2066 int frag_size_max = DEFAULT_FRAG_SIZE;
2070 #ifdef CONFIG_MLX5_EN_IPSEC
2071 if (MLX5_IPSEC_DEV(mdev))
2072 byte_count += MLX5E_METADATA_ETHER_LEN;
2075 if (mlx5e_rx_is_linear_skb(mdev, params)) {
2078 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2079 frag_stride = roundup_pow_of_two(frag_stride);
2081 info->arr[0].frag_size = byte_count;
2082 info->arr[0].frag_stride = frag_stride;
2083 info->num_frags = 1;
2084 info->wqe_bulk = PAGE_SIZE / frag_stride;
2088 if (byte_count > PAGE_SIZE +
2089 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2090 frag_size_max = PAGE_SIZE;
2093 while (buf_size < byte_count) {
2094 int frag_size = byte_count - buf_size;
2096 if (i < MLX5E_MAX_RX_FRAGS - 1)
2097 frag_size = min(frag_size, frag_size_max);
2099 info->arr[i].frag_size = frag_size;
2100 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2102 buf_size += frag_size;
2105 info->num_frags = i;
2106 /* number of different wqes sharing a page */
2107 info->wqe_bulk = 1 + (info->num_frags % 2);
2110 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2111 info->log_num_frags = order_base_2(info->num_frags);
2114 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2116 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2119 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2120 sz += sizeof(struct mlx5e_rx_wqe_ll);
2122 default: /* MLX5_WQ_TYPE_CYCLIC */
2123 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2126 return order_base_2(sz);
2129 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2130 struct mlx5e_params *params,
2131 struct mlx5e_rq_param *param)
2133 struct mlx5_core_dev *mdev = priv->mdev;
2134 void *rqc = param->rqc;
2135 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2138 switch (params->rq_wq_type) {
2139 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2140 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2141 mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2142 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2143 MLX5_SET(wq, wq, log_wqe_stride_size,
2144 mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2145 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2146 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2148 default: /* MLX5_WQ_TYPE_CYCLIC */
2149 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2150 mlx5e_build_rq_frags_info(mdev, params, ¶m->frags_info);
2151 ndsegs = param->frags_info.num_frags;
2154 MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
2155 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2156 MLX5_SET(wq, wq, log_wq_stride,
2157 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2158 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
2159 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2160 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
2161 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
2163 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2166 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2167 struct mlx5e_rq_param *param)
2169 struct mlx5_core_dev *mdev = priv->mdev;
2170 void *rqc = param->rqc;
2171 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2173 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2174 MLX5_SET(wq, wq, log_wq_stride,
2175 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2176 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2178 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2181 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2182 struct mlx5e_sq_param *param)
2184 void *sqc = param->sqc;
2185 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2187 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2188 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
2190 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2193 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2194 struct mlx5e_params *params,
2195 struct mlx5e_sq_param *param)
2197 void *sqc = param->sqc;
2198 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2200 mlx5e_build_sq_param_common(priv, param);
2201 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2202 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2205 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2206 struct mlx5e_cq_param *param)
2208 void *cqc = param->cqc;
2210 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2213 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2214 struct mlx5e_params *params,
2215 struct mlx5e_cq_param *param)
2217 struct mlx5_core_dev *mdev = priv->mdev;
2218 void *cqc = param->cqc;
2221 switch (params->rq_wq_type) {
2222 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2223 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2224 mlx5e_mpwqe_get_log_num_strides(mdev, params);
2226 default: /* MLX5_WQ_TYPE_CYCLIC */
2227 log_cq_size = params->log_rq_mtu_frames;
2230 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2231 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2232 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2233 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2236 mlx5e_build_common_cq_param(priv, param);
2237 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2240 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2241 struct mlx5e_params *params,
2242 struct mlx5e_cq_param *param)
2244 void *cqc = param->cqc;
2246 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2248 mlx5e_build_common_cq_param(priv, param);
2249 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2252 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2254 struct mlx5e_cq_param *param)
2256 void *cqc = param->cqc;
2258 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2260 mlx5e_build_common_cq_param(priv, param);
2262 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2265 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2267 struct mlx5e_sq_param *param)
2269 void *sqc = param->sqc;
2270 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2272 mlx5e_build_sq_param_common(priv, param);
2274 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2275 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2278 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2279 struct mlx5e_params *params,
2280 struct mlx5e_sq_param *param)
2282 void *sqc = param->sqc;
2283 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2285 mlx5e_build_sq_param_common(priv, param);
2286 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2289 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2290 struct mlx5e_params *params,
2291 struct mlx5e_channel_param *cparam)
2293 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2295 mlx5e_build_rq_param(priv, params, &cparam->rq);
2296 mlx5e_build_sq_param(priv, params, &cparam->sq);
2297 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2298 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2299 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2300 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2301 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2304 int mlx5e_open_channels(struct mlx5e_priv *priv,
2305 struct mlx5e_channels *chs)
2307 struct mlx5e_channel_param *cparam;
2311 chs->num = chs->params.num_channels;
2313 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2314 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2315 if (!chs->c || !cparam)
2318 mlx5e_build_channel_param(priv, &chs->params, cparam);
2319 for (i = 0; i < chs->num; i++) {
2320 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2322 goto err_close_channels;
2329 for (i--; i >= 0; i--)
2330 mlx5e_close_channel(chs->c[i]);
2339 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2343 for (i = 0; i < chs->num; i++)
2344 mlx5e_activate_channel(chs->c[i]);
2347 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2352 for (i = 0; i < chs->num; i++)
2353 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2356 return err ? -ETIMEDOUT : 0;
2359 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2363 for (i = 0; i < chs->num; i++)
2364 mlx5e_deactivate_channel(chs->c[i]);
2367 void mlx5e_close_channels(struct mlx5e_channels *chs)
2371 for (i = 0; i < chs->num; i++)
2372 mlx5e_close_channel(chs->c[i]);
2379 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2381 struct mlx5_core_dev *mdev = priv->mdev;
2388 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2389 in = kvzalloc(inlen, GFP_KERNEL);
2393 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2395 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2396 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2398 for (i = 0; i < sz; i++)
2399 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2401 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2403 rqt->enabled = true;
2409 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2411 rqt->enabled = false;
2412 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2415 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2417 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2420 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2422 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2426 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2428 struct mlx5e_rqt *rqt;
2432 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2433 rqt = &priv->direct_tir[ix].rqt;
2434 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2436 goto err_destroy_rqts;
2442 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2443 for (ix--; ix >= 0; ix--)
2444 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2449 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2453 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2454 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2457 static int mlx5e_rx_hash_fn(int hfunc)
2459 return (hfunc == ETH_RSS_HASH_TOP) ?
2460 MLX5_RX_HASH_FN_TOEPLITZ :
2461 MLX5_RX_HASH_FN_INVERTED_XOR8;
2464 int mlx5e_bits_invert(unsigned long a, int size)
2469 for (i = 0; i < size; i++)
2470 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2475 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2476 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2480 for (i = 0; i < sz; i++) {
2486 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2487 ix = mlx5e_bits_invert(i, ilog2(sz));
2489 ix = priv->channels.params.indirection_rqt[ix];
2490 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2494 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2498 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2499 struct mlx5e_redirect_rqt_param rrp)
2501 struct mlx5_core_dev *mdev = priv->mdev;
2507 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2508 in = kvzalloc(inlen, GFP_KERNEL);
2512 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2514 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2515 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2516 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2517 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2523 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2524 struct mlx5e_redirect_rqt_param rrp)
2529 if (ix >= rrp.rss.channels->num)
2530 return priv->drop_rq.rqn;
2532 return rrp.rss.channels->c[ix]->rq.rqn;
2535 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2536 struct mlx5e_redirect_rqt_param rrp)
2541 if (priv->indir_rqt.enabled) {
2543 rqtn = priv->indir_rqt.rqtn;
2544 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2547 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2548 struct mlx5e_redirect_rqt_param direct_rrp = {
2551 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2555 /* Direct RQ Tables */
2556 if (!priv->direct_tir[ix].rqt.enabled)
2559 rqtn = priv->direct_tir[ix].rqt.rqtn;
2560 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2564 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2565 struct mlx5e_channels *chs)
2567 struct mlx5e_redirect_rqt_param rrp = {
2572 .hfunc = chs->params.rss_hfunc,
2577 mlx5e_redirect_rqts(priv, rrp);
2580 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2582 struct mlx5e_redirect_rqt_param drop_rrp = {
2585 .rqn = priv->drop_rq.rqn,
2589 mlx5e_redirect_rqts(priv, drop_rrp);
2592 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2594 if (!params->lro_en)
2597 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2599 MLX5_SET(tirc, tirc, lro_enable_mask,
2600 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2601 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2602 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2603 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2604 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2607 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2608 enum mlx5e_traffic_types tt,
2609 void *tirc, bool inner)
2611 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2612 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2614 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2615 MLX5_HASH_FIELD_SEL_DST_IP)
2617 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2618 MLX5_HASH_FIELD_SEL_DST_IP |\
2619 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2620 MLX5_HASH_FIELD_SEL_L4_DPORT)
2622 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2623 MLX5_HASH_FIELD_SEL_DST_IP |\
2624 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2626 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2627 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2628 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2629 rx_hash_toeplitz_key);
2630 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2631 rx_hash_toeplitz_key);
2633 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2634 memcpy(rss_key, params->toeplitz_hash_key, len);
2638 case MLX5E_TT_IPV4_TCP:
2639 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2640 MLX5_L3_PROT_TYPE_IPV4);
2641 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2642 MLX5_L4_PROT_TYPE_TCP);
2643 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2644 MLX5_HASH_IP_L4PORTS);
2647 case MLX5E_TT_IPV6_TCP:
2648 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2649 MLX5_L3_PROT_TYPE_IPV6);
2650 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2651 MLX5_L4_PROT_TYPE_TCP);
2652 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2653 MLX5_HASH_IP_L4PORTS);
2656 case MLX5E_TT_IPV4_UDP:
2657 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2658 MLX5_L3_PROT_TYPE_IPV4);
2659 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2660 MLX5_L4_PROT_TYPE_UDP);
2661 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2662 MLX5_HASH_IP_L4PORTS);
2665 case MLX5E_TT_IPV6_UDP:
2666 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2667 MLX5_L3_PROT_TYPE_IPV6);
2668 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2669 MLX5_L4_PROT_TYPE_UDP);
2670 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2671 MLX5_HASH_IP_L4PORTS);
2674 case MLX5E_TT_IPV4_IPSEC_AH:
2675 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2676 MLX5_L3_PROT_TYPE_IPV4);
2677 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2678 MLX5_HASH_IP_IPSEC_SPI);
2681 case MLX5E_TT_IPV6_IPSEC_AH:
2682 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2683 MLX5_L3_PROT_TYPE_IPV6);
2684 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2685 MLX5_HASH_IP_IPSEC_SPI);
2688 case MLX5E_TT_IPV4_IPSEC_ESP:
2689 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2690 MLX5_L3_PROT_TYPE_IPV4);
2691 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2692 MLX5_HASH_IP_IPSEC_SPI);
2695 case MLX5E_TT_IPV6_IPSEC_ESP:
2696 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2697 MLX5_L3_PROT_TYPE_IPV6);
2698 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2699 MLX5_HASH_IP_IPSEC_SPI);
2703 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2704 MLX5_L3_PROT_TYPE_IPV4);
2705 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2710 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2711 MLX5_L3_PROT_TYPE_IPV6);
2712 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2716 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2720 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2722 struct mlx5_core_dev *mdev = priv->mdev;
2731 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2732 in = kvzalloc(inlen, GFP_KERNEL);
2736 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2737 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2739 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2741 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2742 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2748 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2749 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2761 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2762 enum mlx5e_traffic_types tt,
2765 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2767 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2769 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2770 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2771 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2773 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2776 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2777 struct mlx5e_params *params, u16 mtu)
2779 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2782 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2786 /* Update vport context MTU */
2787 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2791 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2792 struct mlx5e_params *params, u16 *mtu)
2797 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2798 if (err || !hw_mtu) /* fallback to port oper mtu */
2799 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2801 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2804 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2806 struct mlx5e_params *params = &priv->channels.params;
2807 struct net_device *netdev = priv->netdev;
2808 struct mlx5_core_dev *mdev = priv->mdev;
2812 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2816 mlx5e_query_mtu(mdev, params, &mtu);
2817 if (mtu != params->sw_mtu)
2818 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2819 __func__, mtu, params->sw_mtu);
2821 params->sw_mtu = mtu;
2825 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2827 struct mlx5e_priv *priv = netdev_priv(netdev);
2828 int nch = priv->channels.params.num_channels;
2829 int ntc = priv->channels.params.num_tc;
2832 netdev_reset_tc(netdev);
2837 netdev_set_num_tc(netdev, ntc);
2839 /* Map netdev TCs to offset 0
2840 * We have our own UP to TXQ mapping for QoS
2842 for (tc = 0; tc < ntc; tc++)
2843 netdev_set_tc_queue(netdev, tc, nch, 0);
2846 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2848 int max_nch = priv->profile->max_nch(priv->mdev);
2851 for (i = 0; i < max_nch; i++)
2852 for (tc = 0; tc < priv->profile->max_tc; tc++)
2853 priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2856 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2858 struct mlx5e_channel *c;
2859 struct mlx5e_txqsq *sq;
2862 for (i = 0; i < priv->channels.num; i++) {
2863 c = priv->channels.c[i];
2864 for (tc = 0; tc < c->num_tc; tc++) {
2866 priv->txq2sq[sq->txq_ix] = sq;
2871 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2873 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2874 struct net_device *netdev = priv->netdev;
2876 mlx5e_netdev_set_tcs(netdev);
2877 netif_set_real_num_tx_queues(netdev, num_txqs);
2878 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2880 mlx5e_build_tx2sq_maps(priv);
2881 mlx5e_activate_channels(&priv->channels);
2882 netif_tx_start_all_queues(priv->netdev);
2884 if (MLX5_ESWITCH_MANAGER(priv->mdev))
2885 mlx5e_add_sqs_fwd_rules(priv);
2887 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2888 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2891 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2893 mlx5e_redirect_rqts_to_drop(priv);
2895 if (MLX5_ESWITCH_MANAGER(priv->mdev))
2896 mlx5e_remove_sqs_fwd_rules(priv);
2898 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2899 * polling for inactive tx queues.
2901 netif_tx_stop_all_queues(priv->netdev);
2902 netif_tx_disable(priv->netdev);
2903 mlx5e_deactivate_channels(&priv->channels);
2906 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2907 struct mlx5e_channels *new_chs,
2908 mlx5e_fp_hw_modify hw_modify)
2910 struct net_device *netdev = priv->netdev;
2913 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2915 carrier_ok = netif_carrier_ok(netdev);
2916 netif_carrier_off(netdev);
2918 if (new_num_txqs < netdev->real_num_tx_queues)
2919 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2921 mlx5e_deactivate_priv_channels(priv);
2922 mlx5e_close_channels(&priv->channels);
2924 priv->channels = *new_chs;
2926 /* New channels are ready to roll, modify HW settings if needed */
2930 mlx5e_refresh_tirs(priv, false);
2931 mlx5e_activate_priv_channels(priv);
2933 /* return carrier back if needed */
2935 netif_carrier_on(netdev);
2938 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2940 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2941 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2944 int mlx5e_open_locked(struct net_device *netdev)
2946 struct mlx5e_priv *priv = netdev_priv(netdev);
2949 set_bit(MLX5E_STATE_OPENED, &priv->state);
2951 err = mlx5e_open_channels(priv, &priv->channels);
2953 goto err_clear_state_opened_flag;
2955 mlx5e_refresh_tirs(priv, false);
2956 mlx5e_activate_priv_channels(priv);
2957 if (priv->profile->update_carrier)
2958 priv->profile->update_carrier(priv);
2960 if (priv->profile->update_stats)
2961 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2965 err_clear_state_opened_flag:
2966 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2970 int mlx5e_open(struct net_device *netdev)
2972 struct mlx5e_priv *priv = netdev_priv(netdev);
2975 mutex_lock(&priv->state_lock);
2976 err = mlx5e_open_locked(netdev);
2978 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2979 mutex_unlock(&priv->state_lock);
2981 if (mlx5_vxlan_allowed(priv->mdev->vxlan))
2982 udp_tunnel_get_rx_info(netdev);
2987 int mlx5e_close_locked(struct net_device *netdev)
2989 struct mlx5e_priv *priv = netdev_priv(netdev);
2991 /* May already be CLOSED in case a previous configuration operation
2992 * (e.g RX/TX queue size change) that involves close&open failed.
2994 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2997 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2999 netif_carrier_off(priv->netdev);
3000 mlx5e_deactivate_priv_channels(priv);
3001 mlx5e_close_channels(&priv->channels);
3006 int mlx5e_close(struct net_device *netdev)
3008 struct mlx5e_priv *priv = netdev_priv(netdev);
3011 if (!netif_device_present(netdev))
3014 mutex_lock(&priv->state_lock);
3015 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3016 err = mlx5e_close_locked(netdev);
3017 mutex_unlock(&priv->state_lock);
3022 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3023 struct mlx5e_rq *rq,
3024 struct mlx5e_rq_param *param)
3026 void *rqc = param->rqc;
3027 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3030 param->wq.db_numa_node = param->wq.buf_numa_node;
3032 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
3037 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3038 xdp_rxq_info_unused(&rq->xdp_rxq);
3045 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3046 struct mlx5e_cq *cq,
3047 struct mlx5e_cq_param *param)
3049 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3050 param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev);
3052 return mlx5e_alloc_cq_common(mdev, param, cq);
3055 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3056 struct mlx5e_rq *drop_rq)
3058 struct mlx5_core_dev *mdev = priv->mdev;
3059 struct mlx5e_cq_param cq_param = {};
3060 struct mlx5e_rq_param rq_param = {};
3061 struct mlx5e_cq *cq = &drop_rq->cq;
3064 mlx5e_build_drop_rq_param(priv, &rq_param);
3066 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3070 err = mlx5e_create_cq(cq, &cq_param);
3074 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3076 goto err_destroy_cq;
3078 err = mlx5e_create_rq(drop_rq, &rq_param);
3082 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3084 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3089 mlx5e_free_rq(drop_rq);
3092 mlx5e_destroy_cq(cq);
3100 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3102 mlx5e_destroy_rq(drop_rq);
3103 mlx5e_free_rq(drop_rq);
3104 mlx5e_destroy_cq(&drop_rq->cq);
3105 mlx5e_free_cq(&drop_rq->cq);
3108 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3109 u32 underlay_qpn, u32 *tisn)
3111 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3112 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3114 MLX5_SET(tisc, tisc, prio, tc << 1);
3115 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3116 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3118 if (mlx5_lag_is_lacp_owner(mdev))
3119 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3121 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3124 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3126 mlx5_core_destroy_tis(mdev, tisn);
3129 int mlx5e_create_tises(struct mlx5e_priv *priv)
3134 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3135 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3137 goto err_close_tises;
3143 for (tc--; tc >= 0; tc--)
3144 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3149 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3153 for (tc = 0; tc < priv->profile->max_tc; tc++)
3154 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3157 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3158 enum mlx5e_traffic_types tt,
3161 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3163 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3165 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3166 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3167 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
3170 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3172 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3174 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3176 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3177 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3178 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3181 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3183 struct mlx5e_tir *tir;
3191 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3192 in = kvzalloc(inlen, GFP_KERNEL);
3196 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3197 memset(in, 0, inlen);
3198 tir = &priv->indir_tir[tt];
3199 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3200 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3201 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3203 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3204 goto err_destroy_inner_tirs;
3208 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3211 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3212 memset(in, 0, inlen);
3213 tir = &priv->inner_indir_tir[i];
3214 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3215 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3216 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3218 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3219 goto err_destroy_inner_tirs;
3228 err_destroy_inner_tirs:
3229 for (i--; i >= 0; i--)
3230 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3232 for (tt--; tt >= 0; tt--)
3233 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3240 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3242 int nch = priv->profile->max_nch(priv->mdev);
3243 struct mlx5e_tir *tir;
3250 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3251 in = kvzalloc(inlen, GFP_KERNEL);
3255 for (ix = 0; ix < nch; ix++) {
3256 memset(in, 0, inlen);
3257 tir = &priv->direct_tir[ix];
3258 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3259 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3260 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3262 goto err_destroy_ch_tirs;
3269 err_destroy_ch_tirs:
3270 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3271 for (ix--; ix >= 0; ix--)
3272 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3279 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3283 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3284 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3286 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3289 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3290 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3293 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3295 int nch = priv->profile->max_nch(priv->mdev);
3298 for (i = 0; i < nch; i++)
3299 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3302 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3307 for (i = 0; i < chs->num; i++) {
3308 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3316 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3321 for (i = 0; i < chs->num; i++) {
3322 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3330 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3331 struct tc_mqprio_qopt *mqprio)
3333 struct mlx5e_priv *priv = netdev_priv(netdev);
3334 struct mlx5e_channels new_channels = {};
3335 u8 tc = mqprio->num_tc;
3338 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3340 if (tc && tc != MLX5E_MAX_NUM_TC)
3343 mutex_lock(&priv->state_lock);
3345 new_channels.params = priv->channels.params;
3346 new_channels.params.num_tc = tc ? tc : 1;
3348 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3349 priv->channels.params = new_channels.params;
3353 err = mlx5e_open_channels(priv, &new_channels);
3357 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3358 new_channels.params.num_tc);
3359 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3361 mutex_unlock(&priv->state_lock);
3365 #ifdef CONFIG_MLX5_ESWITCH
3366 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3367 struct tc_cls_flower_offload *cls_flower,
3370 switch (cls_flower->command) {
3371 case TC_CLSFLOWER_REPLACE:
3372 return mlx5e_configure_flower(priv, cls_flower, flags);
3373 case TC_CLSFLOWER_DESTROY:
3374 return mlx5e_delete_flower(priv, cls_flower, flags);
3375 case TC_CLSFLOWER_STATS:
3376 return mlx5e_stats_flower(priv, cls_flower, flags);
3382 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3385 struct mlx5e_priv *priv = cb_priv;
3387 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3391 case TC_SETUP_CLSFLOWER:
3392 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS);
3398 static int mlx5e_setup_tc_block(struct net_device *dev,
3399 struct tc_block_offload *f)
3401 struct mlx5e_priv *priv = netdev_priv(dev);
3403 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3406 switch (f->command) {
3408 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3409 priv, priv, f->extack);
3410 case TC_BLOCK_UNBIND:
3411 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3420 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3424 #ifdef CONFIG_MLX5_ESWITCH
3425 case TC_SETUP_BLOCK:
3426 return mlx5e_setup_tc_block(dev, type_data);
3428 case TC_SETUP_QDISC_MQPRIO:
3429 return mlx5e_setup_tc_mqprio(dev, type_data);
3436 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3438 struct mlx5e_priv *priv = netdev_priv(dev);
3439 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3440 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3441 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3443 /* update HW stats in background for next time */
3444 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
3446 if (mlx5e_is_uplink_rep(priv)) {
3447 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3448 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3449 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3450 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3452 mlx5e_grp_sw_update_stats(priv);
3453 stats->rx_packets = sstats->rx_packets;
3454 stats->rx_bytes = sstats->rx_bytes;
3455 stats->tx_packets = sstats->tx_packets;
3456 stats->tx_bytes = sstats->tx_bytes;
3457 stats->tx_dropped = sstats->tx_queue_dropped;
3460 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3462 stats->rx_length_errors =
3463 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3464 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3465 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3466 stats->rx_crc_errors =
3467 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3468 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3469 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3470 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3471 stats->rx_frame_errors;
3472 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3474 /* vport multicast also counts packets that are dropped due to steering
3475 * or rx out of buffer
3478 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3481 static void mlx5e_set_rx_mode(struct net_device *dev)
3483 struct mlx5e_priv *priv = netdev_priv(dev);
3485 queue_work(priv->wq, &priv->set_rx_mode_work);
3488 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3490 struct mlx5e_priv *priv = netdev_priv(netdev);
3491 struct sockaddr *saddr = addr;
3493 if (!is_valid_ether_addr(saddr->sa_data))
3494 return -EADDRNOTAVAIL;
3496 netif_addr_lock_bh(netdev);
3497 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3498 netif_addr_unlock_bh(netdev);
3500 queue_work(priv->wq, &priv->set_rx_mode_work);
3505 #define MLX5E_SET_FEATURE(features, feature, enable) \
3508 *features |= feature; \
3510 *features &= ~feature; \
3513 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3515 static int set_feature_lro(struct net_device *netdev, bool enable)
3517 struct mlx5e_priv *priv = netdev_priv(netdev);
3518 struct mlx5_core_dev *mdev = priv->mdev;
3519 struct mlx5e_channels new_channels = {};
3520 struct mlx5e_params *old_params;
3524 mutex_lock(&priv->state_lock);
3526 old_params = &priv->channels.params;
3527 if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3528 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3533 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3535 new_channels.params = *old_params;
3536 new_channels.params.lro_en = enable;
3538 if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3539 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3540 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3545 *old_params = new_channels.params;
3546 err = mlx5e_modify_tirs_lro(priv);
3550 err = mlx5e_open_channels(priv, &new_channels);
3554 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3556 mutex_unlock(&priv->state_lock);
3560 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3562 struct mlx5e_priv *priv = netdev_priv(netdev);
3565 mlx5e_enable_cvlan_filter(priv);
3567 mlx5e_disable_cvlan_filter(priv);
3572 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3574 struct mlx5e_priv *priv = netdev_priv(netdev);
3576 if (!enable && mlx5e_tc_num_filters(priv)) {
3578 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3585 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3587 struct mlx5e_priv *priv = netdev_priv(netdev);
3588 struct mlx5_core_dev *mdev = priv->mdev;
3590 return mlx5_set_port_fcs(mdev, !enable);
3593 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3595 struct mlx5e_priv *priv = netdev_priv(netdev);
3598 mutex_lock(&priv->state_lock);
3600 priv->channels.params.scatter_fcs_en = enable;
3601 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3603 priv->channels.params.scatter_fcs_en = !enable;
3605 mutex_unlock(&priv->state_lock);
3610 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3612 struct mlx5e_priv *priv = netdev_priv(netdev);
3615 mutex_lock(&priv->state_lock);
3617 priv->channels.params.vlan_strip_disable = !enable;
3618 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3621 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3623 priv->channels.params.vlan_strip_disable = enable;
3626 mutex_unlock(&priv->state_lock);
3631 #ifdef CONFIG_MLX5_EN_ARFS
3632 static int set_feature_arfs(struct net_device *netdev, bool enable)
3634 struct mlx5e_priv *priv = netdev_priv(netdev);
3638 err = mlx5e_arfs_enable(priv);
3640 err = mlx5e_arfs_disable(priv);
3646 static int mlx5e_handle_feature(struct net_device *netdev,
3647 netdev_features_t *features,
3648 netdev_features_t wanted_features,
3649 netdev_features_t feature,
3650 mlx5e_feature_handler feature_handler)
3652 netdev_features_t changes = wanted_features ^ netdev->features;
3653 bool enable = !!(wanted_features & feature);
3656 if (!(changes & feature))
3659 err = feature_handler(netdev, enable);
3661 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3662 enable ? "Enable" : "Disable", &feature, err);
3666 MLX5E_SET_FEATURE(features, feature, enable);
3670 static int mlx5e_set_features(struct net_device *netdev,
3671 netdev_features_t features)
3673 netdev_features_t oper_features = netdev->features;
3676 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3677 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3679 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3680 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3681 set_feature_cvlan_filter);
3682 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3683 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3684 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3685 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3686 #ifdef CONFIG_MLX5_EN_ARFS
3687 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3691 netdev->features = oper_features;
3698 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3699 netdev_features_t features)
3701 struct mlx5e_priv *priv = netdev_priv(netdev);
3702 struct mlx5e_params *params;
3704 mutex_lock(&priv->state_lock);
3705 params = &priv->channels.params;
3706 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3707 /* HW strips the outer C-tag header, this is a problem
3708 * for S-tag traffic.
3710 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3711 if (!params->vlan_strip_disable)
3712 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3714 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3715 features &= ~NETIF_F_LRO;
3717 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3720 mutex_unlock(&priv->state_lock);
3725 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3726 change_hw_mtu_cb set_mtu_cb)
3728 struct mlx5e_priv *priv = netdev_priv(netdev);
3729 struct mlx5e_channels new_channels = {};
3730 struct mlx5e_params *params;
3734 mutex_lock(&priv->state_lock);
3736 params = &priv->channels.params;
3738 reset = !params->lro_en;
3739 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3741 new_channels.params = *params;
3742 new_channels.params.sw_mtu = new_mtu;
3744 if (params->xdp_prog &&
3745 !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3746 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3747 new_mtu, MLX5E_XDP_MAX_MTU);
3752 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3753 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3754 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3756 reset = reset && (ppw_old != ppw_new);
3760 params->sw_mtu = new_mtu;
3763 netdev->mtu = params->sw_mtu;
3767 err = mlx5e_open_channels(priv, &new_channels);
3771 mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
3772 netdev->mtu = new_channels.params.sw_mtu;
3775 mutex_unlock(&priv->state_lock);
3779 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3781 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3784 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3786 struct hwtstamp_config config;
3789 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3790 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3793 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3796 /* TX HW timestamp */
3797 switch (config.tx_type) {
3798 case HWTSTAMP_TX_OFF:
3799 case HWTSTAMP_TX_ON:
3805 mutex_lock(&priv->state_lock);
3806 /* RX HW timestamp */
3807 switch (config.rx_filter) {
3808 case HWTSTAMP_FILTER_NONE:
3809 /* Reset CQE compression to Admin default */
3810 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3812 case HWTSTAMP_FILTER_ALL:
3813 case HWTSTAMP_FILTER_SOME:
3814 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3815 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3816 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3817 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3818 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3819 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3820 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3821 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3822 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3823 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3824 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3825 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3826 case HWTSTAMP_FILTER_NTP_ALL:
3827 /* Disable CQE compression */
3828 netdev_warn(priv->netdev, "Disabling cqe compression");
3829 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3831 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3832 mutex_unlock(&priv->state_lock);
3835 config.rx_filter = HWTSTAMP_FILTER_ALL;
3838 mutex_unlock(&priv->state_lock);
3842 memcpy(&priv->tstamp, &config, sizeof(config));
3843 mutex_unlock(&priv->state_lock);
3845 return copy_to_user(ifr->ifr_data, &config,
3846 sizeof(config)) ? -EFAULT : 0;
3849 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3851 struct hwtstamp_config *cfg = &priv->tstamp;
3853 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3856 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3859 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3861 struct mlx5e_priv *priv = netdev_priv(dev);
3865 return mlx5e_hwstamp_set(priv, ifr);
3867 return mlx5e_hwstamp_get(priv, ifr);
3873 #ifdef CONFIG_MLX5_ESWITCH
3874 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3876 struct mlx5e_priv *priv = netdev_priv(dev);
3877 struct mlx5_core_dev *mdev = priv->mdev;
3879 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3882 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3885 struct mlx5e_priv *priv = netdev_priv(dev);
3886 struct mlx5_core_dev *mdev = priv->mdev;
3888 if (vlan_proto != htons(ETH_P_8021Q))
3889 return -EPROTONOSUPPORT;
3891 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3895 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3897 struct mlx5e_priv *priv = netdev_priv(dev);
3898 struct mlx5_core_dev *mdev = priv->mdev;
3900 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3903 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3905 struct mlx5e_priv *priv = netdev_priv(dev);
3906 struct mlx5_core_dev *mdev = priv->mdev;
3908 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3911 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3914 struct mlx5e_priv *priv = netdev_priv(dev);
3915 struct mlx5_core_dev *mdev = priv->mdev;
3917 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3918 max_tx_rate, min_tx_rate);
3921 static int mlx5_vport_link2ifla(u8 esw_link)
3924 case MLX5_VPORT_ADMIN_STATE_DOWN:
3925 return IFLA_VF_LINK_STATE_DISABLE;
3926 case MLX5_VPORT_ADMIN_STATE_UP:
3927 return IFLA_VF_LINK_STATE_ENABLE;
3929 return IFLA_VF_LINK_STATE_AUTO;
3932 static int mlx5_ifla_link2vport(u8 ifla_link)
3934 switch (ifla_link) {
3935 case IFLA_VF_LINK_STATE_DISABLE:
3936 return MLX5_VPORT_ADMIN_STATE_DOWN;
3937 case IFLA_VF_LINK_STATE_ENABLE:
3938 return MLX5_VPORT_ADMIN_STATE_UP;
3940 return MLX5_VPORT_ADMIN_STATE_AUTO;
3943 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3946 struct mlx5e_priv *priv = netdev_priv(dev);
3947 struct mlx5_core_dev *mdev = priv->mdev;
3949 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3950 mlx5_ifla_link2vport(link_state));
3953 static int mlx5e_get_vf_config(struct net_device *dev,
3954 int vf, struct ifla_vf_info *ivi)
3956 struct mlx5e_priv *priv = netdev_priv(dev);
3957 struct mlx5_core_dev *mdev = priv->mdev;
3960 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3963 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3967 static int mlx5e_get_vf_stats(struct net_device *dev,
3968 int vf, struct ifla_vf_stats *vf_stats)
3970 struct mlx5e_priv *priv = netdev_priv(dev);
3971 struct mlx5_core_dev *mdev = priv->mdev;
3973 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3978 struct mlx5e_vxlan_work {
3979 struct work_struct work;
3980 struct mlx5e_priv *priv;
3984 static void mlx5e_vxlan_add_work(struct work_struct *work)
3986 struct mlx5e_vxlan_work *vxlan_work =
3987 container_of(work, struct mlx5e_vxlan_work, work);
3988 struct mlx5e_priv *priv = vxlan_work->priv;
3989 u16 port = vxlan_work->port;
3991 mutex_lock(&priv->state_lock);
3992 mlx5_vxlan_add_port(priv->mdev->vxlan, port);
3993 mutex_unlock(&priv->state_lock);
3998 static void mlx5e_vxlan_del_work(struct work_struct *work)
4000 struct mlx5e_vxlan_work *vxlan_work =
4001 container_of(work, struct mlx5e_vxlan_work, work);
4002 struct mlx5e_priv *priv = vxlan_work->priv;
4003 u16 port = vxlan_work->port;
4005 mutex_lock(&priv->state_lock);
4006 mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4007 mutex_unlock(&priv->state_lock);
4011 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4013 struct mlx5e_vxlan_work *vxlan_work;
4015 vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4020 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4022 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4024 vxlan_work->priv = priv;
4025 vxlan_work->port = port;
4026 queue_work(priv->wq, &vxlan_work->work);
4029 static void mlx5e_add_vxlan_port(struct net_device *netdev,
4030 struct udp_tunnel_info *ti)
4032 struct mlx5e_priv *priv = netdev_priv(netdev);
4034 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4037 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4040 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4043 static void mlx5e_del_vxlan_port(struct net_device *netdev,
4044 struct udp_tunnel_info *ti)
4046 struct mlx5e_priv *priv = netdev_priv(netdev);
4048 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4051 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4054 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4057 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4058 struct sk_buff *skb,
4059 netdev_features_t features)
4061 unsigned int offset = 0;
4062 struct udphdr *udph;
4066 switch (vlan_get_protocol(skb)) {
4067 case htons(ETH_P_IP):
4068 proto = ip_hdr(skb)->protocol;
4070 case htons(ETH_P_IPV6):
4071 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4081 udph = udp_hdr(skb);
4082 port = be16_to_cpu(udph->dest);
4084 /* Verify if UDP port is being offloaded by HW */
4085 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4090 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4091 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4094 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4095 struct net_device *netdev,
4096 netdev_features_t features)
4098 struct mlx5e_priv *priv = netdev_priv(netdev);
4100 features = vlan_features_check(skb, features);
4101 features = vxlan_features_check(skb, features);
4103 #ifdef CONFIG_MLX5_EN_IPSEC
4104 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4108 /* Validate if the tunneled packet is being offloaded by HW */
4109 if (skb->encapsulation &&
4110 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4111 return mlx5e_tunnel_features_check(priv, skb, features);
4116 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4117 struct mlx5e_txqsq *sq)
4119 struct mlx5_eq *eq = sq->cq.mcq.eq;
4122 netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
4123 eq->eqn, eq->cons_index, eq->irqn);
4125 eqe_count = mlx5_eq_poll_irq_disabled(eq);
4129 netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
4130 sq->channel->stats->eq_rearm++;
4134 static void mlx5e_tx_timeout_work(struct work_struct *work)
4136 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4138 struct net_device *dev = priv->netdev;
4139 bool reopen_channels = false;
4143 mutex_lock(&priv->state_lock);
4145 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4148 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4149 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
4150 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4152 if (!netif_xmit_stopped(dev_queue))
4156 "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
4157 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4158 jiffies_to_usecs(jiffies - dev_queue->trans_start));
4160 /* If we recover a lost interrupt, most likely TX timeout will
4161 * be resolved, skip reopening channels
4163 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4164 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4165 reopen_channels = true;
4169 if (!reopen_channels)
4172 mlx5e_close_locked(dev);
4173 err = mlx5e_open_locked(dev);
4175 netdev_err(priv->netdev,
4176 "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4180 mutex_unlock(&priv->state_lock);
4184 static void mlx5e_tx_timeout(struct net_device *dev)
4186 struct mlx5e_priv *priv = netdev_priv(dev);
4188 netdev_err(dev, "TX timeout detected\n");
4189 queue_work(priv->wq, &priv->tx_timeout_work);
4192 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4194 struct net_device *netdev = priv->netdev;
4195 struct mlx5e_channels new_channels = {};
4197 if (priv->channels.params.lro_en) {
4198 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4202 if (MLX5_IPSEC_DEV(priv->mdev)) {
4203 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4207 new_channels.params = priv->channels.params;
4208 new_channels.params.xdp_prog = prog;
4210 if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4211 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4212 new_channels.params.sw_mtu, MLX5E_XDP_MAX_MTU);
4219 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4221 struct mlx5e_priv *priv = netdev_priv(netdev);
4222 struct bpf_prog *old_prog;
4223 bool reset, was_opened;
4227 mutex_lock(&priv->state_lock);
4230 err = mlx5e_xdp_allowed(priv, prog);
4235 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4236 /* no need for full reset when exchanging programs */
4237 reset = (!priv->channels.params.xdp_prog || !prog);
4239 if (was_opened && reset)
4240 mlx5e_close_locked(netdev);
4241 if (was_opened && !reset) {
4242 /* num_channels is invariant here, so we can take the
4243 * batched reference right upfront.
4245 prog = bpf_prog_add(prog, priv->channels.num);
4247 err = PTR_ERR(prog);
4252 /* exchange programs, extra prog reference we got from caller
4253 * as long as we don't fail from this point onwards.
4255 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4257 bpf_prog_put(old_prog);
4259 if (reset) /* change RQ type according to priv->xdp_prog */
4260 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4262 if (was_opened && reset)
4263 mlx5e_open_locked(netdev);
4265 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4268 /* exchanging programs w/o reset, we update ref counts on behalf
4269 * of the channels RQs here.
4271 for (i = 0; i < priv->channels.num; i++) {
4272 struct mlx5e_channel *c = priv->channels.c[i];
4274 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4275 napi_synchronize(&c->napi);
4276 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4278 old_prog = xchg(&c->rq.xdp_prog, prog);
4280 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4281 /* napi_schedule in case we have missed anything */
4282 napi_schedule(&c->napi);
4285 bpf_prog_put(old_prog);
4289 mutex_unlock(&priv->state_lock);
4293 static u32 mlx5e_xdp_query(struct net_device *dev)
4295 struct mlx5e_priv *priv = netdev_priv(dev);
4296 const struct bpf_prog *xdp_prog;
4299 mutex_lock(&priv->state_lock);
4300 xdp_prog = priv->channels.params.xdp_prog;
4302 prog_id = xdp_prog->aux->id;
4303 mutex_unlock(&priv->state_lock);
4308 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4310 switch (xdp->command) {
4311 case XDP_SETUP_PROG:
4312 return mlx5e_xdp_set(dev, xdp->prog);
4313 case XDP_QUERY_PROG:
4314 xdp->prog_id = mlx5e_xdp_query(dev);
4321 static const struct net_device_ops mlx5e_netdev_ops = {
4322 .ndo_open = mlx5e_open,
4323 .ndo_stop = mlx5e_close,
4324 .ndo_start_xmit = mlx5e_xmit,
4325 .ndo_setup_tc = mlx5e_setup_tc,
4326 .ndo_select_queue = mlx5e_select_queue,
4327 .ndo_get_stats64 = mlx5e_get_stats,
4328 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4329 .ndo_set_mac_address = mlx5e_set_mac,
4330 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4331 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4332 .ndo_set_features = mlx5e_set_features,
4333 .ndo_fix_features = mlx5e_fix_features,
4334 .ndo_change_mtu = mlx5e_change_nic_mtu,
4335 .ndo_do_ioctl = mlx5e_ioctl,
4336 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4337 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
4338 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
4339 .ndo_features_check = mlx5e_features_check,
4340 .ndo_tx_timeout = mlx5e_tx_timeout,
4341 .ndo_bpf = mlx5e_xdp,
4342 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4343 #ifdef CONFIG_MLX5_EN_ARFS
4344 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4346 #ifdef CONFIG_MLX5_ESWITCH
4347 /* SRIOV E-Switch NDOs */
4348 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4349 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4350 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4351 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4352 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4353 .ndo_get_vf_config = mlx5e_get_vf_config,
4354 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4355 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4356 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4357 .ndo_get_offload_stats = mlx5e_get_offload_stats,
4361 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4363 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4365 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4366 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4367 !MLX5_CAP_ETH(mdev, csum_cap) ||
4368 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4369 !MLX5_CAP_ETH(mdev, vlan_cap) ||
4370 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4371 MLX5_CAP_FLOWTABLE(mdev,
4372 flow_table_properties_nic_receive.max_ft_level)
4374 mlx5_core_warn(mdev,
4375 "Not creating net device, some required device capabilities are missing\n");
4378 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4379 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4380 if (!MLX5_CAP_GEN(mdev, cq_moderation))
4381 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4386 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4391 for (i = 0; i < len; i++)
4392 indirection_rqt[i] = i % num_channels;
4395 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4400 mlx5e_port_max_linkspeed(mdev, &link_speed);
4401 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4402 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4403 link_speed, pci_bw);
4405 #define MLX5E_SLOW_PCI_RATIO (2)
4407 return link_speed && pci_bw &&
4408 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4411 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4413 struct net_dim_cq_moder moder;
4415 moder.cq_period_mode = cq_period_mode;
4416 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4417 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4418 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4419 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4424 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4426 struct net_dim_cq_moder moder;
4428 moder.cq_period_mode = cq_period_mode;
4429 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4430 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4431 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4432 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4437 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4439 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4440 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4441 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4444 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4446 if (params->tx_dim_enabled) {
4447 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4449 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4451 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4454 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4455 params->tx_cq_moderation.cq_period_mode ==
4456 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4459 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4461 if (params->rx_dim_enabled) {
4462 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4464 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4466 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4469 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4470 params->rx_cq_moderation.cq_period_mode ==
4471 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4474 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4478 /* The supported periods are organized in ascending order */
4479 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4480 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4483 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4486 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4487 struct mlx5e_params *params)
4489 /* Prefer Striding RQ, unless any of the following holds:
4490 * - Striding RQ configuration is not possible/supported.
4491 * - Slow PCI heuristic.
4492 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4494 if (!slow_pci_heuristic(mdev) &&
4495 mlx5e_striding_rq_possible(mdev, params) &&
4496 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4497 !mlx5e_rx_is_linear_skb(mdev, params)))
4498 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4499 mlx5e_set_rq_type(mdev, params);
4500 mlx5e_init_rq_type_params(mdev, params);
4503 void mlx5e_build_rss_params(struct mlx5e_params *params)
4505 params->rss_hfunc = ETH_RSS_HASH_XOR;
4506 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4507 mlx5e_build_default_indir_rqt(params->indirection_rqt,
4508 MLX5E_INDIR_RQT_SIZE, params->num_channels);
4511 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4512 struct mlx5e_params *params,
4513 u16 max_channels, u16 mtu)
4515 u8 rx_cq_period_mode;
4517 params->sw_mtu = mtu;
4518 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4519 params->num_channels = max_channels;
4523 params->log_sq_size = is_kdump_kernel() ?
4524 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4525 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4527 /* set CQE compression */
4528 params->rx_cqe_compress_def = false;
4529 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4530 MLX5_CAP_GEN(mdev, vport_group_manager))
4531 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4533 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4534 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4537 mlx5e_build_rq_params(mdev, params);
4541 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4542 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4543 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4544 params->lro_en = !slow_pci_heuristic(mdev);
4545 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4547 /* CQ moderation params */
4548 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4549 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4550 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4551 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4552 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4553 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4554 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4557 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4560 mlx5e_build_rss_params(params);
4563 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4564 struct net_device *netdev,
4565 const struct mlx5e_profile *profile,
4568 struct mlx5e_priv *priv = netdev_priv(netdev);
4571 priv->netdev = netdev;
4572 priv->profile = profile;
4573 priv->ppriv = ppriv;
4574 priv->msglevel = MLX5E_MSG_LEVEL;
4575 priv->max_opened_tc = 1;
4577 mlx5e_build_nic_params(mdev, &priv->channels.params,
4578 profile->max_nch(mdev), netdev->mtu);
4580 mutex_init(&priv->state_lock);
4582 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4583 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4584 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4585 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4587 mlx5e_timestamp_init(priv);
4590 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4592 struct mlx5e_priv *priv = netdev_priv(netdev);
4594 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4595 if (is_zero_ether_addr(netdev->dev_addr) &&
4596 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4597 eth_hw_addr_random(netdev);
4598 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4602 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4603 static const struct switchdev_ops mlx5e_switchdev_ops = {
4604 .switchdev_port_attr_get = mlx5e_attr_get,
4608 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4610 struct mlx5e_priv *priv = netdev_priv(netdev);
4611 struct mlx5_core_dev *mdev = priv->mdev;
4615 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4617 netdev->netdev_ops = &mlx5e_netdev_ops;
4619 #ifdef CONFIG_MLX5_CORE_EN_DCB
4620 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4621 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4624 netdev->watchdog_timeo = 15 * HZ;
4626 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4628 netdev->vlan_features |= NETIF_F_SG;
4629 netdev->vlan_features |= NETIF_F_IP_CSUM;
4630 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4631 netdev->vlan_features |= NETIF_F_GRO;
4632 netdev->vlan_features |= NETIF_F_TSO;
4633 netdev->vlan_features |= NETIF_F_TSO6;
4634 netdev->vlan_features |= NETIF_F_RXCSUM;
4635 netdev->vlan_features |= NETIF_F_RXHASH;
4637 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4638 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4640 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4641 mlx5e_check_fragmented_striding_rq_cap(mdev))
4642 netdev->vlan_features |= NETIF_F_LRO;
4644 netdev->hw_features = netdev->vlan_features;
4645 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4646 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4647 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4648 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4650 if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4651 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4652 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4653 netdev->hw_enc_features |= NETIF_F_TSO;
4654 netdev->hw_enc_features |= NETIF_F_TSO6;
4655 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4658 if (mlx5_vxlan_allowed(mdev->vxlan)) {
4659 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4660 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4661 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4662 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4663 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4666 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4667 netdev->hw_features |= NETIF_F_GSO_GRE |
4668 NETIF_F_GSO_GRE_CSUM;
4669 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4670 NETIF_F_GSO_GRE_CSUM;
4671 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4672 NETIF_F_GSO_GRE_CSUM;
4675 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4676 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4677 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4678 netdev->features |= NETIF_F_GSO_UDP_L4;
4680 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4683 netdev->hw_features |= NETIF_F_RXALL;
4685 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4686 netdev->hw_features |= NETIF_F_RXFCS;
4688 netdev->features = netdev->hw_features;
4689 if (!priv->channels.params.lro_en)
4690 netdev->features &= ~NETIF_F_LRO;
4693 netdev->features &= ~NETIF_F_RXALL;
4695 if (!priv->channels.params.scatter_fcs_en)
4696 netdev->features &= ~NETIF_F_RXFCS;
4698 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4699 if (FT_CAP(flow_modify_en) &&
4700 FT_CAP(modify_root) &&
4701 FT_CAP(identified_miss_table_mode) &&
4702 FT_CAP(flow_table_modify)) {
4703 netdev->hw_features |= NETIF_F_HW_TC;
4704 #ifdef CONFIG_MLX5_EN_ARFS
4705 netdev->hw_features |= NETIF_F_NTUPLE;
4709 netdev->features |= NETIF_F_HIGHDMA;
4710 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4712 netdev->priv_flags |= IFF_UNICAST_FLT;
4714 mlx5e_set_netdev_dev_addr(netdev);
4716 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4717 if (MLX5_ESWITCH_MANAGER(mdev))
4718 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4721 mlx5e_ipsec_build_netdev(priv);
4722 mlx5e_tls_build_netdev(priv);
4725 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4727 struct mlx5_core_dev *mdev = priv->mdev;
4730 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4732 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4733 priv->q_counter = 0;
4736 err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4738 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4739 priv->drop_rq_q_counter = 0;
4743 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4745 if (priv->q_counter)
4746 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4748 if (priv->drop_rq_q_counter)
4749 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4752 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4753 struct net_device *netdev,
4754 const struct mlx5e_profile *profile,
4757 struct mlx5e_priv *priv = netdev_priv(netdev);
4760 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4761 err = mlx5e_ipsec_init(priv);
4763 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4764 err = mlx5e_tls_init(priv);
4766 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4767 mlx5e_build_nic_netdev(netdev);
4768 mlx5e_build_tc2txq_maps(priv);
4771 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4773 mlx5e_tls_cleanup(priv);
4774 mlx5e_ipsec_cleanup(priv);
4777 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4779 struct mlx5_core_dev *mdev = priv->mdev;
4782 mlx5e_create_q_counters(priv);
4784 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4786 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4787 goto err_destroy_q_counters;
4790 err = mlx5e_create_indirect_rqt(priv);
4792 goto err_close_drop_rq;
4794 err = mlx5e_create_direct_rqts(priv);
4796 goto err_destroy_indirect_rqts;
4798 err = mlx5e_create_indirect_tirs(priv, true);
4800 goto err_destroy_direct_rqts;
4802 err = mlx5e_create_direct_tirs(priv);
4804 goto err_destroy_indirect_tirs;
4806 err = mlx5e_create_flow_steering(priv);
4808 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4809 goto err_destroy_direct_tirs;
4812 err = mlx5e_tc_nic_init(priv);
4814 goto err_destroy_flow_steering;
4818 err_destroy_flow_steering:
4819 mlx5e_destroy_flow_steering(priv);
4820 err_destroy_direct_tirs:
4821 mlx5e_destroy_direct_tirs(priv);
4822 err_destroy_indirect_tirs:
4823 mlx5e_destroy_indirect_tirs(priv, true);
4824 err_destroy_direct_rqts:
4825 mlx5e_destroy_direct_rqts(priv);
4826 err_destroy_indirect_rqts:
4827 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4829 mlx5e_close_drop_rq(&priv->drop_rq);
4830 err_destroy_q_counters:
4831 mlx5e_destroy_q_counters(priv);
4835 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4837 mlx5e_tc_nic_cleanup(priv);
4838 mlx5e_destroy_flow_steering(priv);
4839 mlx5e_destroy_direct_tirs(priv);
4840 mlx5e_destroy_indirect_tirs(priv, true);
4841 mlx5e_destroy_direct_rqts(priv);
4842 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4843 mlx5e_close_drop_rq(&priv->drop_rq);
4844 mlx5e_destroy_q_counters(priv);
4847 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4851 err = mlx5e_create_tises(priv);
4853 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4857 #ifdef CONFIG_MLX5_CORE_EN_DCB
4858 mlx5e_dcbnl_initialize(priv);
4863 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4865 struct net_device *netdev = priv->netdev;
4866 struct mlx5_core_dev *mdev = priv->mdev;
4869 mlx5e_init_l2_addr(priv);
4871 /* Marking the link as currently not needed by the Driver */
4872 if (!netif_running(netdev))
4873 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4875 /* MTU range: 68 - hw-specific max */
4876 netdev->min_mtu = ETH_MIN_MTU;
4877 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4878 netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4879 mlx5e_set_dev_port_mtu(priv);
4881 mlx5_lag_add(mdev, netdev);
4883 mlx5e_enable_async_events(priv);
4885 if (MLX5_ESWITCH_MANAGER(priv->mdev))
4886 mlx5e_register_vport_reps(priv);
4888 if (netdev->reg_state != NETREG_REGISTERED)
4890 #ifdef CONFIG_MLX5_CORE_EN_DCB
4891 mlx5e_dcbnl_init_app(priv);
4894 queue_work(priv->wq, &priv->set_rx_mode_work);
4897 if (netif_running(netdev))
4899 netif_device_attach(netdev);
4903 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4905 struct mlx5_core_dev *mdev = priv->mdev;
4907 #ifdef CONFIG_MLX5_CORE_EN_DCB
4908 if (priv->netdev->reg_state == NETREG_REGISTERED)
4909 mlx5e_dcbnl_delete_app(priv);
4913 if (netif_running(priv->netdev))
4914 mlx5e_close(priv->netdev);
4915 netif_device_detach(priv->netdev);
4918 queue_work(priv->wq, &priv->set_rx_mode_work);
4920 if (MLX5_ESWITCH_MANAGER(priv->mdev))
4921 mlx5e_unregister_vport_reps(priv);
4923 mlx5e_disable_async_events(priv);
4924 mlx5_lag_remove(mdev);
4927 static const struct mlx5e_profile mlx5e_nic_profile = {
4928 .init = mlx5e_nic_init,
4929 .cleanup = mlx5e_nic_cleanup,
4930 .init_rx = mlx5e_init_nic_rx,
4931 .cleanup_rx = mlx5e_cleanup_nic_rx,
4932 .init_tx = mlx5e_init_nic_tx,
4933 .cleanup_tx = mlx5e_cleanup_nic_tx,
4934 .enable = mlx5e_nic_enable,
4935 .disable = mlx5e_nic_disable,
4936 .update_stats = mlx5e_update_ndo_stats,
4937 .max_nch = mlx5e_get_max_num_channels,
4938 .update_carrier = mlx5e_update_carrier,
4939 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4940 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4941 .max_tc = MLX5E_MAX_NUM_TC,
4944 /* mlx5e generic netdev management API (move to en_common.c) */
4946 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4947 const struct mlx5e_profile *profile,
4950 int nch = profile->max_nch(mdev);
4951 struct net_device *netdev;
4952 struct mlx5e_priv *priv;
4954 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4955 nch * profile->max_tc,
4958 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4962 #ifdef CONFIG_MLX5_EN_ARFS
4963 netdev->rx_cpu_rmap = mdev->rmap;
4966 profile->init(mdev, netdev, profile, ppriv);
4968 netif_carrier_off(netdev);
4970 priv = netdev_priv(netdev);
4972 priv->wq = create_singlethread_workqueue("mlx5e");
4974 goto err_cleanup_nic;
4979 if (profile->cleanup)
4980 profile->cleanup(priv);
4981 free_netdev(netdev);
4986 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4988 const struct mlx5e_profile *profile;
4991 profile = priv->profile;
4992 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4994 err = profile->init_tx(priv);
4998 err = profile->init_rx(priv);
5000 goto err_cleanup_tx;
5002 if (profile->enable)
5003 profile->enable(priv);
5008 profile->cleanup_tx(priv);
5014 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5016 const struct mlx5e_profile *profile = priv->profile;
5018 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5020 if (profile->disable)
5021 profile->disable(priv);
5022 flush_workqueue(priv->wq);
5024 profile->cleanup_rx(priv);
5025 profile->cleanup_tx(priv);
5026 cancel_delayed_work_sync(&priv->update_stats_work);
5029 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5031 const struct mlx5e_profile *profile = priv->profile;
5032 struct net_device *netdev = priv->netdev;
5034 destroy_workqueue(priv->wq);
5035 if (profile->cleanup)
5036 profile->cleanup(priv);
5037 free_netdev(netdev);
5040 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5041 * hardware contexts and to connect it to the current netdev.
5043 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5045 struct mlx5e_priv *priv = vpriv;
5046 struct net_device *netdev = priv->netdev;
5049 if (netif_device_present(netdev))
5052 err = mlx5e_create_mdev_resources(mdev);
5056 err = mlx5e_attach_netdev(priv);
5058 mlx5e_destroy_mdev_resources(mdev);
5065 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5067 struct mlx5e_priv *priv = vpriv;
5068 struct net_device *netdev = priv->netdev;
5070 if (!netif_device_present(netdev))
5073 mlx5e_detach_netdev(priv);
5074 mlx5e_destroy_mdev_resources(mdev);
5077 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5079 struct net_device *netdev;
5084 err = mlx5e_check_required_hca_cap(mdev);
5088 #ifdef CONFIG_MLX5_ESWITCH
5089 if (MLX5_ESWITCH_MANAGER(mdev)) {
5090 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
5092 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
5098 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
5100 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5101 goto err_free_rpriv;
5104 priv = netdev_priv(netdev);
5106 err = mlx5e_attach(mdev, priv);
5108 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5109 goto err_destroy_netdev;
5112 err = register_netdev(netdev);
5114 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5118 #ifdef CONFIG_MLX5_CORE_EN_DCB
5119 mlx5e_dcbnl_init_app(priv);
5124 mlx5e_detach(mdev, priv);
5126 mlx5e_destroy_netdev(priv);
5132 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5134 struct mlx5e_priv *priv = vpriv;
5135 void *ppriv = priv->ppriv;
5137 #ifdef CONFIG_MLX5_CORE_EN_DCB
5138 mlx5e_dcbnl_delete_app(priv);
5140 unregister_netdev(priv->netdev);
5141 mlx5e_detach(mdev, vpriv);
5142 mlx5e_destroy_netdev(priv);
5146 static void *mlx5e_get_netdev(void *vpriv)
5148 struct mlx5e_priv *priv = vpriv;
5150 return priv->netdev;
5153 static struct mlx5_interface mlx5e_interface = {
5155 .remove = mlx5e_remove,
5156 .attach = mlx5e_attach,
5157 .detach = mlx5e_detach,
5158 .event = mlx5e_async_event,
5159 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5160 .get_dev = mlx5e_get_netdev,
5163 void mlx5e_init(void)
5165 mlx5e_ipsec_build_inverse_table();
5166 mlx5e_build_ptys2ethtool_map();
5167 mlx5_register_interface(&mlx5e_interface);
5170 void mlx5e_cleanup(void)
5172 mlx5_unregister_interface(&mlx5e_interface);