drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include "eswitch.h"
  39 #include "en.h"
  40 #include "en_tc.h"
  41 #include "en_rep.h"
  42 #include "en_accel/ipsec.h"
  43 #include "en_accel/ipsec_rxtx.h"
  44 #include "accel/ipsec.h"
  45 #include "vxlan.h"
  46
  47 struct mlx5e_rq_param {
  48         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  49         struct mlx5_wq_param    wq;
  50 };
  51
  52 struct mlx5e_sq_param {
  53         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  54         struct mlx5_wq_param       wq;
  55 };
  56
  57 struct mlx5e_cq_param {
  58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  59         struct mlx5_wq_param       wq;
  60         u16                        eq_ix;
  61         u8                         cq_period_mode;
  62 };
  63
  64 struct mlx5e_channel_param {
  65         struct mlx5e_rq_param      rq;
  66         struct mlx5e_sq_param      sq;
  67         struct mlx5e_sq_param      xdp_sq;
  68         struct mlx5e_sq_param      icosq;
  69         struct mlx5e_cq_param      rx_cq;
  70         struct mlx5e_cq_param      tx_cq;
  71         struct mlx5e_cq_param      icosq_cq;
  72 };
  73
  74 static int mlx5e_get_node(struct mlx5e_priv *priv, int ix)
  75 {
  76         return pci_irq_get_node(priv->mdev->pdev, MLX5_EQ_VEC_COMP_BASE + ix);
  77 }
  78
  79 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  80 {
  81         return MLX5_CAP_GEN(mdev, striding_rq) &&
  82                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  83                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  84 }
  85
  86 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
  87                               struct mlx5e_params *params, u8 rq_type)
  88 {
  89         params->rq_wq_type = rq_type;
  90         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
  91         switch (params->rq_wq_type) {
  92         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
  93                 params->log_rq_size = is_kdump_kernel() ?
  94                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
  95                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
  96                 params->mpwqe_log_stride_sz =
  97                         MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
  98                         MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
  99                         MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
 100                 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
 101                         params->mpwqe_log_stride_sz;
 102                 break;
 103         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 104                 params->log_rq_size = is_kdump_kernel() ?
 105                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 106                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 107                 params->rq_headroom = params->xdp_prog ?
 108                         XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 109                 params->rq_headroom += NET_IP_ALIGN;
 110
 111                 /* Extra room needed for build_skb */
 112                 params->lro_wqe_sz -= params->rq_headroom +
 113                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 114         }
 115
 116         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 117                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 118                        BIT(params->log_rq_size),
 119                        BIT(params->mpwqe_log_stride_sz),
 120                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 121 }
 122
 123 static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 124 {
 125         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 126                     !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
 127                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 128                     MLX5_WQ_TYPE_LINKED_LIST;
 129         mlx5e_set_rq_type_params(mdev, params, rq_type);
 130 }
 131
 132 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 133 {
 134         struct mlx5_core_dev *mdev = priv->mdev;
 135         u8 port_state;
 136
 137         port_state = mlx5_query_vport_state(mdev,
 138                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
 139                                             0);
 140
 141         if (port_state == VPORT_STATE_UP) {
 142                 netdev_info(priv->netdev, "Link up\n");
 143                 netif_carrier_on(priv->netdev);
 144         } else {
 145                 netdev_info(priv->netdev, "Link down\n");
 146                 netif_carrier_off(priv->netdev);
 147         }
 148 }
 149
 150 static void mlx5e_update_carrier_work(struct work_struct *work)
 151 {
 152         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 153                                                update_carrier_work);
 154
 155         mutex_lock(&priv->state_lock);
 156         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 157                 if (priv->profile->update_carrier)
 158                         priv->profile->update_carrier(priv);
 159         mutex_unlock(&priv->state_lock);
 160 }
 161
 162 static void mlx5e_tx_timeout_work(struct work_struct *work)
 163 {
 164         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 165                                                tx_timeout_work);
 166         int err;
 167
 168         rtnl_lock();
 169         mutex_lock(&priv->state_lock);
 170         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 171                 goto unlock;
 172         mlx5e_close_locked(priv->netdev);
 173         err = mlx5e_open_locked(priv->netdev);
 174         if (err)
 175                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 176                            err);
 177 unlock:
 178         mutex_unlock(&priv->state_lock);
 179         rtnl_unlock();
 180 }
 181
 182 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 183 {
 184         struct mlx5e_sw_stats temp, *s = &temp;
 185         struct mlx5e_rq_stats *rq_stats;
 186         struct mlx5e_sq_stats *sq_stats;
 187         u64 tx_offload_none = 0;
 188         int i, j;
 189
 190         memset(s, 0, sizeof(*s));
 191         for (i = 0; i < priv->channels.num; i++) {
 192                 struct mlx5e_channel *c = priv->channels.c[i];
 193
 194                 rq_stats = &c->rq.stats;
 195
 196                 s->rx_packets   += rq_stats->packets;
 197                 s->rx_bytes     += rq_stats->bytes;
 198                 s->rx_lro_packets += rq_stats->lro_packets;
 199                 s->rx_lro_bytes += rq_stats->lro_bytes;
 200                 s->rx_csum_none += rq_stats->csum_none;
 201                 s->rx_csum_complete += rq_stats->csum_complete;
 202                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 203                 s->rx_xdp_drop += rq_stats->xdp_drop;
 204                 s->rx_xdp_tx += rq_stats->xdp_tx;
 205                 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
 206                 s->rx_wqe_err   += rq_stats->wqe_err;
 207                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 208                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 209                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 210                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 211                 s->rx_page_reuse  += rq_stats->page_reuse;
 212                 s->rx_cache_reuse += rq_stats->cache_reuse;
 213                 s->rx_cache_full  += rq_stats->cache_full;
 214                 s->rx_cache_empty += rq_stats->cache_empty;
 215                 s->rx_cache_busy  += rq_stats->cache_busy;
 216
 217                 for (j = 0; j < priv->channels.params.num_tc; j++) {
 218                         sq_stats = &c->sq[j].stats;
 219
 220                         s->tx_packets           += sq_stats->packets;
 221                         s->tx_bytes             += sq_stats->bytes;
 222                         s->tx_tso_packets       += sq_stats->tso_packets;
 223                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 224                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 225                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 226                         s->tx_queue_stopped     += sq_stats->stopped;
 227                         s->tx_queue_wake        += sq_stats->wake;
 228                         s->tx_queue_dropped     += sq_stats->dropped;
 229                         s->tx_xmit_more         += sq_stats->xmit_more;
 230                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 231                         tx_offload_none         += sq_stats->csum_none;
 232                 }
 233         }
 234
 235         /* Update calculated offload counters */
 236         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 237         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 238
 239         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 240                                 priv->stats.pport.phy_counters,
 241                                 counter_set.phys_layer_cntrs.link_down_events);
 242         memcpy(&priv->stats.sw, s, sizeof(*s));
 243 }
 244
 245 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 246 {
 247         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 248         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 249         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 250         struct mlx5_core_dev *mdev = priv->mdev;
 251
 252         MLX5_SET(query_vport_counter_in, in, opcode,
 253                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 254         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 255         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 256
 257         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 258 }
 259
 260 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
 261 {
 262         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 263         struct mlx5_core_dev *mdev = priv->mdev;
 264         u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
 265         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 266         int prio;
 267         void *out;
 268
 269         MLX5_SET(ppcnt_reg, in, local_port, 1);
 270
 271         out = pstats->IEEE_802_3_counters;
 272         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 273         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 274
 275         if (!full)
 276                 return;
 277
 278         out = pstats->RFC_2863_counters;
 279         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 280         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 281
 282         out = pstats->RFC_2819_counters;
 283         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 284         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 285
 286         out = pstats->phy_counters;
 287         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 288         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 289
 290         if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
 291                 out = pstats->phy_statistical_counters;
 292                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
 293                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 294         }
 295
 296         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 297         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 298                 out = pstats->per_prio_counters[prio];
 299                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 300                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 301                                      MLX5_REG_PPCNT, 0, 0);
 302         }
 303 }
 304
 305 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 306 {
 307         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 308         u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
 309         int err;
 310
 311         if (!priv->q_counter)
 312                 return;
 313
 314         err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
 315         if (err)
 316                 return;
 317
 318         qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
 319 }
 320
 321 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 322 {
 323         struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
 324         struct mlx5_core_dev *mdev = priv->mdev;
 325         u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
 326         int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 327         void *out;
 328
 329         if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
 330                 return;
 331
 332         out = pcie_stats->pcie_perf_counters;
 333         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 334         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 335 }
 336
 337 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
 338 {
 339         if (full) {
 340                 mlx5e_update_pcie_counters(priv);
 341                 mlx5e_ipsec_update_stats(priv);
 342         }
 343         mlx5e_update_pport_counters(priv, full);
 344         mlx5e_update_vport_counters(priv);
 345         mlx5e_update_q_counter(priv);
 346         mlx5e_update_sw_counters(priv);
 347 }
 348
 349 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 350 {
 351         mlx5e_update_stats(priv, false);
 352 }
 353
 354 void mlx5e_update_stats_work(struct work_struct *work)
 355 {
 356         struct delayed_work *dwork = to_delayed_work(work);
 357         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 358                                                update_stats_work);
 359         mutex_lock(&priv->state_lock);
 360         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 361                 priv->profile->update_stats(priv);
 362                 queue_delayed_work(priv->wq, dwork,
 363                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 364         }
 365         mutex_unlock(&priv->state_lock);
 366 }
 367
 368 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 369                               enum mlx5_dev_event event, unsigned long param)
 370 {
 371         struct mlx5e_priv *priv = vpriv;
 372         struct ptp_clock_event ptp_event;
 373         struct mlx5_eqe *eqe = NULL;
 374
 375         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 376                 return;
 377
 378         switch (event) {
 379         case MLX5_DEV_EVENT_PORT_UP:
 380         case MLX5_DEV_EVENT_PORT_DOWN:
 381                 queue_work(priv->wq, &priv->update_carrier_work);
 382                 break;
 383         case MLX5_DEV_EVENT_PPS:
 384                 eqe = (struct mlx5_eqe *)param;
 385                 ptp_event.type = PTP_CLOCK_EXTTS;
 386                 ptp_event.index = eqe->data.pps.pin;
 387                 ptp_event.timestamp =
 388                         timecounter_cyc2time(&priv->tstamp.clock,
 389                                              be64_to_cpu(eqe->data.pps.time_stamp));
 390                 mlx5e_pps_event_handler(vpriv, &ptp_event);
 391                 break;
 392         default:
 393                 break;
 394         }
 395 }
 396
 397 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 398 {
 399         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 400 }
 401
 402 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 403 {
 404         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 405         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 406 }
 407
 408 static inline int mlx5e_get_wqe_mtt_sz(void)
 409 {
 410         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 411          * To avoid copying garbage after the mtt array, we allocate
 412          * a little more.
 413          */
 414         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 415                      MLX5_UMR_MTT_ALIGNMENT);
 416 }
 417
 418 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 419                                        struct mlx5e_icosq *sq,
 420                                        struct mlx5e_umr_wqe *wqe,
 421                                        u16 ix)
 422 {
 423         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 424         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 425         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 426         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 427         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 428         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 429
 430         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 431                                       ds_cnt);
 432         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 433         cseg->imm       = rq->mkey_be;
 434
 435         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 436         ucseg->xlt_octowords =
 437                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 438         ucseg->bsf_octowords =
 439                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 440         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 441
 442         dseg->lkey = sq->mkey_be;
 443         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 444 }
 445
 446 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 447                                      struct mlx5e_channel *c)
 448 {
 449         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 450         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 451         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
 452         int node = mlx5e_get_node(c->priv, c->ix);
 453         int i;
 454
 455         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 456                                         GFP_KERNEL, node);
 457         if (!rq->mpwqe.info)
 458                 goto err_out;
 459
 460         /* We allocate more than mtt_sz as we will align the pointer */
 461         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz,
 462                                         GFP_KERNEL, node);
 463         if (unlikely(!rq->mpwqe.mtt_no_align))
 464                 goto err_free_wqe_info;
 465
 466         for (i = 0; i < wq_sz; i++) {
 467                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 468
 469                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
 470                                         MLX5_UMR_ALIGN);
 471                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
 472                                                   PCI_DMA_TODEVICE);
 473                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
 474                         goto err_unmap_mtts;
 475
 476                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 477         }
 478
 479         return 0;
 480
 481 err_unmap_mtts:
 482         while (--i >= 0) {
 483                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 484
 485                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
 486                                  PCI_DMA_TODEVICE);
 487         }
 488         kfree(rq->mpwqe.mtt_no_align);
 489 err_free_wqe_info:
 490         kfree(rq->mpwqe.info);
 491
 492 err_out:
 493         return -ENOMEM;
 494 }
 495
 496 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
 497 {
 498         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 499         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 500         int i;
 501
 502         for (i = 0; i < wq_sz; i++) {
 503                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 504
 505                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
 506                                  PCI_DMA_TODEVICE);
 507         }
 508         kfree(rq->mpwqe.mtt_no_align);
 509         kfree(rq->mpwqe.info);
 510 }
 511
 512 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 513                                  u64 npages, u8 page_shift,
 514                                  struct mlx5_core_mkey *umr_mkey)
 515 {
 516         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 517         void *mkc;
 518         u32 *in;
 519         int err;
 520
 521         if (!MLX5E_VALID_NUM_MTTS(npages))
 522                 return -EINVAL;
 523
 524         in = kvzalloc(inlen, GFP_KERNEL);
 525         if (!in)
 526                 return -ENOMEM;
 527
 528         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 529
 530         MLX5_SET(mkc, mkc, free, 1);
 531         MLX5_SET(mkc, mkc, umr_en, 1);
 532         MLX5_SET(mkc, mkc, lw, 1);
 533         MLX5_SET(mkc, mkc, lr, 1);
 534         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
 535
 536         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 537         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 538         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 539         MLX5_SET(mkc, mkc, translations_octword_size,
 540                  MLX5_MTT_OCTW(npages));
 541         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 542
 543         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 544
 545         kvfree(in);
 546         return err;
 547 }
 548
 549 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 550 {
 551         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
 552
 553         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 554 }
 555
 556 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 557                           struct mlx5e_params *params,
 558                           struct mlx5e_rq_param *rqp,
 559                           struct mlx5e_rq *rq)
 560 {
 561         struct mlx5_core_dev *mdev = c->mdev;
 562         void *rqc = rqp->rqc;
 563         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 564         u32 byte_count;
 565         int npages;
 566         int wq_sz;
 567         int err;
 568         int i;
 569
 570         rqp->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
 571
 572         err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
 573                                 &rq->wq_ctrl);
 574         if (err)
 575                 return err;
 576
 577         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 578
 579         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 580
 581         rq->wq_type = params->rq_wq_type;
 582         rq->pdev    = c->pdev;
 583         rq->netdev  = c->netdev;
 584         rq->tstamp  = c->tstamp;
 585         rq->channel = c;
 586         rq->ix      = c->ix;
 587         rq->mdev    = mdev;
 588
 589         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 590         if (IS_ERR(rq->xdp_prog)) {
 591                 err = PTR_ERR(rq->xdp_prog);
 592                 rq->xdp_prog = NULL;
 593                 goto err_rq_wq_destroy;
 594         }
 595
 596         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 597         rq->rx_headroom = params->rq_headroom;
 598
 599         switch (rq->wq_type) {
 600         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 601
 602                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 603                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 604
 605                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 606 #ifdef CONFIG_MLX5_EN_IPSEC
 607                 if (MLX5_IPSEC_DEV(mdev)) {
 608                         err = -EINVAL;
 609                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 610                         goto err_rq_wq_destroy;
 611                 }
 612 #endif
 613                 if (!rq->handle_rx_cqe) {
 614                         err = -EINVAL;
 615                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 616                         goto err_rq_wq_destroy;
 617                 }
 618
 619                 rq->mpwqe_stride_sz = BIT(params->mpwqe_log_stride_sz);
 620                 rq->mpwqe_num_strides = BIT(params->mpwqe_log_num_strides);
 621
 622                 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 623                 byte_count = rq->buff.wqe_sz;
 624
 625                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 626                 if (err)
 627                         goto err_rq_wq_destroy;
 628                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 629
 630                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 631                 if (err)
 632                         goto err_destroy_umr_mkey;
 633                 break;
 634         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 635                 rq->wqe.frag_info =
 636                         kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
 637                                      GFP_KERNEL,
 638                                      mlx5e_get_node(c->priv, c->ix));
 639                 if (!rq->wqe.frag_info) {
 640                         err = -ENOMEM;
 641                         goto err_rq_wq_destroy;
 642                 }
 643                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 644                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 645
 646 #ifdef CONFIG_MLX5_EN_IPSEC
 647                 if (c->priv->ipsec)
 648                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 649                 else
 650 #endif
 651                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 652                 if (!rq->handle_rx_cqe) {
 653                         kfree(rq->wqe.frag_info);
 654                         err = -EINVAL;
 655                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 656                         goto err_rq_wq_destroy;
 657                 }
 658
 659                 rq->buff.wqe_sz = params->lro_en  ?
 660                                 params->lro_wqe_sz :
 661                                 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
 662 #ifdef CONFIG_MLX5_EN_IPSEC
 663                 if (MLX5_IPSEC_DEV(mdev))
 664                         rq->buff.wqe_sz += MLX5E_METADATA_ETHER_LEN;
 665 #endif
 666                 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
 667                 byte_count = rq->buff.wqe_sz;
 668
 669                 /* calc the required page order */
 670                 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->rx_headroom + byte_count);
 671                 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
 672                 rq->buff.page_order = order_base_2(npages);
 673
 674                 byte_count |= MLX5_HW_START_PADDING;
 675                 rq->mkey_be = c->mkey_be;
 676         }
 677
 678         for (i = 0; i < wq_sz; i++) {
 679                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 680
 681                 wqe->data.byte_count = cpu_to_be32(byte_count);
 682                 wqe->data.lkey = rq->mkey_be;
 683         }
 684
 685         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 686         rq->am.mode = params->rx_cq_period_mode;
 687         rq->page_cache.head = 0;
 688         rq->page_cache.tail = 0;
 689
 690         return 0;
 691
 692 err_destroy_umr_mkey:
 693         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 694
 695 err_rq_wq_destroy:
 696         if (rq->xdp_prog)
 697                 bpf_prog_put(rq->xdp_prog);
 698         mlx5_wq_destroy(&rq->wq_ctrl);
 699
 700         return err;
 701 }
 702
 703 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 704 {
 705         int i;
 706
 707         if (rq->xdp_prog)
 708                 bpf_prog_put(rq->xdp_prog);
 709
 710         switch (rq->wq_type) {
 711         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 712                 mlx5e_rq_free_mpwqe_info(rq);
 713                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 714                 break;
 715         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 716                 kfree(rq->wqe.frag_info);
 717         }
 718
 719         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 720              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 721                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 722
 723                 mlx5e_page_release(rq, dma_info, false);
 724         }
 725         mlx5_wq_destroy(&rq->wq_ctrl);
 726 }
 727
 728 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 729                            struct mlx5e_rq_param *param)
 730 {
 731         struct mlx5_core_dev *mdev = rq->mdev;
 732
 733         void *in;
 734         void *rqc;
 735         void *wq;
 736         int inlen;
 737         int err;
 738
 739         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 740                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 741         in = kvzalloc(inlen, GFP_KERNEL);
 742         if (!in)
 743                 return -ENOMEM;
 744
 745         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 746         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 747
 748         memcpy(rqc, param->rqc, sizeof(param->rqc));
 749
 750         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 751         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 752         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 753                                                 MLX5_ADAPTER_PAGE_SHIFT);
 754         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 755
 756         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 757                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 758
 759         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 760
 761         kvfree(in);
 762
 763         return err;
 764 }
 765
 766 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 767                                  int next_state)
 768 {
 769         struct mlx5e_channel *c = rq->channel;
 770         struct mlx5_core_dev *mdev = c->mdev;
 771
 772         void *in;
 773         void *rqc;
 774         int inlen;
 775         int err;
 776
 777         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 778         in = kvzalloc(inlen, GFP_KERNEL);
 779         if (!in)
 780                 return -ENOMEM;
 781
 782         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 783
 784         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 785         MLX5_SET(rqc, rqc, state, next_state);
 786
 787         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 788
 789         kvfree(in);
 790
 791         return err;
 792 }
 793
 794 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 795 {
 796         struct mlx5e_channel *c = rq->channel;
 797         struct mlx5e_priv *priv = c->priv;
 798         struct mlx5_core_dev *mdev = priv->mdev;
 799
 800         void *in;
 801         void *rqc;
 802         int inlen;
 803         int err;
 804
 805         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 806         in = kvzalloc(inlen, GFP_KERNEL);
 807         if (!in)
 808                 return -ENOMEM;
 809
 810         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 811
 812         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 813         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 814                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 815         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 816         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 817
 818         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 819
 820         kvfree(in);
 821
 822         return err;
 823 }
 824
 825 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 826 {
 827         struct mlx5e_channel *c = rq->channel;
 828         struct mlx5_core_dev *mdev = c->mdev;
 829         void *in;
 830         void *rqc;
 831         int inlen;
 832         int err;
 833
 834         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 835         in = kvzalloc(inlen, GFP_KERNEL);
 836         if (!in)
 837                 return -ENOMEM;
 838
 839         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 840
 841         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 842         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 843                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 844         MLX5_SET(rqc, rqc, vsd, vsd);
 845         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 846
 847         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 848
 849         kvfree(in);
 850
 851         return err;
 852 }
 853
 854 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 855 {
 856         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 857 }
 858
 859 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 860 {
 861         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 862         struct mlx5e_channel *c = rq->channel;
 863
 864         struct mlx5_wq_ll *wq = &rq->wq;
 865         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
 866
 867         while (time_before(jiffies, exp_time)) {
 868                 if (wq->cur_sz >= min_wqes)
 869                         return 0;
 870
 871                 msleep(20);
 872         }
 873
 874         netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 875                     rq->rqn, wq->cur_sz, min_wqes);
 876         return -ETIMEDOUT;
 877 }
 878
 879 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 880 {
 881         struct mlx5_wq_ll *wq = &rq->wq;
 882         struct mlx5e_rx_wqe *wqe;
 883         __be16 wqe_ix_be;
 884         u16 wqe_ix;
 885
 886         /* UMR WQE (if in progress) is always at wq->head */
 887         if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 888                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 889
 890         while (!mlx5_wq_ll_is_empty(wq)) {
 891                 wqe_ix_be = *wq->tail_next;
 892                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 893                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 894                 rq->dealloc_wqe(rq, wqe_ix);
 895                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 896                                &wqe->next.next_wqe_index);
 897         }
 898
 899         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
 900                 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
 901                  * but yet to be re-posted.
 902                  */
 903                 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 904
 905                 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
 906                         rq->dealloc_wqe(rq, wqe_ix);
 907         }
 908 }
 909
 910 static int mlx5e_open_rq(struct mlx5e_channel *c,
 911                          struct mlx5e_params *params,
 912                          struct mlx5e_rq_param *param,
 913                          struct mlx5e_rq *rq)
 914 {
 915         int err;
 916
 917         err = mlx5e_alloc_rq(c, params, param, rq);
 918         if (err)
 919                 return err;
 920
 921         err = mlx5e_create_rq(rq, param);
 922         if (err)
 923                 goto err_free_rq;
 924
 925         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 926         if (err)
 927                 goto err_destroy_rq;
 928
 929         if (params->rx_am_enabled)
 930                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 931
 932         return 0;
 933
 934 err_destroy_rq:
 935         mlx5e_destroy_rq(rq);
 936 err_free_rq:
 937         mlx5e_free_rq(rq);
 938
 939         return err;
 940 }
 941
 942 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 943 {
 944         struct mlx5e_icosq *sq = &rq->channel->icosq;
 945         u16 pi = sq->pc & sq->wq.sz_m1;
 946         struct mlx5e_tx_wqe *nopwqe;
 947
 948         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 949         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 950         sq->db.ico_wqe[pi].num_wqebbs = 1;
 951         nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
 952         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 953 }
 954
 955 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 956 {
 957         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 958         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 959 }
 960
 961 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 962 {
 963         cancel_work_sync(&rq->am.work);
 964         mlx5e_destroy_rq(rq);
 965         mlx5e_free_rx_descs(rq);
 966         mlx5e_free_rq(rq);
 967 }
 968
 969 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 970 {
 971         kfree(sq->db.di);
 972 }
 973
 974 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 975 {
 976         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 977
 978         sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
 979                                      GFP_KERNEL, numa);
 980         if (!sq->db.di) {
 981                 mlx5e_free_xdpsq_db(sq);
 982                 return -ENOMEM;
 983         }
 984
 985         return 0;
 986 }
 987
 988 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 989                              struct mlx5e_params *params,
 990                              struct mlx5e_sq_param *param,
 991                              struct mlx5e_xdpsq *sq)
 992 {
 993         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 994         struct mlx5_core_dev *mdev = c->mdev;
 995         int err;
 996
 997         sq->pdev      = c->pdev;
 998         sq->mkey_be   = c->mkey_be;
 999         sq->channel   = c;
1000         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1001         sq->min_inline_mode = params->tx_min_inline_mode;
1002
1003         param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1004         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1005         if (err)
1006                 return err;
1007         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1008
1009         err = mlx5e_alloc_xdpsq_db(sq, mlx5e_get_node(c->priv, c->ix));
1010         if (err)
1011                 goto err_sq_wq_destroy;
1012
1013         return 0;
1014
1015 err_sq_wq_destroy:
1016         mlx5_wq_destroy(&sq->wq_ctrl);
1017
1018         return err;
1019 }
1020
1021 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1022 {
1023         mlx5e_free_xdpsq_db(sq);
1024         mlx5_wq_destroy(&sq->wq_ctrl);
1025 }
1026
1027 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1028 {
1029         kfree(sq->db.ico_wqe);
1030 }
1031
1032 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1033 {
1034         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1035
1036         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1037                                       GFP_KERNEL, numa);
1038         if (!sq->db.ico_wqe)
1039                 return -ENOMEM;
1040
1041         return 0;
1042 }
1043
1044 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1045                              struct mlx5e_sq_param *param,
1046                              struct mlx5e_icosq *sq)
1047 {
1048         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1049         struct mlx5_core_dev *mdev = c->mdev;
1050         int err;
1051
1052         sq->pdev      = c->pdev;
1053         sq->mkey_be   = c->mkey_be;
1054         sq->channel   = c;
1055         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1056
1057         param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1058         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1059         if (err)
1060                 return err;
1061         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1062
1063         err = mlx5e_alloc_icosq_db(sq, mlx5e_get_node(c->priv, c->ix));
1064         if (err)
1065                 goto err_sq_wq_destroy;
1066
1067         sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
1068
1069         return 0;
1070
1071 err_sq_wq_destroy:
1072         mlx5_wq_destroy(&sq->wq_ctrl);
1073
1074         return err;
1075 }
1076
1077 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1078 {
1079         mlx5e_free_icosq_db(sq);
1080         mlx5_wq_destroy(&sq->wq_ctrl);
1081 }
1082
1083 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1084 {
1085         kfree(sq->db.wqe_info);
1086         kfree(sq->db.dma_fifo);
1087 }
1088
1089 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1090 {
1091         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1092         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1093
1094         sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1095                                            GFP_KERNEL, numa);
1096         sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1097                                            GFP_KERNEL, numa);
1098         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1099                 mlx5e_free_txqsq_db(sq);
1100                 return -ENOMEM;
1101         }
1102
1103         sq->dma_fifo_mask = df_sz - 1;
1104
1105         return 0;
1106 }
1107
1108 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1109                              int txq_ix,
1110                              struct mlx5e_params *params,
1111                              struct mlx5e_sq_param *param,
1112                              struct mlx5e_txqsq *sq)
1113 {
1114         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1115         struct mlx5_core_dev *mdev = c->mdev;
1116         int err;
1117
1118         sq->pdev      = c->pdev;
1119         sq->tstamp    = c->tstamp;
1120         sq->mkey_be   = c->mkey_be;
1121         sq->channel   = c;
1122         sq->txq_ix    = txq_ix;
1123         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1124         sq->max_inline      = params->tx_max_inline;
1125         sq->min_inline_mode = params->tx_min_inline_mode;
1126         if (MLX5_IPSEC_DEV(c->priv->mdev))
1127                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1128
1129         param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1130         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1131         if (err)
1132                 return err;
1133         sq->wq.db    = &sq->wq.db[MLX5_SND_DBR];
1134
1135         err = mlx5e_alloc_txqsq_db(sq, mlx5e_get_node(c->priv, c->ix));
1136         if (err)
1137                 goto err_sq_wq_destroy;
1138
1139         sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1140
1141         return 0;
1142
1143 err_sq_wq_destroy:
1144         mlx5_wq_destroy(&sq->wq_ctrl);
1145
1146         return err;
1147 }
1148
1149 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1150 {
1151         mlx5e_free_txqsq_db(sq);
1152         mlx5_wq_destroy(&sq->wq_ctrl);
1153 }
1154
1155 struct mlx5e_create_sq_param {
1156         struct mlx5_wq_ctrl        *wq_ctrl;
1157         u32                         cqn;
1158         u32                         tisn;
1159         u8                          tis_lst_sz;
1160         u8                          min_inline_mode;
1161 };
1162
1163 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1164                            struct mlx5e_sq_param *param,
1165                            struct mlx5e_create_sq_param *csp,
1166                            u32 *sqn)
1167 {
1168         void *in;
1169         void *sqc;
1170         void *wq;
1171         int inlen;
1172         int err;
1173
1174         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1175                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1176         in = kvzalloc(inlen, GFP_KERNEL);
1177         if (!in)
1178                 return -ENOMEM;
1179
1180         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1181         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1182
1183         memcpy(sqc, param->sqc, sizeof(param->sqc));
1184         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1185         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1186         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1187
1188         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1189                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1190
1191         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1192
1193         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1194         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1195         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1196                                           MLX5_ADAPTER_PAGE_SHIFT);
1197         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1198
1199         mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1200
1201         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1202
1203         kvfree(in);
1204
1205         return err;
1206 }
1207
1208 struct mlx5e_modify_sq_param {
1209         int curr_state;
1210         int next_state;
1211         bool rl_update;
1212         int rl_index;
1213 };
1214
1215 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1216                            struct mlx5e_modify_sq_param *p)
1217 {
1218         void *in;
1219         void *sqc;
1220         int inlen;
1221         int err;
1222
1223         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1224         in = kvzalloc(inlen, GFP_KERNEL);
1225         if (!in)
1226                 return -ENOMEM;
1227
1228         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1229
1230         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1231         MLX5_SET(sqc, sqc, state, p->next_state);
1232         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1233                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1234                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1235         }
1236
1237         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1238
1239         kvfree(in);
1240
1241         return err;
1242 }
1243
1244 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1245 {
1246         mlx5_core_destroy_sq(mdev, sqn);
1247 }
1248
1249 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1250                                struct mlx5e_sq_param *param,
1251                                struct mlx5e_create_sq_param *csp,
1252                                u32 *sqn)
1253 {
1254         struct mlx5e_modify_sq_param msp = {0};
1255         int err;
1256
1257         err = mlx5e_create_sq(mdev, param, csp, sqn);
1258         if (err)
1259                 return err;
1260
1261         msp.curr_state = MLX5_SQC_STATE_RST;
1262         msp.next_state = MLX5_SQC_STATE_RDY;
1263         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1264         if (err)
1265                 mlx5e_destroy_sq(mdev, *sqn);
1266
1267         return err;
1268 }
1269
1270 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1271                                 struct mlx5e_txqsq *sq, u32 rate);
1272
1273 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1274                             u32 tisn,
1275                             int txq_ix,
1276                             struct mlx5e_params *params,
1277                             struct mlx5e_sq_param *param,
1278                             struct mlx5e_txqsq *sq)
1279 {
1280         struct mlx5e_create_sq_param csp = {};
1281         u32 tx_rate;
1282         int err;
1283
1284         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1285         if (err)
1286                 return err;
1287
1288         csp.tisn            = tisn;
1289         csp.tis_lst_sz      = 1;
1290         csp.cqn             = sq->cq.mcq.cqn;
1291         csp.wq_ctrl         = &sq->wq_ctrl;
1292         csp.min_inline_mode = sq->min_inline_mode;
1293         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1294         if (err)
1295                 goto err_free_txqsq;
1296
1297         tx_rate = c->priv->tx_rates[sq->txq_ix];
1298         if (tx_rate)
1299                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1300
1301         return 0;
1302
1303 err_free_txqsq:
1304         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1305         mlx5e_free_txqsq(sq);
1306
1307         return err;
1308 }
1309
1310 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1311 {
1312         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1313         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1314         netdev_tx_reset_queue(sq->txq);
1315         netif_tx_start_queue(sq->txq);
1316 }
1317
1318 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1319 {
1320         __netif_tx_lock_bh(txq);
1321         netif_tx_stop_queue(txq);
1322         __netif_tx_unlock_bh(txq);
1323 }
1324
1325 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1326 {
1327         struct mlx5e_channel *c = sq->channel;
1328
1329         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1330         /* prevent netif_tx_wake_queue */
1331         napi_synchronize(&c->napi);
1332
1333         netif_tx_disable_queue(sq->txq);
1334
1335         /* last doorbell out, godspeed .. */
1336         if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1337                 struct mlx5e_tx_wqe *nop;
1338
1339                 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1340                 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1341                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1342         }
1343 }
1344
1345 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1346 {
1347         struct mlx5e_channel *c = sq->channel;
1348         struct mlx5_core_dev *mdev = c->mdev;
1349
1350         mlx5e_destroy_sq(mdev, sq->sqn);
1351         if (sq->rate_limit)
1352                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1353         mlx5e_free_txqsq_descs(sq);
1354         mlx5e_free_txqsq(sq);
1355 }
1356
1357 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1358                             struct mlx5e_params *params,
1359                             struct mlx5e_sq_param *param,
1360                             struct mlx5e_icosq *sq)
1361 {
1362         struct mlx5e_create_sq_param csp = {};
1363         int err;
1364
1365         err = mlx5e_alloc_icosq(c, param, sq);
1366         if (err)
1367                 return err;
1368
1369         csp.cqn             = sq->cq.mcq.cqn;
1370         csp.wq_ctrl         = &sq->wq_ctrl;
1371         csp.min_inline_mode = params->tx_min_inline_mode;
1372         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1373         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1374         if (err)
1375                 goto err_free_icosq;
1376
1377         return 0;
1378
1379 err_free_icosq:
1380         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1381         mlx5e_free_icosq(sq);
1382
1383         return err;
1384 }
1385
1386 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1387 {
1388         struct mlx5e_channel *c = sq->channel;
1389
1390         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1391         napi_synchronize(&c->napi);
1392
1393         mlx5e_destroy_sq(c->mdev, sq->sqn);
1394         mlx5e_free_icosq(sq);
1395 }
1396
1397 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1398                             struct mlx5e_params *params,
1399                             struct mlx5e_sq_param *param,
1400                             struct mlx5e_xdpsq *sq)
1401 {
1402         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1403         struct mlx5e_create_sq_param csp = {};
1404         unsigned int inline_hdr_sz = 0;
1405         int err;
1406         int i;
1407
1408         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1409         if (err)
1410                 return err;
1411
1412         csp.tis_lst_sz      = 1;
1413         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1414         csp.cqn             = sq->cq.mcq.cqn;
1415         csp.wq_ctrl         = &sq->wq_ctrl;
1416         csp.min_inline_mode = sq->min_inline_mode;
1417         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1418         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1419         if (err)
1420                 goto err_free_xdpsq;
1421
1422         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1423                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1424                 ds_cnt++;
1425         }
1426
1427         /* Pre initialize fixed WQE fields */
1428         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1429                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1430                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1431                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1432                 struct mlx5_wqe_data_seg *dseg;
1433
1434                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1435                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1436
1437                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1438                 dseg->lkey = sq->mkey_be;
1439         }
1440
1441         return 0;
1442
1443 err_free_xdpsq:
1444         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1445         mlx5e_free_xdpsq(sq);
1446
1447         return err;
1448 }
1449
1450 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1451 {
1452         struct mlx5e_channel *c = sq->channel;
1453
1454         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1455         napi_synchronize(&c->napi);
1456
1457         mlx5e_destroy_sq(c->mdev, sq->sqn);
1458         mlx5e_free_xdpsq_descs(sq);
1459         mlx5e_free_xdpsq(sq);
1460 }
1461
1462 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1463                                  struct mlx5e_cq_param *param,
1464                                  struct mlx5e_cq *cq)
1465 {
1466         struct mlx5_core_cq *mcq = &cq->mcq;
1467         int eqn_not_used;
1468         unsigned int irqn;
1469         int err;
1470         u32 i;
1471
1472         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1473                                &cq->wq_ctrl);
1474         if (err)
1475                 return err;
1476
1477         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1478
1479         mcq->cqe_sz     = 64;
1480         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1481         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1482         *mcq->set_ci_db = 0;
1483         *mcq->arm_db    = 0;
1484         mcq->vector     = param->eq_ix;
1485         mcq->comp       = mlx5e_completion_event;
1486         mcq->event      = mlx5e_cq_error_event;
1487         mcq->irqn       = irqn;
1488
1489         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1490                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1491
1492                 cqe->op_own = 0xf1;
1493         }
1494
1495         cq->mdev = mdev;
1496
1497         return 0;
1498 }
1499
1500 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1501                           struct mlx5e_cq_param *param,
1502                           struct mlx5e_cq *cq)
1503 {
1504         struct mlx5_core_dev *mdev = c->priv->mdev;
1505         int err;
1506
1507         param->wq.buf_numa_node = mlx5e_get_node(c->priv, c->ix);
1508         param->wq.db_numa_node  = mlx5e_get_node(c->priv, c->ix);
1509         param->eq_ix   = c->ix;
1510
1511         err = mlx5e_alloc_cq_common(mdev, param, cq);
1512
1513         cq->napi    = &c->napi;
1514         cq->channel = c;
1515
1516         return err;
1517 }
1518
1519 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1520 {
1521         mlx5_cqwq_destroy(&cq->wq_ctrl);
1522 }
1523
1524 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1525 {
1526         struct mlx5_core_dev *mdev = cq->mdev;
1527         struct mlx5_core_cq *mcq = &cq->mcq;
1528
1529         void *in;
1530         void *cqc;
1531         int inlen;
1532         unsigned int irqn_not_used;
1533         int eqn;
1534         int err;
1535
1536         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1537                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1538         in = kvzalloc(inlen, GFP_KERNEL);
1539         if (!in)
1540                 return -ENOMEM;
1541
1542         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1543
1544         memcpy(cqc, param->cqc, sizeof(param->cqc));
1545
1546         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1547                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1548
1549         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1550
1551         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1552         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1553         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1554         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1555                                             MLX5_ADAPTER_PAGE_SHIFT);
1556         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1557
1558         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1559
1560         kvfree(in);
1561
1562         if (err)
1563                 return err;
1564
1565         mlx5e_cq_arm(cq);
1566
1567         return 0;
1568 }
1569
1570 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1571 {
1572         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1573 }
1574
1575 static int mlx5e_open_cq(struct mlx5e_channel *c,
1576                          struct mlx5e_cq_moder moder,
1577                          struct mlx5e_cq_param *param,
1578                          struct mlx5e_cq *cq)
1579 {
1580         struct mlx5_core_dev *mdev = c->mdev;
1581         int err;
1582
1583         err = mlx5e_alloc_cq(c, param, cq);
1584         if (err)
1585                 return err;
1586
1587         err = mlx5e_create_cq(cq, param);
1588         if (err)
1589                 goto err_free_cq;
1590
1591         if (MLX5_CAP_GEN(mdev, cq_moderation))
1592                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1593         return 0;
1594
1595 err_free_cq:
1596         mlx5e_free_cq(cq);
1597
1598         return err;
1599 }
1600
1601 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1602 {
1603         mlx5e_destroy_cq(cq);
1604         mlx5e_free_cq(cq);
1605 }
1606
1607 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1608                              struct mlx5e_params *params,
1609                              struct mlx5e_channel_param *cparam)
1610 {
1611         int err;
1612         int tc;
1613
1614         for (tc = 0; tc < c->num_tc; tc++) {
1615                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1616                                     &cparam->tx_cq, &c->sq[tc].cq);
1617                 if (err)
1618                         goto err_close_tx_cqs;
1619         }
1620
1621         return 0;
1622
1623 err_close_tx_cqs:
1624         for (tc--; tc >= 0; tc--)
1625                 mlx5e_close_cq(&c->sq[tc].cq);
1626
1627         return err;
1628 }
1629
1630 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1631 {
1632         int tc;
1633
1634         for (tc = 0; tc < c->num_tc; tc++)
1635                 mlx5e_close_cq(&c->sq[tc].cq);
1636 }
1637
1638 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1639                           struct mlx5e_params *params,
1640                           struct mlx5e_channel_param *cparam)
1641 {
1642         int err;
1643         int tc;
1644
1645         for (tc = 0; tc < params->num_tc; tc++) {
1646                 int txq_ix = c->ix + tc * params->num_channels;
1647
1648                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1649                                        params, &cparam->sq, &c->sq[tc]);
1650                 if (err)
1651                         goto err_close_sqs;
1652         }
1653
1654         return 0;
1655
1656 err_close_sqs:
1657         for (tc--; tc >= 0; tc--)
1658                 mlx5e_close_txqsq(&c->sq[tc]);
1659
1660         return err;
1661 }
1662
1663 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1664 {
1665         int tc;
1666
1667         for (tc = 0; tc < c->num_tc; tc++)
1668                 mlx5e_close_txqsq(&c->sq[tc]);
1669 }
1670
1671 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1672                                 struct mlx5e_txqsq *sq, u32 rate)
1673 {
1674         struct mlx5e_priv *priv = netdev_priv(dev);
1675         struct mlx5_core_dev *mdev = priv->mdev;
1676         struct mlx5e_modify_sq_param msp = {0};
1677         u16 rl_index = 0;
1678         int err;
1679
1680         if (rate == sq->rate_limit)
1681                 /* nothing to do */
1682                 return 0;
1683
1684         if (sq->rate_limit)
1685                 /* remove current rl index to free space to next ones */
1686                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1687
1688         sq->rate_limit = 0;
1689
1690         if (rate) {
1691                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1692                 if (err) {
1693                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1694                                    rate, err);
1695                         return err;
1696                 }
1697         }
1698
1699         msp.curr_state = MLX5_SQC_STATE_RDY;
1700         msp.next_state = MLX5_SQC_STATE_RDY;
1701         msp.rl_index   = rl_index;
1702         msp.rl_update  = true;
1703         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1704         if (err) {
1705                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1706                            rate, err);
1707                 /* remove the rate from the table */
1708                 if (rate)
1709                         mlx5_rl_remove_rate(mdev, rate);
1710                 return err;
1711         }
1712
1713         sq->rate_limit = rate;
1714         return 0;
1715 }
1716
1717 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1718 {
1719         struct mlx5e_priv *priv = netdev_priv(dev);
1720         struct mlx5_core_dev *mdev = priv->mdev;
1721         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1722         int err = 0;
1723
1724         if (!mlx5_rl_is_supported(mdev)) {
1725                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1726                 return -EINVAL;
1727         }
1728
1729         /* rate is given in Mb/sec, HW config is in Kb/sec */
1730         rate = rate << 10;
1731
1732         /* Check whether rate in valid range, 0 is always valid */
1733         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1734                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1735                 return -ERANGE;
1736         }
1737
1738         mutex_lock(&priv->state_lock);
1739         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1740                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1741         if (!err)
1742                 priv->tx_rates[index] = rate;
1743         mutex_unlock(&priv->state_lock);
1744
1745         return err;
1746 }
1747
1748 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1749                               struct mlx5e_params *params,
1750                               struct mlx5e_channel_param *cparam,
1751                               struct mlx5e_channel **cp)
1752 {
1753         struct mlx5e_cq_moder icocq_moder = {0, 0};
1754         struct net_device *netdev = priv->netdev;
1755         struct mlx5e_channel *c;
1756         int err;
1757
1758         c = kzalloc_node(sizeof(*c), GFP_KERNEL, mlx5e_get_node(priv, ix));
1759         if (!c)
1760                 return -ENOMEM;
1761
1762         c->priv     = priv;
1763         c->mdev     = priv->mdev;
1764         c->tstamp   = &priv->tstamp;
1765         c->ix       = ix;
1766         c->pdev     = &priv->mdev->pdev->dev;
1767         c->netdev   = priv->netdev;
1768         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1769         c->num_tc   = params->num_tc;
1770         c->xdp      = !!params->xdp_prog;
1771
1772         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1773
1774         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1775         if (err)
1776                 goto err_napi_del;
1777
1778         err = mlx5e_open_tx_cqs(c, params, cparam);
1779         if (err)
1780                 goto err_close_icosq_cq;
1781
1782         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1783         if (err)
1784                 goto err_close_tx_cqs;
1785
1786         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1787         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1788                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1789         if (err)
1790                 goto err_close_rx_cq;
1791
1792         napi_enable(&c->napi);
1793
1794         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1795         if (err)
1796                 goto err_disable_napi;
1797
1798         err = mlx5e_open_sqs(c, params, cparam);
1799         if (err)
1800                 goto err_close_icosq;
1801
1802         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1803         if (err)
1804                 goto err_close_sqs;
1805
1806         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1807         if (err)
1808                 goto err_close_xdp_sq;
1809
1810         *cp = c;
1811
1812         return 0;
1813 err_close_xdp_sq:
1814         if (c->xdp)
1815                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1816
1817 err_close_sqs:
1818         mlx5e_close_sqs(c);
1819
1820 err_close_icosq:
1821         mlx5e_close_icosq(&c->icosq);
1822
1823 err_disable_napi:
1824         napi_disable(&c->napi);
1825         if (c->xdp)
1826                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1827
1828 err_close_rx_cq:
1829         mlx5e_close_cq(&c->rq.cq);
1830
1831 err_close_tx_cqs:
1832         mlx5e_close_tx_cqs(c);
1833
1834 err_close_icosq_cq:
1835         mlx5e_close_cq(&c->icosq.cq);
1836
1837 err_napi_del:
1838         netif_napi_del(&c->napi);
1839         kfree(c);
1840
1841         return err;
1842 }
1843
1844 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1845 {
1846         int tc;
1847
1848         for (tc = 0; tc < c->num_tc; tc++)
1849                 mlx5e_activate_txqsq(&c->sq[tc]);
1850         mlx5e_activate_rq(&c->rq);
1851         netif_set_xps_queue(c->netdev,
1852                 mlx5_get_vector_affinity(c->priv->mdev, c->ix), c->ix);
1853 }
1854
1855 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1856 {
1857         int tc;
1858
1859         mlx5e_deactivate_rq(&c->rq);
1860         for (tc = 0; tc < c->num_tc; tc++)
1861                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1862 }
1863
1864 static void mlx5e_close_channel(struct mlx5e_channel *c)
1865 {
1866         mlx5e_close_rq(&c->rq);
1867         if (c->xdp)
1868                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1869         mlx5e_close_sqs(c);
1870         mlx5e_close_icosq(&c->icosq);
1871         napi_disable(&c->napi);
1872         if (c->xdp)
1873                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1874         mlx5e_close_cq(&c->rq.cq);
1875         mlx5e_close_tx_cqs(c);
1876         mlx5e_close_cq(&c->icosq.cq);
1877         netif_napi_del(&c->napi);
1878
1879         kfree(c);
1880 }
1881
1882 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1883                                  struct mlx5e_params *params,
1884                                  struct mlx5e_rq_param *param)
1885 {
1886         void *rqc = param->rqc;
1887         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1888
1889         switch (params->rq_wq_type) {
1890         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1891                 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1892                 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
1893                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1894                 break;
1895         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1896                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1897         }
1898
1899         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1900         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1901         MLX5_SET(wq, wq, log_wq_sz,        params->log_rq_size);
1902         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1903         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1904         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
1905         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
1906
1907         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1908         param->wq.linear = 1;
1909 }
1910
1911 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1912 {
1913         void *rqc = param->rqc;
1914         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1915
1916         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1917         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1918 }
1919
1920 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1921                                         struct mlx5e_sq_param *param)
1922 {
1923         void *sqc = param->sqc;
1924         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1925
1926         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1927         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1928
1929         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1930 }
1931
1932 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1933                                  struct mlx5e_params *params,
1934                                  struct mlx5e_sq_param *param)
1935 {
1936         void *sqc = param->sqc;
1937         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1938
1939         mlx5e_build_sq_param_common(priv, param);
1940         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1941         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1942 }
1943
1944 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1945                                         struct mlx5e_cq_param *param)
1946 {
1947         void *cqc = param->cqc;
1948
1949         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1950 }
1951
1952 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1953                                     struct mlx5e_params *params,
1954                                     struct mlx5e_cq_param *param)
1955 {
1956         void *cqc = param->cqc;
1957         u8 log_cq_size;
1958
1959         switch (params->rq_wq_type) {
1960         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1961                 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
1962                 break;
1963         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1964                 log_cq_size = params->log_rq_size;
1965         }
1966
1967         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1968         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1969                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1970                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1971         }
1972
1973         mlx5e_build_common_cq_param(priv, param);
1974 }
1975
1976 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1977                                     struct mlx5e_params *params,
1978                                     struct mlx5e_cq_param *param)
1979 {
1980         void *cqc = param->cqc;
1981
1982         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1983
1984         mlx5e_build_common_cq_param(priv, param);
1985
1986         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1987 }
1988
1989 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1990                                      u8 log_wq_size,
1991                                      struct mlx5e_cq_param *param)
1992 {
1993         void *cqc = param->cqc;
1994
1995         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1996
1997         mlx5e_build_common_cq_param(priv, param);
1998
1999         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2000 }
2001
2002 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2003                                     u8 log_wq_size,
2004                                     struct mlx5e_sq_param *param)
2005 {
2006         void *sqc = param->sqc;
2007         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2008
2009         mlx5e_build_sq_param_common(priv, param);
2010
2011         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2012         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2013 }
2014
2015 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2016                                     struct mlx5e_params *params,
2017                                     struct mlx5e_sq_param *param)
2018 {
2019         void *sqc = param->sqc;
2020         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2021
2022         mlx5e_build_sq_param_common(priv, param);
2023         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2024 }
2025
2026 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2027                                       struct mlx5e_params *params,
2028                                       struct mlx5e_channel_param *cparam)
2029 {
2030         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2031
2032         mlx5e_build_rq_param(priv, params, &cparam->rq);
2033         mlx5e_build_sq_param(priv, params, &cparam->sq);
2034         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2035         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2036         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2037         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2038         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2039 }
2040
2041 int mlx5e_open_channels(struct mlx5e_priv *priv,
2042                         struct mlx5e_channels *chs)
2043 {
2044         struct mlx5e_channel_param *cparam;
2045         int err = -ENOMEM;
2046         int i;
2047
2048         chs->num = chs->params.num_channels;
2049
2050         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2051         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2052         if (!chs->c || !cparam)
2053                 goto err_free;
2054
2055         mlx5e_build_channel_param(priv, &chs->params, cparam);
2056         for (i = 0; i < chs->num; i++) {
2057                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2058                 if (err)
2059                         goto err_close_channels;
2060         }
2061
2062         kfree(cparam);
2063         return 0;
2064
2065 err_close_channels:
2066         for (i--; i >= 0; i--)
2067                 mlx5e_close_channel(chs->c[i]);
2068
2069 err_free:
2070         kfree(chs->c);
2071         kfree(cparam);
2072         chs->num = 0;
2073         return err;
2074 }
2075
2076 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2077 {
2078         int i;
2079
2080         for (i = 0; i < chs->num; i++)
2081                 mlx5e_activate_channel(chs->c[i]);
2082 }
2083
2084 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2085 {
2086         int err = 0;
2087         int i;
2088
2089         for (i = 0; i < chs->num; i++) {
2090                 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2091                 if (err)
2092                         break;
2093         }
2094
2095         return err;
2096 }
2097
2098 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2099 {
2100         int i;
2101
2102         for (i = 0; i < chs->num; i++)
2103                 mlx5e_deactivate_channel(chs->c[i]);
2104 }
2105
2106 void mlx5e_close_channels(struct mlx5e_channels *chs)
2107 {
2108         int i;
2109
2110         for (i = 0; i < chs->num; i++)
2111                 mlx5e_close_channel(chs->c[i]);
2112
2113         kfree(chs->c);
2114         chs->num = 0;
2115 }
2116
2117 static int
2118 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2119 {
2120         struct mlx5_core_dev *mdev = priv->mdev;
2121         void *rqtc;
2122         int inlen;
2123         int err;
2124         u32 *in;
2125         int i;
2126
2127         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2128         in = kvzalloc(inlen, GFP_KERNEL);
2129         if (!in)
2130                 return -ENOMEM;
2131
2132         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2133
2134         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2135         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2136
2137         for (i = 0; i < sz; i++)
2138                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2139
2140         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2141         if (!err)
2142                 rqt->enabled = true;
2143
2144         kvfree(in);
2145         return err;
2146 }
2147
2148 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2149 {
2150         rqt->enabled = false;
2151         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2152 }
2153
2154 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2155 {
2156         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2157         int err;
2158
2159         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2160         if (err)
2161                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2162         return err;
2163 }
2164
2165 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2166 {
2167         struct mlx5e_rqt *rqt;
2168         int err;
2169         int ix;
2170
2171         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2172                 rqt = &priv->direct_tir[ix].rqt;
2173                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2174                 if (err)
2175                         goto err_destroy_rqts;
2176         }
2177
2178         return 0;
2179
2180 err_destroy_rqts:
2181         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2182         for (ix--; ix >= 0; ix--)
2183                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2184
2185         return err;
2186 }
2187
2188 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2189 {
2190         int i;
2191
2192         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2193                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2194 }
2195
2196 static int mlx5e_rx_hash_fn(int hfunc)
2197 {
2198         return (hfunc == ETH_RSS_HASH_TOP) ?
2199                MLX5_RX_HASH_FN_TOEPLITZ :
2200                MLX5_RX_HASH_FN_INVERTED_XOR8;
2201 }
2202
2203 static int mlx5e_bits_invert(unsigned long a, int size)
2204 {
2205         int inv = 0;
2206         int i;
2207
2208         for (i = 0; i < size; i++)
2209                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2210
2211         return inv;
2212 }
2213
2214 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2215                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2216 {
2217         int i;
2218
2219         for (i = 0; i < sz; i++) {
2220                 u32 rqn;
2221
2222                 if (rrp.is_rss) {
2223                         int ix = i;
2224
2225                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2226                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2227
2228                         ix = priv->channels.params.indirection_rqt[ix];
2229                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2230                 } else {
2231                         rqn = rrp.rqn;
2232                 }
2233                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2234         }
2235 }
2236
2237 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2238                        struct mlx5e_redirect_rqt_param rrp)
2239 {
2240         struct mlx5_core_dev *mdev = priv->mdev;
2241         void *rqtc;
2242         int inlen;
2243         u32 *in;
2244         int err;
2245
2246         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2247         in = kvzalloc(inlen, GFP_KERNEL);
2248         if (!in)
2249                 return -ENOMEM;
2250
2251         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2252
2253         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2254         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2255         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2256         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2257
2258         kvfree(in);
2259         return err;
2260 }
2261
2262 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2263                                 struct mlx5e_redirect_rqt_param rrp)
2264 {
2265         if (!rrp.is_rss)
2266                 return rrp.rqn;
2267
2268         if (ix >= rrp.rss.channels->num)
2269                 return priv->drop_rq.rqn;
2270
2271         return rrp.rss.channels->c[ix]->rq.rqn;
2272 }
2273
2274 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2275                                 struct mlx5e_redirect_rqt_param rrp)
2276 {
2277         u32 rqtn;
2278         int ix;
2279
2280         if (priv->indir_rqt.enabled) {
2281                 /* RSS RQ table */
2282                 rqtn = priv->indir_rqt.rqtn;
2283                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2284         }
2285
2286         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2287                 struct mlx5e_redirect_rqt_param direct_rrp = {
2288                         .is_rss = false,
2289                         {
2290                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2291                         },
2292                 };
2293
2294                 /* Direct RQ Tables */
2295                 if (!priv->direct_tir[ix].rqt.enabled)
2296                         continue;
2297
2298                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2299                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2300         }
2301 }
2302
2303 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2304                                             struct mlx5e_channels *chs)
2305 {
2306         struct mlx5e_redirect_rqt_param rrp = {
2307                 .is_rss        = true,
2308                 {
2309                         .rss = {
2310                                 .channels  = chs,
2311                                 .hfunc     = chs->params.rss_hfunc,
2312                         }
2313                 },
2314         };
2315
2316         mlx5e_redirect_rqts(priv, rrp);
2317 }
2318
2319 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2320 {
2321         struct mlx5e_redirect_rqt_param drop_rrp = {
2322                 .is_rss = false,
2323                 {
2324                         .rqn = priv->drop_rq.rqn,
2325                 },
2326         };
2327
2328         mlx5e_redirect_rqts(priv, drop_rrp);
2329 }
2330
2331 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2332 {
2333         if (!params->lro_en)
2334                 return;
2335
2336 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2337
2338         MLX5_SET(tirc, tirc, lro_enable_mask,
2339                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2340                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2341         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2342                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2343         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2344 }
2345
2346 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2347                                     enum mlx5e_traffic_types tt,
2348                                     void *tirc)
2349 {
2350         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2351
2352 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2353                                  MLX5_HASH_FIELD_SEL_DST_IP)
2354
2355 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2356                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2357                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2358                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2359
2360 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2361                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2362                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2363
2364         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2365         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2366                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2367                                              rx_hash_toeplitz_key);
2368                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2369                                                rx_hash_toeplitz_key);
2370
2371                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2372                 memcpy(rss_key, params->toeplitz_hash_key, len);
2373         }
2374
2375         switch (tt) {
2376         case MLX5E_TT_IPV4_TCP:
2377                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2378                          MLX5_L3_PROT_TYPE_IPV4);
2379                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2380                          MLX5_L4_PROT_TYPE_TCP);
2381                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2382                          MLX5_HASH_IP_L4PORTS);
2383                 break;
2384
2385         case MLX5E_TT_IPV6_TCP:
2386                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2387                          MLX5_L3_PROT_TYPE_IPV6);
2388                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2389                          MLX5_L4_PROT_TYPE_TCP);
2390                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2391                          MLX5_HASH_IP_L4PORTS);
2392                 break;
2393
2394         case MLX5E_TT_IPV4_UDP:
2395                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2396                          MLX5_L3_PROT_TYPE_IPV4);
2397                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2398                          MLX5_L4_PROT_TYPE_UDP);
2399                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2400                          MLX5_HASH_IP_L4PORTS);
2401                 break;
2402
2403         case MLX5E_TT_IPV6_UDP:
2404                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2405                          MLX5_L3_PROT_TYPE_IPV6);
2406                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2407                          MLX5_L4_PROT_TYPE_UDP);
2408                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2409                          MLX5_HASH_IP_L4PORTS);
2410                 break;
2411
2412         case MLX5E_TT_IPV4_IPSEC_AH:
2413                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2414                          MLX5_L3_PROT_TYPE_IPV4);
2415                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2416                          MLX5_HASH_IP_IPSEC_SPI);
2417                 break;
2418
2419         case MLX5E_TT_IPV6_IPSEC_AH:
2420                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2421                          MLX5_L3_PROT_TYPE_IPV6);
2422                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2423                          MLX5_HASH_IP_IPSEC_SPI);
2424                 break;
2425
2426         case MLX5E_TT_IPV4_IPSEC_ESP:
2427                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2428                          MLX5_L3_PROT_TYPE_IPV4);
2429                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2430                          MLX5_HASH_IP_IPSEC_SPI);
2431                 break;
2432
2433         case MLX5E_TT_IPV6_IPSEC_ESP:
2434                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2435                          MLX5_L3_PROT_TYPE_IPV6);
2436                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2437                          MLX5_HASH_IP_IPSEC_SPI);
2438                 break;
2439
2440         case MLX5E_TT_IPV4:
2441                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2442                          MLX5_L3_PROT_TYPE_IPV4);
2443                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2444                          MLX5_HASH_IP);
2445                 break;
2446
2447         case MLX5E_TT_IPV6:
2448                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2449                          MLX5_L3_PROT_TYPE_IPV6);
2450                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2451                          MLX5_HASH_IP);
2452                 break;
2453         default:
2454                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2455         }
2456 }
2457
2458 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2459 {
2460         struct mlx5_core_dev *mdev = priv->mdev;
2461
2462         void *in;
2463         void *tirc;
2464         int inlen;
2465         int err;
2466         int tt;
2467         int ix;
2468
2469         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2470         in = kvzalloc(inlen, GFP_KERNEL);
2471         if (!in)
2472                 return -ENOMEM;
2473
2474         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2475         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2476
2477         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2478
2479         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2480                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2481                                            inlen);
2482                 if (err)
2483                         goto free_in;
2484         }
2485
2486         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2487                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2488                                            in, inlen);
2489                 if (err)
2490                         goto free_in;
2491         }
2492
2493 free_in:
2494         kvfree(in);
2495
2496         return err;
2497 }
2498
2499 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2500 {
2501         struct mlx5_core_dev *mdev = priv->mdev;
2502         u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
2503         int err;
2504
2505         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2506         if (err)
2507                 return err;
2508
2509         /* Update vport context MTU */
2510         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2511         return 0;
2512 }
2513
2514 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2515 {
2516         struct mlx5_core_dev *mdev = priv->mdev;
2517         u16 hw_mtu = 0;
2518         int err;
2519
2520         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2521         if (err || !hw_mtu) /* fallback to port oper mtu */
2522                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2523
2524         *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
2525 }
2526
2527 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2528 {
2529         struct net_device *netdev = priv->netdev;
2530         u16 mtu;
2531         int err;
2532
2533         err = mlx5e_set_mtu(priv, netdev->mtu);
2534         if (err)
2535                 return err;
2536
2537         mlx5e_query_mtu(priv, &mtu);
2538         if (mtu != netdev->mtu)
2539                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2540                             __func__, mtu, netdev->mtu);
2541
2542         netdev->mtu = mtu;
2543         return 0;
2544 }
2545
2546 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2547 {
2548         struct mlx5e_priv *priv = netdev_priv(netdev);
2549         int nch = priv->channels.params.num_channels;
2550         int ntc = priv->channels.params.num_tc;
2551         int tc;
2552
2553         netdev_reset_tc(netdev);
2554
2555         if (ntc == 1)
2556                 return;
2557
2558         netdev_set_num_tc(netdev, ntc);
2559
2560         /* Map netdev TCs to offset 0
2561          * We have our own UP to TXQ mapping for QoS
2562          */
2563         for (tc = 0; tc < ntc; tc++)
2564                 netdev_set_tc_queue(netdev, tc, nch, 0);
2565 }
2566
2567 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2568 {
2569         struct mlx5e_channel *c;
2570         struct mlx5e_txqsq *sq;
2571         int i, tc;
2572
2573         for (i = 0; i < priv->channels.num; i++)
2574                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2575                         priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2576
2577         for (i = 0; i < priv->channels.num; i++) {
2578                 c = priv->channels.c[i];
2579                 for (tc = 0; tc < c->num_tc; tc++) {
2580                         sq = &c->sq[tc];
2581                         priv->txq2sq[sq->txq_ix] = sq;
2582                 }
2583         }
2584 }
2585
2586 static bool mlx5e_is_eswitch_vport_mngr(struct mlx5_core_dev *mdev)
2587 {
2588         return (MLX5_CAP_GEN(mdev, vport_group_manager) &&
2589                 MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH);
2590 }
2591
2592 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2593 {
2594         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2595         struct net_device *netdev = priv->netdev;
2596
2597         mlx5e_netdev_set_tcs(netdev);
2598         netif_set_real_num_tx_queues(netdev, num_txqs);
2599         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2600
2601         mlx5e_build_channels_tx_maps(priv);
2602         mlx5e_activate_channels(&priv->channels);
2603         netif_tx_start_all_queues(priv->netdev);
2604
2605         if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
2606                 mlx5e_add_sqs_fwd_rules(priv);
2607
2608         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2609         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2610 }
2611
2612 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2613 {
2614         mlx5e_redirect_rqts_to_drop(priv);
2615
2616         if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
2617                 mlx5e_remove_sqs_fwd_rules(priv);
2618
2619         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2620          * polling for inactive tx queues.
2621          */
2622         netif_tx_stop_all_queues(priv->netdev);
2623         netif_tx_disable(priv->netdev);
2624         mlx5e_deactivate_channels(&priv->channels);
2625 }
2626
2627 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2628                                 struct mlx5e_channels *new_chs,
2629                                 mlx5e_fp_hw_modify hw_modify)
2630 {
2631         struct net_device *netdev = priv->netdev;
2632         int new_num_txqs;
2633         int carrier_ok;
2634         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2635
2636         carrier_ok = netif_carrier_ok(netdev);
2637         netif_carrier_off(netdev);
2638
2639         if (new_num_txqs < netdev->real_num_tx_queues)
2640                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2641
2642         mlx5e_deactivate_priv_channels(priv);
2643         mlx5e_close_channels(&priv->channels);
2644
2645         priv->channels = *new_chs;
2646
2647         /* New channels are ready to roll, modify HW settings if needed */
2648         if (hw_modify)
2649                 hw_modify(priv);
2650
2651         mlx5e_refresh_tirs(priv, false);
2652         mlx5e_activate_priv_channels(priv);
2653
2654         /* return carrier back if needed */
2655         if (carrier_ok)
2656                 netif_carrier_on(netdev);
2657 }
2658
2659 int mlx5e_open_locked(struct net_device *netdev)
2660 {
2661         struct mlx5e_priv *priv = netdev_priv(netdev);
2662         int err;
2663
2664         set_bit(MLX5E_STATE_OPENED, &priv->state);
2665
2666         err = mlx5e_open_channels(priv, &priv->channels);
2667         if (err)
2668                 goto err_clear_state_opened_flag;
2669
2670         mlx5e_refresh_tirs(priv, false);
2671         mlx5e_activate_priv_channels(priv);
2672         if (priv->profile->update_carrier)
2673                 priv->profile->update_carrier(priv);
2674         mlx5e_timestamp_init(priv);
2675
2676         if (priv->profile->update_stats)
2677                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2678
2679         return 0;
2680
2681 err_clear_state_opened_flag:
2682         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2683         return err;
2684 }
2685
2686 int mlx5e_open(struct net_device *netdev)
2687 {
2688         struct mlx5e_priv *priv = netdev_priv(netdev);
2689         int err;
2690
2691         mutex_lock(&priv->state_lock);
2692         err = mlx5e_open_locked(netdev);
2693         mutex_unlock(&priv->state_lock);
2694
2695         return err;
2696 }
2697
2698 int mlx5e_close_locked(struct net_device *netdev)
2699 {
2700         struct mlx5e_priv *priv = netdev_priv(netdev);
2701
2702         /* May already be CLOSED in case a previous configuration operation
2703          * (e.g RX/TX queue size change) that involves close&open failed.
2704          */
2705         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2706                 return 0;
2707
2708         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2709
2710         mlx5e_timestamp_cleanup(priv);
2711         netif_carrier_off(priv->netdev);
2712         mlx5e_deactivate_priv_channels(priv);
2713         mlx5e_close_channels(&priv->channels);
2714
2715         return 0;
2716 }
2717
2718 int mlx5e_close(struct net_device *netdev)
2719 {
2720         struct mlx5e_priv *priv = netdev_priv(netdev);
2721         int err;
2722
2723         if (!netif_device_present(netdev))
2724                 return -ENODEV;
2725
2726         mutex_lock(&priv->state_lock);
2727         err = mlx5e_close_locked(netdev);
2728         mutex_unlock(&priv->state_lock);
2729
2730         return err;
2731 }
2732
2733 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2734                                struct mlx5e_rq *rq,
2735                                struct mlx5e_rq_param *param)
2736 {
2737         void *rqc = param->rqc;
2738         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2739         int err;
2740
2741         param->wq.db_numa_node = param->wq.buf_numa_node;
2742
2743         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2744                                 &rq->wq_ctrl);
2745         if (err)
2746                 return err;
2747
2748         rq->mdev = mdev;
2749
2750         return 0;
2751 }
2752
2753 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2754                                struct mlx5e_cq *cq,
2755                                struct mlx5e_cq_param *param)
2756 {
2757         return mlx5e_alloc_cq_common(mdev, param, cq);
2758 }
2759
2760 static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2761                               struct mlx5e_rq *drop_rq)
2762 {
2763         struct mlx5e_cq_param cq_param = {};
2764         struct mlx5e_rq_param rq_param = {};
2765         struct mlx5e_cq *cq = &drop_rq->cq;
2766         int err;
2767
2768         mlx5e_build_drop_rq_param(&rq_param);
2769
2770         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2771         if (err)
2772                 return err;
2773
2774         err = mlx5e_create_cq(cq, &cq_param);
2775         if (err)
2776                 goto err_free_cq;
2777
2778         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2779         if (err)
2780                 goto err_destroy_cq;
2781
2782         err = mlx5e_create_rq(drop_rq, &rq_param);
2783         if (err)
2784                 goto err_free_rq;
2785
2786         return 0;
2787
2788 err_free_rq:
2789         mlx5e_free_rq(drop_rq);
2790
2791 err_destroy_cq:
2792         mlx5e_destroy_cq(cq);
2793
2794 err_free_cq:
2795         mlx5e_free_cq(cq);
2796
2797         return err;
2798 }
2799
2800 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2801 {
2802         mlx5e_destroy_rq(drop_rq);
2803         mlx5e_free_rq(drop_rq);
2804         mlx5e_destroy_cq(&drop_rq->cq);
2805         mlx5e_free_cq(&drop_rq->cq);
2806 }
2807
2808 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2809                      u32 underlay_qpn, u32 *tisn)
2810 {
2811         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2812         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2813
2814         MLX5_SET(tisc, tisc, prio, tc << 1);
2815         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2816         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2817
2818         if (mlx5_lag_is_lacp_owner(mdev))
2819                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2820
2821         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2822 }
2823
2824 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2825 {
2826         mlx5_core_destroy_tis(mdev, tisn);
2827 }
2828
2829 int mlx5e_create_tises(struct mlx5e_priv *priv)
2830 {
2831         int err;
2832         int tc;
2833
2834         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2835                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2836                 if (err)
2837                         goto err_close_tises;
2838         }
2839
2840         return 0;
2841
2842 err_close_tises:
2843         for (tc--; tc >= 0; tc--)
2844                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2845
2846         return err;
2847 }
2848
2849 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2850 {
2851         int tc;
2852
2853         for (tc = 0; tc < priv->profile->max_tc; tc++)
2854                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2855 }
2856
2857 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2858                                       enum mlx5e_traffic_types tt,
2859                                       u32 *tirc)
2860 {
2861         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2862
2863         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2864
2865         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2866         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2867         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
2868 }
2869
2870 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2871 {
2872         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2873
2874         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2875
2876         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2877         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2878         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2879 }
2880
2881 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2882 {
2883         struct mlx5e_tir *tir;
2884         void *tirc;
2885         int inlen;
2886         int err;
2887         u32 *in;
2888         int tt;
2889
2890         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2891         in = kvzalloc(inlen, GFP_KERNEL);
2892         if (!in)
2893                 return -ENOMEM;
2894
2895         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2896                 memset(in, 0, inlen);
2897                 tir = &priv->indir_tir[tt];
2898                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2899                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2900                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2901                 if (err)
2902                         goto err_destroy_tirs;
2903         }
2904
2905         kvfree(in);
2906
2907         return 0;
2908
2909 err_destroy_tirs:
2910         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2911         for (tt--; tt >= 0; tt--)
2912                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2913
2914         kvfree(in);
2915
2916         return err;
2917 }
2918
2919 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2920 {
2921         int nch = priv->profile->max_nch(priv->mdev);
2922         struct mlx5e_tir *tir;
2923         void *tirc;
2924         int inlen;
2925         int err;
2926         u32 *in;
2927         int ix;
2928
2929         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2930         in = kvzalloc(inlen, GFP_KERNEL);
2931         if (!in)
2932                 return -ENOMEM;
2933
2934         for (ix = 0; ix < nch; ix++) {
2935                 memset(in, 0, inlen);
2936                 tir = &priv->direct_tir[ix];
2937                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2938                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2939                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2940                 if (err)
2941                         goto err_destroy_ch_tirs;
2942         }
2943
2944         kvfree(in);
2945
2946         return 0;
2947
2948 err_destroy_ch_tirs:
2949         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
2950         for (ix--; ix >= 0; ix--)
2951                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2952
2953         kvfree(in);
2954
2955         return err;
2956 }
2957
2958 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2959 {
2960         int i;
2961
2962         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2963                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2964 }
2965
2966 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2967 {
2968         int nch = priv->profile->max_nch(priv->mdev);
2969         int i;
2970
2971         for (i = 0; i < nch; i++)
2972                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2973 }
2974
2975 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2976 {
2977         int err = 0;
2978         int i;
2979
2980         for (i = 0; i < chs->num; i++) {
2981                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2982                 if (err)
2983                         return err;
2984         }
2985
2986         return 0;
2987 }
2988
2989 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
2990 {
2991         int err = 0;
2992         int i;
2993
2994         for (i = 0; i < chs->num; i++) {
2995                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
2996                 if (err)
2997                         return err;
2998         }
2999
3000         return 0;
3001 }
3002
3003 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
3004 {
3005         struct mlx5e_priv *priv = netdev_priv(netdev);
3006         struct mlx5e_channels new_channels = {};
3007         int err = 0;
3008
3009         if (tc && tc != MLX5E_MAX_NUM_TC)
3010                 return -EINVAL;
3011
3012         mutex_lock(&priv->state_lock);
3013
3014         new_channels.params = priv->channels.params;
3015         new_channels.params.num_tc = tc ? tc : 1;
3016
3017         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3018                 priv->channels.params = new_channels.params;
3019                 goto out;
3020         }
3021
3022         err = mlx5e_open_channels(priv, &new_channels);
3023         if (err)
3024                 goto out;
3025
3026         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3027 out:
3028         mutex_unlock(&priv->state_lock);
3029         return err;
3030 }
3031
3032 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
3033                               u32 chain_index, __be16 proto,
3034                               struct tc_to_netdev *tc)
3035 {
3036         struct mlx5e_priv *priv = netdev_priv(dev);
3037
3038         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
3039                 goto mqprio;
3040
3041         if (chain_index)
3042                 return -EOPNOTSUPP;
3043
3044         switch (tc->type) {
3045         case TC_SETUP_CLSFLOWER:
3046                 switch (tc->cls_flower->command) {
3047                 case TC_CLSFLOWER_REPLACE:
3048                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
3049                 case TC_CLSFLOWER_DESTROY:
3050                         return mlx5e_delete_flower(priv, tc->cls_flower);
3051                 case TC_CLSFLOWER_STATS:
3052                         return mlx5e_stats_flower(priv, tc->cls_flower);
3053                 }
3054         default:
3055                 return -EOPNOTSUPP;
3056         }
3057
3058 mqprio:
3059         if (tc->type != TC_SETUP_MQPRIO)
3060                 return -EINVAL;
3061
3062         tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3063
3064         return mlx5e_setup_tc(dev, tc->mqprio->num_tc);
3065 }
3066
3067 static void
3068 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3069 {
3070         struct mlx5e_priv *priv = netdev_priv(dev);
3071         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3072         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3073         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3074
3075         if (mlx5e_is_uplink_rep(priv)) {
3076                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3077                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3078                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3079                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3080         } else {
3081                 stats->rx_packets = sstats->rx_packets;
3082                 stats->rx_bytes   = sstats->rx_bytes;
3083                 stats->tx_packets = sstats->tx_packets;
3084                 stats->tx_bytes   = sstats->tx_bytes;
3085                 stats->tx_dropped = sstats->tx_queue_dropped;
3086         }
3087
3088         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3089
3090         stats->rx_length_errors =
3091                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3092                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3093                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3094         stats->rx_crc_errors =
3095                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3096         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3097         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3098         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3099                            stats->rx_frame_errors;
3100         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3101
3102         /* vport multicast also counts packets that are dropped due to steering
3103          * or rx out of buffer
3104          */
3105         stats->multicast =
3106                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3107 }
3108
3109 static void mlx5e_set_rx_mode(struct net_device *dev)
3110 {
3111         struct mlx5e_priv *priv = netdev_priv(dev);
3112
3113         queue_work(priv->wq, &priv->set_rx_mode_work);
3114 }
3115
3116 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3117 {
3118         struct mlx5e_priv *priv = netdev_priv(netdev);
3119         struct sockaddr *saddr = addr;
3120
3121         if (!is_valid_ether_addr(saddr->sa_data))
3122                 return -EADDRNOTAVAIL;
3123
3124         netif_addr_lock_bh(netdev);
3125         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3126         netif_addr_unlock_bh(netdev);
3127
3128         queue_work(priv->wq, &priv->set_rx_mode_work);
3129
3130         return 0;
3131 }
3132
3133 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
3134         do {                                            \
3135                 if (enable)                             \
3136                         netdev->features |= feature;    \
3137                 else                                    \
3138                         netdev->features &= ~feature;   \
3139         } while (0)
3140
3141 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3142
3143 static int set_feature_lro(struct net_device *netdev, bool enable)
3144 {
3145         struct mlx5e_priv *priv = netdev_priv(netdev);
3146         struct mlx5e_channels new_channels = {};
3147         int err = 0;
3148         bool reset;
3149
3150         mutex_lock(&priv->state_lock);
3151
3152         reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3153         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3154
3155         new_channels.params = priv->channels.params;
3156         new_channels.params.lro_en = enable;
3157
3158         if (!reset) {
3159                 priv->channels.params = new_channels.params;
3160                 err = mlx5e_modify_tirs_lro(priv);
3161                 goto out;
3162         }
3163
3164         err = mlx5e_open_channels(priv, &new_channels);
3165         if (err)
3166                 goto out;
3167
3168         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3169 out:
3170         mutex_unlock(&priv->state_lock);
3171         return err;
3172 }
3173
3174 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3175 {
3176         struct mlx5e_priv *priv = netdev_priv(netdev);
3177
3178         if (enable)
3179                 mlx5e_enable_vlan_filter(priv);
3180         else
3181                 mlx5e_disable_vlan_filter(priv);
3182
3183         return 0;
3184 }
3185
3186 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3187 {
3188         struct mlx5e_priv *priv = netdev_priv(netdev);
3189
3190         if (!enable && mlx5e_tc_num_filters(priv)) {
3191                 netdev_err(netdev,
3192                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3193                 return -EINVAL;
3194         }
3195
3196         return 0;
3197 }
3198
3199 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3200 {
3201         struct mlx5e_priv *priv = netdev_priv(netdev);
3202         struct mlx5_core_dev *mdev = priv->mdev;
3203
3204         return mlx5_set_port_fcs(mdev, !enable);
3205 }
3206
3207 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3208 {
3209         struct mlx5e_priv *priv = netdev_priv(netdev);
3210         int err;
3211
3212         mutex_lock(&priv->state_lock);
3213
3214         priv->channels.params.scatter_fcs_en = enable;
3215         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3216         if (err)
3217                 priv->channels.params.scatter_fcs_en = !enable;
3218
3219         mutex_unlock(&priv->state_lock);
3220
3221         return err;
3222 }
3223
3224 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3225 {
3226         struct mlx5e_priv *priv = netdev_priv(netdev);
3227         int err = 0;
3228
3229         mutex_lock(&priv->state_lock);
3230
3231         priv->channels.params.vlan_strip_disable = !enable;
3232         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3233                 goto unlock;
3234
3235         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3236         if (err)
3237                 priv->channels.params.vlan_strip_disable = enable;
3238
3239 unlock:
3240         mutex_unlock(&priv->state_lock);
3241
3242         return err;
3243 }
3244
3245 #ifdef CONFIG_RFS_ACCEL
3246 static int set_feature_arfs(struct net_device *netdev, bool enable)
3247 {
3248         struct mlx5e_priv *priv = netdev_priv(netdev);
3249         int err;
3250
3251         if (enable)
3252                 err = mlx5e_arfs_enable(priv);
3253         else
3254                 err = mlx5e_arfs_disable(priv);
3255
3256         return err;
3257 }
3258 #endif
3259
3260 static int mlx5e_handle_feature(struct net_device *netdev,
3261                                 netdev_features_t wanted_features,
3262                                 netdev_features_t feature,
3263                                 mlx5e_feature_handler feature_handler)
3264 {
3265         netdev_features_t changes = wanted_features ^ netdev->features;
3266         bool enable = !!(wanted_features & feature);
3267         int err;
3268
3269         if (!(changes & feature))
3270                 return 0;
3271
3272         err = feature_handler(netdev, enable);
3273         if (err) {
3274                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
3275                            enable ? "Enable" : "Disable", feature, err);
3276                 return err;
3277         }
3278
3279         MLX5E_SET_FEATURE(netdev, feature, enable);
3280         return 0;
3281 }
3282
3283 static int mlx5e_set_features(struct net_device *netdev,
3284                               netdev_features_t features)
3285 {
3286         int err;
3287
3288         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3289                                     set_feature_lro);
3290         err |= mlx5e_handle_feature(netdev, features,
3291                                     NETIF_F_HW_VLAN_CTAG_FILTER,
3292                                     set_feature_vlan_filter);
3293         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3294                                     set_feature_tc_num_filters);
3295         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3296                                     set_feature_rx_all);
3297         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3298                                     set_feature_rx_fcs);
3299         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3300                                     set_feature_rx_vlan);
3301 #ifdef CONFIG_RFS_ACCEL
3302         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3303                                     set_feature_arfs);
3304 #endif
3305
3306         return err ? -EINVAL : 0;
3307 }
3308
3309 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3310 {
3311         struct mlx5e_priv *priv = netdev_priv(netdev);
3312         struct mlx5e_channels new_channels = {};
3313         int curr_mtu;
3314         int err = 0;
3315         bool reset;
3316
3317         mutex_lock(&priv->state_lock);
3318
3319         reset = !priv->channels.params.lro_en &&
3320                 (priv->channels.params.rq_wq_type !=
3321                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3322
3323         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3324
3325         curr_mtu    = netdev->mtu;
3326         netdev->mtu = new_mtu;
3327
3328         if (!reset) {
3329                 mlx5e_set_dev_port_mtu(priv);
3330                 goto out;
3331         }
3332
3333         new_channels.params = priv->channels.params;
3334         err = mlx5e_open_channels(priv, &new_channels);
3335         if (err) {
3336                 netdev->mtu = curr_mtu;
3337                 goto out;
3338         }
3339
3340         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3341
3342 out:
3343         mutex_unlock(&priv->state_lock);
3344         return err;
3345 }
3346
3347 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3348 {
3349         struct mlx5e_priv *priv = netdev_priv(dev);
3350
3351         switch (cmd) {
3352         case SIOCSHWTSTAMP:
3353                 return mlx5e_hwstamp_set(priv, ifr);
3354         case SIOCGHWTSTAMP:
3355                 return mlx5e_hwstamp_get(priv, ifr);
3356         default:
3357                 return -EOPNOTSUPP;
3358         }
3359 }
3360
3361 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3362 {
3363         struct mlx5e_priv *priv = netdev_priv(dev);
3364         struct mlx5_core_dev *mdev = priv->mdev;
3365
3366         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3367 }
3368
3369 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3370                              __be16 vlan_proto)
3371 {
3372         struct mlx5e_priv *priv = netdev_priv(dev);
3373         struct mlx5_core_dev *mdev = priv->mdev;
3374
3375         if (vlan_proto != htons(ETH_P_8021Q))
3376                 return -EPROTONOSUPPORT;
3377
3378         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,