net/mlx5: Cleanup unused field in Work Queue parameters
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include "eswitch.h"
39 #include "en.h"
40 #include "en_tc.h"
41 #include "en_rep.h"
42 #include "en_accel/ipsec.h"
43 #include "en_accel/ipsec_rxtx.h"
44 #include "accel/ipsec.h"
45 #include "vxlan.h"
46
47 struct mlx5e_rq_param {
48         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
49         struct mlx5_wq_param    wq;
50 };
51
52 struct mlx5e_sq_param {
53         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
54         struct mlx5_wq_param       wq;
55 };
56
57 struct mlx5e_cq_param {
58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
59         struct mlx5_wq_param       wq;
60         u16                        eq_ix;
61         u8                         cq_period_mode;
62 };
63
64 struct mlx5e_channel_param {
65         struct mlx5e_rq_param      rq;
66         struct mlx5e_sq_param      sq;
67         struct mlx5e_sq_param      xdp_sq;
68         struct mlx5e_sq_param      icosq;
69         struct mlx5e_cq_param      rx_cq;
70         struct mlx5e_cq_param      tx_cq;
71         struct mlx5e_cq_param      icosq_cq;
72 };
73
74 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75 {
76         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
77                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78                 MLX5_CAP_ETH(mdev, reg_umr_sq);
79         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
80         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
81
82         if (!striding_rq_umr)
83                 return false;
84         if (!inline_umr) {
85                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
86                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
87                 return false;
88         }
89         return true;
90 }
91
92 static u32 mlx5e_mpwqe_get_linear_frag_sz(struct mlx5e_params *params)
93 {
94         if (!params->xdp_prog) {
95                 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
96                 u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN;
97
98                 return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu);
99         }
100
101         return PAGE_SIZE;
102 }
103
104 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
105 {
106         u32 linear_frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
107
108         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
109 }
110
111 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
112                                          struct mlx5e_params *params)
113 {
114         u32 frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
115         s8 signed_log_num_strides_param;
116         u8 log_num_strides;
117
118         if (params->lro_en || frag_sz > PAGE_SIZE)
119                 return false;
120
121         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
122                 return true;
123
124         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
125         signed_log_num_strides_param =
126                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
127
128         return signed_log_num_strides_param >= 0;
129 }
130
131 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
132 {
133         if (params->log_rq_mtu_frames <
134             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
135                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
136
137         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
138 }
139
140 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
141                                           struct mlx5e_params *params)
142 {
143         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
144                 return order_base_2(mlx5e_mpwqe_get_linear_frag_sz(params));
145
146         return MLX5E_MPWQE_STRIDE_SZ(mdev,
147                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
148 }
149
150 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
151                                           struct mlx5e_params *params)
152 {
153         return MLX5_MPWRQ_LOG_WQE_SZ -
154                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
155 }
156
157 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
158                                  struct mlx5e_params *params)
159 {
160         u16 linear_rq_headroom = params->xdp_prog ?
161                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
162
163         linear_rq_headroom += NET_IP_ALIGN;
164
165         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)
166                 return linear_rq_headroom;
167
168         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
169                 return linear_rq_headroom;
170
171         return 0;
172 }
173
174 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
175                                struct mlx5e_params *params)
176 {
177         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
178         params->log_rq_mtu_frames = is_kdump_kernel() ?
179                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
180                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
181         switch (params->rq_wq_type) {
182         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
183                 break;
184         default: /* MLX5_WQ_TYPE_LINKED_LIST */
185                 /* Extra room needed for build_skb */
186                 params->lro_wqe_sz -= mlx5e_get_rq_headroom(mdev, params) +
187                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
188         }
189
190         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
191                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
192                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
193                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
194                        BIT(params->log_rq_mtu_frames),
195                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
196                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
197 }
198
199 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
200                                 struct mlx5e_params *params)
201 {
202         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
203                 !MLX5_IPSEC_DEV(mdev) &&
204                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
205 }
206
207 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
208 {
209         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
210                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
211                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
212                 MLX5_WQ_TYPE_LINKED_LIST;
213 }
214
215 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
216 {
217         struct mlx5_core_dev *mdev = priv->mdev;
218         u8 port_state;
219
220         port_state = mlx5_query_vport_state(mdev,
221                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
222                                             0);
223
224         if (port_state == VPORT_STATE_UP) {
225                 netdev_info(priv->netdev, "Link up\n");
226                 netif_carrier_on(priv->netdev);
227         } else {
228                 netdev_info(priv->netdev, "Link down\n");
229                 netif_carrier_off(priv->netdev);
230         }
231 }
232
233 static void mlx5e_update_carrier_work(struct work_struct *work)
234 {
235         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
236                                                update_carrier_work);
237
238         mutex_lock(&priv->state_lock);
239         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
240                 if (priv->profile->update_carrier)
241                         priv->profile->update_carrier(priv);
242         mutex_unlock(&priv->state_lock);
243 }
244
245 void mlx5e_update_stats(struct mlx5e_priv *priv)
246 {
247         int i;
248
249         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
250                 if (mlx5e_stats_grps[i].update_stats)
251                         mlx5e_stats_grps[i].update_stats(priv);
252 }
253
254 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
255 {
256         int i;
257
258         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
259                 if (mlx5e_stats_grps[i].update_stats_mask &
260                     MLX5E_NDO_UPDATE_STATS)
261                         mlx5e_stats_grps[i].update_stats(priv);
262 }
263
264 void mlx5e_update_stats_work(struct work_struct *work)
265 {
266         struct delayed_work *dwork = to_delayed_work(work);
267         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
268                                                update_stats_work);
269         mutex_lock(&priv->state_lock);
270         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
271                 priv->profile->update_stats(priv);
272                 queue_delayed_work(priv->wq, dwork,
273                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
274         }
275         mutex_unlock(&priv->state_lock);
276 }
277
278 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
279                               enum mlx5_dev_event event, unsigned long param)
280 {
281         struct mlx5e_priv *priv = vpriv;
282
283         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
284                 return;
285
286         switch (event) {
287         case MLX5_DEV_EVENT_PORT_UP:
288         case MLX5_DEV_EVENT_PORT_DOWN:
289                 queue_work(priv->wq, &priv->update_carrier_work);
290                 break;
291         default:
292                 break;
293         }
294 }
295
296 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
297 {
298         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
299 }
300
301 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
302 {
303         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
304         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
305 }
306
307 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
308                                        struct mlx5e_icosq *sq,
309                                        struct mlx5e_umr_wqe *wqe)
310 {
311         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
312         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
313         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
314
315         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
316                                       ds_cnt);
317         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
318         cseg->imm       = rq->mkey_be;
319
320         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
321         ucseg->xlt_octowords =
322                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
323         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
324 }
325
326 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
327                                      struct mlx5e_channel *c)
328 {
329         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
330
331         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
332                                       GFP_KERNEL, cpu_to_node(c->cpu));
333         if (!rq->mpwqe.info)
334                 return -ENOMEM;
335
336         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
337
338         return 0;
339 }
340
341 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
342                                  u64 npages, u8 page_shift,
343                                  struct mlx5_core_mkey *umr_mkey)
344 {
345         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
346         void *mkc;
347         u32 *in;
348         int err;
349
350         in = kvzalloc(inlen, GFP_KERNEL);
351         if (!in)
352                 return -ENOMEM;
353
354         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
355
356         MLX5_SET(mkc, mkc, free, 1);
357         MLX5_SET(mkc, mkc, umr_en, 1);
358         MLX5_SET(mkc, mkc, lw, 1);
359         MLX5_SET(mkc, mkc, lr, 1);
360         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
361
362         MLX5_SET(mkc, mkc, qpn, 0xffffff);
363         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
364         MLX5_SET64(mkc, mkc, len, npages << page_shift);
365         MLX5_SET(mkc, mkc, translations_octword_size,
366                  MLX5_MTT_OCTW(npages));
367         MLX5_SET(mkc, mkc, log_page_size, page_shift);
368
369         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
370
371         kvfree(in);
372         return err;
373 }
374
375 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
376 {
377         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
378
379         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
380 }
381
382 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
383 {
384         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
385 }
386
387 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
388                           struct mlx5e_params *params,
389                           struct mlx5e_rq_param *rqp,
390                           struct mlx5e_rq *rq)
391 {
392         struct mlx5_core_dev *mdev = c->mdev;
393         void *rqc = rqp->rqc;
394         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
395         u32 byte_count;
396         int npages;
397         int wq_sz;
398         int err;
399         int i;
400
401         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
402
403         err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
404                                 &rq->wq_ctrl);
405         if (err)
406                 return err;
407
408         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
409
410         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
411
412         rq->wq_type = params->rq_wq_type;
413         rq->pdev    = c->pdev;
414         rq->netdev  = c->netdev;
415         rq->tstamp  = c->tstamp;
416         rq->clock   = &mdev->clock;
417         rq->channel = c;
418         rq->ix      = c->ix;
419         rq->mdev    = mdev;
420         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
421
422         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
423         if (IS_ERR(rq->xdp_prog)) {
424                 err = PTR_ERR(rq->xdp_prog);
425                 rq->xdp_prog = NULL;
426                 goto err_rq_wq_destroy;
427         }
428
429         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
430         if (err < 0)
431                 goto err_rq_wq_destroy;
432
433         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
434         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
435
436         switch (rq->wq_type) {
437         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
438                 rq->post_wqes = mlx5e_post_rx_mpwqes;
439                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
440
441                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
442 #ifdef CONFIG_MLX5_EN_IPSEC
443                 if (MLX5_IPSEC_DEV(mdev)) {
444                         err = -EINVAL;
445                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
446                         goto err_rq_wq_destroy;
447                 }
448 #endif
449                 if (!rq->handle_rx_cqe) {
450                         err = -EINVAL;
451                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
452                         goto err_rq_wq_destroy;
453                 }
454
455                 rq->mpwqe.skb_from_cqe_mpwrq =
456                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
457                         mlx5e_skb_from_cqe_mpwrq_linear :
458                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
459                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
460                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
461
462                 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
463
464                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
465                 if (err)
466                         goto err_rq_wq_destroy;
467                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
468
469                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
470                 if (err)
471                         goto err_destroy_umr_mkey;
472                 break;
473         default: /* MLX5_WQ_TYPE_LINKED_LIST */
474                 rq->wqe.frag_info =
475                         kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
476                                      GFP_KERNEL, cpu_to_node(c->cpu));
477                 if (!rq->wqe.frag_info) {
478                         err = -ENOMEM;
479                         goto err_rq_wq_destroy;
480                 }
481                 rq->post_wqes = mlx5e_post_rx_wqes;
482                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
483
484 #ifdef CONFIG_MLX5_EN_IPSEC
485                 if (c->priv->ipsec)
486                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
487                 else
488 #endif
489                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
490                 if (!rq->handle_rx_cqe) {
491                         kfree(rq->wqe.frag_info);
492                         err = -EINVAL;
493                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
494                         goto err_rq_wq_destroy;
495                 }
496
497                 byte_count = params->lro_en  ?
498                                 params->lro_wqe_sz :
499                                 MLX5E_SW2HW_MTU(params, params->sw_mtu);
500 #ifdef CONFIG_MLX5_EN_IPSEC
501                 if (MLX5_IPSEC_DEV(mdev))
502                         byte_count += MLX5E_METADATA_ETHER_LEN;
503 #endif
504                 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
505
506                 /* calc the required page order */
507                 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
508                 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
509                 rq->buff.page_order = order_base_2(npages);
510
511                 byte_count |= MLX5_HW_START_PADDING;
512                 rq->mkey_be = c->mkey_be;
513         }
514
515         for (i = 0; i < wq_sz; i++) {
516                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
517
518                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
519                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
520
521                         wqe->data.addr = cpu_to_be64(dma_offset + rq->buff.headroom);
522                 }
523
524                 wqe->data.byte_count = cpu_to_be32(byte_count);
525                 wqe->data.lkey = rq->mkey_be;
526         }
527
528         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
529
530         switch (params->rx_cq_moderation.cq_period_mode) {
531         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
532                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
533                 break;
534         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
535         default:
536                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
537         }
538
539         rq->page_cache.head = 0;
540         rq->page_cache.tail = 0;
541
542         return 0;
543
544 err_destroy_umr_mkey:
545         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
546
547 err_rq_wq_destroy:
548         if (rq->xdp_prog)
549                 bpf_prog_put(rq->xdp_prog);
550         xdp_rxq_info_unreg(&rq->xdp_rxq);
551         mlx5_wq_destroy(&rq->wq_ctrl);
552
553         return err;
554 }
555
556 static void mlx5e_free_rq(struct mlx5e_rq *rq)
557 {
558         int i;
559
560         if (rq->xdp_prog)
561                 bpf_prog_put(rq->xdp_prog);
562
563         xdp_rxq_info_unreg(&rq->xdp_rxq);
564
565         switch (rq->wq_type) {
566         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
567                 kfree(rq->mpwqe.info);
568                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
569                 break;
570         default: /* MLX5_WQ_TYPE_LINKED_LIST */
571                 kfree(rq->wqe.frag_info);
572         }
573
574         for (i = rq->page_cache.head; i != rq->page_cache.tail;
575              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
576                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
577
578                 mlx5e_page_release(rq, dma_info, false);
579         }
580         mlx5_wq_destroy(&rq->wq_ctrl);
581 }
582
583 static int mlx5e_create_rq(struct mlx5e_rq *rq,
584                            struct mlx5e_rq_param *param)
585 {
586         struct mlx5_core_dev *mdev = rq->mdev;
587
588         void *in;
589         void *rqc;
590         void *wq;
591         int inlen;
592         int err;
593
594         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
595                 sizeof(u64) * rq->wq_ctrl.buf.npages;
596         in = kvzalloc(inlen, GFP_KERNEL);
597         if (!in)
598                 return -ENOMEM;
599
600         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
601         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
602
603         memcpy(rqc, param->rqc, sizeof(param->rqc));
604
605         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
606         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
607         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
608                                                 MLX5_ADAPTER_PAGE_SHIFT);
609         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
610
611         mlx5_fill_page_array(&rq->wq_ctrl.buf,
612                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
613
614         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
615
616         kvfree(in);
617
618         return err;
619 }
620
621 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
622                                  int next_state)
623 {
624         struct mlx5_core_dev *mdev = rq->mdev;
625
626         void *in;
627         void *rqc;
628         int inlen;
629         int err;
630
631         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
632         in = kvzalloc(inlen, GFP_KERNEL);
633         if (!in)
634                 return -ENOMEM;
635
636         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
637
638         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
639         MLX5_SET(rqc, rqc, state, next_state);
640
641         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
642
643         kvfree(in);
644
645         return err;
646 }
647
648 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
649 {
650         struct mlx5e_channel *c = rq->channel;
651         struct mlx5e_priv *priv = c->priv;
652         struct mlx5_core_dev *mdev = priv->mdev;
653
654         void *in;
655         void *rqc;
656         int inlen;
657         int err;
658
659         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
660         in = kvzalloc(inlen, GFP_KERNEL);
661         if (!in)
662                 return -ENOMEM;
663
664         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
665
666         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
667         MLX5_SET64(modify_rq_in, in, modify_bitmask,
668                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
669         MLX5_SET(rqc, rqc, scatter_fcs, enable);
670         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
671
672         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
673
674         kvfree(in);
675
676         return err;
677 }
678
679 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
680 {
681         struct mlx5e_channel *c = rq->channel;
682         struct mlx5_core_dev *mdev = c->mdev;
683         void *in;
684         void *rqc;
685         int inlen;
686         int err;
687
688         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
689         in = kvzalloc(inlen, GFP_KERNEL);
690         if (!in)
691                 return -ENOMEM;
692
693         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
694
695         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
696         MLX5_SET64(modify_rq_in, in, modify_bitmask,
697                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
698         MLX5_SET(rqc, rqc, vsd, vsd);
699         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
700
701         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
702
703         kvfree(in);
704
705         return err;
706 }
707
708 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
709 {
710         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
711 }
712
713 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
714 {
715         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
716         struct mlx5e_channel *c = rq->channel;
717
718         struct mlx5_wq_ll *wq = &rq->wq;
719         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
720
721         while (time_before(jiffies, exp_time)) {
722                 if (wq->cur_sz >= min_wqes)
723                         return 0;
724
725                 msleep(20);
726         }
727
728         netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
729                     rq->rqn, wq->cur_sz, min_wqes);
730         return -ETIMEDOUT;
731 }
732
733 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
734 {
735         struct mlx5_wq_ll *wq = &rq->wq;
736         struct mlx5e_rx_wqe *wqe;
737         __be16 wqe_ix_be;
738         u16 wqe_ix;
739
740         /* UMR WQE (if in progress) is always at wq->head */
741         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
742             rq->mpwqe.umr_in_progress)
743                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
744
745         while (!mlx5_wq_ll_is_empty(wq)) {
746                 wqe_ix_be = *wq->tail_next;
747                 wqe_ix    = be16_to_cpu(wqe_ix_be);
748                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
749                 rq->dealloc_wqe(rq, wqe_ix);
750                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
751                                &wqe->next.next_wqe_index);
752         }
753
754         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
755                 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
756                  * but yet to be re-posted.
757                  */
758                 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
759
760                 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
761                         rq->dealloc_wqe(rq, wqe_ix);
762         }
763 }
764
765 static int mlx5e_open_rq(struct mlx5e_channel *c,
766                          struct mlx5e_params *params,
767                          struct mlx5e_rq_param *param,
768                          struct mlx5e_rq *rq)
769 {
770         int err;
771
772         err = mlx5e_alloc_rq(c, params, param, rq);
773         if (err)
774                 return err;
775
776         err = mlx5e_create_rq(rq, param);
777         if (err)
778                 goto err_free_rq;
779
780         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
781         if (err)
782                 goto err_destroy_rq;
783
784         if (params->rx_dim_enabled)
785                 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
786
787         return 0;
788
789 err_destroy_rq:
790         mlx5e_destroy_rq(rq);
791 err_free_rq:
792         mlx5e_free_rq(rq);
793
794         return err;
795 }
796
797 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
798 {
799         struct mlx5e_icosq *sq = &rq->channel->icosq;
800         u16 pi = sq->pc & sq->wq.sz_m1;
801         struct mlx5e_tx_wqe *nopwqe;
802
803         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
804         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
805         nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
806         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
807 }
808
809 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
810 {
811         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
812         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
813 }
814
815 static void mlx5e_close_rq(struct mlx5e_rq *rq)
816 {
817         cancel_work_sync(&rq->dim.work);
818         mlx5e_destroy_rq(rq);
819         mlx5e_free_rx_descs(rq);
820         mlx5e_free_rq(rq);
821 }
822
823 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
824 {
825         kfree(sq->db.di);
826 }
827
828 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
829 {
830         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
831
832         sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
833                                      GFP_KERNEL, numa);
834         if (!sq->db.di) {
835                 mlx5e_free_xdpsq_db(sq);
836                 return -ENOMEM;
837         }
838
839         return 0;
840 }
841
842 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
843                              struct mlx5e_params *params,
844                              struct mlx5e_sq_param *param,
845                              struct mlx5e_xdpsq *sq)
846 {
847         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
848         struct mlx5_core_dev *mdev = c->mdev;
849         int err;
850
851         sq->pdev      = c->pdev;
852         sq->mkey_be   = c->mkey_be;
853         sq->channel   = c;
854         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
855         sq->min_inline_mode = params->tx_min_inline_mode;
856
857         param->wq.db_numa_node = cpu_to_node(c->cpu);
858         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
859         if (err)
860                 return err;
861         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
862
863         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
864         if (err)
865                 goto err_sq_wq_destroy;
866
867         return 0;
868
869 err_sq_wq_destroy:
870         mlx5_wq_destroy(&sq->wq_ctrl);
871
872         return err;
873 }
874
875 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
876 {
877         mlx5e_free_xdpsq_db(sq);
878         mlx5_wq_destroy(&sq->wq_ctrl);
879 }
880
881 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
882 {
883         kfree(sq->db.ico_wqe);
884 }
885
886 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
887 {
888         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
889
890         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
891                                       GFP_KERNEL, numa);
892         if (!sq->db.ico_wqe)
893                 return -ENOMEM;
894
895         return 0;
896 }
897
898 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
899                              struct mlx5e_sq_param *param,
900                              struct mlx5e_icosq *sq)
901 {
902         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
903         struct mlx5_core_dev *mdev = c->mdev;
904         int err;
905
906         sq->channel   = c;
907         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
908
909         param->wq.db_numa_node = cpu_to_node(c->cpu);
910         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
911         if (err)
912                 return err;
913         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
914
915         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
916         if (err)
917                 goto err_sq_wq_destroy;
918
919         sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
920
921         return 0;
922
923 err_sq_wq_destroy:
924         mlx5_wq_destroy(&sq->wq_ctrl);
925
926         return err;
927 }
928
929 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
930 {
931         mlx5e_free_icosq_db(sq);
932         mlx5_wq_destroy(&sq->wq_ctrl);
933 }
934
935 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
936 {
937         kfree(sq->db.wqe_info);
938         kfree(sq->db.dma_fifo);
939 }
940
941 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
942 {
943         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
944         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
945
946         sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
947                                            GFP_KERNEL, numa);
948         sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
949                                            GFP_KERNEL, numa);
950         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
951                 mlx5e_free_txqsq_db(sq);
952                 return -ENOMEM;
953         }
954
955         sq->dma_fifo_mask = df_sz - 1;
956
957         return 0;
958 }
959
960 static void mlx5e_sq_recover(struct work_struct *work);
961 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
962                              int txq_ix,
963                              struct mlx5e_params *params,
964                              struct mlx5e_sq_param *param,
965                              struct mlx5e_txqsq *sq)
966 {
967         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
968         struct mlx5_core_dev *mdev = c->mdev;
969         int err;
970
971         sq->pdev      = c->pdev;
972         sq->tstamp    = c->tstamp;
973         sq->clock     = &mdev->clock;
974         sq->mkey_be   = c->mkey_be;
975         sq->channel   = c;
976         sq->txq_ix    = txq_ix;
977         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
978         sq->min_inline_mode = params->tx_min_inline_mode;
979         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
980         if (MLX5_IPSEC_DEV(c->priv->mdev))
981                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
982
983         param->wq.db_numa_node = cpu_to_node(c->cpu);
984         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
985         if (err)
986                 return err;
987         sq->wq.db    = &sq->wq.db[MLX5_SND_DBR];
988
989         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
990         if (err)
991                 goto err_sq_wq_destroy;
992
993         sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
994
995         return 0;
996
997 err_sq_wq_destroy:
998         mlx5_wq_destroy(&sq->wq_ctrl);
999
1000         return err;
1001 }
1002
1003 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1004 {
1005         mlx5e_free_txqsq_db(sq);
1006         mlx5_wq_destroy(&sq->wq_ctrl);
1007 }
1008
1009 struct mlx5e_create_sq_param {
1010         struct mlx5_wq_ctrl        *wq_ctrl;
1011         u32                         cqn;
1012         u32                         tisn;
1013         u8                          tis_lst_sz;
1014         u8                          min_inline_mode;
1015 };
1016
1017 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1018                            struct mlx5e_sq_param *param,
1019                            struct mlx5e_create_sq_param *csp,
1020                            u32 *sqn)
1021 {
1022         void *in;
1023         void *sqc;
1024         void *wq;
1025         int inlen;
1026         int err;
1027
1028         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1029                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1030         in = kvzalloc(inlen, GFP_KERNEL);
1031         if (!in)
1032                 return -ENOMEM;
1033
1034         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1035         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1036
1037         memcpy(sqc, param->sqc, sizeof(param->sqc));
1038         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1039         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1040         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1041
1042         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1043                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1044
1045         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1046         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1047
1048         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1049         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1050         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1051                                           MLX5_ADAPTER_PAGE_SHIFT);
1052         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1053
1054         mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1055
1056         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1057
1058         kvfree(in);
1059
1060         return err;
1061 }
1062
1063 struct mlx5e_modify_sq_param {
1064         int curr_state;
1065         int next_state;
1066         bool rl_update;
1067         int rl_index;
1068 };
1069
1070 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1071                            struct mlx5e_modify_sq_param *p)
1072 {
1073         void *in;
1074         void *sqc;
1075         int inlen;
1076         int err;
1077
1078         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1079         in = kvzalloc(inlen, GFP_KERNEL);
1080         if (!in)
1081                 return -ENOMEM;
1082
1083         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1084
1085         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1086         MLX5_SET(sqc, sqc, state, p->next_state);
1087         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1088                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1089                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1090         }
1091
1092         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1093
1094         kvfree(in);
1095
1096         return err;
1097 }
1098
1099 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1100 {
1101         mlx5_core_destroy_sq(mdev, sqn);
1102 }
1103
1104 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1105                                struct mlx5e_sq_param *param,
1106                                struct mlx5e_create_sq_param *csp,
1107                                u32 *sqn)
1108 {
1109         struct mlx5e_modify_sq_param msp = {0};
1110         int err;
1111
1112         err = mlx5e_create_sq(mdev, param, csp, sqn);
1113         if (err)
1114                 return err;
1115
1116         msp.curr_state = MLX5_SQC_STATE_RST;
1117         msp.next_state = MLX5_SQC_STATE_RDY;
1118         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1119         if (err)
1120                 mlx5e_destroy_sq(mdev, *sqn);
1121
1122         return err;
1123 }
1124
1125 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1126                                 struct mlx5e_txqsq *sq, u32 rate);
1127
1128 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1129                             u32 tisn,
1130                             int txq_ix,
1131                             struct mlx5e_params *params,
1132                             struct mlx5e_sq_param *param,
1133                             struct mlx5e_txqsq *sq)
1134 {
1135         struct mlx5e_create_sq_param csp = {};
1136         u32 tx_rate;
1137         int err;
1138
1139         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1140         if (err)
1141                 return err;
1142
1143         csp.tisn            = tisn;
1144         csp.tis_lst_sz      = 1;
1145         csp.cqn             = sq->cq.mcq.cqn;
1146         csp.wq_ctrl         = &sq->wq_ctrl;
1147         csp.min_inline_mode = sq->min_inline_mode;
1148         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1149         if (err)
1150                 goto err_free_txqsq;
1151
1152         tx_rate = c->priv->tx_rates[sq->txq_ix];
1153         if (tx_rate)
1154                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1155
1156         return 0;
1157
1158 err_free_txqsq:
1159         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1160         mlx5e_free_txqsq(sq);
1161
1162         return err;
1163 }
1164
1165 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1166 {
1167         WARN_ONCE(sq->cc != sq->pc,
1168                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1169                   sq->sqn, sq->cc, sq->pc);
1170         sq->cc = 0;
1171         sq->dma_fifo_cc = 0;
1172         sq->pc = 0;
1173 }
1174
1175 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1176 {
1177         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1178         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1179         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1180         netdev_tx_reset_queue(sq->txq);
1181         netif_tx_start_queue(sq->txq);
1182 }
1183
1184 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1185 {
1186         __netif_tx_lock_bh(txq);
1187         netif_tx_stop_queue(txq);
1188         __netif_tx_unlock_bh(txq);
1189 }
1190
1191 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1192 {
1193         struct mlx5e_channel *c = sq->channel;
1194
1195         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1196         /* prevent netif_tx_wake_queue */
1197         napi_synchronize(&c->napi);
1198
1199         netif_tx_disable_queue(sq->txq);
1200
1201         /* last doorbell out, godspeed .. */
1202         if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1203                 struct mlx5e_tx_wqe *nop;
1204
1205                 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1206                 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1207                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1208         }
1209 }
1210
1211 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1212 {
1213         struct mlx5e_channel *c = sq->channel;
1214         struct mlx5_core_dev *mdev = c->mdev;
1215         struct mlx5_rate_limit rl = {0};
1216
1217         mlx5e_destroy_sq(mdev, sq->sqn);
1218         if (sq->rate_limit) {
1219                 rl.rate = sq->rate_limit;
1220                 mlx5_rl_remove_rate(mdev, &rl);
1221         }
1222         mlx5e_free_txqsq_descs(sq);
1223         mlx5e_free_txqsq(sq);
1224 }
1225
1226 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1227 {
1228         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1229
1230         while (time_before(jiffies, exp_time)) {
1231                 if (sq->cc == sq->pc)
1232                         return 0;
1233
1234                 msleep(20);
1235         }
1236
1237         netdev_err(sq->channel->netdev,
1238                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1239                    sq->sqn, sq->cc, sq->pc);
1240
1241         return -ETIMEDOUT;
1242 }
1243
1244 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1245 {
1246         struct mlx5_core_dev *mdev = sq->channel->mdev;
1247         struct net_device *dev = sq->channel->netdev;
1248         struct mlx5e_modify_sq_param msp = {0};
1249         int err;
1250
1251         msp.curr_state = curr_state;
1252         msp.next_state = MLX5_SQC_STATE_RST;
1253
1254         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1255         if (err) {
1256                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1257                 return err;
1258         }
1259
1260         memset(&msp, 0, sizeof(msp));
1261         msp.curr_state = MLX5_SQC_STATE_RST;
1262         msp.next_state = MLX5_SQC_STATE_RDY;
1263
1264         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1265         if (err) {
1266                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1267                 return err;
1268         }
1269
1270         return 0;
1271 }
1272
1273 static void mlx5e_sq_recover(struct work_struct *work)
1274 {
1275         struct mlx5e_txqsq_recover *recover =
1276                 container_of(work, struct mlx5e_txqsq_recover,
1277                              recover_work);
1278         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1279                                               recover);
1280         struct mlx5_core_dev *mdev = sq->channel->mdev;
1281         struct net_device *dev = sq->channel->netdev;
1282         u8 state;
1283         int err;
1284
1285         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1286         if (err) {
1287                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1288                            sq->sqn, err);
1289                 return;
1290         }
1291
1292         if (state != MLX5_RQC_STATE_ERR) {
1293                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1294                 return;
1295         }
1296
1297         netif_tx_disable_queue(sq->txq);
1298
1299         if (mlx5e_wait_for_sq_flush(sq))
1300                 return;
1301
1302         /* If the interval between two consecutive recovers per SQ is too
1303          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1304          * If we reached this state, there is probably a bug that needs to be
1305          * fixed. let's keep the queue close and let tx timeout cleanup.
1306          */
1307         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1308             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1309                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1310                            sq->sqn);
1311                 return;
1312         }
1313
1314         /* At this point, no new packets will arrive from the stack as TXQ is
1315          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1316          * pending WQEs.  SQ can safely reset the SQ.
1317          */
1318         if (mlx5e_sq_to_ready(sq, state))
1319                 return;
1320
1321         mlx5e_reset_txqsq_cc_pc(sq);
1322         sq->stats.recover++;
1323         recover->last_recover = jiffies;
1324         mlx5e_activate_txqsq(sq);
1325 }
1326
1327 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1328                             struct mlx5e_params *params,
1329                             struct mlx5e_sq_param *param,
1330                             struct mlx5e_icosq *sq)
1331 {
1332         struct mlx5e_create_sq_param csp = {};
1333         int err;
1334
1335         err = mlx5e_alloc_icosq(c, param, sq);
1336         if (err)
1337                 return err;
1338
1339         csp.cqn             = sq->cq.mcq.cqn;
1340         csp.wq_ctrl         = &sq->wq_ctrl;
1341         csp.min_inline_mode = params->tx_min_inline_mode;
1342         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1343         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1344         if (err)
1345                 goto err_free_icosq;
1346
1347         return 0;
1348
1349 err_free_icosq:
1350         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1351         mlx5e_free_icosq(sq);
1352
1353         return err;
1354 }
1355
1356 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1357 {
1358         struct mlx5e_channel *c = sq->channel;
1359
1360         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1361         napi_synchronize(&c->napi);
1362
1363         mlx5e_destroy_sq(c->mdev, sq->sqn);
1364         mlx5e_free_icosq(sq);
1365 }
1366
1367 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1368                             struct mlx5e_params *params,
1369                             struct mlx5e_sq_param *param,
1370                             struct mlx5e_xdpsq *sq)
1371 {
1372         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1373         struct mlx5e_create_sq_param csp = {};
1374         unsigned int inline_hdr_sz = 0;
1375         int err;
1376         int i;
1377
1378         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1379         if (err)
1380                 return err;
1381
1382         csp.tis_lst_sz      = 1;
1383         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1384         csp.cqn             = sq->cq.mcq.cqn;
1385         csp.wq_ctrl         = &sq->wq_ctrl;
1386         csp.min_inline_mode = sq->min_inline_mode;
1387         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1388         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1389         if (err)
1390                 goto err_free_xdpsq;
1391
1392         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1393                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1394                 ds_cnt++;
1395         }
1396
1397         /* Pre initialize fixed WQE fields */
1398         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1399                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1400                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1401                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1402                 struct mlx5_wqe_data_seg *dseg;
1403
1404                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1405                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1406
1407                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1408                 dseg->lkey = sq->mkey_be;
1409         }
1410
1411         return 0;
1412
1413 err_free_xdpsq:
1414         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1415         mlx5e_free_xdpsq(sq);
1416
1417         return err;
1418 }
1419
1420 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1421 {
1422         struct mlx5e_channel *c = sq->channel;
1423
1424         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1425         napi_synchronize(&c->napi);
1426
1427         mlx5e_destroy_sq(c->mdev, sq->sqn);
1428         mlx5e_free_xdpsq_descs(sq);
1429         mlx5e_free_xdpsq(sq);
1430 }
1431
1432 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1433                                  struct mlx5e_cq_param *param,
1434                                  struct mlx5e_cq *cq)
1435 {
1436         struct mlx5_core_cq *mcq = &cq->mcq;
1437         int eqn_not_used;
1438         unsigned int irqn;
1439         int err;
1440         u32 i;
1441
1442         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1443                                &cq->wq_ctrl);
1444         if (err)
1445                 return err;
1446
1447         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1448
1449         mcq->cqe_sz     = 64;
1450         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1451         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1452         *mcq->set_ci_db = 0;
1453         *mcq->arm_db    = 0;
1454         mcq->vector     = param->eq_ix;
1455         mcq->comp       = mlx5e_completion_event;
1456         mcq->event      = mlx5e_cq_error_event;
1457         mcq->irqn       = irqn;
1458
1459         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1460                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1461
1462                 cqe->op_own = 0xf1;
1463         }
1464
1465         cq->mdev = mdev;
1466
1467         return 0;
1468 }
1469
1470 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1471                           struct mlx5e_cq_param *param,
1472                           struct mlx5e_cq *cq)
1473 {
1474         struct mlx5_core_dev *mdev = c->priv->mdev;
1475         int err;
1476
1477         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1478         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1479         param->eq_ix   = c->ix;
1480
1481         err = mlx5e_alloc_cq_common(mdev, param, cq);
1482
1483         cq->napi    = &c->napi;
1484         cq->channel = c;
1485
1486         return err;
1487 }
1488
1489 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1490 {
1491         mlx5_cqwq_destroy(&cq->wq_ctrl);
1492 }
1493
1494 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1495 {
1496         struct mlx5_core_dev *mdev = cq->mdev;
1497         struct mlx5_core_cq *mcq = &cq->mcq;
1498
1499         void *in;
1500         void *cqc;
1501         int inlen;
1502         unsigned int irqn_not_used;
1503         int eqn;
1504         int err;
1505
1506         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1507                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1508         in = kvzalloc(inlen, GFP_KERNEL);
1509         if (!in)
1510                 return -ENOMEM;
1511
1512         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1513
1514         memcpy(cqc, param->cqc, sizeof(param->cqc));
1515
1516         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1517                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1518
1519         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1520
1521         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1522         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1523         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1524         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1525                                             MLX5_ADAPTER_PAGE_SHIFT);
1526         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1527
1528         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1529
1530         kvfree(in);
1531
1532         if (err)
1533                 return err;
1534
1535         mlx5e_cq_arm(cq);
1536
1537         return 0;
1538 }
1539
1540 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1541 {
1542         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1543 }
1544
1545 static int mlx5e_open_cq(struct mlx5e_channel *c,
1546                          struct net_dim_cq_moder moder,
1547                          struct mlx5e_cq_param *param,
1548                          struct mlx5e_cq *cq)
1549 {
1550         struct mlx5_core_dev *mdev = c->mdev;
1551         int err;
1552
1553         err = mlx5e_alloc_cq(c, param, cq);
1554         if (err)
1555                 return err;
1556
1557         err = mlx5e_create_cq(cq, param);
1558         if (err)
1559                 goto err_free_cq;
1560
1561         if (MLX5_CAP_GEN(mdev, cq_moderation))
1562                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1563         return 0;
1564
1565 err_free_cq:
1566         mlx5e_free_cq(cq);
1567
1568         return err;
1569 }
1570
1571 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1572 {
1573         mlx5e_destroy_cq(cq);
1574         mlx5e_free_cq(cq);
1575 }
1576
1577 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1578 {
1579         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1580 }
1581
1582 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1583                              struct mlx5e_params *params,
1584                              struct mlx5e_channel_param *cparam)
1585 {
1586         int err;
1587         int tc;
1588
1589         for (tc = 0; tc < c->num_tc; tc++) {
1590                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1591                                     &cparam->tx_cq, &c->sq[tc].cq);
1592                 if (err)
1593                         goto err_close_tx_cqs;
1594         }
1595
1596         return 0;
1597
1598 err_close_tx_cqs:
1599         for (tc--; tc >= 0; tc--)
1600                 mlx5e_close_cq(&c->sq[tc].cq);
1601
1602         return err;
1603 }
1604
1605 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1606 {
1607         int tc;
1608
1609         for (tc = 0; tc < c->num_tc; tc++)
1610                 mlx5e_close_cq(&c->sq[tc].cq);
1611 }
1612
1613 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1614                           struct mlx5e_params *params,
1615                           struct mlx5e_channel_param *cparam)
1616 {
1617         int err;
1618         int tc;
1619
1620         for (tc = 0; tc < params->num_tc; tc++) {
1621                 int txq_ix = c->ix + tc * params->num_channels;
1622
1623                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1624                                        params, &cparam->sq, &c->sq[tc]);
1625                 if (err)
1626                         goto err_close_sqs;
1627         }
1628
1629         return 0;
1630
1631 err_close_sqs:
1632         for (tc--; tc >= 0; tc--)
1633                 mlx5e_close_txqsq(&c->sq[tc]);
1634
1635         return err;
1636 }
1637
1638 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1639 {
1640         int tc;
1641
1642         for (tc = 0; tc < c->num_tc; tc++)
1643                 mlx5e_close_txqsq(&c->sq[tc]);
1644 }
1645
1646 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1647                                 struct mlx5e_txqsq *sq, u32 rate)
1648 {
1649         struct mlx5e_priv *priv = netdev_priv(dev);
1650         struct mlx5_core_dev *mdev = priv->mdev;
1651         struct mlx5e_modify_sq_param msp = {0};
1652         struct mlx5_rate_limit rl = {0};
1653         u16 rl_index = 0;
1654         int err;
1655
1656         if (rate == sq->rate_limit)
1657                 /* nothing to do */
1658                 return 0;
1659
1660         if (sq->rate_limit) {
1661                 rl.rate = sq->rate_limit;
1662                 /* remove current rl index to free space to next ones */
1663                 mlx5_rl_remove_rate(mdev, &rl);
1664         }
1665
1666         sq->rate_limit = 0;
1667
1668         if (rate) {
1669                 rl.rate = rate;
1670                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1671                 if (err) {
1672                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1673                                    rate, err);
1674                         return err;
1675                 }
1676         }
1677
1678         msp.curr_state = MLX5_SQC_STATE_RDY;
1679         msp.next_state = MLX5_SQC_STATE_RDY;
1680         msp.rl_index   = rl_index;
1681         msp.rl_update  = true;
1682         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1683         if (err) {
1684                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1685                            rate, err);
1686                 /* remove the rate from the table */
1687                 if (rate)
1688                         mlx5_rl_remove_rate(mdev, &rl);
1689                 return err;
1690         }
1691
1692         sq->rate_limit = rate;
1693         return 0;
1694 }
1695
1696 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1697 {
1698         struct mlx5e_priv *priv = netdev_priv(dev);
1699         struct mlx5_core_dev *mdev = priv->mdev;
1700         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1701         int err = 0;
1702
1703         if (!mlx5_rl_is_supported(mdev)) {
1704                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1705                 return -EINVAL;
1706         }
1707
1708         /* rate is given in Mb/sec, HW config is in Kb/sec */
1709         rate = rate << 10;
1710
1711         /* Check whether rate in valid range, 0 is always valid */
1712         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1713                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1714                 return -ERANGE;
1715         }
1716
1717         mutex_lock(&priv->state_lock);
1718         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1719                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1720         if (!err)
1721                 priv->tx_rates[index] = rate;
1722         mutex_unlock(&priv->state_lock);
1723
1724         return err;
1725 }
1726
1727 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1728                               struct mlx5e_params *params,
1729                               struct mlx5e_channel_param *cparam,
1730                               struct mlx5e_channel **cp)
1731 {
1732         struct net_dim_cq_moder icocq_moder = {0, 0};
1733         struct net_device *netdev = priv->netdev;
1734         int cpu = mlx5e_get_cpu(priv, ix);
1735         struct mlx5e_channel *c;
1736         unsigned int irq;
1737         int err;
1738         int eqn;
1739
1740         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1741         if (!c)
1742                 return -ENOMEM;
1743
1744         c->priv     = priv;
1745         c->mdev     = priv->mdev;
1746         c->tstamp   = &priv->tstamp;
1747         c->ix       = ix;
1748         c->cpu      = cpu;
1749         c->pdev     = &priv->mdev->pdev->dev;
1750         c->netdev   = priv->netdev;
1751         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1752         c->num_tc   = params->num_tc;
1753         c->xdp      = !!params->xdp_prog;
1754
1755         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1756         c->irq_desc = irq_to_desc(irq);
1757
1758         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1759
1760         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1761         if (err)
1762                 goto err_napi_del;
1763
1764         err = mlx5e_open_tx_cqs(c, params, cparam);
1765         if (err)
1766                 goto err_close_icosq_cq;
1767
1768         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1769         if (err)
1770                 goto err_close_tx_cqs;
1771
1772         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1773         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1774                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1775         if (err)
1776                 goto err_close_rx_cq;
1777
1778         napi_enable(&c->napi);
1779
1780         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1781         if (err)
1782                 goto err_disable_napi;
1783
1784         err = mlx5e_open_sqs(c, params, cparam);
1785         if (err)
1786                 goto err_close_icosq;
1787
1788         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1789         if (err)
1790                 goto err_close_sqs;
1791
1792         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1793         if (err)
1794                 goto err_close_xdp_sq;
1795
1796         *cp = c;
1797
1798         return 0;
1799 err_close_xdp_sq:
1800         if (c->xdp)
1801                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1802
1803 err_close_sqs:
1804         mlx5e_close_sqs(c);
1805
1806 err_close_icosq:
1807         mlx5e_close_icosq(&c->icosq);
1808
1809 err_disable_napi:
1810         napi_disable(&c->napi);
1811         if (c->xdp)
1812                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1813
1814 err_close_rx_cq:
1815         mlx5e_close_cq(&c->rq.cq);
1816
1817 err_close_tx_cqs:
1818         mlx5e_close_tx_cqs(c);
1819
1820 err_close_icosq_cq:
1821         mlx5e_close_cq(&c->icosq.cq);
1822
1823 err_napi_del:
1824         netif_napi_del(&c->napi);
1825         kfree(c);
1826
1827         return err;
1828 }
1829
1830 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1831 {
1832         int tc;
1833
1834         for (tc = 0; tc < c->num_tc; tc++)
1835                 mlx5e_activate_txqsq(&c->sq[tc]);
1836         mlx5e_activate_rq(&c->rq);
1837         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1838 }
1839
1840 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1841 {
1842         int tc;
1843
1844         mlx5e_deactivate_rq(&c->rq);
1845         for (tc = 0; tc < c->num_tc; tc++)
1846                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1847 }
1848
1849 static void mlx5e_close_channel(struct mlx5e_channel *c)
1850 {
1851         mlx5e_close_rq(&c->rq);
1852         if (c->xdp)
1853                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1854         mlx5e_close_sqs(c);
1855         mlx5e_close_icosq(&c->icosq);
1856         napi_disable(&c->napi);
1857         if (c->xdp)
1858                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1859         mlx5e_close_cq(&c->rq.cq);
1860         mlx5e_close_tx_cqs(c);
1861         mlx5e_close_cq(&c->icosq.cq);
1862         netif_napi_del(&c->napi);
1863
1864         kfree(c);
1865 }
1866
1867 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1868                                  struct mlx5e_params *params,
1869                                  struct mlx5e_rq_param *param)
1870 {
1871         struct mlx5_core_dev *mdev = priv->mdev;
1872         void *rqc = param->rqc;
1873         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1874
1875         switch (params->rq_wq_type) {
1876         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1877                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1878                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
1879                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
1880                 MLX5_SET(wq, wq, log_wqe_stride_size,
1881                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
1882                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
1883                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1884                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
1885                 break;
1886         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1887                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1888                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
1889         }
1890
1891         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1892         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1893         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
1894         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1895         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
1896         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
1897
1898         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1899 }
1900
1901 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
1902                                       struct mlx5e_rq_param *param)
1903 {
1904         struct mlx5_core_dev *mdev = priv->mdev;
1905         void *rqc = param->rqc;
1906         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1907
1908         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1909         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1910         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
1911
1912         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1913 }
1914
1915 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1916                                         struct mlx5e_sq_param *param)
1917 {
1918         void *sqc = param->sqc;
1919         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1920
1921         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1922         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1923
1924         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1925 }
1926
1927 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1928                                  struct mlx5e_params *params,
1929                                  struct mlx5e_sq_param *param)
1930 {
1931         void *sqc = param->sqc;
1932         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1933
1934         mlx5e_build_sq_param_common(priv, param);
1935         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1936         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1937 }
1938
1939 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1940                                         struct mlx5e_cq_param *param)
1941 {
1942         void *cqc = param->cqc;
1943
1944         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1945 }
1946
1947 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1948                                     struct mlx5e_params *params,
1949                                     struct mlx5e_cq_param *param)
1950 {
1951         struct mlx5_core_dev *mdev = priv->mdev;
1952         void *cqc = param->cqc;
1953         u8 log_cq_size;
1954
1955         switch (params->rq_wq_type) {
1956         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1957                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
1958                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
1959                 break;
1960         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1961                 log_cq_size = params->log_rq_mtu_frames;
1962         }
1963
1964         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1965         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1966                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1967                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1968         }
1969
1970         mlx5e_build_common_cq_param(priv, param);
1971         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
1972 }
1973
1974 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1975                                     struct mlx5e_params *params,
1976                                     struct mlx5e_cq_param *param)
1977 {
1978         void *cqc = param->cqc;
1979
1980         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1981
1982         mlx5e_build_common_cq_param(priv, param);
1983         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
1984 }
1985
1986 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1987                                      u8 log_wq_size,
1988                                      struct mlx5e_cq_param *param)
1989 {
1990         void *cqc = param->cqc;
1991
1992         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1993
1994         mlx5e_build_common_cq_param(priv, param);
1995
1996         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1997 }
1998
1999 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2000                                     u8 log_wq_size,
2001                                     struct mlx5e_sq_param *param)
2002 {
2003         void *sqc = param->sqc;
2004         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2005
2006         mlx5e_build_sq_param_common(priv, param);
2007
2008         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2009         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2010 }
2011
2012 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2013                                     struct mlx5e_params *params,
2014                                     struct mlx5e_sq_param *param)
2015 {
2016         void *sqc = param->sqc;
2017         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2018
2019         mlx5e_build_sq_param_common(priv, param);
2020         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2021 }
2022
2023 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2024                                       struct mlx5e_params *params,
2025                                       struct mlx5e_channel_param *cparam)
2026 {
2027         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2028
2029         mlx5e_build_rq_param(priv, params, &cparam->rq);
2030         mlx5e_build_sq_param(priv, params, &cparam->sq);
2031         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2032         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2033         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2034         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2035         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2036 }
2037
2038 int mlx5e_open_channels(struct mlx5e_priv *priv,
2039                         struct mlx5e_channels *chs)
2040 {
2041         struct mlx5e_channel_param *cparam;
2042         int err = -ENOMEM;
2043         int i;
2044
2045         chs->num = chs->params.num_channels;
2046
2047         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2048         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2049         if (!chs->c || !cparam)
2050                 goto err_free;
2051
2052         mlx5e_build_channel_param(priv, &chs->params, cparam);
2053         for (i = 0; i < chs->num; i++) {
2054                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2055                 if (err)
2056                         goto err_close_channels;
2057         }
2058
2059         kfree(cparam);
2060         return 0;
2061
2062 err_close_channels:
2063         for (i--; i >= 0; i--)
2064                 mlx5e_close_channel(chs->c[i]);
2065
2066 err_free:
2067         kfree(chs->c);
2068         kfree(cparam);
2069         chs->num = 0;
2070         return err;
2071 }
2072
2073 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2074 {
2075         int i;
2076
2077         for (i = 0; i < chs->num; i++)
2078                 mlx5e_activate_channel(chs->c[i]);
2079 }
2080
2081 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2082 {
2083         int err = 0;
2084         int i;
2085
2086         for (i = 0; i < chs->num; i++) {
2087                 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2088                 if (err)
2089                         break;
2090         }
2091
2092         return err;
2093 }
2094
2095 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2096 {
2097         int i;
2098
2099         for (i = 0; i < chs->num; i++)
2100                 mlx5e_deactivate_channel(chs->c[i]);
2101 }
2102
2103 void mlx5e_close_channels(struct mlx5e_channels *chs)
2104 {
2105         int i;
2106
2107         for (i = 0; i < chs->num; i++)
2108                 mlx5e_close_channel(chs->c[i]);
2109
2110         kfree(chs->c);
2111         chs->num = 0;
2112 }
2113
2114 static int
2115 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2116 {
2117         struct mlx5_core_dev *mdev = priv->mdev;
2118         void *rqtc;
2119         int inlen;
2120         int err;
2121         u32 *in;
2122         int i;
2123
2124         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2125         in = kvzalloc(inlen, GFP_KERNEL);
2126         if (!in)
2127                 return -ENOMEM;
2128
2129         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2130
2131         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2132         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2133
2134         for (i = 0; i < sz; i++)
2135                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2136
2137         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2138         if (!err)
2139                 rqt->enabled = true;
2140
2141         kvfree(in);
2142         return err;
2143 }
2144
2145 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2146 {
2147         rqt->enabled = false;
2148         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2149 }
2150
2151 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2152 {
2153         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2154         int err;
2155
2156         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2157         if (err)
2158                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2159         return err;
2160 }
2161
2162 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2163 {
2164         struct mlx5e_rqt *rqt;
2165         int err;
2166         int ix;
2167
2168         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2169                 rqt = &priv->direct_tir[ix].rqt;
2170                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2171                 if (err)
2172                         goto err_destroy_rqts;
2173         }
2174
2175         return 0;
2176
2177 err_destroy_rqts:
2178         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2179         for (ix--; ix >= 0; ix--)
2180                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2181
2182         return err;
2183 }
2184
2185 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2186 {
2187         int i;
2188
2189         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2190                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2191 }
2192
2193 static int mlx5e_rx_hash_fn(int hfunc)
2194 {
2195         return (hfunc == ETH_RSS_HASH_TOP) ?
2196                MLX5_RX_HASH_FN_TOEPLITZ :
2197                MLX5_RX_HASH_FN_INVERTED_XOR8;
2198 }
2199
2200 int mlx5e_bits_invert(unsigned long a, int size)
2201 {
2202         int inv = 0;
2203         int i;
2204
2205         for (i = 0; i < size; i++)
2206                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2207
2208         return inv;
2209 }
2210
2211 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2212                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2213 {
2214         int i;
2215
2216         for (i = 0; i < sz; i++) {
2217                 u32 rqn;
2218
2219                 if (rrp.is_rss) {
2220                         int ix = i;
2221
2222                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2223                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2224
2225                         ix = priv->channels.params.indirection_rqt[ix];
2226                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2227                 } else {
2228                         rqn = rrp.rqn;
2229                 }
2230                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2231         }
2232 }
2233
2234 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2235                        struct mlx5e_redirect_rqt_param rrp)
2236 {
2237         struct mlx5_core_dev *mdev = priv->mdev;
2238         void *rqtc;
2239         int inlen;
2240         u32 *in;
2241         int err;
2242
2243         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2244         in = kvzalloc(inlen, GFP_KERNEL);
2245         if (!in)
2246                 return -ENOMEM;
2247
2248         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2249
2250         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2251         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2252         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2253         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2254
2255         kvfree(in);
2256         return err;
2257 }
2258
2259 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2260                                 struct mlx5e_redirect_rqt_param rrp)
2261 {
2262         if (!rrp.is_rss)
2263                 return rrp.rqn;
2264
2265         if (ix >= rrp.rss.channels->num)
2266                 return priv->drop_rq.rqn;
2267
2268         return rrp.rss.channels->c[ix]->rq.rqn;
2269 }
2270
2271 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2272                                 struct mlx5e_redirect_rqt_param rrp)
2273 {
2274         u32 rqtn;
2275         int ix;
2276
2277         if (priv->indir_rqt.enabled) {
2278                 /* RSS RQ table */
2279                 rqtn = priv->indir_rqt.rqtn;
2280                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2281         }
2282
2283         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2284                 struct mlx5e_redirect_rqt_param direct_rrp = {
2285                         .is_rss = false,
2286                         {
2287                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2288                         },
2289                 };
2290
2291                 /* Direct RQ Tables */
2292                 if (!priv->direct_tir[ix].rqt.enabled)
2293                         continue;
2294
2295                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2296                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2297         }
2298 }
2299
2300 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2301                                             struct mlx5e_channels *chs)
2302 {
2303         struct mlx5e_redirect_rqt_param rrp = {
2304                 .is_rss        = true,
2305                 {
2306                         .rss = {
2307                                 .channels  = chs,
2308                                 .hfunc     = chs->params.rss_hfunc,
2309                         }
2310                 },
2311         };
2312
2313         mlx5e_redirect_rqts(priv, rrp);
2314 }
2315
2316 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2317 {
2318         struct mlx5e_redirect_rqt_param drop_rrp = {
2319                 .is_rss = false,
2320                 {
2321                         .rqn = priv->drop_rq.rqn,
2322                 },
2323         };
2324
2325         mlx5e_redirect_rqts(priv, drop_rrp);
2326 }
2327
2328 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2329 {
2330         if (!params->lro_en)
2331                 return;
2332
2333 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2334
2335         MLX5_SET(tirc, tirc, lro_enable_mask,
2336                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2337                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2338         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2339                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2340         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2341 }
2342
2343 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2344                                     enum mlx5e_traffic_types tt,
2345                                     void *tirc, bool inner)
2346 {
2347         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2348                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2349
2350 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2351                                  MLX5_HASH_FIELD_SEL_DST_IP)
2352
2353 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2354                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2355                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2356                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2357
2358 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2359                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2360                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2361
2362         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2363         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2364                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2365                                              rx_hash_toeplitz_key);
2366                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2367                                                rx_hash_toeplitz_key);
2368
2369                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2370                 memcpy(rss_key, params->toeplitz_hash_key, len);
2371         }
2372
2373         switch (tt) {
2374         case MLX5E_TT_IPV4_TCP:
2375                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2376                          MLX5_L3_PROT_TYPE_IPV4);
2377                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2378                          MLX5_L4_PROT_TYPE_TCP);
2379                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2380                          MLX5_HASH_IP_L4PORTS);
2381                 break;
2382
2383         case MLX5E_TT_IPV6_TCP:
2384                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2385                          MLX5_L3_PROT_TYPE_IPV6);
2386                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2387                          MLX5_L4_PROT_TYPE_TCP);
2388                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2389                          MLX5_HASH_IP_L4PORTS);
2390                 break;
2391
2392         case MLX5E_TT_IPV4_UDP:
2393                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2394                          MLX5_L3_PROT_TYPE_IPV4);
2395                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2396                          MLX5_L4_PROT_TYPE_UDP);
2397                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2398                          MLX5_HASH_IP_L4PORTS);
2399                 break;
2400
2401         case MLX5E_TT_IPV6_UDP:
2402                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2403                          MLX5_L3_PROT_TYPE_IPV6);
2404                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2405                          MLX5_L4_PROT_TYPE_UDP);
2406                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2407                          MLX5_HASH_IP_L4PORTS);
2408                 break;
2409
2410         case MLX5E_TT_IPV4_IPSEC_AH:
2411                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2412                          MLX5_L3_PROT_TYPE_IPV4);
2413                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2414                          MLX5_HASH_IP_IPSEC_SPI);
2415                 break;
2416
2417         case MLX5E_TT_IPV6_IPSEC_AH:
2418                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2419                          MLX5_L3_PROT_TYPE_IPV6);
2420                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2421                          MLX5_HASH_IP_IPSEC_SPI);
2422                 break;
2423
2424         case MLX5E_TT_IPV4_IPSEC_ESP:
2425                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2426                          MLX5_L3_PROT_TYPE_IPV4);
2427                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2428                          MLX5_HASH_IP_IPSEC_SPI);
2429                 break;
2430
2431         case MLX5E_TT_IPV6_IPSEC_ESP:
2432                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2433                          MLX5_L3_PROT_TYPE_IPV6);
2434                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2435                          MLX5_HASH_IP_IPSEC_SPI);
2436                 break;
2437
2438         case MLX5E_TT_IPV4:
2439                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2440                          MLX5_L3_PROT_TYPE_IPV4);
2441                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2442                          MLX5_HASH_IP);
2443                 break;
2444
2445         case MLX5E_TT_IPV6:
2446                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2447                          MLX5_L3_PROT_TYPE_IPV6);
2448                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2449                          MLX5_HASH_IP);
2450                 break;
2451         default:
2452                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2453         }
2454 }
2455
2456 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2457 {
2458         struct mlx5_core_dev *mdev = priv->mdev;
2459
2460         void *in;
2461         void *tirc;
2462         int inlen;
2463         int err;
2464         int tt;
2465         int ix;
2466
2467         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2468         in = kvzalloc(inlen, GFP_KERNEL);
2469         if (!in)
2470                 return -ENOMEM;
2471
2472         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2473         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2474
2475         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2476
2477         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2478                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2479                                            inlen);
2480                 if (err)
2481                         goto free_in;
2482         }
2483
2484         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2485                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2486                                            in, inlen);
2487                 if (err)
2488                         goto free_in;
2489         }
2490
2491 free_in:
2492         kvfree(in);
2493
2494         return err;
2495 }
2496
2497 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2498                                             enum mlx5e_traffic_types tt,
2499                                             u32 *tirc)
2500 {
2501         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2502
2503         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2504
2505         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2506         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2507         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2508
2509         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2510 }
2511
2512 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2513                          struct mlx5e_params *params, u16 mtu)
2514 {
2515         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2516         int err;
2517
2518         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2519         if (err)
2520                 return err;
2521
2522         /* Update vport context MTU */
2523         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2524         return 0;
2525 }
2526
2527 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2528                             struct mlx5e_params *params, u16 *mtu)
2529 {
2530         u16 hw_mtu = 0;
2531         int err;
2532
2533         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2534         if (err || !hw_mtu) /* fallback to port oper mtu */
2535                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2536
2537         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2538 }
2539
2540 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2541 {
2542         struct mlx5e_params *params = &priv->channels.params;
2543         struct net_device *netdev = priv->netdev;
2544         struct mlx5_core_dev *mdev = priv->mdev;
2545         u16 mtu;
2546         int err;
2547
2548         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2549         if (err)
2550                 return err;
2551
2552         mlx5e_query_mtu(mdev, params, &mtu);
2553         if (mtu != params->sw_mtu)
2554                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2555                             __func__, mtu, params->sw_mtu);
2556
2557         params->sw_mtu = mtu;
2558         return 0;
2559 }
2560
2561 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2562 {
2563         struct mlx5e_priv *priv = netdev_priv(netdev);
2564         int nch = priv->channels.params.num_channels;
2565         int ntc = priv->channels.params.num_tc;
2566         int tc;
2567
2568         netdev_reset_tc(netdev);
2569
2570         if (ntc == 1)
2571                 return;
2572
2573         netdev_set_num_tc(netdev, ntc);
2574
2575         /* Map netdev TCs to offset 0
2576          * We have our own UP to TXQ mapping for QoS
2577          */
2578         for (tc = 0; tc < ntc; tc++)
2579                 netdev_set_tc_queue(netdev, tc, nch, 0);
2580 }
2581
2582 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2583 {
2584         struct mlx5e_channel *c;
2585         struct mlx5e_txqsq *sq;
2586         int i, tc;
2587
2588         for (i = 0; i < priv->channels.num; i++)
2589                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2590                         priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2591
2592         for (i = 0; i < priv->channels.num; i++) {
2593                 c = priv->channels.c[i];
2594                 for (tc = 0; tc < c->num_tc; tc++) {
2595                         sq = &c->sq[tc];
2596                         priv->txq2sq[sq->txq_ix] = sq;
2597                 }
2598         }
2599 }
2600
2601 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2602 {
2603         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2604         struct net_device *netdev = priv->netdev;
2605
2606         mlx5e_netdev_set_tcs(netdev);
2607         netif_set_real_num_tx_queues(netdev, num_txqs);
2608         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2609
2610         mlx5e_build_channels_tx_maps(priv);
2611         mlx5e_activate_channels(&priv->channels);
2612         netif_tx_start_all_queues(priv->netdev);
2613
2614         if (MLX5_VPORT_MANAGER(priv->mdev))
2615                 mlx5e_add_sqs_fwd_rules(priv);
2616
2617         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2618         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2619 }
2620
2621 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2622 {
2623         mlx5e_redirect_rqts_to_drop(priv);
2624
2625         if (MLX5_VPORT_MANAGER(priv->mdev))
2626                 mlx5e_remove_sqs_fwd_rules(priv);
2627
2628         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2629          * polling for inactive tx queues.
2630          */
2631         netif_tx_stop_all_queues(priv->netdev);
2632         netif_tx_disable(priv->netdev);
2633         mlx5e_deactivate_channels(&priv->channels);
2634 }
2635
2636 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2637                                 struct mlx5e_channels *new_chs,
2638                                 mlx5e_fp_hw_modify hw_modify)
2639 {
2640         struct net_device *netdev = priv->netdev;
2641         int new_num_txqs;
2642         int carrier_ok;
2643         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2644
2645         carrier_ok = netif_carrier_ok(netdev);
2646         netif_carrier_off(netdev);
2647
2648         if (new_num_txqs < netdev->real_num_tx_queues)
2649                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2650
2651         mlx5e_deactivate_priv_channels(priv);
2652         mlx5e_close_channels(&priv->channels);
2653
2654         priv->channels = *new_chs;
2655
2656         /* New channels are ready to roll, modify HW settings if needed */
2657         if (hw_modify)
2658                 hw_modify(priv);
2659
2660         mlx5e_refresh_tirs(priv, false);
2661         mlx5e_activate_priv_channels(priv);
2662
2663         /* return carrier back if needed */
2664         if (carrier_ok)
2665                 netif_carrier_on(netdev);
2666 }
2667
2668 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2669 {
2670         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2671         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2672 }
2673
2674 int mlx5e_open_locked(struct net_device *netdev)
2675 {
2676         struct mlx5e_priv *priv = netdev_priv(netdev);
2677         int err;
2678
2679         set_bit(MLX5E_STATE_OPENED, &priv->state);
2680
2681         err = mlx5e_open_channels(priv, &priv->channels);
2682         if (err)
2683                 goto err_clear_state_opened_flag;
2684
2685         mlx5e_refresh_tirs(priv, false);
2686         mlx5e_activate_priv_channels(priv);
2687         if (priv->profile->update_carrier)
2688                 priv->profile->update_carrier(priv);
2689
2690         if (priv->profile->update_stats)
2691                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2692
2693         return 0;
2694
2695 err_clear_state_opened_flag:
2696         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2697         return err;
2698 }
2699
2700 int mlx5e_open(struct net_device *netdev)
2701 {
2702         struct mlx5e_priv *priv = netdev_priv(netdev);
2703         int err;
2704
2705         mutex_lock(&priv->state_lock);
2706         err = mlx5e_open_locked(netdev);
2707         if (!err)
2708                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2709         mutex_unlock(&priv->state_lock);
2710
2711         if (mlx5e_vxlan_allowed(priv->mdev))
2712                 udp_tunnel_get_rx_info(netdev);
2713
2714         return err;
2715 }
2716
2717 int mlx5e_close_locked(struct net_device *netdev)
2718 {
2719         struct mlx5e_priv *priv = netdev_priv(netdev);
2720
2721         /* May already be CLOSED in case a previous configuration operation
2722          * (e.g RX/TX queue size change) that involves close&open failed.
2723          */
2724         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2725                 return 0;
2726
2727         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2728
2729         netif_carrier_off(priv->netdev);
2730         mlx5e_deactivate_priv_channels(priv);
2731         mlx5e_close_channels(&priv->channels);
2732
2733         return 0;
2734 }
2735
2736 int mlx5e_close(struct net_device *netdev)
2737 {
2738         struct mlx5e_priv *priv = netdev_priv(netdev);
2739         int err;
2740
2741         if (!netif_device_present(netdev))
2742                 return -ENODEV;
2743
2744         mutex_lock(&priv->state_lock);
2745         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2746         err = mlx5e_close_locked(netdev);
2747         mutex_unlock(&priv->state_lock);
2748
2749         return err;
2750 }
2751
2752 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2753                                struct mlx5e_rq *rq,
2754                                struct mlx5e_rq_param *param)
2755 {
2756         void *rqc = param->rqc;
2757         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2758         int err;
2759
2760         param->wq.db_numa_node = param->wq.buf_numa_node;
2761
2762         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2763                                 &rq->wq_ctrl);
2764         if (err)
2765                 return err;
2766
2767         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2768         xdp_rxq_info_unused(&rq->xdp_rxq);
2769
2770         rq->mdev = mdev;
2771
2772         return 0;
2773 }
2774
2775 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2776                                struct mlx5e_cq *cq,
2777                                struct mlx5e_cq_param *param)
2778 {
2779         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2780         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
2781
2782         return mlx5e_alloc_cq_common(mdev, param, cq);
2783 }
2784
2785 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2786                               struct mlx5e_rq *drop_rq)
2787 {
2788         struct mlx5_core_dev *mdev = priv->mdev;
2789         struct mlx5e_cq_param cq_param = {};
2790         struct mlx5e_rq_param rq_param = {};
2791         struct mlx5e_cq *cq = &drop_rq->cq;
2792         int err;
2793
2794         mlx5e_build_drop_rq_param(priv, &rq_param);
2795
2796         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2797         if (err)
2798                 return err;
2799
2800         err = mlx5e_create_cq(cq, &cq_param);
2801         if (err)
2802                 goto err_free_cq;
2803
2804         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2805         if (err)
2806                 goto err_destroy_cq;
2807
2808         err = mlx5e_create_rq(drop_rq, &rq_param);
2809         if (err)
2810                 goto err_free_rq;
2811
2812         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2813         if (err)
2814                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2815
2816         return 0;
2817
2818 err_free_rq:
2819         mlx5e_free_rq(drop_rq);
2820
2821 err_destroy_cq:
2822         mlx5e_destroy_cq(cq);
2823
2824 err_free_cq:
2825         mlx5e_free_cq(cq);
2826
2827         return err;
2828 }
2829
2830 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2831 {
2832         mlx5e_destroy_rq(drop_rq);
2833         mlx5e_free_rq(drop_rq);
2834         mlx5e_destroy_cq(&drop_rq->cq);
2835         mlx5e_free_cq(&drop_rq->cq);
2836 }
2837
2838 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2839                      u32 underlay_qpn, u32 *tisn)
2840 {
2841         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2842         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2843
2844         MLX5_SET(tisc, tisc, prio, tc << 1);
2845         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2846         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2847
2848         if (mlx5_lag_is_lacp_owner(mdev))
2849                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2850
2851         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2852 }
2853
2854 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2855 {
2856         mlx5_core_destroy_tis(mdev, tisn);
2857 }
2858
2859 int mlx5e_create_tises(struct mlx5e_priv *priv)
2860 {
2861         int err;
2862         int tc;
2863
2864         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2865                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2866                 if (err)
2867                         goto err_close_tises;
2868         }
2869
2870         return 0;
2871
2872 err_close_tises:
2873         for (tc--; tc >= 0; tc--)
2874                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2875
2876         return err;
2877 }
2878
2879 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2880 {
2881         int tc;
2882
2883         for (tc = 0; tc < priv->profile->max_tc; tc++)
2884                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2885 }
2886
2887 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2888                                       enum mlx5e_traffic_types tt,
2889                                       u32 *tirc)
2890 {
2891         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2892
2893         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2894
2895         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2896         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2897         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2898 }
2899
2900 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2901 {
2902         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2903
2904         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2905
2906         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2907         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2908         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2909 }
2910
2911 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2912 {
2913         struct mlx5e_tir *tir;
2914         void *tirc;
2915         int inlen;
2916         int i = 0;
2917         int err;
2918         u32 *in;
2919         int tt;
2920
2921         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2922         in = kvzalloc(inlen, GFP_KERNEL);
2923         if (!in)
2924                 return -ENOMEM;
2925
2926         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2927                 memset(in, 0, inlen);
2928                 tir = &priv->indir_tir[tt];
2929                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2930                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2931                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2932                 if (err) {
2933                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2934                         goto err_destroy_inner_tirs;
2935                 }
2936         }
2937
2938         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2939                 goto out;
2940
2941         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2942                 memset(in, 0, inlen);
2943                 tir = &priv->inner_indir_tir[i];
2944                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2945                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2946                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2947                 if (err) {
2948                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2949                         goto err_destroy_inner_tirs;
2950                 }
2951         }
2952
2953 out:
2954         kvfree(in);
2955
2956         return 0;
2957
2958 err_destroy_inner_tirs:
2959         for (i--; i >= 0; i--)
2960                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2961
2962         for (tt--; tt >= 0; tt--)
2963                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2964
2965         kvfree(in);
2966
2967         return err;
2968 }
2969
2970 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2971 {
2972         int nch = priv->profile->max_nch(priv->mdev);
2973         struct mlx5e_tir *tir;
2974         void *tirc;
2975         int inlen;
2976         int err;
2977         u32 *in;
2978         int ix;
2979
2980         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2981         in = kvzalloc(inlen, GFP_KERNEL);
2982         if (!in)
2983                 return -ENOMEM;
2984
2985         for (ix = 0; ix < nch; ix++) {
2986                 memset(in, 0, inlen);
2987                 tir = &priv->direct_tir[ix];
2988                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2989                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2990                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2991                 if (err)
2992                         goto err_destroy_ch_tirs;
2993         }
2994
2995         kvfree(in);
2996
2997         return 0;
2998
2999 err_destroy_ch_tirs:
3000         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3001         for (ix--; ix >= 0; ix--)
3002                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3003
3004         kvfree(in);
3005
3006         return err;
3007 }
3008
3009 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3010 {
3011         int i;
3012
3013         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3014                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3015
3016         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3017                 return;
3018
3019         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3020                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3021 }
3022
3023 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3024 {
3025         int nch = priv->profile->max_nch(priv->mdev);
3026         int i;
3027
3028         for (i = 0; i < nch; i++)
3029                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3030 }
3031
3032 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3033 {
3034         int err = 0;
3035         int i;
3036
3037         for (i = 0; i < chs->num; i++) {
3038                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3039                 if (err)
3040                         return err;
3041         }
3042
3043         return 0;
3044 }
3045
3046 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3047 {
3048         int err = 0;
3049         int i;
3050
3051         for (i = 0; i < chs->num; i++) {
3052                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3053                 if (err)
3054                         return err;
3055         }
3056
3057         return 0;
3058 }
3059
3060 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3061                                  struct tc_mqprio_qopt *mqprio)
3062 {
3063         struct mlx5e_priv *priv = netdev_priv(netdev);
3064         struct mlx5e_channels new_channels = {};
3065         u8 tc = mqprio->num_tc;
3066         int err = 0;
3067
3068         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3069
3070         if (tc && tc != MLX5E_MAX_NUM_TC)
3071                 return -EINVAL;
3072
3073         mutex_lock(&priv->state_lock);
3074
3075         new_channels.params = priv->channels.params;
3076         new_channels.params.num_tc = tc ? tc : 1;
3077
3078         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3079                 priv->channels.params = new_channels.params;
3080                 goto out;
3081         }
3082
3083         err = mlx5e_open_channels(priv, &new_channels);
3084         if (err)
3085                 goto out;
3086
3087         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3088 out:
3089         mutex_unlock(&priv->state_lock);
3090         return err;
3091 }
3092
3093 #ifdef CONFIG_MLX5_ESWITCH
3094 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3095                                      struct tc_cls_flower_offload *cls_flower)
3096 {
3097         switch (cls_flower->command) {
3098         case TC_CLSFLOWER_REPLACE:
3099                 return mlx5e_configure_flower(priv, cls_flower);
3100         case TC_CLSFLOWER_DESTROY:
3101                 return mlx5e_delete_flower(priv, cls_flower);
3102         case TC_CLSFLOWER_STATS:
3103                 return mlx5e_stats_flower(priv, cls_flower);
3104         default: