net/mlx5e: Add per priority group to PPort counters
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include "en.h"
38 #include "en_tc.h"
39 #include "eswitch.h"
40 #include "vxlan.h"
41
42 struct mlx5e_rq_param {
43         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
44         struct mlx5_wq_param       wq;
45 };
46
47 struct mlx5e_sq_param {
48         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
49         struct mlx5_wq_param       wq;
50         u16                        max_inline;
51         bool                       icosq;
52 };
53
54 struct mlx5e_cq_param {
55         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
56         struct mlx5_wq_param       wq;
57         u16                        eq_ix;
58 };
59
60 struct mlx5e_channel_param {
61         struct mlx5e_rq_param      rq;
62         struct mlx5e_sq_param      sq;
63         struct mlx5e_sq_param      icosq;
64         struct mlx5e_cq_param      rx_cq;
65         struct mlx5e_cq_param      tx_cq;
66         struct mlx5e_cq_param      icosq_cq;
67 };
68
69 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
70 {
71         struct mlx5_core_dev *mdev = priv->mdev;
72         u8 port_state;
73
74         port_state = mlx5_query_vport_state(mdev,
75                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
76
77         if (port_state == VPORT_STATE_UP)
78                 netif_carrier_on(priv->netdev);
79         else
80                 netif_carrier_off(priv->netdev);
81 }
82
83 static void mlx5e_update_carrier_work(struct work_struct *work)
84 {
85         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
86                                                update_carrier_work);
87
88         mutex_lock(&priv->state_lock);
89         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
90                 mlx5e_update_carrier(priv);
91         mutex_unlock(&priv->state_lock);
92 }
93
94 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
95 {
96         struct mlx5e_sw_stats *s = &priv->stats.sw;
97         struct mlx5e_rq_stats *rq_stats;
98         struct mlx5e_sq_stats *sq_stats;
99         u64 tx_offload_none = 0;
100         int i, j;
101
102         memset(s, 0, sizeof(*s));
103         for (i = 0; i < priv->params.num_channels; i++) {
104                 rq_stats = &priv->channel[i]->rq.stats;
105
106                 s->rx_packets   += rq_stats->packets;
107                 s->rx_bytes     += rq_stats->bytes;
108                 s->lro_packets  += rq_stats->lro_packets;
109                 s->lro_bytes    += rq_stats->lro_bytes;
110                 s->rx_csum_none += rq_stats->csum_none;
111                 s->rx_csum_sw   += rq_stats->csum_sw;
112                 s->rx_wqe_err   += rq_stats->wqe_err;
113                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
114                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
115                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
116
117                 for (j = 0; j < priv->params.num_tc; j++) {
118                         sq_stats = &priv->channel[i]->sq[j].stats;
119
120                         s->tx_packets           += sq_stats->packets;
121                         s->tx_bytes             += sq_stats->bytes;
122                         s->tso_packets          += sq_stats->tso_packets;
123                         s->tso_bytes            += sq_stats->tso_bytes;
124                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
125                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
126                         s->tx_queue_stopped     += sq_stats->stopped;
127                         s->tx_queue_wake        += sq_stats->wake;
128                         s->tx_queue_dropped     += sq_stats->dropped;
129                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
130                         tx_offload_none         += sq_stats->csum_offload_none;
131                 }
132         }
133
134         /* Update calculated offload counters */
135         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
136         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
137                              s->rx_csum_sw;
138 }
139
140 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
141 {
142         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
143         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
144         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
145         struct mlx5_core_dev *mdev = priv->mdev;
146
147         memset(in, 0, sizeof(in));
148
149         MLX5_SET(query_vport_counter_in, in, opcode,
150                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
151         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
152         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
153
154         memset(out, 0, outlen);
155
156         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
157 }
158
159 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
160 {
161         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
162         struct mlx5_core_dev *mdev = priv->mdev;
163         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
164         int prio;
165         void *out;
166         u32 *in;
167
168         in = mlx5_vzalloc(sz);
169         if (!in)
170                 goto free_out;
171
172         MLX5_SET(ppcnt_reg, in, local_port, 1);
173
174         out = pstats->IEEE_802_3_counters;
175         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
176         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
177
178         out = pstats->RFC_2863_counters;
179         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
180         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
181
182         out = pstats->RFC_2819_counters;
183         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
184         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
185
186         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
187         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
188                 out = pstats->per_prio_counters[prio];
189                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
190                 mlx5_core_access_reg(mdev, in, sz, out, sz,
191                                      MLX5_REG_PPCNT, 0, 0);
192         }
193
194 free_out:
195         kvfree(in);
196 }
197
198 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
199 {
200         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
201
202         if (!priv->q_counter)
203                 return;
204
205         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
206                                       &qcnt->rx_out_of_buffer);
207 }
208
209 void mlx5e_update_stats(struct mlx5e_priv *priv)
210 {
211         mlx5e_update_sw_counters(priv);
212         mlx5e_update_q_counter(priv);
213         mlx5e_update_vport_counters(priv);
214         mlx5e_update_pport_counters(priv);
215 }
216
217 static void mlx5e_update_stats_work(struct work_struct *work)
218 {
219         struct delayed_work *dwork = to_delayed_work(work);
220         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
221                                                update_stats_work);
222         mutex_lock(&priv->state_lock);
223         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
224                 mlx5e_update_stats(priv);
225                 schedule_delayed_work(dwork,
226                                       msecs_to_jiffies(
227                                               MLX5E_UPDATE_STATS_INTERVAL));
228         }
229         mutex_unlock(&priv->state_lock);
230 }
231
232 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
233                               enum mlx5_dev_event event, unsigned long param)
234 {
235         struct mlx5e_priv *priv = vpriv;
236
237         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
238                 return;
239
240         switch (event) {
241         case MLX5_DEV_EVENT_PORT_UP:
242         case MLX5_DEV_EVENT_PORT_DOWN:
243                 schedule_work(&priv->update_carrier_work);
244                 break;
245
246         default:
247                 break;
248         }
249 }
250
251 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
252 {
253         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
254 }
255
256 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
257 {
258         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
259         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
260 }
261
262 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
263 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
264
265 static int mlx5e_create_rq(struct mlx5e_channel *c,
266                            struct mlx5e_rq_param *param,
267                            struct mlx5e_rq *rq)
268 {
269         struct mlx5e_priv *priv = c->priv;
270         struct mlx5_core_dev *mdev = priv->mdev;
271         void *rqc = param->rqc;
272         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
273         u32 byte_count;
274         int wq_sz;
275         int err;
276         int i;
277
278         param->wq.db_numa_node = cpu_to_node(c->cpu);
279
280         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
281                                 &rq->wq_ctrl);
282         if (err)
283                 return err;
284
285         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
286
287         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
288
289         switch (priv->params.rq_wq_type) {
290         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
291                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
292                                             GFP_KERNEL, cpu_to_node(c->cpu));
293                 if (!rq->wqe_info) {
294                         err = -ENOMEM;
295                         goto err_rq_wq_destroy;
296                 }
297                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
298                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
299
300                 rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE;
301                 byte_count = rq->wqe_sz;
302                 break;
303         default: /* MLX5_WQ_TYPE_LINKED_LIST */
304                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
305                                        cpu_to_node(c->cpu));
306                 if (!rq->skb) {
307                         err = -ENOMEM;
308                         goto err_rq_wq_destroy;
309                 }
310                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
311                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
312
313                 rq->wqe_sz = (priv->params.lro_en) ?
314                                 priv->params.lro_wqe_sz :
315                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
316                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
317                 byte_count = rq->wqe_sz;
318                 byte_count |= MLX5_HW_START_PADDING;
319         }
320
321         for (i = 0; i < wq_sz; i++) {
322                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
323
324                 wqe->data.byte_count = cpu_to_be32(byte_count);
325         }
326
327         rq->wq_type = priv->params.rq_wq_type;
328         rq->pdev    = c->pdev;
329         rq->netdev  = c->netdev;
330         rq->tstamp  = &priv->tstamp;
331         rq->channel = c;
332         rq->ix      = c->ix;
333         rq->priv    = c->priv;
334         rq->mkey_be = c->mkey_be;
335         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
336
337         return 0;
338
339 err_rq_wq_destroy:
340         mlx5_wq_destroy(&rq->wq_ctrl);
341
342         return err;
343 }
344
345 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
346 {
347         switch (rq->wq_type) {
348         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
349                 kfree(rq->wqe_info);
350                 break;
351         default: /* MLX5_WQ_TYPE_LINKED_LIST */
352                 kfree(rq->skb);
353         }
354
355         mlx5_wq_destroy(&rq->wq_ctrl);
356 }
357
358 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
359 {
360         struct mlx5e_priv *priv = rq->priv;
361         struct mlx5_core_dev *mdev = priv->mdev;
362
363         void *in;
364         void *rqc;
365         void *wq;
366         int inlen;
367         int err;
368
369         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
370                 sizeof(u64) * rq->wq_ctrl.buf.npages;
371         in = mlx5_vzalloc(inlen);
372         if (!in)
373                 return -ENOMEM;
374
375         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
376         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
377
378         memcpy(rqc, param->rqc, sizeof(param->rqc));
379
380         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
381         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
382         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
383         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
384                                                 MLX5_ADAPTER_PAGE_SHIFT);
385         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
386
387         mlx5_fill_page_array(&rq->wq_ctrl.buf,
388                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
389
390         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
391
392         kvfree(in);
393
394         return err;
395 }
396
397 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
398 {
399         struct mlx5e_channel *c = rq->channel;
400         struct mlx5e_priv *priv = c->priv;
401         struct mlx5_core_dev *mdev = priv->mdev;
402
403         void *in;
404         void *rqc;
405         int inlen;
406         int err;
407
408         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
409         in = mlx5_vzalloc(inlen);
410         if (!in)
411                 return -ENOMEM;
412
413         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
414
415         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
416         MLX5_SET(rqc, rqc, state, next_state);
417
418         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
419
420         kvfree(in);
421
422         return err;
423 }
424
425 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
426 {
427         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
428 }
429
430 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
431 {
432         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
433         struct mlx5e_channel *c = rq->channel;
434         struct mlx5e_priv *priv = c->priv;
435         struct mlx5_wq_ll *wq = &rq->wq;
436
437         while (time_before(jiffies, exp_time)) {
438                 if (wq->cur_sz >= priv->params.min_rx_wqes)
439                         return 0;
440
441                 msleep(20);
442         }
443
444         return -ETIMEDOUT;
445 }
446
447 static int mlx5e_open_rq(struct mlx5e_channel *c,
448                          struct mlx5e_rq_param *param,
449                          struct mlx5e_rq *rq)
450 {
451         struct mlx5e_sq *sq = &c->icosq;
452         u16 pi = sq->pc & sq->wq.sz_m1;
453         int err;
454
455         err = mlx5e_create_rq(c, param, rq);
456         if (err)
457                 return err;
458
459         err = mlx5e_enable_rq(rq, param);
460         if (err)
461                 goto err_destroy_rq;
462
463         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
464         if (err)
465                 goto err_disable_rq;
466
467         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
468
469         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
470         sq->ico_wqe_info[pi].num_wqebbs = 1;
471         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
472
473         return 0;
474
475 err_disable_rq:
476         mlx5e_disable_rq(rq);
477 err_destroy_rq:
478         mlx5e_destroy_rq(rq);
479
480         return err;
481 }
482
483 static void mlx5e_close_rq(struct mlx5e_rq *rq)
484 {
485         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
486         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
487
488         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
489         while (!mlx5_wq_ll_is_empty(&rq->wq))
490                 msleep(20);
491
492         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
493         napi_synchronize(&rq->channel->napi);
494
495         mlx5e_disable_rq(rq);
496         mlx5e_destroy_rq(rq);
497 }
498
499 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
500 {
501         kfree(sq->wqe_info);
502         kfree(sq->dma_fifo);
503         kfree(sq->skb);
504 }
505
506 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
507 {
508         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
509         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
510
511         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
512         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
513                                     numa);
514         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
515                                     numa);
516
517         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
518                 mlx5e_free_sq_db(sq);
519                 return -ENOMEM;
520         }
521
522         sq->dma_fifo_mask = df_sz - 1;
523
524         return 0;
525 }
526
527 static int mlx5e_create_sq(struct mlx5e_channel *c,
528                            int tc,
529                            struct mlx5e_sq_param *param,
530                            struct mlx5e_sq *sq)
531 {
532         struct mlx5e_priv *priv = c->priv;
533         struct mlx5_core_dev *mdev = priv->mdev;
534
535         void *sqc = param->sqc;
536         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
537         int err;
538
539         err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
540         if (err)
541                 return err;
542
543         param->wq.db_numa_node = cpu_to_node(c->cpu);
544
545         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
546                                  &sq->wq_ctrl);
547         if (err)
548                 goto err_unmap_free_uar;
549
550         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
551         if (sq->uar.bf_map) {
552                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
553                 sq->uar_map = sq->uar.bf_map;
554         } else {
555                 sq->uar_map = sq->uar.map;
556         }
557         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
558         sq->max_inline  = param->max_inline;
559
560         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
561         if (err)
562                 goto err_sq_wq_destroy;
563
564         if (param->icosq) {
565                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
566
567                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
568                                                 wq_sz,
569                                                 GFP_KERNEL,
570                                                 cpu_to_node(c->cpu));
571                 if (!sq->ico_wqe_info) {
572                         err = -ENOMEM;
573                         goto err_free_sq_db;
574                 }
575         } else {
576                 int txq_ix;
577
578                 txq_ix = c->ix + tc * priv->params.num_channels;
579                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
580                 priv->txq_to_sq_map[txq_ix] = sq;
581         }
582
583         sq->pdev      = c->pdev;
584         sq->tstamp    = &priv->tstamp;
585         sq->mkey_be   = c->mkey_be;
586         sq->channel   = c;
587         sq->tc        = tc;
588         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
589         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
590
591         return 0;
592
593 err_free_sq_db:
594         mlx5e_free_sq_db(sq);
595
596 err_sq_wq_destroy:
597         mlx5_wq_destroy(&sq->wq_ctrl);
598
599 err_unmap_free_uar:
600         mlx5_unmap_free_uar(mdev, &sq->uar);
601
602         return err;
603 }
604
605 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
606 {
607         struct mlx5e_channel *c = sq->channel;
608         struct mlx5e_priv *priv = c->priv;
609
610         kfree(sq->ico_wqe_info);
611         mlx5e_free_sq_db(sq);
612         mlx5_wq_destroy(&sq->wq_ctrl);
613         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
614 }
615
616 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
617 {
618         struct mlx5e_channel *c = sq->channel;
619         struct mlx5e_priv *priv = c->priv;
620         struct mlx5_core_dev *mdev = priv->mdev;
621
622         void *in;
623         void *sqc;
624         void *wq;
625         int inlen;
626         int err;
627
628         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
629                 sizeof(u64) * sq->wq_ctrl.buf.npages;
630         in = mlx5_vzalloc(inlen);
631         if (!in)
632                 return -ENOMEM;
633
634         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
635         wq = MLX5_ADDR_OF(sqc, sqc, wq);
636
637         memcpy(sqc, param->sqc, sizeof(param->sqc));
638
639         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
640         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
641         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
642         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
643         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
644
645         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
646         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
647         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
648                                           MLX5_ADAPTER_PAGE_SHIFT);
649         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
650
651         mlx5_fill_page_array(&sq->wq_ctrl.buf,
652                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
653
654         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
655
656         kvfree(in);
657
658         return err;
659 }
660
661 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
662 {
663         struct mlx5e_channel *c = sq->channel;
664         struct mlx5e_priv *priv = c->priv;
665         struct mlx5_core_dev *mdev = priv->mdev;
666
667         void *in;
668         void *sqc;
669         int inlen;
670         int err;
671
672         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
673         in = mlx5_vzalloc(inlen);
674         if (!in)
675                 return -ENOMEM;
676
677         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
678
679         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
680         MLX5_SET(sqc, sqc, state, next_state);
681
682         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
683
684         kvfree(in);
685
686         return err;
687 }
688
689 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
690 {
691         struct mlx5e_channel *c = sq->channel;
692         struct mlx5e_priv *priv = c->priv;
693         struct mlx5_core_dev *mdev = priv->mdev;
694
695         mlx5_core_destroy_sq(mdev, sq->sqn);
696 }
697
698 static int mlx5e_open_sq(struct mlx5e_channel *c,
699                          int tc,
700                          struct mlx5e_sq_param *param,
701                          struct mlx5e_sq *sq)
702 {
703         int err;
704
705         err = mlx5e_create_sq(c, tc, param, sq);
706         if (err)
707                 return err;
708
709         err = mlx5e_enable_sq(sq, param);
710         if (err)
711                 goto err_destroy_sq;
712
713         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
714         if (err)
715                 goto err_disable_sq;
716
717         if (sq->txq) {
718                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
719                 netdev_tx_reset_queue(sq->txq);
720                 netif_tx_start_queue(sq->txq);
721         }
722
723         return 0;
724
725 err_disable_sq:
726         mlx5e_disable_sq(sq);
727 err_destroy_sq:
728         mlx5e_destroy_sq(sq);
729
730         return err;
731 }
732
733 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
734 {
735         __netif_tx_lock_bh(txq);
736         netif_tx_stop_queue(txq);
737         __netif_tx_unlock_bh(txq);
738 }
739
740 static void mlx5e_close_sq(struct mlx5e_sq *sq)
741 {
742         if (sq->txq) {
743                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
744                 /* prevent netif_tx_wake_queue */
745                 napi_synchronize(&sq->channel->napi);
746                 netif_tx_disable_queue(sq->txq);
747
748                 /* ensure hw is notified of all pending wqes */
749                 if (mlx5e_sq_has_room_for(sq, 1))
750                         mlx5e_send_nop(sq, true);
751
752                 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
753         }
754
755         while (sq->cc != sq->pc) /* wait till sq is empty */
756                 msleep(20);
757
758         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
759         napi_synchronize(&sq->channel->napi);
760
761         mlx5e_disable_sq(sq);
762         mlx5e_destroy_sq(sq);
763 }
764
765 static int mlx5e_create_cq(struct mlx5e_channel *c,
766                            struct mlx5e_cq_param *param,
767                            struct mlx5e_cq *cq)
768 {
769         struct mlx5e_priv *priv = c->priv;
770         struct mlx5_core_dev *mdev = priv->mdev;
771         struct mlx5_core_cq *mcq = &cq->mcq;
772         int eqn_not_used;
773         unsigned int irqn;
774         int err;
775         u32 i;
776
777         param->wq.buf_numa_node = cpu_to_node(c->cpu);
778         param->wq.db_numa_node  = cpu_to_node(c->cpu);
779         param->eq_ix   = c->ix;
780
781         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
782                                &cq->wq_ctrl);
783         if (err)
784                 return err;
785
786         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
787
788         cq->napi        = &c->napi;
789
790         mcq->cqe_sz     = 64;
791         mcq->set_ci_db  = cq->wq_ctrl.db.db;
792         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
793         *mcq->set_ci_db = 0;
794         *mcq->arm_db    = 0;
795         mcq->vector     = param->eq_ix;
796         mcq->comp       = mlx5e_completion_event;
797         mcq->event      = mlx5e_cq_error_event;
798         mcq->irqn       = irqn;
799         mcq->uar        = &priv->cq_uar;
800
801         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
802                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
803
804                 cqe->op_own = 0xf1;
805         }
806
807         cq->channel = c;
808         cq->priv = priv;
809
810         return 0;
811 }
812
813 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
814 {
815         mlx5_wq_destroy(&cq->wq_ctrl);
816 }
817
818 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
819 {
820         struct mlx5e_priv *priv = cq->priv;
821         struct mlx5_core_dev *mdev = priv->mdev;
822         struct mlx5_core_cq *mcq = &cq->mcq;
823
824         void *in;
825         void *cqc;
826         int inlen;
827         unsigned int irqn_not_used;
828         int eqn;
829         int err;
830
831         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
832                 sizeof(u64) * cq->wq_ctrl.buf.npages;
833         in = mlx5_vzalloc(inlen);
834         if (!in)
835                 return -ENOMEM;
836
837         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
838
839         memcpy(cqc, param->cqc, sizeof(param->cqc));
840
841         mlx5_fill_page_array(&cq->wq_ctrl.buf,
842                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
843
844         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
845
846         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
847         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
848         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
849                                             MLX5_ADAPTER_PAGE_SHIFT);
850         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
851
852         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
853
854         kvfree(in);
855
856         if (err)
857                 return err;
858
859         mlx5e_cq_arm(cq);
860
861         return 0;
862 }
863
864 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
865 {
866         struct mlx5e_priv *priv = cq->priv;
867         struct mlx5_core_dev *mdev = priv->mdev;
868
869         mlx5_core_destroy_cq(mdev, &cq->mcq);
870 }
871
872 static int mlx5e_open_cq(struct mlx5e_channel *c,
873                          struct mlx5e_cq_param *param,
874                          struct mlx5e_cq *cq,
875                          u16 moderation_usecs,
876                          u16 moderation_frames)
877 {
878         int err;
879         struct mlx5e_priv *priv = c->priv;
880         struct mlx5_core_dev *mdev = priv->mdev;
881
882         err = mlx5e_create_cq(c, param, cq);
883         if (err)
884                 return err;
885
886         err = mlx5e_enable_cq(cq, param);
887         if (err)
888                 goto err_destroy_cq;
889
890         if (MLX5_CAP_GEN(mdev, cq_moderation))
891                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
892                                                moderation_usecs,
893                                                moderation_frames);
894         return 0;
895
896 err_destroy_cq:
897         mlx5e_destroy_cq(cq);
898
899         return err;
900 }
901
902 static void mlx5e_close_cq(struct mlx5e_cq *cq)
903 {
904         mlx5e_disable_cq(cq);
905         mlx5e_destroy_cq(cq);
906 }
907
908 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
909 {
910         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
911 }
912
913 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
914                              struct mlx5e_channel_param *cparam)
915 {
916         struct mlx5e_priv *priv = c->priv;
917         int err;
918         int tc;
919
920         for (tc = 0; tc < c->num_tc; tc++) {
921                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
922                                     priv->params.tx_cq_moderation_usec,
923                                     priv->params.tx_cq_moderation_pkts);
924                 if (err)
925                         goto err_close_tx_cqs;
926         }
927
928         return 0;
929
930 err_close_tx_cqs:
931         for (tc--; tc >= 0; tc--)
932                 mlx5e_close_cq(&c->sq[tc].cq);
933
934         return err;
935 }
936
937 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
938 {
939         int tc;
940
941         for (tc = 0; tc < c->num_tc; tc++)
942                 mlx5e_close_cq(&c->sq[tc].cq);
943 }
944
945 static int mlx5e_open_sqs(struct mlx5e_channel *c,
946                           struct mlx5e_channel_param *cparam)
947 {
948         int err;
949         int tc;
950
951         for (tc = 0; tc < c->num_tc; tc++) {
952                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
953                 if (err)
954                         goto err_close_sqs;
955         }
956
957         return 0;
958
959 err_close_sqs:
960         for (tc--; tc >= 0; tc--)
961                 mlx5e_close_sq(&c->sq[tc]);
962
963         return err;
964 }
965
966 static void mlx5e_close_sqs(struct mlx5e_channel *c)
967 {
968         int tc;
969
970         for (tc = 0; tc < c->num_tc; tc++)
971                 mlx5e_close_sq(&c->sq[tc]);
972 }
973
974 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
975 {
976         int i;
977
978         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
979                 priv->channeltc_to_txq_map[ix][i] =
980                         ix + i * priv->params.num_channels;
981 }
982
983 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
984                               struct mlx5e_channel_param *cparam,
985                               struct mlx5e_channel **cp)
986 {
987         struct net_device *netdev = priv->netdev;
988         int cpu = mlx5e_get_cpu(priv, ix);
989         struct mlx5e_channel *c;
990         int err;
991
992         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
993         if (!c)
994                 return -ENOMEM;
995
996         c->priv     = priv;
997         c->ix       = ix;
998         c->cpu      = cpu;
999         c->pdev     = &priv->mdev->pdev->dev;
1000         c->netdev   = priv->netdev;
1001         c->mkey_be  = cpu_to_be32(priv->mkey.key);
1002         c->num_tc   = priv->params.num_tc;
1003
1004         mlx5e_build_channeltc_to_txq_map(priv, ix);
1005
1006         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1007
1008         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1009         if (err)
1010                 goto err_napi_del;
1011
1012         err = mlx5e_open_tx_cqs(c, cparam);
1013         if (err)
1014                 goto err_close_icosq_cq;
1015
1016         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1017                             priv->params.rx_cq_moderation_usec,
1018                             priv->params.rx_cq_moderation_pkts);
1019         if (err)
1020                 goto err_close_tx_cqs;
1021
1022         napi_enable(&c->napi);
1023
1024         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1025         if (err)
1026                 goto err_disable_napi;
1027
1028         err = mlx5e_open_sqs(c, cparam);
1029         if (err)
1030                 goto err_close_icosq;
1031
1032         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1033         if (err)
1034                 goto err_close_sqs;
1035
1036         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1037         *cp = c;
1038
1039         return 0;
1040
1041 err_close_sqs:
1042         mlx5e_close_sqs(c);
1043
1044 err_close_icosq:
1045         mlx5e_close_sq(&c->icosq);
1046
1047 err_disable_napi:
1048         napi_disable(&c->napi);
1049         mlx5e_close_cq(&c->rq.cq);
1050
1051 err_close_tx_cqs:
1052         mlx5e_close_tx_cqs(c);
1053
1054 err_close_icosq_cq:
1055         mlx5e_close_cq(&c->icosq.cq);
1056
1057 err_napi_del:
1058         netif_napi_del(&c->napi);
1059         napi_hash_del(&c->napi);
1060         kfree(c);
1061
1062         return err;
1063 }
1064
1065 static void mlx5e_close_channel(struct mlx5e_channel *c)
1066 {
1067         mlx5e_close_rq(&c->rq);
1068         mlx5e_close_sqs(c);
1069         mlx5e_close_sq(&c->icosq);
1070         napi_disable(&c->napi);
1071         mlx5e_close_cq(&c->rq.cq);
1072         mlx5e_close_tx_cqs(c);
1073         mlx5e_close_cq(&c->icosq.cq);
1074         netif_napi_del(&c->napi);
1075
1076         napi_hash_del(&c->napi);
1077         synchronize_rcu();
1078
1079         kfree(c);
1080 }
1081
1082 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1083                                  struct mlx5e_rq_param *param)
1084 {
1085         void *rqc = param->rqc;
1086         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1087
1088         switch (priv->params.rq_wq_type) {
1089         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1090                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1091                          MLX5_MPWRQ_LOG_NUM_STRIDES - 9);
1092                 MLX5_SET(wq, wq, log_wqe_stride_size,
1093                          MLX5_MPWRQ_LOG_STRIDE_SIZE - 6);
1094                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1095                 break;
1096         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1097                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1098         }
1099
1100         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1101         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1102         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1103         MLX5_SET(wq, wq, pd,               priv->pdn);
1104         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1105
1106         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1107         param->wq.linear = 1;
1108 }
1109
1110 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1111 {
1112         void *rqc = param->rqc;
1113         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1114
1115         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1116         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1117 }
1118
1119 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1120                                         struct mlx5e_sq_param *param)
1121 {
1122         void *sqc = param->sqc;
1123         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1124
1125         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1126         MLX5_SET(wq, wq, pd,            priv->pdn);
1127
1128         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1129 }
1130
1131 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1132                                  struct mlx5e_sq_param *param)
1133 {
1134         void *sqc = param->sqc;
1135         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1136
1137         mlx5e_build_sq_param_common(priv, param);
1138         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1139
1140         param->max_inline = priv->params.tx_max_inline;
1141 }
1142
1143 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1144                                         struct mlx5e_cq_param *param)
1145 {
1146         void *cqc = param->cqc;
1147
1148         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1149 }
1150
1151 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1152                                     struct mlx5e_cq_param *param)
1153 {
1154         void *cqc = param->cqc;
1155         u8 log_cq_size;
1156
1157         switch (priv->params.rq_wq_type) {
1158         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1159                 log_cq_size = priv->params.log_rq_size +
1160                         MLX5_MPWRQ_LOG_NUM_STRIDES;
1161                 break;
1162         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1163                 log_cq_size = priv->params.log_rq_size;
1164         }
1165
1166         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1167
1168         mlx5e_build_common_cq_param(priv, param);
1169 }
1170
1171 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1172                                     struct mlx5e_cq_param *param)
1173 {
1174         void *cqc = param->cqc;
1175
1176         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1177
1178         mlx5e_build_common_cq_param(priv, param);
1179 }
1180
1181 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1182                                      struct mlx5e_cq_param *param,
1183                                      u8 log_wq_size)
1184 {
1185         void *cqc = param->cqc;
1186
1187         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1188
1189         mlx5e_build_common_cq_param(priv, param);
1190 }
1191
1192 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1193                                     struct mlx5e_sq_param *param,
1194                                     u8 log_wq_size)
1195 {
1196         void *sqc = param->sqc;
1197         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1198
1199         mlx5e_build_sq_param_common(priv, param);
1200
1201         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1202         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1203
1204         param->icosq = true;
1205 }
1206
1207 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1208                                       struct mlx5e_channel_param *cparam)
1209 {
1210         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1211
1212         memset(cparam, 0, sizeof(*cparam));
1213
1214         mlx5e_build_rq_param(priv, &cparam->rq);
1215         mlx5e_build_sq_param(priv, &cparam->sq);
1216         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1217         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1218         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1219         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1220 }
1221
1222 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1223 {
1224         struct mlx5e_channel_param cparam;
1225         int nch = priv->params.num_channels;
1226         int err = -ENOMEM;
1227         int i;
1228         int j;
1229
1230         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1231                                 GFP_KERNEL);
1232
1233         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1234                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1235
1236         if (!priv->channel || !priv->txq_to_sq_map)
1237                 goto err_free_txq_to_sq_map;
1238
1239         mlx5e_build_channel_param(priv, &cparam);
1240         for (i = 0; i < nch; i++) {
1241                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1242                 if (err)
1243                         goto err_close_channels;
1244         }
1245
1246         for (j = 0; j < nch; j++) {
1247                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1248                 if (err)
1249                         goto err_close_channels;
1250         }
1251
1252         return 0;
1253
1254 err_close_channels:
1255         for (i--; i >= 0; i--)
1256                 mlx5e_close_channel(priv->channel[i]);
1257
1258 err_free_txq_to_sq_map:
1259         kfree(priv->txq_to_sq_map);
1260         kfree(priv->channel);
1261
1262         return err;
1263 }
1264
1265 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1266 {
1267         int i;
1268
1269         for (i = 0; i < priv->params.num_channels; i++)
1270                 mlx5e_close_channel(priv->channel[i]);
1271
1272         kfree(priv->txq_to_sq_map);
1273         kfree(priv->channel);
1274 }
1275
1276 static int mlx5e_rx_hash_fn(int hfunc)
1277 {
1278         return (hfunc == ETH_RSS_HASH_TOP) ?
1279                MLX5_RX_HASH_FN_TOEPLITZ :
1280                MLX5_RX_HASH_FN_INVERTED_XOR8;
1281 }
1282
1283 static int mlx5e_bits_invert(unsigned long a, int size)
1284 {
1285         int inv = 0;
1286         int i;
1287
1288         for (i = 0; i < size; i++)
1289                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1290
1291         return inv;
1292 }
1293
1294 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1295 {
1296         int i;
1297
1298         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1299                 int ix = i;
1300
1301                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1302                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1303
1304                 ix = priv->params.indirection_rqt[ix];
1305                 MLX5_SET(rqtc, rqtc, rq_num[i],
1306                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1307                          priv->channel[ix]->rq.rqn :
1308                          priv->drop_rq.rqn);
1309         }
1310 }
1311
1312 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1313                                 enum mlx5e_rqt_ix rqt_ix)
1314 {
1315
1316         switch (rqt_ix) {
1317         case MLX5E_INDIRECTION_RQT:
1318                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1319
1320                 break;
1321
1322         default: /* MLX5E_SINGLE_RQ_RQT */
1323                 MLX5_SET(rqtc, rqtc, rq_num[0],
1324                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1325                          priv->channel[0]->rq.rqn :
1326                          priv->drop_rq.rqn);
1327
1328                 break;
1329         }
1330 }
1331
1332 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1333 {
1334         struct mlx5_core_dev *mdev = priv->mdev;
1335         u32 *in;
1336         void *rqtc;
1337         int inlen;
1338         int sz;
1339         int err;
1340
1341         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1342
1343         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1344         in = mlx5_vzalloc(inlen);
1345         if (!in)
1346                 return -ENOMEM;
1347
1348         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1349
1350         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1351         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1352
1353         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1354
1355         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1356
1357         kvfree(in);
1358
1359         return err;
1360 }
1361
1362 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1363 {
1364         struct mlx5_core_dev *mdev = priv->mdev;
1365         u32 *in;
1366         void *rqtc;
1367         int inlen;
1368         int sz;
1369         int err;
1370
1371         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1372
1373         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1374         in = mlx5_vzalloc(inlen);
1375         if (!in)
1376                 return -ENOMEM;
1377
1378         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1379
1380         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1381
1382         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1383
1384         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1385
1386         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1387
1388         kvfree(in);
1389
1390         return err;
1391 }
1392
1393 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1394 {
1395         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1396 }
1397
1398 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1399 {
1400         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1401         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1402 }
1403
1404 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1405 {
1406         if (!priv->params.lro_en)
1407                 return;
1408
1409 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1410
1411         MLX5_SET(tirc, tirc, lro_enable_mask,
1412                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1413                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1414         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1415                  (priv->params.lro_wqe_sz -
1416                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1417         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1418                  MLX5_CAP_ETH(priv->mdev,
1419                               lro_timer_supported_periods[2]));
1420 }
1421
1422 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1423 {
1424         MLX5_SET(tirc, tirc, rx_hash_fn,
1425                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1426         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1427                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1428                                              rx_hash_toeplitz_key);
1429                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1430                                                rx_hash_toeplitz_key);
1431
1432                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1433                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1434         }
1435 }
1436
1437 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1438 {
1439         struct mlx5_core_dev *mdev = priv->mdev;
1440
1441         void *in;
1442         void *tirc;
1443         int inlen;
1444         int err;
1445         int tt;
1446
1447         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1448         in = mlx5_vzalloc(inlen);
1449         if (!in)
1450                 return -ENOMEM;
1451
1452         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1453         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1454
1455         mlx5e_build_tir_ctx_lro(tirc, priv);
1456
1457         for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1458                 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1459                 if (err)
1460                         break;
1461         }
1462
1463         kvfree(in);
1464
1465         return err;
1466 }
1467
1468 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1469                                                   u32 tirn)
1470 {
1471         void *in;
1472         int inlen;
1473         int err;
1474
1475         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1476         in = mlx5_vzalloc(inlen);
1477         if (!in)
1478                 return -ENOMEM;
1479
1480         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1481
1482         err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1483
1484         kvfree(in);
1485
1486         return err;
1487 }
1488
1489 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1490 {
1491         int err;
1492         int i;
1493
1494         for (i = 0; i < MLX5E_NUM_TT; i++) {
1495                 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1496                                                              priv->tirn[i]);
1497                 if (err)
1498                         return err;
1499         }
1500
1501         return 0;
1502 }
1503
1504 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1505 {
1506         struct mlx5e_priv *priv = netdev_priv(netdev);
1507         struct mlx5_core_dev *mdev = priv->mdev;
1508         int hw_mtu;
1509         int err;
1510
1511         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1512         if (err)
1513                 return err;
1514
1515         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1516
1517         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1518                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1519                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1520
1521         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1522         return 0;
1523 }
1524
1525 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1526 {
1527         struct mlx5e_priv *priv = netdev_priv(netdev);
1528         int nch = priv->params.num_channels;
1529         int ntc = priv->params.num_tc;
1530         int tc;
1531
1532         netdev_reset_tc(netdev);
1533
1534         if (ntc == 1)
1535                 return;
1536
1537         netdev_set_num_tc(netdev, ntc);
1538
1539         for (tc = 0; tc < ntc; tc++)
1540                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1541 }
1542
1543 int mlx5e_open_locked(struct net_device *netdev)
1544 {
1545         struct mlx5e_priv *priv = netdev_priv(netdev);
1546         int num_txqs;
1547         int err;
1548
1549         set_bit(MLX5E_STATE_OPENED, &priv->state);
1550
1551         mlx5e_netdev_set_tcs(netdev);
1552
1553         num_txqs = priv->params.num_channels * priv->params.num_tc;
1554         netif_set_real_num_tx_queues(netdev, num_txqs);
1555         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1556
1557         err = mlx5e_set_dev_port_mtu(netdev);
1558         if (err)
1559                 goto err_clear_state_opened_flag;
1560
1561         err = mlx5e_open_channels(priv);
1562         if (err) {
1563                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1564                            __func__, err);
1565                 goto err_clear_state_opened_flag;
1566         }
1567
1568         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1569         if (err) {
1570                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1571                            __func__, err);
1572                 goto err_close_channels;
1573         }
1574
1575         mlx5e_redirect_rqts(priv);
1576         mlx5e_update_carrier(priv);
1577         mlx5e_timestamp_init(priv);
1578
1579         schedule_delayed_work(&priv->update_stats_work, 0);
1580
1581         return 0;
1582
1583 err_close_channels:
1584         mlx5e_close_channels(priv);
1585 err_clear_state_opened_flag:
1586         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1587         return err;
1588 }
1589
1590 static int mlx5e_open(struct net_device *netdev)
1591 {
1592         struct mlx5e_priv *priv = netdev_priv(netdev);
1593         int err;
1594
1595         mutex_lock(&priv->state_lock);
1596         err = mlx5e_open_locked(netdev);
1597         mutex_unlock(&priv->state_lock);
1598
1599         return err;
1600 }
1601
1602 int mlx5e_close_locked(struct net_device *netdev)
1603 {
1604         struct mlx5e_priv *priv = netdev_priv(netdev);
1605
1606         /* May already be CLOSED in case a previous configuration operation
1607          * (e.g RX/TX queue size change) that involves close&open failed.
1608          */
1609         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1610                 return 0;
1611
1612         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1613
1614         mlx5e_timestamp_cleanup(priv);
1615         netif_carrier_off(priv->netdev);
1616         mlx5e_redirect_rqts(priv);
1617         mlx5e_close_channels(priv);
1618
1619         return 0;
1620 }
1621
1622 static int mlx5e_close(struct net_device *netdev)
1623 {
1624         struct mlx5e_priv *priv = netdev_priv(netdev);
1625         int err;
1626
1627         mutex_lock(&priv->state_lock);
1628         err = mlx5e_close_locked(netdev);
1629         mutex_unlock(&priv->state_lock);
1630
1631         return err;
1632 }
1633
1634 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1635                                 struct mlx5e_rq *rq,
1636                                 struct mlx5e_rq_param *param)
1637 {
1638         struct mlx5_core_dev *mdev = priv->mdev;
1639         void *rqc = param->rqc;
1640         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1641         int err;
1642
1643         param->wq.db_numa_node = param->wq.buf_numa_node;
1644
1645         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1646                                 &rq->wq_ctrl);
1647         if (err)
1648                 return err;
1649
1650         rq->priv = priv;
1651
1652         return 0;
1653 }
1654
1655 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1656                                 struct mlx5e_cq *cq,
1657                                 struct mlx5e_cq_param *param)
1658 {
1659         struct mlx5_core_dev *mdev = priv->mdev;
1660         struct mlx5_core_cq *mcq = &cq->mcq;
1661         int eqn_not_used;
1662         unsigned int irqn;
1663         int err;
1664
1665         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1666                                &cq->wq_ctrl);
1667         if (err)
1668                 return err;
1669
1670         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1671
1672         mcq->cqe_sz     = 64;
1673         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1674         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1675         *mcq->set_ci_db = 0;
1676         *mcq->arm_db    = 0;
1677         mcq->vector     = param->eq_ix;
1678         mcq->comp       = mlx5e_completion_event;
1679         mcq->event      = mlx5e_cq_error_event;
1680         mcq->irqn       = irqn;
1681         mcq->uar        = &priv->cq_uar;
1682
1683         cq->priv = priv;
1684
1685         return 0;
1686 }
1687
1688 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1689 {
1690         struct mlx5e_cq_param cq_param;
1691         struct mlx5e_rq_param rq_param;
1692         struct mlx5e_rq *rq = &priv->drop_rq;
1693         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1694         int err;
1695
1696         memset(&cq_param, 0, sizeof(cq_param));
1697         memset(&rq_param, 0, sizeof(rq_param));
1698         mlx5e_build_drop_rq_param(&rq_param);
1699
1700         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1701         if (err)
1702                 return err;
1703
1704         err = mlx5e_enable_cq(cq, &cq_param);
1705         if (err)
1706                 goto err_destroy_cq;
1707
1708         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1709         if (err)
1710                 goto err_disable_cq;
1711
1712         err = mlx5e_enable_rq(rq, &rq_param);
1713         if (err)
1714                 goto err_destroy_rq;
1715
1716         return 0;
1717
1718 err_destroy_rq:
1719         mlx5e_destroy_rq(&priv->drop_rq);
1720
1721 err_disable_cq:
1722         mlx5e_disable_cq(&priv->drop_rq.cq);
1723
1724 err_destroy_cq:
1725         mlx5e_destroy_cq(&priv->drop_rq.cq);
1726
1727         return err;
1728 }
1729
1730 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1731 {
1732         mlx5e_disable_rq(&priv->drop_rq);
1733         mlx5e_destroy_rq(&priv->drop_rq);
1734         mlx5e_disable_cq(&priv->drop_rq.cq);
1735         mlx5e_destroy_cq(&priv->drop_rq.cq);
1736 }
1737
1738 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1739 {
1740         struct mlx5_core_dev *mdev = priv->mdev;
1741         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1742         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1743
1744         memset(in, 0, sizeof(in));
1745
1746         MLX5_SET(tisc, tisc, prio, tc << 1);
1747         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1748
1749         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1750 }
1751
1752 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1753 {
1754         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1755 }
1756
1757 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1758 {
1759         int err;
1760         int tc;
1761
1762         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1763                 err = mlx5e_create_tis(priv, tc);
1764                 if (err)
1765                         goto err_close_tises;
1766         }
1767
1768         return 0;
1769
1770 err_close_tises:
1771         for (tc--; tc >= 0; tc--)
1772                 mlx5e_destroy_tis(priv, tc);
1773
1774         return err;
1775 }
1776
1777 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1778 {
1779         int tc;
1780
1781         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1782                 mlx5e_destroy_tis(priv, tc);
1783 }
1784
1785 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1786 {
1787         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1788
1789         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1790
1791 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1792                                  MLX5_HASH_FIELD_SEL_DST_IP)
1793
1794 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1795                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1796                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1797                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1798
1799 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1800                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1801                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1802
1803         mlx5e_build_tir_ctx_lro(tirc, priv);
1804
1805         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1806
1807         switch (tt) {
1808         case MLX5E_TT_ANY:
1809                 MLX5_SET(tirc, tirc, indirect_table,
1810                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1811                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1812                 break;
1813         default:
1814                 MLX5_SET(tirc, tirc, indirect_table,
1815                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1816                 mlx5e_build_tir_ctx_hash(tirc, priv);
1817                 break;
1818         }
1819
1820         switch (tt) {
1821         case MLX5E_TT_IPV4_TCP:
1822                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1823                          MLX5_L3_PROT_TYPE_IPV4);
1824                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1825                          MLX5_L4_PROT_TYPE_TCP);
1826                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1827                          MLX5_HASH_IP_L4PORTS);
1828                 break;
1829
1830         case MLX5E_TT_IPV6_TCP:
1831                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1832                          MLX5_L3_PROT_TYPE_IPV6);
1833                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1834                          MLX5_L4_PROT_TYPE_TCP);
1835                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1836                          MLX5_HASH_IP_L4PORTS);
1837                 break;
1838
1839         case MLX5E_TT_IPV4_UDP:
1840                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1841                          MLX5_L3_PROT_TYPE_IPV4);
1842                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1843                          MLX5_L4_PROT_TYPE_UDP);
1844                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1845                          MLX5_HASH_IP_L4PORTS);
1846                 break;
1847
1848         case MLX5E_TT_IPV6_UDP:
1849                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1850                          MLX5_L3_PROT_TYPE_IPV6);
1851                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1852                          MLX5_L4_PROT_TYPE_UDP);
1853                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1854                          MLX5_HASH_IP_L4PORTS);
1855                 break;
1856
1857         case MLX5E_TT_IPV4_IPSEC_AH:
1858                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1859                          MLX5_L3_PROT_TYPE_IPV4);
1860                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1861                          MLX5_HASH_IP_IPSEC_SPI);
1862                 break;
1863
1864         case MLX5E_TT_IPV6_IPSEC_AH:
1865                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1866                          MLX5_L3_PROT_TYPE_IPV6);
1867                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1868                          MLX5_HASH_IP_IPSEC_SPI);
1869                 break;
1870
1871         case MLX5E_TT_IPV4_IPSEC_ESP:
1872                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1873                          MLX5_L3_PROT_TYPE_IPV4);
1874                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1875                          MLX5_HASH_IP_IPSEC_SPI);
1876                 break;
1877
1878         case MLX5E_TT_IPV6_IPSEC_ESP:
1879                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1880                          MLX5_L3_PROT_TYPE_IPV6);
1881                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1882                          MLX5_HASH_IP_IPSEC_SPI);
1883                 break;
1884
1885         case MLX5E_TT_IPV4:
1886                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1887                          MLX5_L3_PROT_TYPE_IPV4);
1888                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1889                          MLX5_HASH_IP);
1890                 break;
1891
1892         case MLX5E_TT_IPV6:
1893                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1894                          MLX5_L3_PROT_TYPE_IPV6);
1895                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1896                          MLX5_HASH_IP);
1897                 break;
1898         }
1899 }
1900
1901 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1902 {
1903         struct mlx5_core_dev *mdev = priv->mdev;
1904         u32 *in;
1905         void *tirc;
1906         int inlen;
1907         int err;
1908
1909         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1910         in = mlx5_vzalloc(inlen);
1911         if (!in)
1912                 return -ENOMEM;
1913
1914         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1915
1916         mlx5e_build_tir_ctx(priv, tirc, tt);
1917
1918         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1919
1920         kvfree(in);
1921
1922         return err;
1923 }
1924
1925 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1926 {
1927         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1928 }
1929
1930 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1931 {
1932         int err;
1933         int i;
1934
1935         for (i = 0; i < MLX5E_NUM_TT; i++) {
1936                 err = mlx5e_create_tir(priv, i);
1937                 if (err)
1938                         goto err_destroy_tirs;
1939         }
1940
1941         return 0;
1942
1943 err_destroy_tirs:
1944         for (i--; i >= 0; i--)
1945                 mlx5e_destroy_tir(priv, i);
1946
1947         return err;
1948 }
1949
1950 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1951 {
1952         int i;
1953
1954         for (i = 0; i < MLX5E_NUM_TT; i++)
1955                 mlx5e_destroy_tir(priv, i);
1956 }
1957
1958 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1959 {
1960         struct mlx5e_priv *priv = netdev_priv(netdev);
1961         bool was_opened;
1962         int err = 0;
1963
1964         if (tc && tc != MLX5E_MAX_NUM_TC)
1965                 return -EINVAL;
1966
1967         mutex_lock(&priv->state_lock);
1968
1969         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1970         if (was_opened)
1971                 mlx5e_close_locked(priv->netdev);
1972
1973         priv->params.num_tc = tc ? tc : 1;
1974
1975         if (was_opened)
1976                 err = mlx5e_open_locked(priv->netdev);
1977
1978         mutex_unlock(&priv->state_lock);
1979
1980         return err;
1981 }
1982
1983 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1984                               __be16 proto, struct tc_to_netdev *tc)
1985 {
1986         struct mlx5e_priv *priv = netdev_priv(dev);
1987
1988         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
1989                 goto mqprio;
1990
1991         switch (tc->type) {
1992         case TC_SETUP_CLSFLOWER:
1993                 switch (tc->cls_flower->command) {
1994                 case TC_CLSFLOWER_REPLACE:
1995                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
1996                 case TC_CLSFLOWER_DESTROY:
1997                         return mlx5e_delete_flower(priv, tc->cls_flower);
1998                 }
1999         default:
2000                 return -EOPNOTSUPP;
2001         }
2002
2003 mqprio:
2004         if (tc->type != TC_SETUP_MQPRIO)
2005                 return -EINVAL;
2006
2007         return mlx5e_setup_tc(dev, tc->tc);
2008 }
2009
2010 static struct rtnl_link_stats64 *
2011 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2012 {
2013         struct mlx5e_priv *priv = netdev_priv(dev);
2014         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2015         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2016         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2017
2018         stats->rx_packets = sstats->rx_packets;
2019         stats->rx_bytes   = sstats->rx_bytes;
2020         stats->tx_packets = sstats->tx_packets;
2021         stats->tx_bytes   = sstats->tx_bytes;
2022
2023         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2024         stats->tx_dropped = sstats->tx_queue_dropped;
2025
2026         stats->rx_length_errors =
2027                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2028                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2029                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2030         stats->rx_crc_errors =
2031                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2032         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2033         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2034         stats->tx_carrier_errors =
2035                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2036         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2037                            stats->rx_frame_errors;
2038         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2039
2040         /* vport multicast also counts packets that are dropped due to steering
2041          * or rx out of buffer
2042          */
2043         stats->multicast =
2044                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2045
2046         return stats;
2047 }
2048
2049 static void mlx5e_set_rx_mode(struct net_device *dev)
2050 {
2051         struct mlx5e_priv *priv = netdev_priv(dev);
2052
2053         schedule_work(&priv->set_rx_mode_work);
2054 }
2055
2056 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2057 {
2058         struct mlx5e_priv *priv = netdev_priv(netdev);
2059         struct sockaddr *saddr = addr;
2060
2061         if (!is_valid_ether_addr(saddr->sa_data))
2062                 return -EADDRNOTAVAIL;
2063
2064         netif_addr_lock_bh(netdev);
2065         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2066         netif_addr_unlock_bh(netdev);
2067
2068         schedule_work(&priv->set_rx_mode_work);
2069
2070         return 0;
2071 }
2072
2073 static int mlx5e_set_features(struct net_device *netdev,
2074                               netdev_features_t features)
2075 {
2076         struct mlx5e_priv *priv = netdev_priv(netdev);
2077         int err = 0;
2078         netdev_features_t changes = features ^ netdev->features;
2079
2080         mutex_lock(&priv->state_lock);
2081
2082         if (changes & NETIF_F_LRO) {
2083                 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2084
2085                 if (was_opened && (priv->params.rq_wq_type ==
2086                                    MLX5_WQ_TYPE_LINKED_LIST))
2087                         mlx5e_close_locked(priv->netdev);
2088
2089                 priv->params.lro_en = !!(features & NETIF_F_LRO);
2090                 err = mlx5e_modify_tirs_lro(priv);
2091                 if (err)
2092                         mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
2093                                        err);
2094
2095                 if (was_opened && (priv->params.rq_wq_type ==
2096                                    MLX5_WQ_TYPE_LINKED_LIST))
2097                         err = mlx5e_open_locked(priv->netdev);
2098         }
2099
2100         mutex_unlock(&priv->state_lock);
2101
2102         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
2103                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
2104                         mlx5e_enable_vlan_filter(priv);
2105                 else
2106                         mlx5e_disable_vlan_filter(priv);
2107         }
2108
2109         if ((changes & NETIF_F_HW_TC) && !(features & NETIF_F_HW_TC) &&
2110             mlx5e_tc_num_filters(priv)) {
2111                 netdev_err(netdev,
2112                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2113                 return -EINVAL;
2114         }
2115
2116         return err;
2117 }
2118
2119 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2120 {
2121         struct mlx5e_priv *priv = netdev_priv(netdev);
2122         struct mlx5_core_dev *mdev = priv->mdev;
2123         bool was_opened;
2124         int max_mtu;
2125         int err = 0;
2126
2127         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2128
2129         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2130
2131         if (new_mtu > max_mtu) {
2132                 netdev_err(netdev,
2133                            "%s: Bad MTU (%d) > (%d) Max\n",
2134                            __func__, new_mtu, max_mtu);
2135                 return -EINVAL;
2136         }
2137
2138         mutex_lock(&priv->state_lock);
2139
2140         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2141         if (was_opened)
2142                 mlx5e_close_locked(netdev);
2143
2144         netdev->mtu = new_mtu;
2145
2146         if (was_opened)
2147                 err = mlx5e_open_locked(netdev);
2148
2149         mutex_unlock(&priv->state_lock);
2150
2151         return err;
2152 }
2153
2154 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2155 {
2156         switch (cmd) {
2157         case SIOCSHWTSTAMP:
2158                 return mlx5e_hwstamp_set(dev, ifr);
2159         case SIOCGHWTSTAMP:
2160                 return mlx5e_hwstamp_get(dev, ifr);
2161         default:
2162                 return -EOPNOTSUPP;
2163         }
2164 }
2165
2166 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2167 {
2168         struct mlx5e_priv *priv = netdev_priv(dev);
2169         struct mlx5_core_dev *mdev = priv->mdev;
2170
2171         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2172 }
2173
2174 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2175 {
2176         struct mlx5e_priv *priv = netdev_priv(dev);
2177         struct mlx5_core_dev *mdev = priv->mdev;
2178
2179         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2180                                            vlan, qos);
2181 }
2182
2183 static int mlx5_vport_link2ifla(u8 esw_link)
2184 {
2185         switch (esw_link) {
2186         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2187                 return IFLA_VF_LINK_STATE_DISABLE;
2188         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2189                 return IFLA_VF_LINK_STATE_ENABLE;
2190         }
2191         return IFLA_VF_LINK_STATE_AUTO;
2192 }
2193
2194 static int mlx5_ifla_link2vport(u8 ifla_link)
2195 {
2196         switch (ifla_link) {
2197         case IFLA_VF_LINK_STATE_DISABLE:
2198                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2199         case IFLA_VF_LINK_STATE_ENABLE:
2200                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2201         }
2202         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2203 }
2204
2205 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2206                                    int link_state)
2207 {
2208         struct mlx5e_priv *priv = netdev_priv(dev);
2209         struct mlx5_core_dev *mdev = priv->mdev;
2210
2211         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2212                                             mlx5_ifla_link2vport(link_state));
2213 }
2214
2215 static int mlx5e_get_vf_config(struct net_device *dev,
2216                                int vf, struct ifla_vf_info *ivi)
2217 {
2218         struct mlx5e_priv *priv = netdev_priv(dev);
2219         struct mlx5_core_dev *mdev = priv->mdev;
2220         int err;
2221
2222         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2223         if (err)
2224                 return err;
2225         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2226         return 0;
2227 }
2228
2229 static int mlx5e_get_vf_stats(struct net_device *dev,
2230                               int vf, struct ifla_vf_stats *vf_stats)
2231 {
2232         struct mlx5e_priv *priv = netdev_priv(dev);
2233         struct mlx5_core_dev *mdev = priv->mdev;
2234
2235         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2236                                             vf_stats);
2237 }
2238
2239 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2240                                  sa_family_t sa_family, __be16 port)
2241 {
2242         struct mlx5e_priv *priv = netdev_priv(netdev);
2243
2244         if (!mlx5e_vxlan_allowed(priv->mdev))
2245                 return;
2246
2247         mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2248 }
2249
2250 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2251                                  sa_family_t sa_family, __be16 port)
2252 {
2253         struct mlx5e_priv *priv = netdev_priv(netdev);
2254
2255         if (!mlx5e_vxlan_allowed(priv->mdev))
2256                 return;
2257
2258         mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2259 }
2260
2261 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2262                                                     struct sk_buff *skb,
2263                                                     netdev_features_t features)
2264 {
2265         struct udphdr *udph;
2266         u16 proto;
2267         u16 port = 0;
2268
2269         switch (vlan_get_protocol(skb)) {
2270         case htons(ETH_P_IP):
2271                 proto = ip_hdr(skb)->protocol;
2272                 break;
2273         case htons(ETH_P_IPV6):
2274                 proto = ipv6_hdr(skb)->nexthdr;
2275                 break;
2276         default:
2277                 goto out;
2278         }
2279
2280         if (proto == IPPROTO_UDP) {
2281                 udph = udp_hdr(skb);
2282                 port = be16_to_cpu(udph->dest);
2283         }
2284
2285         /* Verify if UDP port is being offloaded by HW */
2286         if (port && mlx5e_vxlan_lookup_port(priv, port))
2287                 return features;
2288
2289 out:
2290         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2291         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2292 }
2293
2294 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2295                                               struct net_device *netdev,
2296                                               netdev_features_t features)
2297 {
2298         struct mlx5e_priv *priv = netdev_priv(netdev);
2299
2300         features = vlan_features_check(skb, features);
2301         features = vxlan_features_check(skb, features);
2302
2303         /* Validate if the tunneled packet is being offloaded by HW */
2304         if (skb->encapsulation &&
2305             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2306                 return mlx5e_vxlan_features_check(priv, skb, features);
2307
2308         return features;
2309 }
2310
2311 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2312         .ndo_open                = mlx5e_open,
2313         .ndo_stop                = mlx5e_close,
2314         .ndo_start_xmit          = mlx5e_xmit,
2315         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2316         .ndo_select_queue        = mlx5e_select_queue,
2317         .ndo_get_stats64         = mlx5e_get_stats,
2318         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2319         .ndo_set_mac_address     = mlx5e_set_mac,
2320         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2321         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2322         .ndo_set_features        = mlx5e_set_features,
2323         .ndo_change_mtu          = mlx5e_change_mtu,
2324         .ndo_do_ioctl            = mlx5e_ioctl,
2325 };
2326
2327 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2328         .ndo_open                = mlx5e_open,
2329         .ndo_stop                = mlx5e_close,
2330         .ndo_start_xmit          = mlx5e_xmit,
2331         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2332         .ndo_select_queue        = mlx5e_select_queue,
2333         .ndo_get_stats64         = mlx5e_get_stats,
2334         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2335         .ndo_set_mac_address     = mlx5e_set_mac,
2336         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2337         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2338         .ndo_set_features        = mlx5e_set_features,
2339         .ndo_change_mtu          = mlx5e_change_mtu,
2340         .ndo_do_ioctl            = mlx5e_ioctl,
2341         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2342         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2343         .ndo_features_check      = mlx5e_features_check,
2344         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2345         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2346         .ndo_get_vf_config       = mlx5e_get_vf_config,
2347         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2348         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2349 };
2350
2351 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2352 {
2353         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2354                 return -ENOTSUPP;
2355         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2356             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2357             !MLX5_CAP_ETH(mdev, csum_cap) ||
2358             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2359             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2360             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2361             MLX5_CAP_FLOWTABLE(mdev,
2362                                flow_table_properties_nic_receive.max_ft_level)
2363                                < 3) {
2364                 mlx5_core_warn(mdev,
2365                                "Not creating net device, some required device capabilities are missing\n");
2366                 return -ENOTSUPP;
2367         }
2368         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2369                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2370         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2371                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2372
2373         return 0;
2374 }
2375
2376 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2377 {
2378         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2379
2380         return bf_buf_size -
2381                sizeof(struct mlx5e_tx_wqe) +
2382                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2383 }
2384
2385 #ifdef CONFIG_MLX5_CORE_EN_DCB
2386 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2387 {
2388         int i;
2389
2390         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2391         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2392                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2393                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2394                 priv->params.ets.prio_tc[i] = i;
2395         }
2396
2397         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2398         priv->params.ets.prio_tc[0] = 1;
2399         priv->params.ets.prio_tc[1] = 0;
2400 }
2401 #endif
2402
2403 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2404                                    u32 *indirection_rqt, int len,
2405                                    int num_channels)
2406 {
2407         int node = mdev->priv.numa_node;
2408         int node_num_of_cores;
2409         int i;
2410
2411         if (node == -1)
2412                 node = first_online_node;
2413
2414         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2415
2416         if (node_num_of_cores)
2417                 num_channels = min_t(int, num_channels, node_num_of_cores);
2418
2419         for (i = 0; i < len; i++)
2420                 indirection_rqt[i] = i % num_channels;
2421 }
2422
2423 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2424 {
2425         return MLX5_CAP_GEN(mdev, striding_rq) &&
2426                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2427                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2428 }
2429
2430 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2431                                     struct net_device *netdev,
2432                                     int num_channels)
2433 {
2434         struct mlx5e_priv *priv = netdev_priv(netdev);
2435
2436         priv->params.log_sq_size           =
2437                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2438         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2439                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2440                 MLX5_WQ_TYPE_LINKED_LIST;
2441
2442         switch (priv->params.rq_wq_type) {
2443         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2444                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2445                 priv->params.lro_en = true;
2446                 break;
2447         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2448                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2449         }
2450
2451         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2452                                             BIT(priv->params.log_rq_size));
2453         priv->params.rx_cq_moderation_usec =
2454                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2455         priv->params.rx_cq_moderation_pkts =
2456                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2457         priv->params.tx_cq_moderation_usec =
2458                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2459         priv->params.tx_cq_moderation_pkts =
2460                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2461         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2462         priv->params.num_tc                = 1;
2463         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2464
2465         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2466                             sizeof(priv->params.toeplitz_hash_key));
2467
2468         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2469                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2470
2471         priv->params.lro_wqe_sz            =
2472                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2473
2474         priv->mdev                         = mdev;
2475         priv->netdev                       = netdev;
2476         priv->params.num_channels          = num_channels;
2477
2478 #ifdef CONFIG_MLX5_CORE_EN_DCB
2479         mlx5e_ets_init(priv);
2480 #endif
2481
2482         mutex_init(&priv->state_lock);
2483
2484         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2485         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2486         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2487 }
2488
2489 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2490 {
2491         struct mlx5e_priv *priv = netdev_priv(netdev);
2492
2493         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2494         if (is_zero_ether_addr(netdev->dev_addr) &&
2495             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2496                 eth_hw_addr_random(netdev);
2497                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2498         }
2499 }
2500
2501 static void mlx5e_build_netdev(struct net_device *netdev)
2502 {
2503         struct mlx5e_priv *priv = netdev_priv(netdev);
2504         struct mlx5_core_dev *mdev = priv->mdev;
2505
2506         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2507
2508         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2509                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2510 #ifdef CONFIG_MLX5_CORE_EN_DCB
2511                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2512 #endif
2513         } else {
2514                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2515         }
2516
2517         netdev->watchdog_timeo    = 15 * HZ;
2518
2519         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2520
2521         netdev->vlan_features    |= NETIF_F_SG;
2522         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2523         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2524         netdev->vlan_features    |= NETIF_F_GRO;
2525         netdev->vlan_features    |= NETIF_F_TSO;
2526         netdev->vlan_features    |= NETIF_F_TSO6;
2527         netdev->vlan_features    |= NETIF_F_RXCSUM;
2528         netdev->vlan_features    |= NETIF_F_RXHASH;
2529
2530         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2531                 netdev->vlan_features    |= NETIF_F_LRO;
2532
2533         netdev->hw_features       = netdev->vlan_features;
2534         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2535         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2536         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2537
2538         if (mlx5e_vxlan_allowed(mdev)) {
2539                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
2540                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2541                 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2542                 netdev->hw_enc_features |= NETIF_F_TSO;
2543                 netdev->hw_enc_features |= NETIF_F_TSO6;
2544                 netdev->hw_enc_features |= NETIF_F_RXHASH;
2545                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2546         }
2547
2548         netdev->features          = netdev->hw_features;
2549         if (!priv->params.lro_en)
2550                 netdev->features  &= ~NETIF_F_LRO;
2551
2552 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2553         if (FT_CAP(flow_modify_en) &&
2554             FT_CAP(modify_root) &&
2555             FT_CAP(identified_miss_table_mode) &&
2556             FT_CAP(flow_table_modify))
2557                 priv->netdev->hw_features      |= NETIF_F_HW_TC;
2558
2559         netdev->features         |= NETIF_F_HIGHDMA;
2560
2561         netdev->priv_flags       |= IFF_UNICAST_FLT;
2562
2563         mlx5e_set_netdev_dev_addr(netdev);
2564 }
2565
2566 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2567                              struct mlx5_core_mkey *mkey)
2568 {
2569         struct mlx5_core_dev *mdev = priv->mdev;
2570         struct mlx5_create_mkey_mbox_in *in;
2571         int err;
2572
2573         in = mlx5_vzalloc(sizeof(*in));
2574         if (!in)
2575                 return -ENOMEM;
2576
2577         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2578                         MLX5_PERM_LOCAL_READ  |
2579                         MLX5_ACCESS_MODE_PA;
2580         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2581         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2582
2583         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2584                                     NULL);
2585
2586         kvfree(in);
2587
2588         return err;
2589 }
2590
2591 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2592 {
2593         struct mlx5_core_dev *mdev = priv->mdev;
2594         int err;
2595
2596         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2597         if (err) {
2598                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2599                 priv->q_counter = 0;
2600         }
2601 }
2602
2603 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2604 {
2605         if (!priv->q_counter)
2606                 return;
2607
2608         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2609 }
2610
2611 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2612 {
2613         struct mlx5_core_dev *mdev = priv->mdev;
2614         struct mlx5_create_mkey_mbox_in *in;
2615         struct mlx5_mkey_seg *mkc;
2616         int inlen = sizeof(*in);
2617         u64 npages =
2618                 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2619         int err;
2620
2621         in = mlx5_vzalloc(inlen);
2622         if (!in)
2623                 return -ENOMEM;
2624
2625         mkc = &in->seg;
2626         mkc->status = MLX5_MKEY_STATUS_FREE;
2627         mkc->flags = MLX5_PERM_UMR_EN |
2628                      MLX5_PERM_LOCAL_READ |
2629                      MLX5_PERM_LOCAL_WRITE |
2630                      MLX5_ACCESS_MODE_MTT;
2631
2632         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2633         mkc->flags_pd = cpu_to_be32(priv->pdn);
2634         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
2635         mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
2636         mkc->log2_page_size = PAGE_SHIFT;
2637
2638         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
2639                                     NULL, NULL);
2640
2641         kvfree(in);
2642
2643         return err;
2644 }
2645
2646 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2647 {
2648         struct net_device *netdev;
2649         struct mlx5e_priv *priv;
2650         int nch = mlx5e_get_max_num_channels(mdev);
2651         int err;
2652
2653         if (mlx5e_check_required_hca_cap(mdev))
2654                 return NULL;
2655
2656         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2657                                     nch * MLX5E_MAX_NUM_TC,
2658                                     nch);
2659         if (!netdev) {
2660                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2661                 return NULL;
2662         }
2663
2664         mlx5e_build_netdev_priv(mdev, netdev, nch);
2665         mlx5e_build_netdev(netdev);
2666
2667         netif_carrier_off(netdev);
2668
2669         priv = netdev_priv(netdev);
2670
2671         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2672         if (err) {
2673                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2674                 goto err_free_netdev;
2675         }
2676
2677         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2678         if (err) {
2679                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2680                 goto err_unmap_free_uar;
2681         }
2682
2683         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2684         if (err) {
2685                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2686                 goto err_dealloc_pd;
2687         }
2688
2689         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2690         if (err) {
2691                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2692                 goto err_dealloc_transport_domain;
2693         }
2694
2695         err = mlx5e_create_umr_mkey(priv);
2696         if (err) {
2697                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
2698                 goto err_destroy_mkey;
2699         }
2700
2701         err = mlx5e_create_tises(priv);
2702         if (err) {
2703                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2704                 goto err_destroy_umr_mkey;
2705         }
2706
2707         err = mlx5e_open_drop_rq(priv);
2708         if (err) {
2709                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2710                 goto err_destroy_tises;
2711         }
2712
2713         err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2714         if (err) {
2715                 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2716                 goto err_close_drop_rq;
2717         }
2718
2719         err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2720         if (err) {
2721                 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2722                 goto err_destroy_rqt_indir;
2723         }
2724
2725         err = mlx5e_create_tirs(priv);
2726         if (err) {
2727                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2728                 goto err_destroy_rqt_single;
2729         }
2730
2731         err = mlx5e_create_flow_tables(priv);
2732         if (err) {
2733                 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2734                 goto err_destroy_tirs;
2735         }
2736
2737         mlx5e_create_q_counter(priv);
2738
2739         mlx5e_init_eth_addr(priv);
2740
2741         mlx5e_vxlan_init(priv);
2742
2743         err = mlx5e_tc_init(priv);
2744         if (err)
2745                 goto err_dealloc_q_counters;
2746
2747 #ifdef CONFIG_MLX5_CORE_EN_DCB
2748         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2749 #endif
2750
2751         err = register_netdev(netdev);
2752         if (err) {
2753                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2754                 goto err_tc_cleanup;
2755         }
2756
2757         if (mlx5e_vxlan_allowed(mdev))
2758                 vxlan_get_rx_port(netdev);
2759
2760         mlx5e_enable_async_events(priv);
2761         schedule_work(&priv->set_rx_mode_work);
2762
2763         return priv;
2764
2765 err_tc_cleanup:
2766         mlx5e_tc_cleanup(priv);
2767
2768 err_dealloc_q_counters:
2769         mlx5e_destroy_q_counter(priv);
2770         mlx5e_destroy_flow_tables(priv);
2771
2772 err_destroy_tirs:
2773         mlx5e_destroy_tirs(priv);
2774
2775 err_destroy_rqt_single:
2776         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2777
2778 err_destroy_rqt_indir:
2779         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2780
2781 err_close_drop_rq:
2782         mlx5e_close_drop_rq(priv);
2783
2784 err_destroy_tises:
2785         mlx5e_destroy_tises(priv);
2786
2787 err_destroy_umr_mkey:
2788         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
2789
2790 err_destroy_mkey:
2791         mlx5_core_destroy_mkey(mdev, &priv->mkey);
2792
2793 err_dealloc_transport_domain:
2794         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2795
2796 err_dealloc_pd:
2797         mlx5_core_dealloc_pd(mdev, priv->pdn);
2798
2799 err_unmap_free_uar:
2800         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2801
2802 err_free_netdev:
2803         free_netdev(netdev);
2804
2805         return NULL;
2806 }
2807
2808 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2809 {
2810         struct mlx5e_priv *priv = vpriv;
2811         struct net_device *netdev = priv->netdev;
2812
2813         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2814
2815         schedule_work(&priv->set_rx_mode_work);
2816         mlx5e_disable_async_events(priv);
2817         flush_scheduled_work();
2818         unregister_netdev(netdev);
2819         mlx5e_tc_cleanup(priv);
2820         mlx5e_vxlan_cleanup(priv);
2821         mlx5e_destroy_q_counter(priv);
2822         mlx5e_destroy_flow_tables(priv);
2823         mlx5e_destroy_tirs(priv);
2824         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2825         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2826         mlx5e_close_drop_rq(priv);
2827         mlx5e_destroy_tises(priv);
2828         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
2829         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
2830         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2831         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2832         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2833         free_netdev(netdev);
2834 }
2835
2836 static void *mlx5e_get_netdev(void *vpriv)
2837 {
2838         struct mlx5e_priv *priv = vpriv;
2839
2840         return priv->netdev;
2841 }
2842
2843 static struct mlx5_interface mlx5e_interface = {
2844         .add       = mlx5e_create_netdev,
2845         .remove    = mlx5e_destroy_netdev,
2846         .event     = mlx5e_async_event,
2847         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2848         .get_dev   = mlx5e_get_netdev,
2849 };
2850
2851 void mlx5e_init(void)
2852 {
2853         mlx5_register_interface(&mlx5e_interface);
2854 }
2855
2856 void mlx5e_cleanup(void)
2857 {
2858         mlx5_unregister_interface(&mlx5e_interface);
2859 }