net/mlx5e: Remove redundant active_channels indication
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include <net/page_pool.h>
39 #include "eswitch.h"
40 #include "en.h"
41 #include "en_tc.h"
42 #include "en_rep.h"
43 #include "en_accel/ipsec.h"
44 #include "en_accel/ipsec_rxtx.h"
45 #include "en_accel/tls.h"
46 #include "accel/ipsec.h"
47 #include "accel/tls.h"
48 #include "vxlan.h"
49 #include "en/port.h"
50
51 struct mlx5e_rq_param {
52         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
53         struct mlx5_wq_param    wq;
54 };
55
56 struct mlx5e_sq_param {
57         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
58         struct mlx5_wq_param       wq;
59 };
60
61 struct mlx5e_cq_param {
62         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
63         struct mlx5_wq_param       wq;
64         u16                        eq_ix;
65         u8                         cq_period_mode;
66 };
67
68 struct mlx5e_channel_param {
69         struct mlx5e_rq_param      rq;
70         struct mlx5e_sq_param      sq;
71         struct mlx5e_sq_param      xdp_sq;
72         struct mlx5e_sq_param      icosq;
73         struct mlx5e_cq_param      rx_cq;
74         struct mlx5e_cq_param      tx_cq;
75         struct mlx5e_cq_param      icosq_cq;
76 };
77
78 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
79 {
80         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
81                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
82                 MLX5_CAP_ETH(mdev, reg_umr_sq);
83         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
84         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
85
86         if (!striding_rq_umr)
87                 return false;
88         if (!inline_umr) {
89                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
90                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
91                 return false;
92         }
93         return true;
94 }
95
96 static u32 mlx5e_mpwqe_get_linear_frag_sz(struct mlx5e_params *params)
97 {
98         if (!params->xdp_prog) {
99                 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
100                 u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN;
101
102                 return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu);
103         }
104
105         return PAGE_SIZE;
106 }
107
108 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
109 {
110         u32 linear_frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
111
112         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
113 }
114
115 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
116                                          struct mlx5e_params *params)
117 {
118         u32 frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
119         s8 signed_log_num_strides_param;
120         u8 log_num_strides;
121
122         if (params->lro_en || frag_sz > PAGE_SIZE)
123                 return false;
124
125         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
126                 return true;
127
128         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
129         signed_log_num_strides_param =
130                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
131
132         return signed_log_num_strides_param >= 0;
133 }
134
135 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
136 {
137         if (params->log_rq_mtu_frames <
138             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
139                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
140
141         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
142 }
143
144 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
145                                           struct mlx5e_params *params)
146 {
147         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
148                 return order_base_2(mlx5e_mpwqe_get_linear_frag_sz(params));
149
150         return MLX5E_MPWQE_STRIDE_SZ(mdev,
151                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
152 }
153
154 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
155                                           struct mlx5e_params *params)
156 {
157         return MLX5_MPWRQ_LOG_WQE_SZ -
158                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
159 }
160
161 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
162                                  struct mlx5e_params *params)
163 {
164         u16 linear_rq_headroom = params->xdp_prog ?
165                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
166
167         linear_rq_headroom += NET_IP_ALIGN;
168
169         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)
170                 return linear_rq_headroom;
171
172         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
173                 return linear_rq_headroom;
174
175         return 0;
176 }
177
178 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
179                                struct mlx5e_params *params)
180 {
181         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
182         params->log_rq_mtu_frames = is_kdump_kernel() ?
183                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
184                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
185         switch (params->rq_wq_type) {
186         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
187                 break;
188         default: /* MLX5_WQ_TYPE_LINKED_LIST */
189                 /* Extra room needed for build_skb */
190                 params->lro_wqe_sz -= mlx5e_get_rq_headroom(mdev, params) +
191                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
192         }
193
194         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
195                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
196                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
197                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
198                        BIT(params->log_rq_mtu_frames),
199                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
200                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
201 }
202
203 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
204                                 struct mlx5e_params *params)
205 {
206         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
207                 !MLX5_IPSEC_DEV(mdev) &&
208                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
209 }
210
211 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
212 {
213         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
214                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
215                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
216                 MLX5_WQ_TYPE_LINKED_LIST;
217 }
218
219 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
220 {
221         struct mlx5_core_dev *mdev = priv->mdev;
222         u8 port_state;
223
224         port_state = mlx5_query_vport_state(mdev,
225                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
226                                             0);
227
228         if (port_state == VPORT_STATE_UP) {
229                 netdev_info(priv->netdev, "Link up\n");
230                 netif_carrier_on(priv->netdev);
231         } else {
232                 netdev_info(priv->netdev, "Link down\n");
233                 netif_carrier_off(priv->netdev);
234         }
235 }
236
237 static void mlx5e_update_carrier_work(struct work_struct *work)
238 {
239         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
240                                                update_carrier_work);
241
242         mutex_lock(&priv->state_lock);
243         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
244                 if (priv->profile->update_carrier)
245                         priv->profile->update_carrier(priv);
246         mutex_unlock(&priv->state_lock);
247 }
248
249 void mlx5e_update_stats(struct mlx5e_priv *priv)
250 {
251         int i;
252
253         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
254                 if (mlx5e_stats_grps[i].update_stats)
255                         mlx5e_stats_grps[i].update_stats(priv);
256 }
257
258 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
259 {
260         int i;
261
262         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
263                 if (mlx5e_stats_grps[i].update_stats_mask &
264                     MLX5E_NDO_UPDATE_STATS)
265                         mlx5e_stats_grps[i].update_stats(priv);
266 }
267
268 void mlx5e_update_stats_work(struct work_struct *work)
269 {
270         struct delayed_work *dwork = to_delayed_work(work);
271         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
272                                                update_stats_work);
273         mutex_lock(&priv->state_lock);
274         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
275                 priv->profile->update_stats(priv);
276                 queue_delayed_work(priv->wq, dwork,
277                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
278         }
279         mutex_unlock(&priv->state_lock);
280 }
281
282 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
283                               enum mlx5_dev_event event, unsigned long param)
284 {
285         struct mlx5e_priv *priv = vpriv;
286
287         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
288                 return;
289
290         switch (event) {
291         case MLX5_DEV_EVENT_PORT_UP:
292         case MLX5_DEV_EVENT_PORT_DOWN:
293                 queue_work(priv->wq, &priv->update_carrier_work);
294                 break;
295         default:
296                 break;
297         }
298 }
299
300 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
301 {
302         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
303 }
304
305 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
306 {
307         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
308         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
309 }
310
311 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
312                                        struct mlx5e_icosq *sq,
313                                        struct mlx5e_umr_wqe *wqe)
314 {
315         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
316         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
317         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
318
319         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
320                                       ds_cnt);
321         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
322         cseg->imm       = rq->mkey_be;
323
324         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
325         ucseg->xlt_octowords =
326                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
327         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
328 }
329
330 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
331                                      struct mlx5e_channel *c)
332 {
333         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
334
335         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
336                                       GFP_KERNEL, cpu_to_node(c->cpu));
337         if (!rq->mpwqe.info)
338                 return -ENOMEM;
339
340         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
341
342         return 0;
343 }
344
345 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
346                                  u64 npages, u8 page_shift,
347                                  struct mlx5_core_mkey *umr_mkey)
348 {
349         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
350         void *mkc;
351         u32 *in;
352         int err;
353
354         in = kvzalloc(inlen, GFP_KERNEL);
355         if (!in)
356                 return -ENOMEM;
357
358         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
359
360         MLX5_SET(mkc, mkc, free, 1);
361         MLX5_SET(mkc, mkc, umr_en, 1);
362         MLX5_SET(mkc, mkc, lw, 1);
363         MLX5_SET(mkc, mkc, lr, 1);
364         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
365
366         MLX5_SET(mkc, mkc, qpn, 0xffffff);
367         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
368         MLX5_SET64(mkc, mkc, len, npages << page_shift);
369         MLX5_SET(mkc, mkc, translations_octword_size,
370                  MLX5_MTT_OCTW(npages));
371         MLX5_SET(mkc, mkc, log_page_size, page_shift);
372
373         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
374
375         kvfree(in);
376         return err;
377 }
378
379 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
380 {
381         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
382
383         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
384 }
385
386 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
387 {
388         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
389 }
390
391 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
392                           struct mlx5e_params *params,
393                           struct mlx5e_rq_param *rqp,
394                           struct mlx5e_rq *rq)
395 {
396         struct page_pool_params pp_params = { 0 };
397         struct mlx5_core_dev *mdev = c->mdev;
398         void *rqc = rqp->rqc;
399         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
400         u32 byte_count, pool_size;
401         int npages;
402         int wq_sz;
403         int err;
404         int i;
405
406         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
407
408         err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
409                                 &rq->wq_ctrl);
410         if (err)
411                 return err;
412
413         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
414
415         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
416
417         rq->wq_type = params->rq_wq_type;
418         rq->pdev    = c->pdev;
419         rq->netdev  = c->netdev;
420         rq->tstamp  = c->tstamp;
421         rq->clock   = &mdev->clock;
422         rq->channel = c;
423         rq->ix      = c->ix;
424         rq->mdev    = mdev;
425         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
426         rq->stats   = &c->priv->channel_stats[c->ix].rq;
427
428         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
429         if (IS_ERR(rq->xdp_prog)) {
430                 err = PTR_ERR(rq->xdp_prog);
431                 rq->xdp_prog = NULL;
432                 goto err_rq_wq_destroy;
433         }
434
435         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
436         if (err < 0)
437                 goto err_rq_wq_destroy;
438
439         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
440         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
441         pool_size = 1 << params->log_rq_mtu_frames;
442
443         switch (rq->wq_type) {
444         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
445
446                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
447                 rq->post_wqes = mlx5e_post_rx_mpwqes;
448                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
449
450                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
451 #ifdef CONFIG_MLX5_EN_IPSEC
452                 if (MLX5_IPSEC_DEV(mdev)) {
453                         err = -EINVAL;
454                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
455                         goto err_rq_wq_destroy;
456                 }
457 #endif
458                 if (!rq->handle_rx_cqe) {
459                         err = -EINVAL;
460                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
461                         goto err_rq_wq_destroy;
462                 }
463
464                 rq->mpwqe.skb_from_cqe_mpwrq =
465                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
466                         mlx5e_skb_from_cqe_mpwrq_linear :
467                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
468                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
469                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
470
471                 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
472
473                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
474                 if (err)
475                         goto err_rq_wq_destroy;
476                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
477
478                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
479                 if (err)
480                         goto err_destroy_umr_mkey;
481                 break;
482         default: /* MLX5_WQ_TYPE_LINKED_LIST */
483                 rq->wqe.frag_info =
484                         kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
485                                      GFP_KERNEL, cpu_to_node(c->cpu));
486                 if (!rq->wqe.frag_info) {
487                         err = -ENOMEM;
488                         goto err_rq_wq_destroy;
489                 }
490                 rq->post_wqes = mlx5e_post_rx_wqes;
491                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
492
493 #ifdef CONFIG_MLX5_EN_IPSEC
494                 if (c->priv->ipsec)
495                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
496                 else
497 #endif
498                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
499                 if (!rq->handle_rx_cqe) {
500                         kfree(rq->wqe.frag_info);
501                         err = -EINVAL;
502                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
503                         goto err_rq_wq_destroy;
504                 }
505
506                 byte_count = params->lro_en  ?
507                                 params->lro_wqe_sz :
508                                 MLX5E_SW2HW_MTU(params, params->sw_mtu);
509 #ifdef CONFIG_MLX5_EN_IPSEC
510                 if (MLX5_IPSEC_DEV(mdev))
511                         byte_count += MLX5E_METADATA_ETHER_LEN;
512 #endif
513                 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
514
515                 /* calc the required page order */
516                 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
517                 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
518                 rq->buff.page_order = order_base_2(npages);
519
520                 byte_count |= MLX5_HW_START_PADDING;
521                 rq->mkey_be = c->mkey_be;
522         }
523
524         /* Create a page_pool and register it with rxq */
525         pp_params.order     = rq->buff.page_order;
526         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
527         pp_params.pool_size = pool_size;
528         pp_params.nid       = cpu_to_node(c->cpu);
529         pp_params.dev       = c->pdev;
530         pp_params.dma_dir   = rq->buff.map_dir;
531
532         /* page_pool can be used even when there is no rq->xdp_prog,
533          * given page_pool does not handle DMA mapping there is no
534          * required state to clear. And page_pool gracefully handle
535          * elevated refcnt.
536          */
537         rq->page_pool = page_pool_create(&pp_params);
538         if (IS_ERR(rq->page_pool)) {
539                 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
540                         kfree(rq->wqe.frag_info);
541                 err = PTR_ERR(rq->page_pool);
542                 rq->page_pool = NULL;
543                 goto err_rq_wq_destroy;
544         }
545         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
546                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
547         if (err)
548                 goto err_rq_wq_destroy;
549
550         for (i = 0; i < wq_sz; i++) {
551                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
552
553                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
554                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
555
556                         wqe->data.addr = cpu_to_be64(dma_offset + rq->buff.headroom);
557                 }
558
559                 wqe->data.byte_count = cpu_to_be32(byte_count);
560                 wqe->data.lkey = rq->mkey_be;
561         }
562
563         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
564
565         switch (params->rx_cq_moderation.cq_period_mode) {
566         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
567                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
568                 break;
569         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
570         default:
571                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
572         }
573
574         rq->page_cache.head = 0;
575         rq->page_cache.tail = 0;
576
577         return 0;
578
579 err_destroy_umr_mkey:
580         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
581
582 err_rq_wq_destroy:
583         if (rq->xdp_prog)
584                 bpf_prog_put(rq->xdp_prog);
585         xdp_rxq_info_unreg(&rq->xdp_rxq);
586         if (rq->page_pool)
587                 page_pool_destroy(rq->page_pool);
588         mlx5_wq_destroy(&rq->wq_ctrl);
589
590         return err;
591 }
592
593 static void mlx5e_free_rq(struct mlx5e_rq *rq)
594 {
595         int i;
596
597         if (rq->xdp_prog)
598                 bpf_prog_put(rq->xdp_prog);
599
600         xdp_rxq_info_unreg(&rq->xdp_rxq);
601         if (rq->page_pool)
602                 page_pool_destroy(rq->page_pool);
603
604         switch (rq->wq_type) {
605         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
606                 kfree(rq->mpwqe.info);
607                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
608                 break;
609         default: /* MLX5_WQ_TYPE_LINKED_LIST */
610                 kfree(rq->wqe.frag_info);
611         }
612
613         for (i = rq->page_cache.head; i != rq->page_cache.tail;
614              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
615                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
616
617                 mlx5e_page_release(rq, dma_info, false);
618         }
619         mlx5_wq_destroy(&rq->wq_ctrl);
620 }
621
622 static int mlx5e_create_rq(struct mlx5e_rq *rq,
623                            struct mlx5e_rq_param *param)
624 {
625         struct mlx5_core_dev *mdev = rq->mdev;
626
627         void *in;
628         void *rqc;
629         void *wq;
630         int inlen;
631         int err;
632
633         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
634                 sizeof(u64) * rq->wq_ctrl.buf.npages;
635         in = kvzalloc(inlen, GFP_KERNEL);
636         if (!in)
637                 return -ENOMEM;
638
639         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
640         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
641
642         memcpy(rqc, param->rqc, sizeof(param->rqc));
643
644         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
645         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
646         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
647                                                 MLX5_ADAPTER_PAGE_SHIFT);
648         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
649
650         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
651                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
652
653         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
654
655         kvfree(in);
656
657         return err;
658 }
659
660 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
661                                  int next_state)
662 {
663         struct mlx5_core_dev *mdev = rq->mdev;
664
665         void *in;
666         void *rqc;
667         int inlen;
668         int err;
669
670         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
671         in = kvzalloc(inlen, GFP_KERNEL);
672         if (!in)
673                 return -ENOMEM;
674
675         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
676
677         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
678         MLX5_SET(rqc, rqc, state, next_state);
679
680         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
681
682         kvfree(in);
683
684         return err;
685 }
686
687 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
688 {
689         struct mlx5e_channel *c = rq->channel;
690         struct mlx5e_priv *priv = c->priv;
691         struct mlx5_core_dev *mdev = priv->mdev;
692
693         void *in;
694         void *rqc;
695         int inlen;
696         int err;
697
698         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
699         in = kvzalloc(inlen, GFP_KERNEL);
700         if (!in)
701                 return -ENOMEM;
702
703         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
704
705         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
706         MLX5_SET64(modify_rq_in, in, modify_bitmask,
707                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
708         MLX5_SET(rqc, rqc, scatter_fcs, enable);
709         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
710
711         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
712
713         kvfree(in);
714
715         return err;
716 }
717
718 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
719 {
720         struct mlx5e_channel *c = rq->channel;
721         struct mlx5_core_dev *mdev = c->mdev;
722         void *in;
723         void *rqc;
724         int inlen;
725         int err;
726
727         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
728         in = kvzalloc(inlen, GFP_KERNEL);
729         if (!in)
730                 return -ENOMEM;
731
732         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
733
734         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
735         MLX5_SET64(modify_rq_in, in, modify_bitmask,
736                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
737         MLX5_SET(rqc, rqc, vsd, vsd);
738         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
739
740         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
741
742         kvfree(in);
743
744         return err;
745 }
746
747 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
748 {
749         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
750 }
751
752 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
753 {
754         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
755         struct mlx5e_channel *c = rq->channel;
756
757         struct mlx5_wq_ll *wq = &rq->wq;
758         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
759
760         do {
761                 if (wq->cur_sz >= min_wqes)
762                         return 0;
763
764                 msleep(20);
765         } while (time_before(jiffies, exp_time));
766
767         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
768                     c->ix, rq->rqn, wq->cur_sz, min_wqes);
769
770         return -ETIMEDOUT;
771 }
772
773 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
774 {
775         struct mlx5_wq_ll *wq = &rq->wq;
776         struct mlx5e_rx_wqe *wqe;
777         __be16 wqe_ix_be;
778         u16 wqe_ix;
779
780         /* UMR WQE (if in progress) is always at wq->head */
781         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
782             rq->mpwqe.umr_in_progress)
783                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
784
785         while (!mlx5_wq_ll_is_empty(wq)) {
786                 wqe_ix_be = *wq->tail_next;
787                 wqe_ix    = be16_to_cpu(wqe_ix_be);
788                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
789                 rq->dealloc_wqe(rq, wqe_ix);
790                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
791                                &wqe->next.next_wqe_index);
792         }
793
794         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
795                 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
796                  * but yet to be re-posted.
797                  */
798                 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
799
800                 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
801                         rq->dealloc_wqe(rq, wqe_ix);
802         }
803 }
804
805 static int mlx5e_open_rq(struct mlx5e_channel *c,
806                          struct mlx5e_params *params,
807                          struct mlx5e_rq_param *param,
808                          struct mlx5e_rq *rq)
809 {
810         int err;
811
812         err = mlx5e_alloc_rq(c, params, param, rq);
813         if (err)
814                 return err;
815
816         err = mlx5e_create_rq(rq, param);
817         if (err)
818                 goto err_free_rq;
819
820         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
821         if (err)
822                 goto err_destroy_rq;
823
824         if (params->rx_dim_enabled)
825                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
826
827         return 0;
828
829 err_destroy_rq:
830         mlx5e_destroy_rq(rq);
831 err_free_rq:
832         mlx5e_free_rq(rq);
833
834         return err;
835 }
836
837 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
838 {
839         struct mlx5e_icosq *sq = &rq->channel->icosq;
840         struct mlx5_wq_cyc *wq = &sq->wq;
841         struct mlx5e_tx_wqe *nopwqe;
842
843         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
844
845         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
846         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
847         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
848         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
849 }
850
851 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
852 {
853         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
854         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
855 }
856
857 static void mlx5e_close_rq(struct mlx5e_rq *rq)
858 {
859         cancel_work_sync(&rq->dim.work);
860         mlx5e_destroy_rq(rq);
861         mlx5e_free_rx_descs(rq);
862         mlx5e_free_rq(rq);
863 }
864
865 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
866 {
867         kfree(sq->db.di);
868 }
869
870 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
871 {
872         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
873
874         sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
875                                      GFP_KERNEL, numa);
876         if (!sq->db.di) {
877                 mlx5e_free_xdpsq_db(sq);
878                 return -ENOMEM;
879         }
880
881         return 0;
882 }
883
884 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
885                              struct mlx5e_params *params,
886                              struct mlx5e_sq_param *param,
887                              struct mlx5e_xdpsq *sq)
888 {
889         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
890         struct mlx5_core_dev *mdev = c->mdev;
891         struct mlx5_wq_cyc *wq = &sq->wq;
892         int err;
893
894         sq->pdev      = c->pdev;
895         sq->mkey_be   = c->mkey_be;
896         sq->channel   = c;
897         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
898         sq->min_inline_mode = params->tx_min_inline_mode;
899
900         param->wq.db_numa_node = cpu_to_node(c->cpu);
901         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
902         if (err)
903                 return err;
904         wq->db = &wq->db[MLX5_SND_DBR];
905
906         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
907         if (err)
908                 goto err_sq_wq_destroy;
909
910         return 0;
911
912 err_sq_wq_destroy:
913         mlx5_wq_destroy(&sq->wq_ctrl);
914
915         return err;
916 }
917
918 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
919 {
920         mlx5e_free_xdpsq_db(sq);
921         mlx5_wq_destroy(&sq->wq_ctrl);
922 }
923
924 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
925 {
926         kfree(sq->db.ico_wqe);
927 }
928
929 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
930 {
931         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
932
933         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
934                                       GFP_KERNEL, numa);
935         if (!sq->db.ico_wqe)
936                 return -ENOMEM;
937
938         return 0;
939 }
940
941 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
942                              struct mlx5e_sq_param *param,
943                              struct mlx5e_icosq *sq)
944 {
945         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
946         struct mlx5_core_dev *mdev = c->mdev;
947         struct mlx5_wq_cyc *wq = &sq->wq;
948         int err;
949
950         sq->channel   = c;
951         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
952
953         param->wq.db_numa_node = cpu_to_node(c->cpu);
954         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
955         if (err)
956                 return err;
957         wq->db = &wq->db[MLX5_SND_DBR];
958
959         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
960         if (err)
961                 goto err_sq_wq_destroy;
962
963         return 0;
964
965 err_sq_wq_destroy:
966         mlx5_wq_destroy(&sq->wq_ctrl);
967
968         return err;
969 }
970
971 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
972 {
973         mlx5e_free_icosq_db(sq);
974         mlx5_wq_destroy(&sq->wq_ctrl);
975 }
976
977 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
978 {
979         kfree(sq->db.wqe_info);
980         kfree(sq->db.dma_fifo);
981 }
982
983 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
984 {
985         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
986         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
987
988         sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
989                                            GFP_KERNEL, numa);
990         sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
991                                            GFP_KERNEL, numa);
992         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
993                 mlx5e_free_txqsq_db(sq);
994                 return -ENOMEM;
995         }
996
997         sq->dma_fifo_mask = df_sz - 1;
998
999         return 0;
1000 }
1001
1002 static void mlx5e_sq_recover(struct work_struct *work);
1003 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1004                              int txq_ix,
1005                              struct mlx5e_params *params,
1006                              struct mlx5e_sq_param *param,
1007                              struct mlx5e_txqsq *sq,
1008                              int tc)
1009 {
1010         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1011         struct mlx5_core_dev *mdev = c->mdev;
1012         struct mlx5_wq_cyc *wq = &sq->wq;
1013         int err;
1014
1015         sq->pdev      = c->pdev;
1016         sq->tstamp    = c->tstamp;
1017         sq->clock     = &mdev->clock;
1018         sq->mkey_be   = c->mkey_be;
1019         sq->channel   = c;
1020         sq->txq_ix    = txq_ix;
1021         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1022         sq->min_inline_mode = params->tx_min_inline_mode;
1023         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1024         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1025         if (MLX5_IPSEC_DEV(c->priv->mdev))
1026                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1027         if (mlx5_accel_is_tls_device(c->priv->mdev))
1028                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1029
1030         param->wq.db_numa_node = cpu_to_node(c->cpu);
1031         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1032         if (err)
1033                 return err;
1034         wq->db    = &wq->db[MLX5_SND_DBR];
1035
1036         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1037         if (err)
1038                 goto err_sq_wq_destroy;
1039
1040         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1041         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1042
1043         return 0;
1044
1045 err_sq_wq_destroy:
1046         mlx5_wq_destroy(&sq->wq_ctrl);
1047
1048         return err;
1049 }
1050
1051 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1052 {
1053         mlx5e_free_txqsq_db(sq);
1054         mlx5_wq_destroy(&sq->wq_ctrl);
1055 }
1056
1057 struct mlx5e_create_sq_param {
1058         struct mlx5_wq_ctrl        *wq_ctrl;
1059         u32                         cqn;
1060         u32                         tisn;
1061         u8                          tis_lst_sz;
1062         u8                          min_inline_mode;
1063 };
1064
1065 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1066                            struct mlx5e_sq_param *param,
1067                            struct mlx5e_create_sq_param *csp,
1068                            u32 *sqn)
1069 {
1070         void *in;
1071         void *sqc;
1072         void *wq;
1073         int inlen;
1074         int err;
1075
1076         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1077                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1078         in = kvzalloc(inlen, GFP_KERNEL);
1079         if (!in)
1080                 return -ENOMEM;
1081
1082         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1083         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1084
1085         memcpy(sqc, param->sqc, sizeof(param->sqc));
1086         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1087         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1088         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1089
1090         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1091                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1092
1093         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1094         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1095
1096         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1097         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1098         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1099                                           MLX5_ADAPTER_PAGE_SHIFT);
1100         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1101
1102         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1103                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1104
1105         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1106
1107         kvfree(in);
1108
1109         return err;
1110 }
1111
1112 struct mlx5e_modify_sq_param {
1113         int curr_state;
1114         int next_state;
1115         bool rl_update;
1116         int rl_index;
1117 };
1118
1119 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1120                            struct mlx5e_modify_sq_param *p)
1121 {
1122         void *in;
1123         void *sqc;
1124         int inlen;
1125         int err;
1126
1127         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1128         in = kvzalloc(inlen, GFP_KERNEL);
1129         if (!in)
1130                 return -ENOMEM;
1131
1132         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1133
1134         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1135         MLX5_SET(sqc, sqc, state, p->next_state);
1136         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1137                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1138                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1139         }
1140
1141         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1142
1143         kvfree(in);
1144
1145         return err;
1146 }
1147
1148 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1149 {
1150         mlx5_core_destroy_sq(mdev, sqn);
1151 }
1152
1153 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1154                                struct mlx5e_sq_param *param,
1155                                struct mlx5e_create_sq_param *csp,
1156                                u32 *sqn)
1157 {
1158         struct mlx5e_modify_sq_param msp = {0};
1159         int err;
1160
1161         err = mlx5e_create_sq(mdev, param, csp, sqn);
1162         if (err)
1163                 return err;
1164
1165         msp.curr_state = MLX5_SQC_STATE_RST;
1166         msp.next_state = MLX5_SQC_STATE_RDY;
1167         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1168         if (err)
1169                 mlx5e_destroy_sq(mdev, *sqn);
1170
1171         return err;
1172 }
1173
1174 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1175                                 struct mlx5e_txqsq *sq, u32 rate);
1176
1177 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1178                             u32 tisn,
1179                             int txq_ix,
1180                             struct mlx5e_params *params,
1181                             struct mlx5e_sq_param *param,
1182                             struct mlx5e_txqsq *sq,
1183                             int tc)
1184 {
1185         struct mlx5e_create_sq_param csp = {};
1186         u32 tx_rate;
1187         int err;
1188
1189         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1190         if (err)
1191                 return err;
1192
1193         csp.tisn            = tisn;
1194         csp.tis_lst_sz      = 1;
1195         csp.cqn             = sq->cq.mcq.cqn;
1196         csp.wq_ctrl         = &sq->wq_ctrl;
1197         csp.min_inline_mode = sq->min_inline_mode;
1198         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1199         if (err)
1200                 goto err_free_txqsq;
1201
1202         tx_rate = c->priv->tx_rates[sq->txq_ix];
1203         if (tx_rate)
1204                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1205
1206         if (params->tx_dim_enabled)
1207                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1208
1209         return 0;
1210
1211 err_free_txqsq:
1212         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1213         mlx5e_free_txqsq(sq);
1214
1215         return err;
1216 }
1217
1218 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1219 {
1220         WARN_ONCE(sq->cc != sq->pc,
1221                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1222                   sq->sqn, sq->cc, sq->pc);
1223         sq->cc = 0;
1224         sq->dma_fifo_cc = 0;
1225         sq->pc = 0;
1226 }
1227
1228 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1229 {
1230         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1231         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1232         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1233         netdev_tx_reset_queue(sq->txq);
1234         netif_tx_start_queue(sq->txq);
1235 }
1236
1237 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1238 {
1239         __netif_tx_lock_bh(txq);
1240         netif_tx_stop_queue(txq);
1241         __netif_tx_unlock_bh(txq);
1242 }
1243
1244 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1245 {
1246         struct mlx5e_channel *c = sq->channel;
1247         struct mlx5_wq_cyc *wq = &sq->wq;
1248
1249         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1250         /* prevent netif_tx_wake_queue */
1251         napi_synchronize(&c->napi);
1252
1253         netif_tx_disable_queue(sq->txq);
1254
1255         /* last doorbell out, godspeed .. */
1256         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1257                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1258                 struct mlx5e_tx_wqe *nop;
1259
1260                 sq->db.wqe_info[pi].skb = NULL;
1261                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1262                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1263         }
1264 }
1265
1266 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1267 {
1268         struct mlx5e_channel *c = sq->channel;
1269         struct mlx5_core_dev *mdev = c->mdev;
1270         struct mlx5_rate_limit rl = {0};
1271
1272         mlx5e_destroy_sq(mdev, sq->sqn);
1273         if (sq->rate_limit) {
1274                 rl.rate = sq->rate_limit;
1275                 mlx5_rl_remove_rate(mdev, &rl);
1276         }
1277         mlx5e_free_txqsq_descs(sq);
1278         mlx5e_free_txqsq(sq);
1279 }
1280
1281 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1282 {
1283         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1284
1285         while (time_before(jiffies, exp_time)) {
1286                 if (sq->cc == sq->pc)
1287                         return 0;
1288
1289                 msleep(20);
1290         }
1291
1292         netdev_err(sq->channel->netdev,
1293                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1294                    sq->sqn, sq->cc, sq->pc);
1295
1296         return -ETIMEDOUT;
1297 }
1298
1299 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1300 {
1301         struct mlx5_core_dev *mdev = sq->channel->mdev;
1302         struct net_device *dev = sq->channel->netdev;
1303         struct mlx5e_modify_sq_param msp = {0};
1304         int err;
1305
1306         msp.curr_state = curr_state;
1307         msp.next_state = MLX5_SQC_STATE_RST;
1308
1309         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1310         if (err) {
1311                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1312                 return err;
1313         }
1314
1315         memset(&msp, 0, sizeof(msp));
1316         msp.curr_state = MLX5_SQC_STATE_RST;
1317         msp.next_state = MLX5_SQC_STATE_RDY;
1318
1319         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1320         if (err) {
1321                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1322                 return err;
1323         }
1324
1325         return 0;
1326 }
1327
1328 static void mlx5e_sq_recover(struct work_struct *work)
1329 {
1330         struct mlx5e_txqsq_recover *recover =
1331                 container_of(work, struct mlx5e_txqsq_recover,
1332                              recover_work);
1333         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1334                                               recover);
1335         struct mlx5_core_dev *mdev = sq->channel->mdev;
1336         struct net_device *dev = sq->channel->netdev;
1337         u8 state;
1338         int err;
1339
1340         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1341         if (err) {
1342                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1343                            sq->sqn, err);
1344                 return;
1345         }
1346
1347         if (state != MLX5_RQC_STATE_ERR) {
1348                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1349                 return;
1350         }
1351
1352         netif_tx_disable_queue(sq->txq);
1353
1354         if (mlx5e_wait_for_sq_flush(sq))
1355                 return;
1356
1357         /* If the interval between two consecutive recovers per SQ is too
1358          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1359          * If we reached this state, there is probably a bug that needs to be
1360          * fixed. let's keep the queue close and let tx timeout cleanup.
1361          */
1362         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1363             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1364                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1365                            sq->sqn);
1366                 return;
1367         }
1368
1369         /* At this point, no new packets will arrive from the stack as TXQ is
1370          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1371          * pending WQEs.  SQ can safely reset the SQ.
1372          */
1373         if (mlx5e_sq_to_ready(sq, state))
1374                 return;
1375
1376         mlx5e_reset_txqsq_cc_pc(sq);
1377         sq->stats->recover++;
1378         recover->last_recover = jiffies;
1379         mlx5e_activate_txqsq(sq);
1380 }
1381
1382 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1383                             struct mlx5e_params *params,
1384                             struct mlx5e_sq_param *param,
1385                             struct mlx5e_icosq *sq)
1386 {
1387         struct mlx5e_create_sq_param csp = {};
1388         int err;
1389
1390         err = mlx5e_alloc_icosq(c, param, sq);
1391         if (err)
1392                 return err;
1393
1394         csp.cqn             = sq->cq.mcq.cqn;
1395         csp.wq_ctrl         = &sq->wq_ctrl;
1396         csp.min_inline_mode = params->tx_min_inline_mode;
1397         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1398         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1399         if (err)
1400                 goto err_free_icosq;
1401
1402         return 0;
1403
1404 err_free_icosq:
1405         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1406         mlx5e_free_icosq(sq);
1407
1408         return err;
1409 }
1410
1411 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1412 {
1413         struct mlx5e_channel *c = sq->channel;
1414
1415         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1416         napi_synchronize(&c->napi);
1417
1418         mlx5e_destroy_sq(c->mdev, sq->sqn);
1419         mlx5e_free_icosq(sq);
1420 }
1421
1422 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1423                             struct mlx5e_params *params,
1424                             struct mlx5e_sq_param *param,
1425                             struct mlx5e_xdpsq *sq)
1426 {
1427         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1428         struct mlx5e_create_sq_param csp = {};
1429         unsigned int inline_hdr_sz = 0;
1430         int err;
1431         int i;
1432
1433         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1434         if (err)
1435                 return err;
1436
1437         csp.tis_lst_sz      = 1;
1438         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1439         csp.cqn             = sq->cq.mcq.cqn;
1440         csp.wq_ctrl         = &sq->wq_ctrl;
1441         csp.min_inline_mode = sq->min_inline_mode;
1442         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1443         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1444         if (err)
1445                 goto err_free_xdpsq;
1446
1447         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1448                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1449                 ds_cnt++;
1450         }
1451
1452         /* Pre initialize fixed WQE fields */
1453         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1454                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1455                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1456                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1457                 struct mlx5_wqe_data_seg *dseg;
1458
1459                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1460                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1461
1462                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1463                 dseg->lkey = sq->mkey_be;
1464         }
1465
1466         return 0;
1467
1468 err_free_xdpsq:
1469         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1470         mlx5e_free_xdpsq(sq);
1471
1472         return err;
1473 }
1474
1475 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1476 {
1477         struct mlx5e_channel *c = sq->channel;
1478
1479         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1480         napi_synchronize(&c->napi);
1481
1482         mlx5e_destroy_sq(c->mdev, sq->sqn);
1483         mlx5e_free_xdpsq_descs(sq);
1484         mlx5e_free_xdpsq(sq);
1485 }
1486
1487 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1488                                  struct mlx5e_cq_param *param,
1489                                  struct mlx5e_cq *cq)
1490 {
1491         struct mlx5_core_cq *mcq = &cq->mcq;
1492         int eqn_not_used;
1493         unsigned int irqn;
1494         int err;
1495         u32 i;
1496
1497         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1498                                &cq->wq_ctrl);
1499         if (err)
1500                 return err;
1501
1502         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1503
1504         mcq->cqe_sz     = 64;
1505         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1506         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1507         *mcq->set_ci_db = 0;
1508         *mcq->arm_db    = 0;
1509         mcq->vector     = param->eq_ix;
1510         mcq->comp       = mlx5e_completion_event;
1511         mcq->event      = mlx5e_cq_error_event;
1512         mcq->irqn       = irqn;
1513
1514         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1515                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1516
1517                 cqe->op_own = 0xf1;
1518         }
1519
1520         cq->mdev = mdev;
1521
1522         return 0;
1523 }
1524
1525 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1526                           struct mlx5e_cq_param *param,
1527                           struct mlx5e_cq *cq)
1528 {
1529         struct mlx5_core_dev *mdev = c->priv->mdev;
1530         int err;
1531
1532         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1533         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1534         param->eq_ix   = c->ix;
1535
1536         err = mlx5e_alloc_cq_common(mdev, param, cq);
1537
1538         cq->napi    = &c->napi;
1539         cq->channel = c;
1540
1541         return err;
1542 }
1543
1544 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1545 {
1546         mlx5_wq_destroy(&cq->wq_ctrl);
1547 }
1548
1549 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1550 {
1551         struct mlx5_core_dev *mdev = cq->mdev;
1552         struct mlx5_core_cq *mcq = &cq->mcq;
1553
1554         void *in;
1555         void *cqc;
1556         int inlen;
1557         unsigned int irqn_not_used;
1558         int eqn;
1559         int err;
1560
1561         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1562                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1563         in = kvzalloc(inlen, GFP_KERNEL);
1564         if (!in)
1565                 return -ENOMEM;
1566
1567         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1568
1569         memcpy(cqc, param->cqc, sizeof(param->cqc));
1570
1571         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1572                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1573
1574         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1575
1576         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1577         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1578         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1579         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1580                                             MLX5_ADAPTER_PAGE_SHIFT);
1581         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1582
1583         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1584
1585         kvfree(in);
1586
1587         if (err)
1588                 return err;
1589
1590         mlx5e_cq_arm(cq);
1591
1592         return 0;
1593 }
1594
1595 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1596 {
1597         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1598 }
1599
1600 static int mlx5e_open_cq(struct mlx5e_channel *c,
1601                          struct net_dim_cq_moder moder,
1602                          struct mlx5e_cq_param *param,
1603                          struct mlx5e_cq *cq)
1604 {
1605         struct mlx5_core_dev *mdev = c->mdev;
1606         int err;
1607
1608         err = mlx5e_alloc_cq(c, param, cq);
1609         if (err)
1610                 return err;
1611
1612         err = mlx5e_create_cq(cq, param);
1613         if (err)
1614                 goto err_free_cq;
1615
1616         if (MLX5_CAP_GEN(mdev, cq_moderation))
1617                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1618         return 0;
1619
1620 err_free_cq:
1621         mlx5e_free_cq(cq);
1622
1623         return err;
1624 }
1625
1626 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1627 {
1628         mlx5e_destroy_cq(cq);
1629         mlx5e_free_cq(cq);
1630 }
1631
1632 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1633 {
1634         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1635 }
1636
1637 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1638                              struct mlx5e_params *params,
1639                              struct mlx5e_channel_param *cparam)
1640 {
1641         int err;
1642         int tc;
1643
1644         for (tc = 0; tc < c->num_tc; tc++) {
1645                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1646                                     &cparam->tx_cq, &c->sq[tc].cq);
1647                 if (err)
1648                         goto err_close_tx_cqs;
1649         }
1650
1651         return 0;
1652
1653 err_close_tx_cqs:
1654         for (tc--; tc >= 0; tc--)
1655                 mlx5e_close_cq(&c->sq[tc].cq);
1656
1657         return err;
1658 }
1659
1660 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1661 {
1662         int tc;
1663
1664         for (tc = 0; tc < c->num_tc; tc++)
1665                 mlx5e_close_cq(&c->sq[tc].cq);
1666 }
1667
1668 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1669                           struct mlx5e_params *params,
1670                           struct mlx5e_channel_param *cparam)
1671 {
1672         struct mlx5e_priv *priv = c->priv;
1673         int err, tc, max_nch = priv->profile->max_nch(priv->mdev);
1674
1675         for (tc = 0; tc < params->num_tc; tc++) {
1676                 int txq_ix = c->ix + tc * max_nch;
1677
1678                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1679                                        params, &cparam->sq, &c->sq[tc], tc);
1680                 if (err)
1681                         goto err_close_sqs;
1682         }
1683
1684         return 0;
1685
1686 err_close_sqs:
1687         for (tc--; tc >= 0; tc--)
1688                 mlx5e_close_txqsq(&c->sq[tc]);
1689
1690         return err;
1691 }
1692
1693 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1694 {
1695         int tc;
1696
1697         for (tc = 0; tc < c->num_tc; tc++)
1698                 mlx5e_close_txqsq(&c->sq[tc]);
1699 }
1700
1701 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1702                                 struct mlx5e_txqsq *sq, u32 rate)
1703 {
1704         struct mlx5e_priv *priv = netdev_priv(dev);
1705         struct mlx5_core_dev *mdev = priv->mdev;
1706         struct mlx5e_modify_sq_param msp = {0};
1707         struct mlx5_rate_limit rl = {0};
1708         u16 rl_index = 0;
1709         int err;
1710
1711         if (rate == sq->rate_limit)
1712                 /* nothing to do */
1713                 return 0;
1714
1715         if (sq->rate_limit) {
1716                 rl.rate = sq->rate_limit;
1717                 /* remove current rl index to free space to next ones */
1718                 mlx5_rl_remove_rate(mdev, &rl);
1719         }
1720
1721         sq->rate_limit = 0;
1722
1723         if (rate) {
1724                 rl.rate = rate;
1725                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1726                 if (err) {
1727                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1728                                    rate, err);
1729                         return err;
1730                 }
1731         }
1732
1733         msp.curr_state = MLX5_SQC_STATE_RDY;
1734         msp.next_state = MLX5_SQC_STATE_RDY;
1735         msp.rl_index   = rl_index;
1736         msp.rl_update  = true;
1737         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1738         if (err) {
1739                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1740                            rate, err);
1741                 /* remove the rate from the table */
1742                 if (rate)
1743                         mlx5_rl_remove_rate(mdev, &rl);
1744                 return err;
1745         }
1746
1747         sq->rate_limit = rate;
1748         return 0;
1749 }
1750
1751 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1752 {
1753         struct mlx5e_priv *priv = netdev_priv(dev);
1754         struct mlx5_core_dev *mdev = priv->mdev;
1755         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1756         int err = 0;
1757
1758         if (!mlx5_rl_is_supported(mdev)) {
1759                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1760                 return -EINVAL;
1761         }
1762
1763         /* rate is given in Mb/sec, HW config is in Kb/sec */
1764         rate = rate << 10;
1765
1766         /* Check whether rate in valid range, 0 is always valid */
1767         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1768                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1769                 return -ERANGE;
1770         }
1771
1772         mutex_lock(&priv->state_lock);
1773         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1774                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1775         if (!err)
1776                 priv->tx_rates[index] = rate;
1777         mutex_unlock(&priv->state_lock);
1778
1779         return err;
1780 }
1781
1782 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1783                               struct mlx5e_params *params,
1784                               struct mlx5e_channel_param *cparam,
1785                               struct mlx5e_channel **cp)
1786 {
1787         struct net_dim_cq_moder icocq_moder = {0, 0};
1788         struct net_device *netdev = priv->netdev;
1789         int cpu = mlx5e_get_cpu(priv, ix);
1790         struct mlx5e_channel *c;
1791         unsigned int irq;
1792         int err;
1793         int eqn;
1794
1795         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1796         if (!c)
1797                 return -ENOMEM;
1798
1799         c->priv     = priv;
1800         c->mdev     = priv->mdev;
1801         c->tstamp   = &priv->tstamp;
1802         c->ix       = ix;
1803         c->cpu      = cpu;
1804         c->pdev     = &priv->mdev->pdev->dev;
1805         c->netdev   = priv->netdev;
1806         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1807         c->num_tc   = params->num_tc;
1808         c->xdp      = !!params->xdp_prog;
1809         c->stats    = &priv->channel_stats[ix].ch;
1810
1811         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1812         c->irq_desc = irq_to_desc(irq);
1813
1814         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1815
1816         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1817         if (err)
1818                 goto err_napi_del;
1819
1820         err = mlx5e_open_tx_cqs(c, params, cparam);
1821         if (err)
1822                 goto err_close_icosq_cq;
1823
1824         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1825         if (err)
1826                 goto err_close_tx_cqs;
1827
1828         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1829         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1830                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1831         if (err)
1832                 goto err_close_rx_cq;
1833
1834         napi_enable(&c->napi);
1835
1836         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1837         if (err)
1838                 goto err_disable_napi;
1839
1840         err = mlx5e_open_sqs(c, params, cparam);
1841         if (err)
1842                 goto err_close_icosq;
1843
1844         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1845         if (err)
1846                 goto err_close_sqs;
1847
1848         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1849         if (err)
1850                 goto err_close_xdp_sq;
1851
1852         *cp = c;
1853
1854         return 0;
1855 err_close_xdp_sq:
1856         if (c->xdp)
1857                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1858
1859 err_close_sqs:
1860         mlx5e_close_sqs(c);
1861
1862 err_close_icosq:
1863         mlx5e_close_icosq(&c->icosq);
1864
1865 err_disable_napi:
1866         napi_disable(&c->napi);
1867         if (c->xdp)
1868                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1869
1870 err_close_rx_cq:
1871         mlx5e_close_cq(&c->rq.cq);
1872
1873 err_close_tx_cqs:
1874         mlx5e_close_tx_cqs(c);
1875
1876 err_close_icosq_cq:
1877         mlx5e_close_cq(&c->icosq.cq);
1878
1879 err_napi_del:
1880         netif_napi_del(&c->napi);
1881         kfree(c);
1882
1883         return err;
1884 }
1885
1886 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1887 {
1888         int tc;
1889
1890         for (tc = 0; tc < c->num_tc; tc++)
1891                 mlx5e_activate_txqsq(&c->sq[tc]);
1892         mlx5e_activate_rq(&c->rq);
1893         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1894 }
1895
1896 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1897 {
1898         int tc;
1899
1900         mlx5e_deactivate_rq(&c->rq);
1901         for (tc = 0; tc < c->num_tc; tc++)
1902                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1903 }
1904
1905 static void mlx5e_close_channel(struct mlx5e_channel *c)
1906 {
1907         mlx5e_close_rq(&c->rq);
1908         if (c->xdp)
1909                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1910         mlx5e_close_sqs(c);
1911         mlx5e_close_icosq(&c->icosq);
1912         napi_disable(&c->napi);
1913         if (c->xdp)
1914                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1915         mlx5e_close_cq(&c->rq.cq);
1916         mlx5e_close_tx_cqs(c);
1917         mlx5e_close_cq(&c->icosq.cq);
1918         netif_napi_del(&c->napi);
1919
1920         kfree(c);
1921 }
1922
1923 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1924                                  struct mlx5e_params *params,
1925                                  struct mlx5e_rq_param *param)
1926 {
1927         struct mlx5_core_dev *mdev = priv->mdev;
1928         void *rqc = param->rqc;
1929         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1930
1931         switch (params->rq_wq_type) {
1932         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1933                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1934                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
1935                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
1936                 MLX5_SET(wq, wq, log_wqe_stride_size,
1937                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
1938                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
1939                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1940                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
1941                 break;
1942         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1943                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1944                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
1945         }
1946
1947         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1948         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1949         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
1950         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1951         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
1952         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
1953
1954         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1955 }
1956
1957 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
1958                                       struct mlx5e_rq_param *param)
1959 {
1960         struct mlx5_core_dev *mdev = priv->mdev;
1961         void *rqc = param->rqc;
1962         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1963
1964         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1965         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1966         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
1967
1968         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1969 }
1970
1971 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1972                                         struct mlx5e_sq_param *param)
1973 {
1974         void *sqc = param->sqc;
1975         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1976
1977         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1978         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1979
1980         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1981 }
1982
1983 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1984                                  struct mlx5e_params *params,
1985                                  struct mlx5e_sq_param *param)
1986 {
1987         void *sqc = param->sqc;
1988         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1989
1990         mlx5e_build_sq_param_common(priv, param);
1991         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1992         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1993 }
1994
1995 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1996                                         struct mlx5e_cq_param *param)
1997 {
1998         void *cqc = param->cqc;
1999
2000         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2001 }
2002
2003 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2004                                     struct mlx5e_params *params,
2005                                     struct mlx5e_cq_param *param)
2006 {
2007         struct mlx5_core_dev *mdev = priv->mdev;
2008         void *cqc = param->cqc;
2009         u8 log_cq_size;
2010
2011         switch (params->rq_wq_type) {
2012         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2013                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2014                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2015                 break;
2016         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2017                 log_cq_size = params->log_rq_mtu_frames;
2018         }
2019
2020         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2021         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2022                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2023                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2024         }
2025
2026         mlx5e_build_common_cq_param(priv, param);
2027         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2028 }
2029
2030 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2031                                     struct mlx5e_params *params,
2032                                     struct mlx5e_cq_param *param)
2033 {
2034         void *cqc = param->cqc;
2035
2036         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2037
2038         mlx5e_build_common_cq_param(priv, param);
2039         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2040 }
2041
2042 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2043                                      u8 log_wq_size,
2044                                      struct mlx5e_cq_param *param)
2045 {
2046         void *cqc = param->cqc;
2047
2048         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2049
2050         mlx5e_build_common_cq_param(priv, param);
2051
2052         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2053 }
2054
2055 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2056                                     u8 log_wq_size,
2057                                     struct mlx5e_sq_param *param)
2058 {
2059         void *sqc = param->sqc;
2060         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2061
2062         mlx5e_build_sq_param_common(priv, param);
2063
2064         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2065         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2066 }
2067
2068 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2069                                     struct mlx5e_params *params,
2070                                     struct mlx5e_sq_param *param)
2071 {
2072         void *sqc = param->sqc;
2073         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2074
2075         mlx5e_build_sq_param_common(priv, param);
2076         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2077 }
2078
2079 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2080                                       struct mlx5e_params *params,
2081                                       struct mlx5e_channel_param *cparam)
2082 {
2083         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2084
2085         mlx5e_build_rq_param(priv, params, &cparam->rq);
2086         mlx5e_build_sq_param(priv, params, &cparam->sq);
2087         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2088         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2089         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2090         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2091         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2092 }
2093
2094 int mlx5e_open_channels(struct mlx5e_priv *priv,
2095                         struct mlx5e_channels *chs)
2096 {
2097         struct mlx5e_channel_param *cparam;
2098         int err = -ENOMEM;
2099         int i;
2100
2101         chs->num = chs->params.num_channels;
2102
2103         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2104         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2105         if (!chs->c || !cparam)
2106                 goto err_free;
2107
2108         mlx5e_build_channel_param(priv, &chs->params, cparam);
2109         for (i = 0; i < chs->num; i++) {
2110                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2111                 if (err)
2112                         goto err_close_channels;
2113         }
2114
2115         kfree(cparam);
2116         return 0;
2117
2118 err_close_channels:
2119         for (i--; i >= 0; i--)
2120                 mlx5e_close_channel(chs->c[i]);
2121
2122 err_free:
2123         kfree(chs->c);
2124         kfree(cparam);
2125         chs->num = 0;
2126         return err;
2127 }
2128
2129 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2130 {
2131         int i;
2132
2133         for (i = 0; i < chs->num; i++)
2134                 mlx5e_activate_channel(chs->c[i]);
2135 }
2136
2137 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2138 {
2139         int err = 0;
2140         int i;
2141
2142         for (i = 0; i < chs->num; i++)
2143                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2144                                                   err ? 0 : 20000);
2145
2146         return err ? -ETIMEDOUT : 0;
2147 }
2148
2149 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2150 {
2151         int i;
2152
2153         for (i = 0; i < chs->num; i++)
2154                 mlx5e_deactivate_channel(chs->c[i]);
2155 }
2156
2157 void mlx5e_close_channels(struct mlx5e_channels *chs)
2158 {
2159         int i;
2160
2161         for (i = 0; i < chs->num; i++)
2162                 mlx5e_close_channel(chs->c[i]);
2163
2164         kfree(chs->c);
2165         chs->num = 0;
2166 }
2167
2168 static int
2169 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2170 {
2171         struct mlx5_core_dev *mdev = priv->mdev;
2172         void *rqtc;
2173         int inlen;
2174         int err;
2175         u32 *in;
2176         int i;
2177
2178         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2179         in = kvzalloc(inlen, GFP_KERNEL);
2180         if (!in)
2181                 return -ENOMEM;
2182
2183         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2184
2185         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2186         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2187
2188         for (i = 0; i < sz; i++)
2189                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2190
2191         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2192         if (!err)
2193                 rqt->enabled = true;
2194
2195         kvfree(in);
2196         return err;
2197 }
2198
2199 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2200 {
2201         rqt->enabled = false;
2202         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2203 }
2204
2205 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2206 {
2207         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2208         int err;
2209
2210         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2211         if (err)
2212                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2213         return err;
2214 }
2215
2216 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2217 {
2218         struct mlx5e_rqt *rqt;
2219         int err;
2220         int ix;
2221
2222         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2223                 rqt = &priv->direct_tir[ix].rqt;
2224                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2225                 if (err)
2226                         goto err_destroy_rqts;
2227         }
2228
2229         return 0;
2230
2231 err_destroy_rqts:
2232         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2233         for (ix--; ix >= 0; ix--)
2234                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2235
2236         return err;
2237 }
2238
2239 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2240 {
2241         int i;
2242
2243         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2244                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2245 }
2246
2247 static int mlx5e_rx_hash_fn(int hfunc)
2248 {
2249         return (hfunc == ETH_RSS_HASH_TOP) ?
2250                MLX5_RX_HASH_FN_TOEPLITZ :
2251                MLX5_RX_HASH_FN_INVERTED_XOR8;
2252 }
2253
2254 int mlx5e_bits_invert(unsigned long a, int size)
2255 {
2256         int inv = 0;
2257         int i;
2258
2259         for (i = 0; i < size; i++)
2260                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2261
2262         return inv;
2263 }
2264
2265 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2266                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2267 {
2268         int i;
2269
2270         for (i = 0; i < sz; i++) {
2271                 u32 rqn;
2272
2273                 if (rrp.is_rss) {
2274                         int ix = i;
2275
2276                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2277                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2278
2279                         ix = priv->channels.params.indirection_rqt[ix];
2280                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2281                 } else {
2282                         rqn = rrp.rqn;
2283                 }
2284                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2285         }
2286 }
2287
2288 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2289                        struct mlx5e_redirect_rqt_param rrp)
2290 {
2291         struct mlx5_core_dev *mdev = priv->mdev;
2292         void *rqtc;
2293         int inlen;
2294         u32 *in;
2295         int err;
2296
2297         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2298         in = kvzalloc(inlen, GFP_KERNEL);
2299         if (!in)
2300                 return -ENOMEM;
2301
2302         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2303
2304         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2305         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2306         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2307         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2308
2309         kvfree(in);
2310         return err;
2311 }
2312
2313 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2314                                 struct mlx5e_redirect_rqt_param rrp)
2315 {
2316         if (!rrp.is_rss)
2317                 return rrp.rqn;
2318
2319         if (ix >= rrp.rss.channels->num)
2320                 return priv->drop_rq.rqn;
2321
2322         return rrp.rss.channels->c[ix]->rq.rqn;
2323 }
2324
2325 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2326                                 struct mlx5e_redirect_rqt_param rrp)
2327 {
2328         u32 rqtn;
2329         int ix;
2330
2331         if (priv->indir_rqt.enabled) {
2332                 /* RSS RQ table */
2333                 rqtn = priv->indir_rqt.rqtn;
2334                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2335         }
2336
2337         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2338                 struct mlx5e_redirect_rqt_param direct_rrp = {
2339                         .is_rss = false,
2340                         {
2341                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2342                         },
2343                 };
2344
2345                 /* Direct RQ Tables */
2346                 if (!priv->direct_tir[ix].rqt.enabled)
2347                         continue;
2348
2349                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2350                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2351         }
2352 }
2353
2354 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2355                                             struct mlx5e_channels *chs)
2356 {
2357         struct mlx5e_redirect_rqt_param rrp = {
2358                 .is_rss        = true,
2359                 {
2360                         .rss = {
2361                                 .channels  = chs,
2362                                 .hfunc     = chs->params.rss_hfunc,
2363                         }
2364                 },
2365         };
2366
2367         mlx5e_redirect_rqts(priv, rrp);
2368 }
2369
2370 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2371 {
2372         struct mlx5e_redirect_rqt_param drop_rrp = {
2373                 .is_rss = false,
2374                 {
2375                         .rqn = priv->drop_rq.rqn,
2376                 },
2377         };
2378
2379         mlx5e_redirect_rqts(priv, drop_rrp);
2380 }
2381
2382 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2383 {
2384         if (!params->lro_en)
2385                 return;
2386
2387 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2388
2389         MLX5_SET(tirc, tirc, lro_enable_mask,
2390                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2391                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2392         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2393                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2394         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2395 }
2396
2397 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2398                                     enum mlx5e_traffic_types tt,
2399                                     void *tirc, bool inner)
2400 {
2401         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2402                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2403
2404 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2405                                  MLX5_HASH_FIELD_SEL_DST_IP)
2406
2407 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2408                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2409                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2410                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2411
2412 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2413                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2414                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2415
2416         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2417         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2418                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2419                                              rx_hash_toeplitz_key);
2420                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2421                                                rx_hash_toeplitz_key);
2422
2423                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2424                 memcpy(rss_key, params->toeplitz_hash_key, len);
2425         }
2426
2427         switch (tt) {
2428         case MLX5E_TT_IPV4_TCP:
2429                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2430                          MLX5_L3_PROT_TYPE_IPV4);
2431                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2432                          MLX5_L4_PROT_TYPE_TCP);
2433                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2434                          MLX5_HASH_IP_L4PORTS);
2435                 break;
2436
2437         case MLX5E_TT_IPV6_TCP:
2438                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2439                          MLX5_L3_PROT_TYPE_IPV6);
2440                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2441                          MLX5_L4_PROT_TYPE_TCP);
2442                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2443                          MLX5_HASH_IP_L4PORTS);
2444                 break;
2445
2446         case MLX5E_TT_IPV4_UDP:
2447                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2448                          MLX5_L3_PROT_TYPE_IPV4);
2449                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2450                          MLX5_L4_PROT_TYPE_UDP);
2451                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2452                          MLX5_HASH_IP_L4PORTS);
2453                 break;
2454
2455         case MLX5E_TT_IPV6_UDP:
2456                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2457                          MLX5_L3_PROT_TYPE_IPV6);
2458                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2459                          MLX5_L4_PROT_TYPE_UDP);
2460                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2461                          MLX5_HASH_IP_L4PORTS);
2462                 break;
2463
2464         case MLX5E_TT_IPV4_IPSEC_AH:
2465                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2466                          MLX5_L3_PROT_TYPE_IPV4);
2467                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2468                          MLX5_HASH_IP_IPSEC_SPI);
2469                 break;
2470
2471         case MLX5E_TT_IPV6_IPSEC_AH:
2472                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2473                          MLX5_L3_PROT_TYPE_IPV6);
2474                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2475                          MLX5_HASH_IP_IPSEC_SPI);
2476                 break;
2477
2478         case MLX5E_TT_IPV4_IPSEC_ESP:
2479                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2480                          MLX5_L3_PROT_TYPE_IPV4);
2481                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2482                          MLX5_HASH_IP_IPSEC_SPI);
2483                 break;
2484
2485         case MLX5E_TT_IPV6_IPSEC_ESP:
2486                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2487                          MLX5_L3_PROT_TYPE_IPV6);
2488                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2489                          MLX5_HASH_IP_IPSEC_SPI);
2490                 break;
2491
2492         case MLX5E_TT_IPV4:
2493                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2494                          MLX5_L3_PROT_TYPE_IPV4);
2495                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2496                          MLX5_HASH_IP);
2497                 break;
2498
2499         case MLX5E_TT_IPV6:
2500                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2501                          MLX5_L3_PROT_TYPE_IPV6);
2502                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2503                          MLX5_HASH_IP);
2504                 break;
2505         default:
2506                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2507         }
2508 }
2509
2510 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2511 {
2512         struct mlx5_core_dev *mdev = priv->mdev;
2513
2514         void *in;
2515         void *tirc;
2516         int inlen;
2517         int err;
2518         int tt;
2519         int ix;
2520
2521         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2522         in = kvzalloc(inlen, GFP_KERNEL);
2523         if (!in)
2524                 return -ENOMEM;
2525
2526         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2527         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2528
2529         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2530
2531         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2532                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2533                                            inlen);
2534                 if (err)
2535                         goto free_in;
2536         }
2537
2538         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2539                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2540                                            in, inlen);
2541                 if (err)
2542                         goto free_in;
2543         }
2544
2545 free_in:
2546         kvfree(in);
2547
2548         return err;
2549 }
2550
2551 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2552                                             enum mlx5e_traffic_types tt,
2553                                             u32 *tirc)
2554 {
2555         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2556
2557         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2558
2559         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2560         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2561         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2562
2563         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2564 }
2565
2566 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2567                          struct mlx5e_params *params, u16 mtu)
2568 {
2569         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2570         int err;
2571
2572         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2573         if (err)
2574                 return err;
2575
2576         /* Update vport context MTU */
2577         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2578         return 0;
2579 }
2580
2581 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2582                             struct mlx5e_params *params, u16 *mtu)
2583 {
2584         u16 hw_mtu = 0;
2585         int err;
2586
2587         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2588         if (err || !hw_mtu) /* fallback to port oper mtu */
2589                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2590
2591         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2592 }
2593
2594 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2595 {
2596         struct mlx5e_params *params = &priv->channels.params;
2597         struct net_device *netdev = priv->netdev;
2598         struct mlx5_core_dev *mdev = priv->mdev;
2599         u16 mtu;
2600         int err;
2601
2602         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2603         if (err)
2604                 return err;
2605
2606         mlx5e_query_mtu(mdev, params, &mtu);
2607         if (mtu != params->sw_mtu)
2608                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2609                             __func__, mtu, params->sw_mtu);
2610
2611         params->sw_mtu = mtu;
2612         return 0;
2613 }
2614
2615 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2616 {
2617         struct mlx5e_priv *priv = netdev_priv(netdev);
2618         int nch = priv->channels.params.num_channels;
2619         int ntc = priv->channels.params.num_tc;
2620         int tc;
2621
2622         netdev_reset_tc(netdev);
2623
2624         if (ntc == 1)
2625                 return;
2626
2627         netdev_set_num_tc(netdev, ntc);
2628
2629         /* Map netdev TCs to offset 0
2630          * We have our own UP to TXQ mapping for QoS
2631          */
2632         for (tc = 0; tc < ntc; tc++)
2633                 netdev_set_tc_queue(netdev, tc, nch, 0);
2634 }
2635
2636 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2637 {
2638         int max_nch = priv->profile->max_nch(priv->mdev);
2639         int i, tc;
2640
2641         for (i = 0; i < max_nch; i++)
2642                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2643                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2644 }
2645
2646 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2647 {
2648         struct mlx5e_channel *c;
2649         struct mlx5e_txqsq *sq;
2650         int i, tc;
2651
2652         for (i = 0; i < priv->channels.num; i++) {
2653                 c = priv->channels.c[i];
2654                 for (tc = 0; tc < c->num_tc; tc++) {
2655                         sq = &c->sq[tc];
2656                         priv->txq2sq[sq->txq_ix] = sq;
2657                 }
2658         }
2659 }
2660
2661 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2662 {
2663         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2664         struct net_device *netdev = priv->netdev;
2665
2666         mlx5e_netdev_set_tcs(netdev);
2667         netif_set_real_num_tx_queues(netdev, num_txqs);
2668         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2669
2670         mlx5e_build_tx2sq_maps(priv);
2671         mlx5e_activate_channels(&priv->channels);
2672         netif_tx_start_all_queues(priv->netdev);
2673
2674         if (MLX5_VPORT_MANAGER(priv->mdev))
2675                 mlx5e_add_sqs_fwd_rules(priv);
2676
2677         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2678         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2679 }
2680
2681 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2682 {
2683         mlx5e_redirect_rqts_to_drop(priv);
2684
2685         if (MLX5_VPORT_MANAGER(priv->mdev))
2686                 mlx5e_remove_sqs_fwd_rules(priv);
2687
2688         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2689          * polling for inactive tx queues.
2690          */
2691         netif_tx_stop_all_queues(priv->netdev);
2692         netif_tx_disable(priv->netdev);
2693         mlx5e_deactivate_channels(&priv->channels);
2694 }
2695
2696 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2697                                 struct mlx5e_channels *new_chs,
2698                                 mlx5e_fp_hw_modify hw_modify)
2699 {
2700         struct net_device *netdev = priv->netdev;
2701         int new_num_txqs;
2702         int carrier_ok;
2703         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2704
2705         carrier_ok = netif_carrier_ok(netdev);
2706         netif_carrier_off(netdev);
2707
2708         if (new_num_txqs < netdev->real_num_tx_queues)
2709                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2710
2711         mlx5e_deactivate_priv_channels(priv);
2712         mlx5e_close_channels(&priv->channels);
2713
2714         priv->channels = *new_chs;
2715
2716         /* New channels are ready to roll, modify HW settings if needed */
2717         if (hw_modify)
2718                 hw_modify(priv);
2719
2720         mlx5e_refresh_tirs(priv, false);
2721         mlx5e_activate_priv_channels(priv);
2722
2723         /* return carrier back if needed */
2724         if (carrier_ok)
2725                 netif_carrier_on(netdev);
2726 }
2727
2728 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2729 {
2730         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2731         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2732 }
2733
2734 int mlx5e_open_locked(struct net_device *netdev)
2735 {
2736         struct mlx5e_priv *priv = netdev_priv(netdev);
2737         int err;
2738
2739         set_bit(MLX5E_STATE_OPENED, &priv->state);
2740
2741         err = mlx5e_open_channels(priv, &priv->channels);
2742         if (err)
2743                 goto err_clear_state_opened_flag;
2744
2745         mlx5e_refresh_tirs(priv, false);
2746         mlx5e_activate_priv_channels(priv);
2747         if (priv->profile->update_carrier)
2748                 priv->profile->update_carrier(priv);
2749
2750         if (priv->profile->update_stats)
2751                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2752
2753         return 0;
2754
2755 err_clear_state_opened_flag:
2756         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2757         return err;
2758 }
2759
2760 int mlx5e_open(struct net_device *netdev)
2761 {
2762         struct mlx5e_priv *priv = netdev_priv(netdev);
2763         int err;
2764
2765         mutex_lock(&priv->state_lock);
2766         err = mlx5e_open_locked(netdev);
2767         if (!err)
2768                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2769         mutex_unlock(&priv->state_lock);
2770
2771         if (mlx5e_vxlan_allowed(priv->mdev))
2772                 udp_tunnel_get_rx_info(netdev);
2773
2774         return err;
2775 }
2776
2777 int mlx5e_close_locked(struct net_device *netdev)
2778 {
2779         struct mlx5e_priv *priv = netdev_priv(netdev);
2780
2781         /* May already be CLOSED in case a previous configuration operation
2782          * (e.g RX/TX queue size change) that involves close&open failed.
2783          */
2784         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2785                 return 0;
2786
2787         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2788
2789         netif_carrier_off(priv->netdev);
2790         mlx5e_deactivate_priv_channels(priv);
2791         mlx5e_close_channels(&priv->channels);
2792
2793         return 0;
2794 }
2795
2796 int mlx5e_close(struct net_device *netdev)
2797 {
2798         struct mlx5e_priv *priv = netdev_priv(netdev);
2799         int err;
2800
2801         if (!netif_device_present(netdev))
2802                 return -ENODEV;
2803
2804         mutex_lock(&priv->state_lock);
2805         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2806         err = mlx5e_close_locked(netdev);
2807         mutex_unlock(&priv->state_lock);
2808
2809         return err;
2810 }
2811
2812 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2813                                struct mlx5e_rq *rq,
2814                                struct mlx5e_rq_param *param)
2815 {
2816         void *rqc = param->rqc;
2817         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2818         int err;
2819
2820         param->wq.db_numa_node = param->wq.buf_numa_node;
2821
2822         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2823                                 &rq->wq_ctrl);
2824         if (err)
2825                 return err;
2826
2827         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2828         xdp_rxq_info_unused(&rq->xdp_rxq);
2829
2830         rq->mdev = mdev;
2831
2832         return 0;
2833 }
2834
2835 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2836                                struct mlx5e_cq *cq,
2837                                struct mlx5e_cq_param *param)
2838 {
2839         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2840         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
2841
2842         return mlx5e_alloc_cq_common(mdev, param, cq);
2843 }
2844
2845 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2846                               struct mlx5e_rq *drop_rq)
2847 {
2848         struct mlx5_core_dev *mdev = priv->mdev;
2849         struct mlx5e_cq_param cq_param = {};
2850         struct mlx5e_rq_param rq_param = {};
2851         struct mlx5e_cq *cq = &drop_rq->cq;
2852         int err;
2853
2854         mlx5e_build_drop_rq_param(priv, &rq_param);
2855
2856         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2857         if (err)
2858                 return err;
2859
2860         err = mlx5e_create_cq(cq, &cq_param);
2861         if (err)
2862                 goto err_free_cq;
2863
2864         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2865         if (err)
2866                 goto err_destroy_cq;
2867
2868         err = mlx5e_create_rq(drop_rq, &rq_param);
2869         if (err)
2870                 goto err_free_rq;
2871
2872         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2873         if (err)
2874                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2875
2876         return 0;
2877
2878 err_free_rq:
2879         mlx5e_free_rq(drop_rq);
2880
2881 err_destroy_cq:
2882         mlx5e_destroy_cq(cq);
2883
2884 err_free_cq:
2885         mlx5e_free_cq(cq);
2886
2887         return err;
2888 }
2889
2890 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2891 {
2892         mlx5e_destroy_rq(drop_rq);
2893         mlx5e_free_rq(drop_rq);
2894         mlx5e_destroy_cq(&drop_rq->cq);
2895         mlx5e_free_cq(&drop_rq->cq);
2896 }
2897
2898 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2899                      u32 underlay_qpn, u32 *tisn)
2900 {
2901         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2902         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2903
2904         MLX5_SET(tisc, tisc, prio, tc << 1);
2905         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2906         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2907
2908         if (mlx5_lag_is_lacp_owner(mdev))
2909                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2910
2911         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2912 }
2913
2914 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2915 {
2916         mlx5_core_destroy_tis(mdev, tisn);
2917 }
2918
2919 int mlx5e_create_tises(struct mlx5e_priv *priv)
2920 {
2921         int err;
2922         int tc;
2923
2924         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2925                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2926                 if (err)
2927                         goto err_close_tises;
2928         }
2929
2930         return 0;
2931
2932 err_close_tises:
2933         for (tc--; tc >= 0; tc--)
2934                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2935
2936         return err;
2937 }
2938
2939 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2940 {
2941         int tc;
2942
2943         for (tc = 0; tc < priv->profile->max_tc; tc++)
2944                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2945 }
2946
2947 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2948                                       enum mlx5e_traffic_types tt,
2949                                       u32 *tirc)
2950 {
2951         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2952
2953         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2954
2955         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2956         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2957         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2958 }
2959
2960 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2961 {
2962         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2963
2964         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2965
2966         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2967         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2968         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2969 }
2970
2971 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2972 {
2973         struct mlx5e_tir *tir;
2974         void *tirc;
2975         int inlen;
2976         int i = 0;
2977         int err;
2978         u32 *in;
2979         int tt;
2980
2981         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2982         in = kvzalloc(inlen, GFP_KERNEL);
2983         if (!in)
2984                 return -ENOMEM;
2985
2986         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2987                 memset(in, 0, inlen);
2988                 tir = &priv->indir_tir[tt];
2989                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2990                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2991                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2992                 if (err) {
2993                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2994                         goto err_destroy_inner_tirs;
2995                 }
2996         }
2997
2998         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2999                 goto out;
3000
3001         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3002                 memset(in, 0, inlen);
3003                 tir = &priv->inner_indir_tir[i];
3004                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3005                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3006                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3007                 if (err) {
3008                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3009                         goto err_destroy_inner_tirs;
3010                 }
3011         }
3012
3013 out:
3014         kvfree(in);
3015
3016         return 0;
3017
3018 err_destroy_inner_tirs:
3019         for (i--; i >= 0; i--)
3020                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3021
3022         for (tt--; tt >= 0; tt--)
3023                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3024
3025         kvfree(in);
3026
3027         return err;
3028 }
3029
3030 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3031 {
3032         int nch = priv->profile->max_nch(priv->mdev);
3033         struct mlx5e_tir *tir;
3034         void *tirc;
3035         int inlen;
3036         int err;
3037         u32 *in;
3038         int ix;
3039
3040         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3041         in = kvzalloc(inlen, GFP_KERNEL);
3042         if (!in)
3043                 return -ENOMEM;
3044
3045         for (ix = 0; ix < nch; ix++) {
3046                 memset(in, 0, inlen);
3047                 tir = &priv->direct_tir[ix];
3048                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3049                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3050                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3051                 if (err)
3052                         goto err_destroy_ch_tirs;
3053         }
3054
3055         kvfree(in);
3056
3057         return 0;
3058
3059 err_destroy_ch_tirs:
3060         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3061         for (ix--; ix >= 0; ix--)
3062                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3063
3064         kvfree(in);
3065
3066         return err;
3067 }
3068
3069 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3070 {
3071         int i;
3072
3073         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3074                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3075
3076         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3077                 return;
3078
3079         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3080                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3081 }
3082
3083 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3084 {
3085         int nch = priv->profile->max_nch(priv->mdev);
3086         int i;
3087
3088         for (i = 0; i < nch; i++)
3089                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3090 }
3091
3092 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3093 {
3094         int err = 0;
3095         int i;
3096
3097         for (i = 0; i < chs->num; i++) {
3098                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);