net/mlx5e: Use PARTIAL_GSO for UDP segmentation
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include <net/page_pool.h>
39 #include "eswitch.h"
40 #include "en.h"
41 #include "en_tc.h"
42 #include "en_rep.h"
43 #include "en_accel/ipsec.h"
44 #include "en_accel/ipsec_rxtx.h"
45 #include "en_accel/tls.h"
46 #include "accel/ipsec.h"
47 #include "accel/tls.h"
48 #include "vxlan.h"
49 #include "en/port.h"
50
51 struct mlx5e_rq_param {
52         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
53         struct mlx5_wq_param    wq;
54         struct mlx5e_rq_frags_info frags_info;
55 };
56
57 struct mlx5e_sq_param {
58         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
59         struct mlx5_wq_param       wq;
60 };
61
62 struct mlx5e_cq_param {
63         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
64         struct mlx5_wq_param       wq;
65         u16                        eq_ix;
66         u8                         cq_period_mode;
67 };
68
69 struct mlx5e_channel_param {
70         struct mlx5e_rq_param      rq;
71         struct mlx5e_sq_param      sq;
72         struct mlx5e_sq_param      xdp_sq;
73         struct mlx5e_sq_param      icosq;
74         struct mlx5e_cq_param      rx_cq;
75         struct mlx5e_cq_param      tx_cq;
76         struct mlx5e_cq_param      icosq_cq;
77 };
78
79 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
80 {
81         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
82                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
83                 MLX5_CAP_ETH(mdev, reg_umr_sq);
84         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
85         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
86
87         if (!striding_rq_umr)
88                 return false;
89         if (!inline_umr) {
90                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
91                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
92                 return false;
93         }
94         return true;
95 }
96
97 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
98 {
99         if (!params->xdp_prog) {
100                 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
101                 u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN;
102
103                 return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu);
104         }
105
106         return PAGE_SIZE;
107 }
108
109 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
110 {
111         u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
112
113         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
114 }
115
116 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
117                                    struct mlx5e_params *params)
118 {
119         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
120
121         return !params->lro_en && frag_sz <= PAGE_SIZE;
122 }
123
124 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
125                                          struct mlx5e_params *params)
126 {
127         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
128         s8 signed_log_num_strides_param;
129         u8 log_num_strides;
130
131         if (!mlx5e_rx_is_linear_skb(mdev, params))
132                 return false;
133
134         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
135                 return true;
136
137         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
138         signed_log_num_strides_param =
139                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
140
141         return signed_log_num_strides_param >= 0;
142 }
143
144 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
145 {
146         if (params->log_rq_mtu_frames <
147             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
148                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
149
150         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
151 }
152
153 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
154                                           struct mlx5e_params *params)
155 {
156         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
157                 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
158
159         return MLX5E_MPWQE_STRIDE_SZ(mdev,
160                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
161 }
162
163 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
164                                           struct mlx5e_params *params)
165 {
166         return MLX5_MPWRQ_LOG_WQE_SZ -
167                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
168 }
169
170 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
171                                  struct mlx5e_params *params)
172 {
173         u16 linear_rq_headroom = params->xdp_prog ?
174                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
175         bool is_linear_skb;
176
177         linear_rq_headroom += NET_IP_ALIGN;
178
179         is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
180                 mlx5e_rx_is_linear_skb(mdev, params) :
181                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
182
183         return is_linear_skb ? linear_rq_headroom : 0;
184 }
185
186 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
187                                struct mlx5e_params *params)
188 {
189         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
190         params->log_rq_mtu_frames = is_kdump_kernel() ?
191                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
192                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
193
194         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
195                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
196                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
197                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
198                        BIT(params->log_rq_mtu_frames),
199                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
200                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
201 }
202
203 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
204                                 struct mlx5e_params *params)
205 {
206         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
207                 !MLX5_IPSEC_DEV(mdev) &&
208                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
209 }
210
211 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
212 {
213         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
214                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
215                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
216                 MLX5_WQ_TYPE_CYCLIC;
217 }
218
219 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
220 {
221         struct mlx5_core_dev *mdev = priv->mdev;
222         u8 port_state;
223
224         port_state = mlx5_query_vport_state(mdev,
225                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
226                                             0);
227
228         if (port_state == VPORT_STATE_UP) {
229                 netdev_info(priv->netdev, "Link up\n");
230                 netif_carrier_on(priv->netdev);
231         } else {
232                 netdev_info(priv->netdev, "Link down\n");
233                 netif_carrier_off(priv->netdev);
234         }
235 }
236
237 static void mlx5e_update_carrier_work(struct work_struct *work)
238 {
239         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
240                                                update_carrier_work);
241
242         mutex_lock(&priv->state_lock);
243         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
244                 if (priv->profile->update_carrier)
245                         priv->profile->update_carrier(priv);
246         mutex_unlock(&priv->state_lock);
247 }
248
249 void mlx5e_update_stats(struct mlx5e_priv *priv)
250 {
251         int i;
252
253         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
254                 if (mlx5e_stats_grps[i].update_stats)
255                         mlx5e_stats_grps[i].update_stats(priv);
256 }
257
258 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
259 {
260         int i;
261
262         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
263                 if (mlx5e_stats_grps[i].update_stats_mask &
264                     MLX5E_NDO_UPDATE_STATS)
265                         mlx5e_stats_grps[i].update_stats(priv);
266 }
267
268 void mlx5e_update_stats_work(struct work_struct *work)
269 {
270         struct delayed_work *dwork = to_delayed_work(work);
271         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
272                                                update_stats_work);
273
274         mutex_lock(&priv->state_lock);
275         priv->profile->update_stats(priv);
276         mutex_unlock(&priv->state_lock);
277 }
278
279 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
280                               enum mlx5_dev_event event, unsigned long param)
281 {
282         struct mlx5e_priv *priv = vpriv;
283
284         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
285                 return;
286
287         switch (event) {
288         case MLX5_DEV_EVENT_PORT_UP:
289         case MLX5_DEV_EVENT_PORT_DOWN:
290                 queue_work(priv->wq, &priv->update_carrier_work);
291                 break;
292         default:
293                 break;
294         }
295 }
296
297 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
298 {
299         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
300 }
301
302 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
303 {
304         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
305         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
306 }
307
308 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
309                                        struct mlx5e_icosq *sq,
310                                        struct mlx5e_umr_wqe *wqe)
311 {
312         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
313         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
314         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
315
316         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
317                                       ds_cnt);
318         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
319         cseg->imm       = rq->mkey_be;
320
321         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
322         ucseg->xlt_octowords =
323                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
324         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
325 }
326
327 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
328 {
329         switch (rq->wq_type) {
330         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
331                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
332         default:
333                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
334         }
335 }
336
337 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
338 {
339         switch (rq->wq_type) {
340         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
341                 return rq->mpwqe.wq.cur_sz;
342         default:
343                 return rq->wqe.wq.cur_sz;
344         }
345 }
346
347 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
348                                      struct mlx5e_channel *c)
349 {
350         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
351
352         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
353                                                   sizeof(*rq->mpwqe.info)),
354                                        GFP_KERNEL, cpu_to_node(c->cpu));
355         if (!rq->mpwqe.info)
356                 return -ENOMEM;
357
358         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
359
360         return 0;
361 }
362
363 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
364                                  u64 npages, u8 page_shift,
365                                  struct mlx5_core_mkey *umr_mkey)
366 {
367         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
368         void *mkc;
369         u32 *in;
370         int err;
371
372         in = kvzalloc(inlen, GFP_KERNEL);
373         if (!in)
374                 return -ENOMEM;
375
376         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
377
378         MLX5_SET(mkc, mkc, free, 1);
379         MLX5_SET(mkc, mkc, umr_en, 1);
380         MLX5_SET(mkc, mkc, lw, 1);
381         MLX5_SET(mkc, mkc, lr, 1);
382         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
383
384         MLX5_SET(mkc, mkc, qpn, 0xffffff);
385         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
386         MLX5_SET64(mkc, mkc, len, npages << page_shift);
387         MLX5_SET(mkc, mkc, translations_octword_size,
388                  MLX5_MTT_OCTW(npages));
389         MLX5_SET(mkc, mkc, log_page_size, page_shift);
390
391         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
392
393         kvfree(in);
394         return err;
395 }
396
397 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
398 {
399         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
400
401         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
402 }
403
404 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
405 {
406         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
407 }
408
409 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
410 {
411         struct mlx5e_wqe_frag_info next_frag, *prev;
412         int i;
413
414         next_frag.di = &rq->wqe.di[0];
415         next_frag.offset = 0;
416         prev = NULL;
417
418         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
419                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
420                 struct mlx5e_wqe_frag_info *frag =
421                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
422                 int f;
423
424                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
425                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
426                                 next_frag.di++;
427                                 next_frag.offset = 0;
428                                 if (prev)
429                                         prev->last_in_page = true;
430                         }
431                         *frag = next_frag;
432
433                         /* prepare next */
434                         next_frag.offset += frag_info[f].frag_stride;
435                         prev = frag;
436                 }
437         }
438
439         if (prev)
440                 prev->last_in_page = true;
441 }
442
443 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
444                               struct mlx5e_params *params,
445                               int wq_sz, int cpu)
446 {
447         int len = wq_sz << rq->wqe.info.log_num_frags;
448
449         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
450                                    GFP_KERNEL, cpu_to_node(cpu));
451         if (!rq->wqe.di)
452                 return -ENOMEM;
453
454         mlx5e_init_frags_partition(rq);
455
456         return 0;
457 }
458
459 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
460 {
461         kvfree(rq->wqe.di);
462 }
463
464 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
465                           struct mlx5e_params *params,
466                           struct mlx5e_rq_param *rqp,
467                           struct mlx5e_rq *rq)
468 {
469         struct page_pool_params pp_params = { 0 };
470         struct mlx5_core_dev *mdev = c->mdev;
471         void *rqc = rqp->rqc;
472         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
473         u32 pool_size;
474         int wq_sz;
475         int err;
476         int i;
477
478         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
479
480         rq->wq_type = params->rq_wq_type;
481         rq->pdev    = c->pdev;
482         rq->netdev  = c->netdev;
483         rq->tstamp  = c->tstamp;
484         rq->clock   = &mdev->clock;
485         rq->channel = c;
486         rq->ix      = c->ix;
487         rq->mdev    = mdev;
488         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
489         rq->stats   = &c->priv->channel_stats[c->ix].rq;
490
491         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
492         if (IS_ERR(rq->xdp_prog)) {
493                 err = PTR_ERR(rq->xdp_prog);
494                 rq->xdp_prog = NULL;
495                 goto err_rq_wq_destroy;
496         }
497
498         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
499         if (err < 0)
500                 goto err_rq_wq_destroy;
501
502         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
503         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
504         pool_size = 1 << params->log_rq_mtu_frames;
505
506         switch (rq->wq_type) {
507         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
508                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
509                                         &rq->wq_ctrl);
510                 if (err)
511                         return err;
512
513                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
514
515                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
516
517                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
518
519                 rq->post_wqes = mlx5e_post_rx_mpwqes;
520                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
521
522                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
523 #ifdef CONFIG_MLX5_EN_IPSEC
524                 if (MLX5_IPSEC_DEV(mdev)) {
525                         err = -EINVAL;
526                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
527                         goto err_rq_wq_destroy;
528                 }
529 #endif
530                 if (!rq->handle_rx_cqe) {
531                         err = -EINVAL;
532                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
533                         goto err_rq_wq_destroy;
534                 }
535
536                 rq->mpwqe.skb_from_cqe_mpwrq =
537                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
538                         mlx5e_skb_from_cqe_mpwrq_linear :
539                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
540                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
541                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
542
543                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
544                 if (err)
545                         goto err_rq_wq_destroy;
546                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
547
548                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
549                 if (err)
550                         goto err_free;
551                 break;
552         default: /* MLX5_WQ_TYPE_CYCLIC */
553                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
554                                          &rq->wq_ctrl);
555                 if (err)
556                         return err;
557
558                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
559
560                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
561
562                 rq->wqe.info = rqp->frags_info;
563                 rq->wqe.frags =
564                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
565                                         (wq_sz << rq->wqe.info.log_num_frags)),
566                                       GFP_KERNEL, cpu_to_node(c->cpu));
567                 if (!rq->wqe.frags) {
568                         err = -ENOMEM;
569                         goto err_free;
570                 }
571
572                 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
573                 if (err)
574                         goto err_free;
575                 rq->post_wqes = mlx5e_post_rx_wqes;
576                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
577
578 #ifdef CONFIG_MLX5_EN_IPSEC
579                 if (c->priv->ipsec)
580                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
581                 else
582 #endif
583                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
584                 if (!rq->handle_rx_cqe) {
585                         err = -EINVAL;
586                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
587                         goto err_free;
588                 }
589
590                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
591                         mlx5e_skb_from_cqe_linear :
592                         mlx5e_skb_from_cqe_nonlinear;
593                 rq->mkey_be = c->mkey_be;
594         }
595
596         /* Create a page_pool and register it with rxq */
597         pp_params.order     = 0;
598         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
599         pp_params.pool_size = pool_size;
600         pp_params.nid       = cpu_to_node(c->cpu);
601         pp_params.dev       = c->pdev;
602         pp_params.dma_dir   = rq->buff.map_dir;
603
604         /* page_pool can be used even when there is no rq->xdp_prog,
605          * given page_pool does not handle DMA mapping there is no
606          * required state to clear. And page_pool gracefully handle
607          * elevated refcnt.
608          */
609         rq->page_pool = page_pool_create(&pp_params);
610         if (IS_ERR(rq->page_pool)) {
611                 err = PTR_ERR(rq->page_pool);
612                 rq->page_pool = NULL;
613                 goto err_free;
614         }
615         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
616                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
617         if (err)
618                 goto err_free;
619
620         for (i = 0; i < wq_sz; i++) {
621                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
622                         struct mlx5e_rx_wqe_ll *wqe =
623                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
624                         u32 byte_count =
625                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
626                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
627
628                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
629                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
630                         wqe->data[0].lkey = rq->mkey_be;
631                 } else {
632                         struct mlx5e_rx_wqe_cyc *wqe =
633                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
634                         int f;
635
636                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
637                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
638                                         MLX5_HW_START_PADDING;
639
640                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
641                                 wqe->data[f].lkey = rq->mkey_be;
642                         }
643                         /* check if num_frags is not a pow of two */
644                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
645                                 wqe->data[f].byte_count = 0;
646                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
647                                 wqe->data[f].addr = 0;
648                         }
649                 }
650         }
651
652         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
653
654         switch (params->rx_cq_moderation.cq_period_mode) {
655         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
656                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
657                 break;
658         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
659         default:
660                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
661         }
662
663         rq->page_cache.head = 0;
664         rq->page_cache.tail = 0;
665
666         return 0;
667
668 err_free:
669         switch (rq->wq_type) {
670         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
671                 kvfree(rq->mpwqe.info);
672                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
673                 break;
674         default: /* MLX5_WQ_TYPE_CYCLIC */
675                 kvfree(rq->wqe.frags);
676                 mlx5e_free_di_list(rq);
677         }
678
679 err_rq_wq_destroy:
680         if (rq->xdp_prog)
681                 bpf_prog_put(rq->xdp_prog);
682         xdp_rxq_info_unreg(&rq->xdp_rxq);
683         if (rq->page_pool)
684                 page_pool_destroy(rq->page_pool);
685         mlx5_wq_destroy(&rq->wq_ctrl);
686
687         return err;
688 }
689
690 static void mlx5e_free_rq(struct mlx5e_rq *rq)
691 {
692         int i;
693
694         if (rq->xdp_prog)
695                 bpf_prog_put(rq->xdp_prog);
696
697         xdp_rxq_info_unreg(&rq->xdp_rxq);
698         if (rq->page_pool)
699                 page_pool_destroy(rq->page_pool);
700
701         switch (rq->wq_type) {
702         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
703                 kvfree(rq->mpwqe.info);
704                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
705                 break;
706         default: /* MLX5_WQ_TYPE_CYCLIC */
707                 kvfree(rq->wqe.frags);
708                 mlx5e_free_di_list(rq);
709         }
710
711         for (i = rq->page_cache.head; i != rq->page_cache.tail;
712              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
713                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
714
715                 mlx5e_page_release(rq, dma_info, false);
716         }
717         mlx5_wq_destroy(&rq->wq_ctrl);
718 }
719
720 static int mlx5e_create_rq(struct mlx5e_rq *rq,
721                            struct mlx5e_rq_param *param)
722 {
723         struct mlx5_core_dev *mdev = rq->mdev;
724
725         void *in;
726         void *rqc;
727         void *wq;
728         int inlen;
729         int err;
730
731         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
732                 sizeof(u64) * rq->wq_ctrl.buf.npages;
733         in = kvzalloc(inlen, GFP_KERNEL);
734         if (!in)
735                 return -ENOMEM;
736
737         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
738         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
739
740         memcpy(rqc, param->rqc, sizeof(param->rqc));
741
742         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
743         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
744         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
745                                                 MLX5_ADAPTER_PAGE_SHIFT);
746         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
747
748         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
749                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
750
751         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
752
753         kvfree(in);
754
755         return err;
756 }
757
758 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
759                                  int next_state)
760 {
761         struct mlx5_core_dev *mdev = rq->mdev;
762
763         void *in;
764         void *rqc;
765         int inlen;
766         int err;
767
768         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
769         in = kvzalloc(inlen, GFP_KERNEL);
770         if (!in)
771                 return -ENOMEM;
772
773         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
774
775         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
776         MLX5_SET(rqc, rqc, state, next_state);
777
778         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
779
780         kvfree(in);
781
782         return err;
783 }
784
785 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
786 {
787         struct mlx5e_channel *c = rq->channel;
788         struct mlx5e_priv *priv = c->priv;
789         struct mlx5_core_dev *mdev = priv->mdev;
790
791         void *in;
792         void *rqc;
793         int inlen;
794         int err;
795
796         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
797         in = kvzalloc(inlen, GFP_KERNEL);
798         if (!in)
799                 return -ENOMEM;
800
801         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
802
803         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
804         MLX5_SET64(modify_rq_in, in, modify_bitmask,
805                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
806         MLX5_SET(rqc, rqc, scatter_fcs, enable);
807         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
808
809         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
810
811         kvfree(in);
812
813         return err;
814 }
815
816 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
817 {
818         struct mlx5e_channel *c = rq->channel;
819         struct mlx5_core_dev *mdev = c->mdev;
820         void *in;
821         void *rqc;
822         int inlen;
823         int err;
824
825         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
826         in = kvzalloc(inlen, GFP_KERNEL);
827         if (!in)
828                 return -ENOMEM;
829
830         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
831
832         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
833         MLX5_SET64(modify_rq_in, in, modify_bitmask,
834                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
835         MLX5_SET(rqc, rqc, vsd, vsd);
836         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
837
838         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
839
840         kvfree(in);
841
842         return err;
843 }
844
845 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
846 {
847         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
848 }
849
850 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
851 {
852         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
853         struct mlx5e_channel *c = rq->channel;
854
855         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
856
857         do {
858                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
859                         return 0;
860
861                 msleep(20);
862         } while (time_before(jiffies, exp_time));
863
864         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
865                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
866
867         return -ETIMEDOUT;
868 }
869
870 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
871 {
872         __be16 wqe_ix_be;
873         u16 wqe_ix;
874
875         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
876                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
877
878                 /* UMR WQE (if in progress) is always at wq->head */
879                 if (rq->mpwqe.umr_in_progress)
880                         mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
881
882                 while (!mlx5_wq_ll_is_empty(wq)) {
883                         struct mlx5e_rx_wqe_ll *wqe;
884
885                         wqe_ix_be = *wq->tail_next;
886                         wqe_ix    = be16_to_cpu(wqe_ix_be);
887                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
888                         rq->dealloc_wqe(rq, wqe_ix);
889                         mlx5_wq_ll_pop(wq, wqe_ix_be,
890                                        &wqe->next.next_wqe_index);
891                 }
892         } else {
893                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
894
895                 while (!mlx5_wq_cyc_is_empty(wq)) {
896                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
897                         rq->dealloc_wqe(rq, wqe_ix);
898                         mlx5_wq_cyc_pop(wq);
899                 }
900         }
901
902 }
903
904 static int mlx5e_open_rq(struct mlx5e_channel *c,
905                          struct mlx5e_params *params,
906                          struct mlx5e_rq_param *param,
907                          struct mlx5e_rq *rq)
908 {
909         int err;
910
911         err = mlx5e_alloc_rq(c, params, param, rq);
912         if (err)
913                 return err;
914
915         err = mlx5e_create_rq(rq, param);
916         if (err)
917                 goto err_free_rq;
918
919         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
920         if (err)
921                 goto err_destroy_rq;
922
923         if (params->rx_dim_enabled)
924                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
925
926         return 0;
927
928 err_destroy_rq:
929         mlx5e_destroy_rq(rq);
930 err_free_rq:
931         mlx5e_free_rq(rq);
932
933         return err;
934 }
935
936 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
937 {
938         struct mlx5e_icosq *sq = &rq->channel->icosq;
939         struct mlx5_wq_cyc *wq = &sq->wq;
940         struct mlx5e_tx_wqe *nopwqe;
941
942         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
943
944         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
945         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
946         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
947         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
948 }
949
950 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
951 {
952         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
953         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
954 }
955
956 static void mlx5e_close_rq(struct mlx5e_rq *rq)
957 {
958         cancel_work_sync(&rq->dim.work);
959         mlx5e_destroy_rq(rq);
960         mlx5e_free_rx_descs(rq);
961         mlx5e_free_rq(rq);
962 }
963
964 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
965 {
966         kvfree(sq->db.di);
967 }
968
969 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
970 {
971         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
972
973         sq->db.di = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.di)),
974                                   GFP_KERNEL, numa);
975         if (!sq->db.di) {
976                 mlx5e_free_xdpsq_db(sq);
977                 return -ENOMEM;
978         }
979
980         return 0;
981 }
982
983 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
984                              struct mlx5e_params *params,
985                              struct mlx5e_sq_param *param,
986                              struct mlx5e_xdpsq *sq)
987 {
988         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
989         struct mlx5_core_dev *mdev = c->mdev;
990         struct mlx5_wq_cyc *wq = &sq->wq;
991         int err;
992
993         sq->pdev      = c->pdev;
994         sq->mkey_be   = c->mkey_be;
995         sq->channel   = c;
996         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
997         sq->min_inline_mode = params->tx_min_inline_mode;
998
999         param->wq.db_numa_node = cpu_to_node(c->cpu);
1000         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1001         if (err)
1002                 return err;
1003         wq->db = &wq->db[MLX5_SND_DBR];
1004
1005         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1006         if (err)
1007                 goto err_sq_wq_destroy;
1008
1009         return 0;
1010
1011 err_sq_wq_destroy:
1012         mlx5_wq_destroy(&sq->wq_ctrl);
1013
1014         return err;
1015 }
1016
1017 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1018 {
1019         mlx5e_free_xdpsq_db(sq);
1020         mlx5_wq_destroy(&sq->wq_ctrl);
1021 }
1022
1023 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1024 {
1025         kvfree(sq->db.ico_wqe);
1026 }
1027
1028 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1029 {
1030         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1031
1032         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1033                                                   sizeof(*sq->db.ico_wqe)),
1034                                        GFP_KERNEL, numa);
1035         if (!sq->db.ico_wqe)
1036                 return -ENOMEM;
1037
1038         return 0;
1039 }
1040
1041 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1042                              struct mlx5e_sq_param *param,
1043                              struct mlx5e_icosq *sq)
1044 {
1045         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1046         struct mlx5_core_dev *mdev = c->mdev;
1047         struct mlx5_wq_cyc *wq = &sq->wq;
1048         int err;
1049
1050         sq->channel   = c;
1051         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1052
1053         param->wq.db_numa_node = cpu_to_node(c->cpu);
1054         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1055         if (err)
1056                 return err;
1057         wq->db = &wq->db[MLX5_SND_DBR];
1058
1059         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1060         if (err)
1061                 goto err_sq_wq_destroy;
1062
1063         return 0;
1064
1065 err_sq_wq_destroy:
1066         mlx5_wq_destroy(&sq->wq_ctrl);
1067
1068         return err;
1069 }
1070
1071 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1072 {
1073         mlx5e_free_icosq_db(sq);
1074         mlx5_wq_destroy(&sq->wq_ctrl);
1075 }
1076
1077 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1078 {
1079         kvfree(sq->db.wqe_info);
1080         kvfree(sq->db.dma_fifo);
1081 }
1082
1083 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1084 {
1085         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1086         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1087
1088         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1089                                                    sizeof(*sq->db.dma_fifo)),
1090                                         GFP_KERNEL, numa);
1091         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1092                                                    sizeof(*sq->db.wqe_info)),
1093                                         GFP_KERNEL, numa);
1094         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1095                 mlx5e_free_txqsq_db(sq);
1096                 return -ENOMEM;
1097         }
1098
1099         sq->dma_fifo_mask = df_sz - 1;
1100
1101         return 0;
1102 }
1103
1104 static void mlx5e_sq_recover(struct work_struct *work);
1105 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1106                              int txq_ix,
1107                              struct mlx5e_params *params,
1108                              struct mlx5e_sq_param *param,
1109                              struct mlx5e_txqsq *sq,
1110                              int tc)
1111 {
1112         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1113         struct mlx5_core_dev *mdev = c->mdev;
1114         struct mlx5_wq_cyc *wq = &sq->wq;
1115         int err;
1116
1117         sq->pdev      = c->pdev;
1118         sq->tstamp    = c->tstamp;
1119         sq->clock     = &mdev->clock;
1120         sq->mkey_be   = c->mkey_be;
1121         sq->channel   = c;
1122         sq->txq_ix    = txq_ix;
1123         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1124         sq->min_inline_mode = params->tx_min_inline_mode;
1125         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1126         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1127         if (MLX5_IPSEC_DEV(c->priv->mdev))
1128                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1129         if (mlx5_accel_is_tls_device(c->priv->mdev))
1130                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1131
1132         param->wq.db_numa_node = cpu_to_node(c->cpu);
1133         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1134         if (err)
1135                 return err;
1136         wq->db    = &wq->db[MLX5_SND_DBR];
1137
1138         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1139         if (err)
1140                 goto err_sq_wq_destroy;
1141
1142         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1143         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1144
1145         return 0;
1146
1147 err_sq_wq_destroy:
1148         mlx5_wq_destroy(&sq->wq_ctrl);
1149
1150         return err;
1151 }
1152
1153 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1154 {
1155         mlx5e_free_txqsq_db(sq);
1156         mlx5_wq_destroy(&sq->wq_ctrl);
1157 }
1158
1159 struct mlx5e_create_sq_param {
1160         struct mlx5_wq_ctrl        *wq_ctrl;
1161         u32                         cqn;
1162         u32                         tisn;
1163         u8                          tis_lst_sz;
1164         u8                          min_inline_mode;
1165 };
1166
1167 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1168                            struct mlx5e_sq_param *param,
1169                            struct mlx5e_create_sq_param *csp,
1170                            u32 *sqn)
1171 {
1172         void *in;
1173         void *sqc;
1174         void *wq;
1175         int inlen;
1176         int err;
1177
1178         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1179                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1180         in = kvzalloc(inlen, GFP_KERNEL);
1181         if (!in)
1182                 return -ENOMEM;
1183
1184         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1185         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1186
1187         memcpy(sqc, param->sqc, sizeof(param->sqc));
1188         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1189         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1190         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1191
1192         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1193                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1194
1195         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1196         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1197
1198         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1199         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1200         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1201                                           MLX5_ADAPTER_PAGE_SHIFT);
1202         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1203
1204         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1205                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1206
1207         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1208
1209         kvfree(in);
1210
1211         return err;
1212 }
1213
1214 struct mlx5e_modify_sq_param {
1215         int curr_state;
1216         int next_state;
1217         bool rl_update;
1218         int rl_index;
1219 };
1220
1221 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1222                            struct mlx5e_modify_sq_param *p)
1223 {
1224         void *in;
1225         void *sqc;
1226         int inlen;
1227         int err;
1228
1229         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1230         in = kvzalloc(inlen, GFP_KERNEL);
1231         if (!in)
1232                 return -ENOMEM;
1233
1234         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1235
1236         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1237         MLX5_SET(sqc, sqc, state, p->next_state);
1238         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1239                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1240                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1241         }
1242
1243         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1244
1245         kvfree(in);
1246
1247         return err;
1248 }
1249
1250 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1251 {
1252         mlx5_core_destroy_sq(mdev, sqn);
1253 }
1254
1255 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1256                                struct mlx5e_sq_param *param,
1257                                struct mlx5e_create_sq_param *csp,
1258                                u32 *sqn)
1259 {
1260         struct mlx5e_modify_sq_param msp = {0};
1261         int err;
1262
1263         err = mlx5e_create_sq(mdev, param, csp, sqn);
1264         if (err)
1265                 return err;
1266
1267         msp.curr_state = MLX5_SQC_STATE_RST;
1268         msp.next_state = MLX5_SQC_STATE_RDY;
1269         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1270         if (err)
1271                 mlx5e_destroy_sq(mdev, *sqn);
1272
1273         return err;
1274 }
1275
1276 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1277                                 struct mlx5e_txqsq *sq, u32 rate);
1278
1279 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1280                             u32 tisn,
1281                             int txq_ix,
1282                             struct mlx5e_params *params,
1283                             struct mlx5e_sq_param *param,
1284                             struct mlx5e_txqsq *sq,
1285                             int tc)
1286 {
1287         struct mlx5e_create_sq_param csp = {};
1288         u32 tx_rate;
1289         int err;
1290
1291         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1292         if (err)
1293                 return err;
1294
1295         csp.tisn            = tisn;
1296         csp.tis_lst_sz      = 1;
1297         csp.cqn             = sq->cq.mcq.cqn;
1298         csp.wq_ctrl         = &sq->wq_ctrl;
1299         csp.min_inline_mode = sq->min_inline_mode;
1300         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1301         if (err)
1302                 goto err_free_txqsq;
1303
1304         tx_rate = c->priv->tx_rates[sq->txq_ix];
1305         if (tx_rate)
1306                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1307
1308         if (params->tx_dim_enabled)
1309                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1310
1311         return 0;
1312
1313 err_free_txqsq:
1314         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1315         mlx5e_free_txqsq(sq);
1316
1317         return err;
1318 }
1319
1320 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1321 {
1322         WARN_ONCE(sq->cc != sq->pc,
1323                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1324                   sq->sqn, sq->cc, sq->pc);
1325         sq->cc = 0;
1326         sq->dma_fifo_cc = 0;
1327         sq->pc = 0;
1328 }
1329
1330 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1331 {
1332         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1333         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1334         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1335         netdev_tx_reset_queue(sq->txq);
1336         netif_tx_start_queue(sq->txq);
1337 }
1338
1339 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1340 {
1341         __netif_tx_lock_bh(txq);
1342         netif_tx_stop_queue(txq);
1343         __netif_tx_unlock_bh(txq);
1344 }
1345
1346 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1347 {
1348         struct mlx5e_channel *c = sq->channel;
1349         struct mlx5_wq_cyc *wq = &sq->wq;
1350
1351         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1352         /* prevent netif_tx_wake_queue */
1353         napi_synchronize(&c->napi);
1354
1355         netif_tx_disable_queue(sq->txq);
1356
1357         /* last doorbell out, godspeed .. */
1358         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1359                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1360                 struct mlx5e_tx_wqe *nop;
1361
1362                 sq->db.wqe_info[pi].skb = NULL;
1363                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1364                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1365         }
1366 }
1367
1368 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1369 {
1370         struct mlx5e_channel *c = sq->channel;
1371         struct mlx5_core_dev *mdev = c->mdev;
1372         struct mlx5_rate_limit rl = {0};
1373
1374         mlx5e_destroy_sq(mdev, sq->sqn);
1375         if (sq->rate_limit) {
1376                 rl.rate = sq->rate_limit;
1377                 mlx5_rl_remove_rate(mdev, &rl);
1378         }
1379         mlx5e_free_txqsq_descs(sq);
1380         mlx5e_free_txqsq(sq);
1381 }
1382
1383 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1384 {
1385         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1386
1387         while (time_before(jiffies, exp_time)) {
1388                 if (sq->cc == sq->pc)
1389                         return 0;
1390
1391                 msleep(20);
1392         }
1393
1394         netdev_err(sq->channel->netdev,
1395                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1396                    sq->sqn, sq->cc, sq->pc);
1397
1398         return -ETIMEDOUT;
1399 }
1400
1401 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1402 {
1403         struct mlx5_core_dev *mdev = sq->channel->mdev;
1404         struct net_device *dev = sq->channel->netdev;
1405         struct mlx5e_modify_sq_param msp = {0};
1406         int err;
1407
1408         msp.curr_state = curr_state;
1409         msp.next_state = MLX5_SQC_STATE_RST;
1410
1411         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1412         if (err) {
1413                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1414                 return err;
1415         }
1416
1417         memset(&msp, 0, sizeof(msp));
1418         msp.curr_state = MLX5_SQC_STATE_RST;
1419         msp.next_state = MLX5_SQC_STATE_RDY;
1420
1421         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1422         if (err) {
1423                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1424                 return err;
1425         }
1426
1427         return 0;
1428 }
1429
1430 static void mlx5e_sq_recover(struct work_struct *work)
1431 {
1432         struct mlx5e_txqsq_recover *recover =
1433                 container_of(work, struct mlx5e_txqsq_recover,
1434                              recover_work);
1435         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1436                                               recover);
1437         struct mlx5_core_dev *mdev = sq->channel->mdev;
1438         struct net_device *dev = sq->channel->netdev;
1439         u8 state;
1440         int err;
1441
1442         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1443         if (err) {
1444                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1445                            sq->sqn, err);
1446                 return;
1447         }
1448
1449         if (state != MLX5_RQC_STATE_ERR) {
1450                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1451                 return;
1452         }
1453
1454         netif_tx_disable_queue(sq->txq);
1455
1456         if (mlx5e_wait_for_sq_flush(sq))
1457                 return;
1458
1459         /* If the interval between two consecutive recovers per SQ is too
1460          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1461          * If we reached this state, there is probably a bug that needs to be
1462          * fixed. let's keep the queue close and let tx timeout cleanup.
1463          */
1464         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1465             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1466                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1467                            sq->sqn);
1468                 return;
1469         }
1470
1471         /* At this point, no new packets will arrive from the stack as TXQ is
1472          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1473          * pending WQEs.  SQ can safely reset the SQ.
1474          */
1475         if (mlx5e_sq_to_ready(sq, state))
1476                 return;
1477
1478         mlx5e_reset_txqsq_cc_pc(sq);
1479         sq->stats->recover++;
1480         recover->last_recover = jiffies;
1481         mlx5e_activate_txqsq(sq);
1482 }
1483
1484 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1485                             struct mlx5e_params *params,
1486                             struct mlx5e_sq_param *param,
1487                             struct mlx5e_icosq *sq)
1488 {
1489         struct mlx5e_create_sq_param csp = {};
1490         int err;
1491
1492         err = mlx5e_alloc_icosq(c, param, sq);
1493         if (err)
1494                 return err;
1495
1496         csp.cqn             = sq->cq.mcq.cqn;
1497         csp.wq_ctrl         = &sq->wq_ctrl;
1498         csp.min_inline_mode = params->tx_min_inline_mode;
1499         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1500         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1501         if (err)
1502                 goto err_free_icosq;
1503
1504         return 0;
1505
1506 err_free_icosq:
1507         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1508         mlx5e_free_icosq(sq);
1509
1510         return err;
1511 }
1512
1513 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1514 {
1515         struct mlx5e_channel *c = sq->channel;
1516
1517         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1518         napi_synchronize(&c->napi);
1519
1520         mlx5e_destroy_sq(c->mdev, sq->sqn);
1521         mlx5e_free_icosq(sq);
1522 }
1523
1524 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1525                             struct mlx5e_params *params,
1526                             struct mlx5e_sq_param *param,
1527                             struct mlx5e_xdpsq *sq)
1528 {
1529         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1530         struct mlx5e_create_sq_param csp = {};
1531         unsigned int inline_hdr_sz = 0;
1532         int err;
1533         int i;
1534
1535         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1536         if (err)
1537                 return err;
1538
1539         csp.tis_lst_sz      = 1;
1540         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1541         csp.cqn             = sq->cq.mcq.cqn;
1542         csp.wq_ctrl         = &sq->wq_ctrl;
1543         csp.min_inline_mode = sq->min_inline_mode;
1544         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1545         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1546         if (err)
1547                 goto err_free_xdpsq;
1548
1549         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1550                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1551                 ds_cnt++;
1552         }
1553
1554         /* Pre initialize fixed WQE fields */
1555         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1556                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1557                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1558                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1559                 struct mlx5_wqe_data_seg *dseg;
1560
1561                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1562                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1563
1564                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1565                 dseg->lkey = sq->mkey_be;
1566         }
1567
1568         return 0;
1569
1570 err_free_xdpsq:
1571         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1572         mlx5e_free_xdpsq(sq);
1573
1574         return err;
1575 }
1576
1577 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1578 {
1579         struct mlx5e_channel *c = sq->channel;
1580
1581         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1582         napi_synchronize(&c->napi);
1583
1584         mlx5e_destroy_sq(c->mdev, sq->sqn);
1585         mlx5e_free_xdpsq_descs(sq);
1586         mlx5e_free_xdpsq(sq);
1587 }
1588
1589 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1590                                  struct mlx5e_cq_param *param,
1591                                  struct mlx5e_cq *cq)
1592 {
1593         struct mlx5_core_cq *mcq = &cq->mcq;
1594         int eqn_not_used;
1595         unsigned int irqn;
1596         int err;
1597         u32 i;
1598
1599         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1600                                &cq->wq_ctrl);
1601         if (err)
1602                 return err;
1603
1604         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1605
1606         mcq->cqe_sz     = 64;
1607         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1608         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1609         *mcq->set_ci_db = 0;
1610         *mcq->arm_db    = 0;
1611         mcq->vector     = param->eq_ix;
1612         mcq->comp       = mlx5e_completion_event;
1613         mcq->event      = mlx5e_cq_error_event;
1614         mcq->irqn       = irqn;
1615
1616         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1617                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1618
1619                 cqe->op_own = 0xf1;
1620         }
1621
1622         cq->mdev = mdev;
1623
1624         return 0;
1625 }
1626
1627 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1628                           struct mlx5e_cq_param *param,
1629                           struct mlx5e_cq *cq)
1630 {
1631         struct mlx5_core_dev *mdev = c->priv->mdev;
1632         int err;
1633
1634         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1635         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1636         param->eq_ix   = c->ix;
1637
1638         err = mlx5e_alloc_cq_common(mdev, param, cq);
1639
1640         cq->napi    = &c->napi;
1641         cq->channel = c;
1642
1643         return err;
1644 }
1645
1646 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1647 {
1648         mlx5_wq_destroy(&cq->wq_ctrl);
1649 }
1650
1651 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1652 {
1653         struct mlx5_core_dev *mdev = cq->mdev;
1654         struct mlx5_core_cq *mcq = &cq->mcq;
1655
1656         void *in;
1657         void *cqc;
1658         int inlen;
1659         unsigned int irqn_not_used;
1660         int eqn;
1661         int err;
1662
1663         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1664                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1665         in = kvzalloc(inlen, GFP_KERNEL);
1666         if (!in)
1667                 return -ENOMEM;
1668
1669         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1670
1671         memcpy(cqc, param->cqc, sizeof(param->cqc));
1672
1673         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1674                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1675
1676         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1677
1678         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1679         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1680         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1681         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1682                                             MLX5_ADAPTER_PAGE_SHIFT);
1683         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1684
1685         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1686
1687         kvfree(in);
1688
1689         if (err)
1690                 return err;
1691
1692         mlx5e_cq_arm(cq);
1693
1694         return 0;
1695 }
1696
1697 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1698 {
1699         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1700 }
1701
1702 static int mlx5e_open_cq(struct mlx5e_channel *c,
1703                          struct net_dim_cq_moder moder,
1704                          struct mlx5e_cq_param *param,
1705                          struct mlx5e_cq *cq)
1706 {
1707         struct mlx5_core_dev *mdev = c->mdev;
1708         int err;
1709
1710         err = mlx5e_alloc_cq(c, param, cq);
1711         if (err)
1712                 return err;
1713
1714         err = mlx5e_create_cq(cq, param);
1715         if (err)
1716                 goto err_free_cq;
1717
1718         if (MLX5_CAP_GEN(mdev, cq_moderation))
1719                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1720         return 0;
1721
1722 err_free_cq:
1723         mlx5e_free_cq(cq);
1724
1725         return err;
1726 }
1727
1728 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1729 {
1730         mlx5e_destroy_cq(cq);
1731         mlx5e_free_cq(cq);
1732 }
1733
1734 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1735 {
1736         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1737 }
1738
1739 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1740                              struct mlx5e_params *params,
1741                              struct mlx5e_channel_param *cparam)
1742 {
1743         int err;
1744         int tc;
1745
1746         for (tc = 0; tc < c->num_tc; tc++) {
1747                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1748                                     &cparam->tx_cq, &c->sq[tc].cq);
1749                 if (err)
1750                         goto err_close_tx_cqs;
1751         }
1752
1753         return 0;
1754
1755 err_close_tx_cqs:
1756         for (tc--; tc >= 0; tc--)
1757                 mlx5e_close_cq(&c->sq[tc].cq);
1758
1759         return err;
1760 }
1761
1762 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1763 {
1764         int tc;
1765
1766         for (tc = 0; tc < c->num_tc; tc++)
1767                 mlx5e_close_cq(&c->sq[tc].cq);
1768 }
1769
1770 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1771                           struct mlx5e_params *params,
1772                           struct mlx5e_channel_param *cparam)
1773 {
1774         struct mlx5e_priv *priv = c->priv;
1775         int err, tc, max_nch = priv->profile->max_nch(priv->mdev);
1776
1777         for (tc = 0; tc < params->num_tc; tc++) {
1778                 int txq_ix = c->ix + tc * max_nch;
1779
1780                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1781                                        params, &cparam->sq, &c->sq[tc], tc);
1782                 if (err)
1783                         goto err_close_sqs;
1784         }
1785
1786         return 0;
1787
1788 err_close_sqs:
1789         for (tc--; tc >= 0; tc--)
1790                 mlx5e_close_txqsq(&c->sq[tc]);
1791
1792         return err;
1793 }
1794
1795 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1796 {
1797         int tc;
1798
1799         for (tc = 0; tc < c->num_tc; tc++)
1800                 mlx5e_close_txqsq(&c->sq[tc]);
1801 }
1802
1803 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1804                                 struct mlx5e_txqsq *sq, u32 rate)
1805 {
1806         struct mlx5e_priv *priv = netdev_priv(dev);
1807         struct mlx5_core_dev *mdev = priv->mdev;
1808         struct mlx5e_modify_sq_param msp = {0};
1809         struct mlx5_rate_limit rl = {0};
1810         u16 rl_index = 0;
1811         int err;
1812
1813         if (rate == sq->rate_limit)
1814                 /* nothing to do */
1815                 return 0;
1816
1817         if (sq->rate_limit) {
1818                 rl.rate = sq->rate_limit;
1819                 /* remove current rl index to free space to next ones */
1820                 mlx5_rl_remove_rate(mdev, &rl);
1821         }
1822
1823         sq->rate_limit = 0;
1824
1825         if (rate) {
1826                 rl.rate = rate;
1827                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1828                 if (err) {
1829                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1830                                    rate, err);
1831                         return err;
1832                 }
1833         }
1834
1835         msp.curr_state = MLX5_SQC_STATE_RDY;
1836         msp.next_state = MLX5_SQC_STATE_RDY;
1837         msp.rl_index   = rl_index;
1838         msp.rl_update  = true;
1839         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1840         if (err) {
1841                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1842                            rate, err);
1843                 /* remove the rate from the table */
1844                 if (rate)
1845                         mlx5_rl_remove_rate(mdev, &rl);
1846                 return err;
1847         }
1848
1849         sq->rate_limit = rate;
1850         return 0;
1851 }
1852
1853 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1854 {
1855         struct mlx5e_priv *priv = netdev_priv(dev);
1856         struct mlx5_core_dev *mdev = priv->mdev;
1857         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1858         int err = 0;
1859
1860         if (!mlx5_rl_is_supported(mdev)) {
1861                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1862                 return -EINVAL;
1863         }
1864
1865         /* rate is given in Mb/sec, HW config is in Kb/sec */
1866         rate = rate << 10;
1867
1868         /* Check whether rate in valid range, 0 is always valid */
1869         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1870                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1871                 return -ERANGE;
1872         }
1873
1874         mutex_lock(&priv->state_lock);
1875         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1876                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1877         if (!err)
1878                 priv->tx_rates[index] = rate;
1879         mutex_unlock(&priv->state_lock);
1880
1881         return err;
1882 }
1883
1884 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1885                               struct mlx5e_params *params,
1886                               struct mlx5e_channel_param *cparam,
1887                               struct mlx5e_channel **cp)
1888 {
1889         struct net_dim_cq_moder icocq_moder = {0, 0};
1890         struct net_device *netdev = priv->netdev;
1891         int cpu = mlx5e_get_cpu(priv, ix);
1892         struct mlx5e_channel *c;
1893         unsigned int irq;
1894         int err;
1895         int eqn;
1896
1897         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1898         if (!c)
1899                 return -ENOMEM;
1900
1901         c->priv     = priv;
1902         c->mdev     = priv->mdev;
1903         c->tstamp   = &priv->tstamp;
1904         c->ix       = ix;
1905         c->cpu      = cpu;
1906         c->pdev     = &priv->mdev->pdev->dev;
1907         c->netdev   = priv->netdev;
1908         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1909         c->num_tc   = params->num_tc;
1910         c->xdp      = !!params->xdp_prog;
1911         c->stats    = &priv->channel_stats[ix].ch;
1912
1913         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1914         c->irq_desc = irq_to_desc(irq);
1915
1916         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1917
1918         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1919         if (err)
1920                 goto err_napi_del;
1921
1922         err = mlx5e_open_tx_cqs(c, params, cparam);
1923         if (err)
1924                 goto err_close_icosq_cq;
1925
1926         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1927         if (err)
1928                 goto err_close_tx_cqs;
1929
1930         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1931         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1932                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1933         if (err)
1934                 goto err_close_rx_cq;
1935
1936         napi_enable(&c->napi);
1937
1938         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1939         if (err)
1940                 goto err_disable_napi;
1941
1942         err = mlx5e_open_sqs(c, params, cparam);
1943         if (err)
1944                 goto err_close_icosq;
1945
1946         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1947         if (err)
1948                 goto err_close_sqs;
1949
1950         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1951         if (err)
1952                 goto err_close_xdp_sq;
1953
1954         *cp = c;
1955
1956         return 0;
1957 err_close_xdp_sq:
1958         if (c->xdp)
1959                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1960
1961 err_close_sqs:
1962         mlx5e_close_sqs(c);
1963
1964 err_close_icosq:
1965         mlx5e_close_icosq(&c->icosq);
1966
1967 err_disable_napi:
1968         napi_disable(&c->napi);
1969         if (c->xdp)
1970                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1971
1972 err_close_rx_cq:
1973         mlx5e_close_cq(&c->rq.cq);
1974
1975 err_close_tx_cqs:
1976         mlx5e_close_tx_cqs(c);
1977
1978 err_close_icosq_cq:
1979         mlx5e_close_cq(&c->icosq.cq);
1980
1981 err_napi_del:
1982         netif_napi_del(&c->napi);
1983         kvfree(c);
1984
1985         return err;
1986 }
1987
1988 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1989 {
1990         int tc;
1991
1992         for (tc = 0; tc < c->num_tc; tc++)
1993                 mlx5e_activate_txqsq(&c->sq[tc]);
1994         mlx5e_activate_rq(&c->rq);
1995         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1996 }
1997
1998 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1999 {
2000         int tc;
2001
2002         mlx5e_deactivate_rq(&c->rq);
2003         for (tc = 0; tc < c->num_tc; tc++)
2004                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2005 }
2006
2007 static void mlx5e_close_channel(struct mlx5e_channel *c)
2008 {
2009         mlx5e_close_rq(&c->rq);
2010         if (c->xdp)
2011                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2012         mlx5e_close_sqs(c);
2013         mlx5e_close_icosq(&c->icosq);
2014         napi_disable(&c->napi);
2015         if (c->xdp)
2016                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2017         mlx5e_close_cq(&c->rq.cq);
2018         mlx5e_close_tx_cqs(c);
2019         mlx5e_close_cq(&c->icosq.cq);
2020         netif_napi_del(&c->napi);
2021
2022         kvfree(c);
2023 }
2024
2025 #define DEFAULT_FRAG_SIZE (2048)
2026
2027 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2028                                       struct mlx5e_params *params,
2029                                       struct mlx5e_rq_frags_info *info)
2030 {
2031         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2032         int frag_size_max = DEFAULT_FRAG_SIZE;
2033         u32 buf_size = 0;
2034         int i;
2035
2036 #ifdef CONFIG_MLX5_EN_IPSEC
2037         if (MLX5_IPSEC_DEV(mdev))
2038                 byte_count += MLX5E_METADATA_ETHER_LEN;
2039 #endif
2040
2041         if (mlx5e_rx_is_linear_skb(mdev, params)) {
2042                 int frag_stride;
2043
2044                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2045                 frag_stride = roundup_pow_of_two(frag_stride);
2046
2047                 info->arr[0].frag_size = byte_count;
2048                 info->arr[0].frag_stride = frag_stride;
2049                 info->num_frags = 1;
2050                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2051                 goto out;
2052         }
2053
2054         if (byte_count > PAGE_SIZE +
2055             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2056                 frag_size_max = PAGE_SIZE;
2057
2058         i = 0;
2059         while (buf_size < byte_count) {
2060                 int frag_size = byte_count - buf_size;
2061
2062                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2063                         frag_size = min(frag_size, frag_size_max);
2064
2065                 info->arr[i].frag_size = frag_size;
2066                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2067
2068                 buf_size += frag_size;
2069                 i++;
2070         }
2071         info->num_frags = i;
2072         /* number of different wqes sharing a page */
2073         info->wqe_bulk = 1 + (info->num_frags % 2);
2074
2075 out:
2076         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2077         info->log_num_frags = order_base_2(info->num_frags);
2078 }
2079
2080 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2081 {
2082         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2083
2084         switch (wq_type) {
2085         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2086                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2087                 break;
2088         default: /* MLX5_WQ_TYPE_CYCLIC */
2089                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2090         }
2091
2092         return order_base_2(sz);
2093 }
2094
2095 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2096                                  struct mlx5e_params *params,
2097                                  struct mlx5e_rq_param *param)
2098 {
2099         struct mlx5_core_dev *mdev = priv->mdev;
2100         void *rqc = param->rqc;
2101         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2102         int ndsegs = 1;
2103
2104         switch (params->rq_wq_type) {
2105         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2106                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2107                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2108                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2109                 MLX5_SET(wq, wq, log_wqe_stride_size,
2110                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2111                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2112                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2113                 break;
2114         default: /* MLX5_WQ_TYPE_CYCLIC */
2115                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2116                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2117                 ndsegs = param->frags_info.num_frags;
2118         }
2119
2120         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2121         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2122         MLX5_SET(wq, wq, log_wq_stride,
2123                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2124         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2125         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2126         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2127         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2128
2129         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2130 }
2131
2132 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2133                                       struct mlx5e_rq_param *param)
2134 {
2135         struct mlx5_core_dev *mdev = priv->mdev;
2136         void *rqc = param->rqc;
2137         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2138
2139         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2140         MLX5_SET(wq, wq, log_wq_stride,
2141                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2142         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2143
2144         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2145 }
2146
2147 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2148                                         struct mlx5e_sq_param *param)
2149 {
2150         void *sqc = param->sqc;
2151         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2152
2153         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2154         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2155
2156         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2157 }
2158
2159 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2160                                  struct mlx5e_params *params,
2161                                  struct mlx5e_sq_param *param)
2162 {
2163         void *sqc = param->sqc;
2164         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2165
2166         mlx5e_build_sq_param_common(priv, param);
2167         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2168         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2169 }
2170
2171 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2172                                         struct mlx5e_cq_param *param)
2173 {
2174         void *cqc = param->cqc;
2175
2176         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2177 }
2178
2179 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2180                                     struct mlx5e_params *params,
2181                                     struct mlx5e_cq_param *param)
2182 {
2183         struct mlx5_core_dev *mdev = priv->mdev;
2184         void *cqc = param->cqc;
2185         u8 log_cq_size;
2186
2187         switch (params->rq_wq_type) {
2188         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2189                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2190                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2191                 break;
2192         default: /* MLX5_WQ_TYPE_CYCLIC */
2193                 log_cq_size = params->log_rq_mtu_frames;
2194         }
2195
2196         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2197         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2198                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2199                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2200         }
2201
2202         mlx5e_build_common_cq_param(priv, param);
2203         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2204 }
2205
2206 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2207                                     struct mlx5e_params *params,
2208                                     struct mlx5e_cq_param *param)
2209 {
2210         void *cqc = param->cqc;
2211
2212         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2213
2214         mlx5e_build_common_cq_param(priv, param);
2215         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2216 }
2217
2218 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2219                                      u8 log_wq_size,
2220                                      struct mlx5e_cq_param *param)
2221 {
2222         void *cqc = param->cqc;
2223
2224         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2225
2226         mlx5e_build_common_cq_param(priv, param);
2227
2228         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2229 }
2230
2231 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2232                                     u8 log_wq_size,
2233                                     struct mlx5e_sq_param *param)
2234 {
2235         void *sqc = param->sqc;
2236         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2237
2238         mlx5e_build_sq_param_common(priv, param);
2239
2240         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2241         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2242 }
2243
2244 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2245                                     struct mlx5e_params *params,
2246                                     struct mlx5e_sq_param *param)
2247 {
2248         void *sqc = param->sqc;
2249         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2250
2251         mlx5e_build_sq_param_common(priv, param);
2252         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2253 }
2254
2255 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2256                                       struct mlx5e_params *params,
2257                                       struct mlx5e_channel_param *cparam)
2258 {
2259         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2260
2261         mlx5e_build_rq_param(priv, params, &cparam->rq);
2262         mlx5e_build_sq_param(priv, params, &cparam->sq);
2263         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2264         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2265         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2266         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2267         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2268 }
2269
2270 int mlx5e_open_channels(struct mlx5e_priv *priv,
2271                         struct mlx5e_channels *chs)
2272 {
2273         struct mlx5e_channel_param *cparam;
2274         int err = -ENOMEM;
2275         int i;
2276
2277         chs->num = chs->params.num_channels;
2278
2279         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2280         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2281         if (!chs->c || !cparam)
2282                 goto err_free;
2283
2284         mlx5e_build_channel_param(priv, &chs->params, cparam);
2285         for (i = 0; i < chs->num; i++) {
2286                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2287                 if (err)
2288                         goto err_close_channels;
2289         }
2290
2291         kvfree(cparam);
2292         return 0;
2293
2294 err_close_channels:
2295         for (i--; i >= 0; i--)
2296                 mlx5e_close_channel(chs->c[i]);
2297
2298 err_free:
2299         kfree(chs->c);
2300         kvfree(cparam);
2301         chs->num = 0;
2302         return err;
2303 }
2304
2305 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2306 {
2307         int i;
2308
2309         for (i = 0; i < chs->num; i++)
2310                 mlx5e_activate_channel(chs->c[i]);
2311 }
2312
2313 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2314 {
2315         int err = 0;
2316         int i;
2317
2318         for (i = 0; i < chs->num; i++)
2319                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2320                                                   err ? 0 : 20000);
2321
2322         return err ? -ETIMEDOUT : 0;
2323 }
2324
2325 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2326 {
2327         int i;
2328
2329         for (i = 0; i < chs->num; i++)
2330                 mlx5e_deactivate_channel(chs->c[i]);
2331 }
2332
2333 void mlx5e_close_channels(struct mlx5e_channels *chs)
2334 {
2335         int i;
2336
2337         for (i = 0; i < chs->num; i++)
2338                 mlx5e_close_channel(chs->c[i]);
2339
2340         kfree(chs->c);
2341         chs->num = 0;
2342 }
2343
2344 static int
2345 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2346 {
2347         struct mlx5_core_dev *mdev = priv->mdev;
2348         void *rqtc;
2349         int inlen;
2350         int err;
2351         u32 *in;
2352         int i;
2353
2354         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2355         in = kvzalloc(inlen, GFP_KERNEL);
2356         if (!in)
2357                 return -ENOMEM;
2358
2359         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2360
2361         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2362         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2363
2364         for (i = 0; i < sz; i++)
2365                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2366
2367         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2368         if (!err)
2369                 rqt->enabled = true;
2370
2371         kvfree(in);
2372         return err;
2373 }
2374
2375 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2376 {
2377         rqt->enabled = false;
2378         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2379 }
2380
2381 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2382 {
2383         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2384         int err;
2385
2386         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2387         if (err)
2388                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2389         return err;
2390 }
2391
2392 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2393 {
2394         struct mlx5e_rqt *rqt;
2395         int err;
2396         int ix;
2397
2398         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2399                 rqt = &priv->direct_tir[ix].rqt;
2400                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2401                 if (err)
2402                         goto err_destroy_rqts;
2403         }
2404
2405         return 0;
2406
2407 err_destroy_rqts:
2408         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2409         for (ix--; ix >= 0; ix--)
2410                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2411
2412         return err;
2413 }
2414
2415 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2416 {
2417         int i;
2418
2419         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2420                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2421 }
2422
2423 static int mlx5e_rx_hash_fn(int hfunc)
2424 {
2425         return (hfunc == ETH_RSS_HASH_TOP) ?
2426                MLX5_RX_HASH_FN_TOEPLITZ :
2427                MLX5_RX_HASH_FN_INVERTED_XOR8;
2428 }
2429
2430 int mlx5e_bits_invert(unsigned long a, int size)
2431 {
2432         int inv = 0;
2433         int i;
2434
2435         for (i = 0; i < size; i++)
2436                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2437
2438         return inv;
2439 }
2440
2441 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2442                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2443 {
2444         int i;
2445
2446         for (i = 0; i < sz; i++) {
2447                 u32 rqn;
2448
2449                 if (rrp.is_rss) {
2450                         int ix = i;
2451
2452                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2453                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2454
2455                         ix = priv->channels.params.indirection_rqt[ix];
2456                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2457                 } else {
2458                         rqn = rrp.rqn;
2459                 }
2460                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2461         }
2462 }
2463
2464 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2465                        struct mlx5e_redirect_rqt_param rrp)
2466 {
2467         struct mlx5_core_dev *mdev = priv->mdev;
2468         void *rqtc;
2469         int inlen;
2470         u32 *in;
2471         int err;
2472
2473         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2474         in = kvzalloc(inlen, GFP_KERNEL);
2475         if (!in)
2476                 return -ENOMEM;
2477
2478         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2479
2480         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2481         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2482         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2483         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2484
2485         kvfree(in);
2486         return err;
2487 }
2488
2489 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2490                                 struct mlx5e_redirect_rqt_param rrp)
2491 {
2492         if (!rrp.is_rss)
2493                 return rrp.rqn;
2494
2495         if (ix >= rrp.rss.channels->num)
2496                 return priv->drop_rq.rqn;
2497
2498         return rrp.rss.channels->c[ix]->rq.rqn;
2499 }
2500
2501 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2502                                 struct mlx5e_redirect_rqt_param rrp)
2503 {
2504         u32 rqtn;
2505         int ix;
2506
2507         if (priv->indir_rqt.enabled) {
2508                 /* RSS RQ table */
2509                 rqtn = priv->indir_rqt.rqtn;
2510                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2511         }
2512
2513         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2514                 struct mlx5e_redirect_rqt_param direct_rrp = {
2515                         .is_rss = false,
2516                         {
2517                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2518                         },
2519                 };
2520
2521                 /* Direct RQ Tables */
2522                 if (!priv->direct_tir[ix].rqt.enabled)
2523                         continue;
2524
2525                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2526                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2527         }
2528 }
2529
2530 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2531                                             struct mlx5e_channels *chs)
2532 {
2533         struct mlx5e_redirect_rqt_param rrp = {
2534                 .is_rss        = true,
2535                 {
2536                         .rss = {
2537                                 .channels  = chs,
2538                                 .hfunc     = chs->params.rss_hfunc,
2539                         }
2540                 },
2541         };
2542
2543         mlx5e_redirect_rqts(priv, rrp);
2544 }
2545
2546 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2547 {
2548         struct mlx5e_redirect_rqt_param drop_rrp = {
2549                 .is_rss = false,
2550                 {
2551                         .rqn = priv->drop_rq.rqn,
2552                 },
2553         };
2554
2555         mlx5e_redirect_rqts(priv, drop_rrp);
2556 }
2557
2558 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2559 {
2560         if (!params->lro_en)
2561                 return;
2562
2563 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2564
2565         MLX5_SET(tirc, tirc, lro_enable_mask,
2566                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2567                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2568         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2569                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2570         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2571 }
2572
2573 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2574                                     enum mlx5e_traffic_types tt,
2575                                     void *tirc, bool inner)
2576 {
2577         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2578                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2579
2580 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2581                                  MLX5_HASH_FIELD_SEL_DST_IP)
2582
2583 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2584                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2585                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2586                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2587
2588 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2589                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2590                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2591
2592         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2593         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2594                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2595                                              rx_hash_toeplitz_key);
2596                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2597                                                rx_hash_toeplitz_key);
2598
2599                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2600                 memcpy(rss_key, params->toeplitz_hash_key, len);
2601         }
2602
2603         switch (tt) {
2604         case MLX5E_TT_IPV4_TCP:
2605                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2606                          MLX5_L3_PROT_TYPE_IPV4);
2607                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2608                          MLX5_L4_PROT_TYPE_TCP);
2609                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2610                          MLX5_HASH_IP_L4PORTS);
2611                 break;
2612
2613         case MLX5E_TT_IPV6_TCP:
2614                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2615                          MLX5_L3_PROT_TYPE_IPV6);
2616                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2617                          MLX5_L4_PROT_TYPE_TCP);
2618                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2619                          MLX5_HASH_IP_L4PORTS);
2620                 break;
2621
2622         case MLX5E_TT_IPV4_UDP:
2623                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2624                          MLX5_L3_PROT_TYPE_IPV4);
2625                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2626                          MLX5_L4_PROT_TYPE_UDP);
2627                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2628                          MLX5_HASH_IP_L4PORTS);
2629                 break;
2630
2631         case MLX5E_TT_IPV6_UDP:
2632                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2633                          MLX5_L3_PROT_TYPE_IPV6);
2634                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2635                          MLX5_L4_PROT_TYPE_UDP);
2636                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2637                          MLX5_HASH_IP_L4PORTS);
2638                 break;
2639
2640         case MLX5E_TT_IPV4_IPSEC_AH:
2641                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2642                          MLX5_L3_PROT_TYPE_IPV4);
2643                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2644                          MLX5_HASH_IP_IPSEC_SPI);
2645                 break;
2646
2647         case MLX5E_TT_IPV6_IPSEC_AH:
2648                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2649                          MLX5_L3_PROT_TYPE_IPV6);
2650                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2651                          MLX5_HASH_IP_IPSEC_SPI);
2652                 break;
2653
2654         case MLX5E_TT_IPV4_IPSEC_ESP:
2655                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2656                          MLX5_L3_PROT_TYPE_IPV4);
2657                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2658                          MLX5_HASH_IP_IPSEC_SPI);
2659                 break;
2660
2661         case MLX5E_TT_IPV6_IPSEC_ESP:
2662                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2663                          MLX5_L3_PROT_TYPE_IPV6);
2664                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2665                          MLX5_HASH_IP_IPSEC_SPI);
2666                 break;
2667
2668         case MLX5E_TT_IPV4:
2669                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2670                          MLX5_L3_PROT_TYPE_IPV4);
2671                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2672                          MLX5_HASH_IP);
2673                 break;
2674
2675         case MLX5E_TT_IPV6:
2676                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2677                          MLX5_L3_PROT_TYPE_IPV6);
2678                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2679                          MLX5_HASH_IP);
2680                 break;
2681         default:
2682                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2683         }
2684 }
2685
2686 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2687 {
2688         struct mlx5_core_dev *mdev = priv->mdev;
2689
2690         void *in;
2691         void *tirc;
2692         int inlen;
2693         int err;
2694         int tt;
2695         int ix;
2696
2697         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2698         in = kvzalloc(inlen, GFP_KERNEL);
2699         if (!in)
2700                 return -ENOMEM;
2701
2702         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2703         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2704
2705         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2706
2707         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2708                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2709                                            inlen);
2710                 if (err)
2711                         goto free_in;
2712         }
2713
2714         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2715                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2716                                            in, inlen);
2717                 if (err)
2718                         goto free_in;
2719         }
2720
2721 free_in:
2722         kvfree(in);
2723
2724         return err;
2725 }
2726
2727 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2728                                             enum mlx5e_traffic_types tt,
2729                                             u32 *tirc)
2730 {
2731         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2732
2733         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2734
2735         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2736         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2737         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2738
2739         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2740 }
2741
2742 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2743                          struct mlx5e_params *params, u16 mtu)
2744 {
2745         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2746         int err;
2747
2748         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2749         if (err)
2750                 return err;
2751
2752         /* Update vport context MTU */
2753         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2754         return 0;
2755 }
2756
2757 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2758                             struct mlx5e_params *params, u16 *mtu)
2759 {
2760         u16 hw_mtu = 0;
2761         int err;
2762
2763         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2764         if (err || !hw_mtu) /* fallback to port oper mtu */
2765                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2766
2767         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2768 }
2769
2770 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2771 {
2772         struct mlx5e_params *params = &priv->channels.params;
2773         struct net_device *netdev = priv->netdev;
2774         struct mlx5_core_dev *mdev = priv->mdev;
2775         u16 mtu;
2776         int err;
2777
2778         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2779         if (err)
2780                 return err;
2781
2782         mlx5e_query_mtu(mdev, params, &mtu);
2783         if (mtu != params->sw_mtu)
2784                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2785                             __func__, mtu, params->sw_mtu);
2786
2787         params->sw_mtu = mtu;
2788         return 0;
2789 }
2790
2791 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2792 {
2793         struct mlx5e_priv *priv = netdev_priv(netdev);
2794         int nch = priv->channels.params.num_channels;
2795         int ntc = priv->channels.params.num_tc;
2796         int tc;
2797
2798         netdev_reset_tc(netdev);
2799
2800         if (ntc == 1)
2801                 return;
2802
2803         netdev_set_num_tc(netdev, ntc);
2804
2805         /* Map netdev TCs to offset 0
2806          * We have our own UP to TXQ mapping for QoS
2807          */
2808         for (tc = 0; tc < ntc; tc++)
2809                 netdev_set_tc_queue(netdev, tc, nch, 0);
2810 }
2811
2812 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2813 {
2814         int max_nch = priv->profile->max_nch(priv->mdev);
2815         int i, tc;
2816
2817         for (i = 0; i < max_nch; i++)
2818                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2819                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2820 }
2821
2822 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2823 {
2824         struct mlx5e_channel *c;
2825         struct mlx5e_txqsq *sq;
2826         int i, tc;
2827
2828         for (i = 0; i < priv->channels.num; i++) {
2829                 c = priv->channels.c[i];
2830                 for (tc = 0; tc < c->num_tc; tc++) {
2831                         sq = &c->sq[tc];
2832                         priv->txq2sq[sq->txq_ix] = sq;
2833                 }
2834         }
2835 }
2836
2837 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2838 {
2839         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2840         struct net_device *netdev = priv->netdev;
2841
2842         mlx5e_netdev_set_tcs(netdev);
2843         netif_set_real_num_tx_queues(netdev, num_txqs);
2844         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2845
2846         mlx5e_build_tx2sq_maps(priv);
2847         mlx5e_activate_channels(&priv->channels);
2848         netif_tx_start_all_queues(priv->netdev);
2849
2850         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2851                 mlx5e_add_sqs_fwd_rules(priv);
2852
2853         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2854         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2855 }
2856
2857 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2858 {
2859         mlx5e_redirect_rqts_to_drop(priv);
2860
2861         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2862                 mlx5e_remove_sqs_fwd_rules(priv);
2863
2864         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2865          * polling for inactive tx queues.
2866          */
2867         netif_tx_stop_all_queues(priv->netdev);
2868         netif_tx_disable(priv->netdev);
2869         mlx5e_deactivate_channels(&priv->channels);
2870 }
2871
2872 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2873                                 struct mlx5e_channels *new_chs,
2874                                 mlx5e_fp_hw_modify hw_modify)
2875 {
2876         struct net_device *netdev = priv->netdev;
2877         int new_num_txqs;
2878         int carrier_ok;
2879         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2880
2881         carrier_ok = netif_carrier_ok(netdev);
2882         netif_carrier_off(netdev);
2883
2884         if (new_num_txqs < netdev->real_num_tx_queues)
2885                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2886
2887         mlx5e_deactivate_priv_channels(priv);
2888         mlx5e_close_channels(&priv->channels);
2889
2890         priv->channels = *new_chs;
2891
2892         /* New channels are ready to roll, modify HW settings if needed */
2893         if (hw_modify)
2894                 hw_modify(priv);
2895
2896         mlx5e_refresh_tirs(priv, false);
2897         mlx5e_activate_priv_channels(priv);
2898
2899         /* return carrier back if needed */
2900         if (carrier_ok)
2901                 netif_carrier_on(netdev);
2902 }
2903
2904 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2905 {
2906         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2907         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2908 }
2909
2910 int mlx5e_open_locked(struct net_device *netdev)
2911 {
2912         struct mlx5e_priv *priv = netdev_priv(netdev);
2913         int err;
2914
2915         set_bit(MLX5E_STATE_OPENED, &priv->state);
2916
2917         err = mlx5e_open_channels(priv, &priv->channels);
2918         if (err)
2919                 goto err_clear_state_opened_flag;
2920
2921         mlx5e_refresh_tirs(priv, false);
2922         mlx5e_activate_priv_channels(priv);
2923         if (priv->profile->update_carrier)
2924                 priv->profile->update_carrier(priv);
2925
2926         if (priv->profile->update_stats)
2927                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2928
2929         return 0;
2930
2931 err_clear_state_opened_flag:
2932         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2933         return err;
2934 }
2935
2936 int mlx5e_open(struct net_device *netdev)
2937 {
2938         struct mlx5e_priv *priv = netdev_priv(netdev);
2939         int err;
2940
2941         mutex_lock(&priv->state_lock);
2942         err = mlx5e_open_locked(netdev);
2943         if (!err)
2944                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2945         mutex_unlock(&priv->state_lock);
2946
2947         if (mlx5e_vxlan_allowed(priv->mdev))
2948                 udp_tunnel_get_rx_info(netdev);
2949
2950         return err;
2951 }
2952
2953 int mlx5e_close_locked(struct net_device *netdev)
2954 {
2955         struct mlx5e_priv *priv = netdev_priv(netdev);
2956
2957         /* May already be CLOSED in case a previous configuration operation
2958          * (e.g RX/TX queue size change) that involves close&open failed.
2959          */
2960         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2961                 return 0;
2962
2963         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2964
2965         netif_carrier_off(priv->netdev);
2966         mlx5e_deactivate_priv_channels(priv);
2967         mlx5e_close_channels(&priv->channels);
2968
2969         return 0;
2970 }
2971
2972 int mlx5e_close(struct net_device *netdev)
2973 {
2974         struct mlx5e_priv *priv = netdev_priv(netdev);
2975         int err;
2976
2977         if (!netif_device_present(netdev))
2978                 return -ENODEV;
2979
2980         mutex_lock(&priv->state_lock);
2981         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2982         err = mlx5e_close_locked(netdev);
2983         mutex_unlock(&priv->state_lock);
2984
2985         return err;
2986 }
2987
2988 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2989                                struct mlx5e_rq *rq,
2990                                struct mlx5e_rq_param *param)
2991 {
2992         void *rqc = param->rqc;
2993         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2994         int err;
2995
2996         param->wq.db_numa_node = param->wq.buf_numa_node;
2997
2998         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2999                                  &rq->wq_ctrl);
3000         if (err)
3001                 return err;
3002
3003         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3004         xdp_rxq_info_unused(&rq->xdp_rxq);
3005
3006         rq->mdev = mdev;
3007
3008         return 0;
3009 }
3010
3011 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3012                                struct mlx5e_cq *cq,
3013                                struct mlx5e_cq_param *param)
3014 {
3015         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3016         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
3017
3018         return mlx5e_alloc_cq_common(mdev, param, cq);
3019 }
3020
3021 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3022                               struct mlx5e_rq *drop_rq)
3023 {
3024         struct mlx5_core_dev *mdev = priv->mdev;
3025         struct mlx5e_cq_param cq_param = {};
3026         struct mlx5e_rq_param rq_param = {};
3027         struct mlx5e_cq *cq = &drop_rq->cq;
3028         int err;
3029
3030         mlx5e_build_drop_rq_param(priv, &rq_param);
3031
3032         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3033         if (err)
3034                 return err;
3035
3036         err = mlx5e_create_cq(cq, &cq_param);
3037         if (err)
3038                 goto err_free_cq;
3039
3040         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3041         if (err)
3042                 goto err_destroy_cq;
3043
3044         err = mlx5e_create_rq(drop_rq, &rq_param);
3045         if (err)
3046                 goto err_free_rq;
3047
3048         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3049         if (err)
3050                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3051
3052         return 0;
3053
3054 err_free_rq:
3055         mlx5e_free_rq(drop_rq);
3056
3057 err_destroy_cq:
3058         mlx5e_destroy_cq(cq);
3059
3060 err_free_cq:
3061         mlx5e_free_cq(cq);
3062
3063         return err;
3064 }
3065
3066 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3067 {
3068         mlx5e_destroy_rq(drop_rq);
3069         mlx5e_free_rq(drop_rq);
3070         mlx5e_destroy_cq(&drop_rq->cq);
3071         mlx5e_free_cq(&drop_rq->cq);
3072 }
3073
3074 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3075                      u32 underlay_qpn, u32 *tisn)
3076 {
3077         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3078         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3079
3080         MLX5_SET(tisc, tisc, prio, tc << 1);
3081         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);