bc034958c8468c33b561c8c40a6c5284e5b2692e
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include <net/page_pool.h>
39 #include "eswitch.h"
40 #include "en.h"
41 #include "en_tc.h"
42 #include "en_rep.h"
43 #include "en_accel/ipsec.h"
44 #include "en_accel/ipsec_rxtx.h"
45 #include "en_accel/tls.h"
46 #include "accel/ipsec.h"
47 #include "accel/tls.h"
48 #include "lib/vxlan.h"
49 #include "lib/clock.h"
50 #include "en/port.h"
51 #include "en/xdp.h"
52
53 struct mlx5e_rq_param {
54         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
55         struct mlx5_wq_param    wq;
56         struct mlx5e_rq_frags_info frags_info;
57 };
58
59 struct mlx5e_sq_param {
60         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
61         struct mlx5_wq_param       wq;
62 };
63
64 struct mlx5e_cq_param {
65         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
66         struct mlx5_wq_param       wq;
67         u16                        eq_ix;
68         u8                         cq_period_mode;
69 };
70
71 struct mlx5e_channel_param {
72         struct mlx5e_rq_param      rq;
73         struct mlx5e_sq_param      sq;
74         struct mlx5e_sq_param      xdp_sq;
75         struct mlx5e_sq_param      icosq;
76         struct mlx5e_cq_param      rx_cq;
77         struct mlx5e_cq_param      tx_cq;
78         struct mlx5e_cq_param      icosq_cq;
79 };
80
81 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
82 {
83         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
84                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
85                 MLX5_CAP_ETH(mdev, reg_umr_sq);
86         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
87         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
88
89         if (!striding_rq_umr)
90                 return false;
91         if (!inline_umr) {
92                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
93                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
94                 return false;
95         }
96         return true;
97 }
98
99 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
100 {
101         u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
102         u16 linear_rq_headroom = params->xdp_prog ?
103                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
104         u32 frag_sz;
105
106         linear_rq_headroom += NET_IP_ALIGN;
107
108         frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
109
110         if (params->xdp_prog && frag_sz < PAGE_SIZE)
111                 frag_sz = PAGE_SIZE;
112
113         return frag_sz;
114 }
115
116 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
117 {
118         u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
119
120         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
121 }
122
123 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
124                                    struct mlx5e_params *params)
125 {
126         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
127
128         return !params->lro_en && frag_sz <= PAGE_SIZE;
129 }
130
131 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
132                                          struct mlx5e_params *params)
133 {
134         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
135         s8 signed_log_num_strides_param;
136         u8 log_num_strides;
137
138         if (!mlx5e_rx_is_linear_skb(mdev, params))
139                 return false;
140
141         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
142                 return true;
143
144         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
145         signed_log_num_strides_param =
146                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
147
148         return signed_log_num_strides_param >= 0;
149 }
150
151 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
152 {
153         if (params->log_rq_mtu_frames <
154             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
155                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
156
157         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
158 }
159
160 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
161                                           struct mlx5e_params *params)
162 {
163         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
164                 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
165
166         return MLX5E_MPWQE_STRIDE_SZ(mdev,
167                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
168 }
169
170 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
171                                           struct mlx5e_params *params)
172 {
173         return MLX5_MPWRQ_LOG_WQE_SZ -
174                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
175 }
176
177 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
178                                  struct mlx5e_params *params)
179 {
180         u16 linear_rq_headroom = params->xdp_prog ?
181                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
182         bool is_linear_skb;
183
184         linear_rq_headroom += NET_IP_ALIGN;
185
186         is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
187                 mlx5e_rx_is_linear_skb(mdev, params) :
188                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
189
190         return is_linear_skb ? linear_rq_headroom : 0;
191 }
192
193 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
194                                struct mlx5e_params *params)
195 {
196         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
197         params->log_rq_mtu_frames = is_kdump_kernel() ?
198                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
199                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
200
201         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
202                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
203                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
204                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
205                        BIT(params->log_rq_mtu_frames),
206                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
207                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
208 }
209
210 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
211                                 struct mlx5e_params *params)
212 {
213         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
214                 !MLX5_IPSEC_DEV(mdev) &&
215                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
216 }
217
218 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
219 {
220         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
221                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
222                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
223                 MLX5_WQ_TYPE_CYCLIC;
224 }
225
226 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
227 {
228         struct mlx5_core_dev *mdev = priv->mdev;
229         u8 port_state;
230
231         port_state = mlx5_query_vport_state(mdev,
232                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
233                                             0);
234
235         if (port_state == VPORT_STATE_UP) {
236                 netdev_info(priv->netdev, "Link up\n");
237                 netif_carrier_on(priv->netdev);
238         } else {
239                 netdev_info(priv->netdev, "Link down\n");
240                 netif_carrier_off(priv->netdev);
241         }
242 }
243
244 static void mlx5e_update_carrier_work(struct work_struct *work)
245 {
246         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
247                                                update_carrier_work);
248
249         mutex_lock(&priv->state_lock);
250         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
251                 if (priv->profile->update_carrier)
252                         priv->profile->update_carrier(priv);
253         mutex_unlock(&priv->state_lock);
254 }
255
256 void mlx5e_update_stats(struct mlx5e_priv *priv)
257 {
258         int i;
259
260         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
261                 if (mlx5e_stats_grps[i].update_stats)
262                         mlx5e_stats_grps[i].update_stats(priv);
263 }
264
265 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
266 {
267         int i;
268
269         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
270                 if (mlx5e_stats_grps[i].update_stats_mask &
271                     MLX5E_NDO_UPDATE_STATS)
272                         mlx5e_stats_grps[i].update_stats(priv);
273 }
274
275 void mlx5e_update_stats_work(struct work_struct *work)
276 {
277         struct delayed_work *dwork = to_delayed_work(work);
278         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
279                                                update_stats_work);
280
281         mutex_lock(&priv->state_lock);
282         priv->profile->update_stats(priv);
283         mutex_unlock(&priv->state_lock);
284 }
285
286 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
287                               enum mlx5_dev_event event, unsigned long param)
288 {
289         struct mlx5e_priv *priv = vpriv;
290
291         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
292                 return;
293
294         switch (event) {
295         case MLX5_DEV_EVENT_PORT_UP:
296         case MLX5_DEV_EVENT_PORT_DOWN:
297                 queue_work(priv->wq, &priv->update_carrier_work);
298                 break;
299         default:
300                 break;
301         }
302 }
303
304 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
305 {
306         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
307 }
308
309 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
310 {
311         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
312         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
313 }
314
315 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
316                                        struct mlx5e_icosq *sq,
317                                        struct mlx5e_umr_wqe *wqe)
318 {
319         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
320         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
321         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
322
323         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
324                                       ds_cnt);
325         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
326         cseg->imm       = rq->mkey_be;
327
328         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
329         ucseg->xlt_octowords =
330                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
331         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
332 }
333
334 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
335 {
336         switch (rq->wq_type) {
337         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
338                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
339         default:
340                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
341         }
342 }
343
344 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
345 {
346         switch (rq->wq_type) {
347         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
348                 return rq->mpwqe.wq.cur_sz;
349         default:
350                 return rq->wqe.wq.cur_sz;
351         }
352 }
353
354 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
355                                      struct mlx5e_channel *c)
356 {
357         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
358
359         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
360                                                   sizeof(*rq->mpwqe.info)),
361                                        GFP_KERNEL, cpu_to_node(c->cpu));
362         if (!rq->mpwqe.info)
363                 return -ENOMEM;
364
365         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
366
367         return 0;
368 }
369
370 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
371                                  u64 npages, u8 page_shift,
372                                  struct mlx5_core_mkey *umr_mkey)
373 {
374         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
375         void *mkc;
376         u32 *in;
377         int err;
378
379         in = kvzalloc(inlen, GFP_KERNEL);
380         if (!in)
381                 return -ENOMEM;
382
383         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
384
385         MLX5_SET(mkc, mkc, free, 1);
386         MLX5_SET(mkc, mkc, umr_en, 1);
387         MLX5_SET(mkc, mkc, lw, 1);
388         MLX5_SET(mkc, mkc, lr, 1);
389         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
390
391         MLX5_SET(mkc, mkc, qpn, 0xffffff);
392         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
393         MLX5_SET64(mkc, mkc, len, npages << page_shift);
394         MLX5_SET(mkc, mkc, translations_octword_size,
395                  MLX5_MTT_OCTW(npages));
396         MLX5_SET(mkc, mkc, log_page_size, page_shift);
397
398         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
399
400         kvfree(in);
401         return err;
402 }
403
404 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
405 {
406         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
407
408         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
409 }
410
411 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
412 {
413         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
414 }
415
416 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
417 {
418         struct mlx5e_wqe_frag_info next_frag, *prev;
419         int i;
420
421         next_frag.di = &rq->wqe.di[0];
422         next_frag.offset = 0;
423         prev = NULL;
424
425         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
426                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
427                 struct mlx5e_wqe_frag_info *frag =
428                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
429                 int f;
430
431                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
432                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
433                                 next_frag.di++;
434                                 next_frag.offset = 0;
435                                 if (prev)
436                                         prev->last_in_page = true;
437                         }
438                         *frag = next_frag;
439
440                         /* prepare next */
441                         next_frag.offset += frag_info[f].frag_stride;
442                         prev = frag;
443                 }
444         }
445
446         if (prev)
447                 prev->last_in_page = true;
448 }
449
450 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
451                               struct mlx5e_params *params,
452                               int wq_sz, int cpu)
453 {
454         int len = wq_sz << rq->wqe.info.log_num_frags;
455
456         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
457                                    GFP_KERNEL, cpu_to_node(cpu));
458         if (!rq->wqe.di)
459                 return -ENOMEM;
460
461         mlx5e_init_frags_partition(rq);
462
463         return 0;
464 }
465
466 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
467 {
468         kvfree(rq->wqe.di);
469 }
470
471 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
472                           struct mlx5e_params *params,
473                           struct mlx5e_rq_param *rqp,
474                           struct mlx5e_rq *rq)
475 {
476         struct page_pool_params pp_params = { 0 };
477         struct mlx5_core_dev *mdev = c->mdev;
478         void *rqc = rqp->rqc;
479         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
480         u32 pool_size;
481         int wq_sz;
482         int err;
483         int i;
484
485         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
486
487         rq->wq_type = params->rq_wq_type;
488         rq->pdev    = c->pdev;
489         rq->netdev  = c->netdev;
490         rq->tstamp  = c->tstamp;
491         rq->clock   = &mdev->clock;
492         rq->channel = c;
493         rq->ix      = c->ix;
494         rq->mdev    = mdev;
495         rq->stats   = &c->priv->channel_stats[c->ix].rq;
496
497         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
498         if (IS_ERR(rq->xdp_prog)) {
499                 err = PTR_ERR(rq->xdp_prog);
500                 rq->xdp_prog = NULL;
501                 goto err_rq_wq_destroy;
502         }
503
504         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
505         if (err < 0)
506                 goto err_rq_wq_destroy;
507
508         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
509         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
510         pool_size = 1 << params->log_rq_mtu_frames;
511
512         switch (rq->wq_type) {
513         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
514                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
515                                         &rq->wq_ctrl);
516                 if (err)
517                         return err;
518
519                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
520
521                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
522
523                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
524
525                 rq->post_wqes = mlx5e_post_rx_mpwqes;
526                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
527
528                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
529 #ifdef CONFIG_MLX5_EN_IPSEC
530                 if (MLX5_IPSEC_DEV(mdev)) {
531                         err = -EINVAL;
532                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
533                         goto err_rq_wq_destroy;
534                 }
535 #endif
536                 if (!rq->handle_rx_cqe) {
537                         err = -EINVAL;
538                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
539                         goto err_rq_wq_destroy;
540                 }
541
542                 rq->mpwqe.skb_from_cqe_mpwrq =
543                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
544                         mlx5e_skb_from_cqe_mpwrq_linear :
545                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
546                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
547                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
548
549                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
550                 if (err)
551                         goto err_rq_wq_destroy;
552                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
553
554                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
555                 if (err)
556                         goto err_free;
557                 break;
558         default: /* MLX5_WQ_TYPE_CYCLIC */
559                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
560                                          &rq->wq_ctrl);
561                 if (err)
562                         return err;
563
564                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
565
566                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
567
568                 rq->wqe.info = rqp->frags_info;
569                 rq->wqe.frags =
570                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
571                                         (wq_sz << rq->wqe.info.log_num_frags)),
572                                       GFP_KERNEL, cpu_to_node(c->cpu));
573                 if (!rq->wqe.frags) {
574                         err = -ENOMEM;
575                         goto err_free;
576                 }
577
578                 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
579                 if (err)
580                         goto err_free;
581                 rq->post_wqes = mlx5e_post_rx_wqes;
582                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
583
584 #ifdef CONFIG_MLX5_EN_IPSEC
585                 if (c->priv->ipsec)
586                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
587                 else
588 #endif
589                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
590                 if (!rq->handle_rx_cqe) {
591                         err = -EINVAL;
592                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
593                         goto err_free;
594                 }
595
596                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
597                         mlx5e_skb_from_cqe_linear :
598                         mlx5e_skb_from_cqe_nonlinear;
599                 rq->mkey_be = c->mkey_be;
600         }
601
602         /* Create a page_pool and register it with rxq */
603         pp_params.order     = 0;
604         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
605         pp_params.pool_size = pool_size;
606         pp_params.nid       = cpu_to_node(c->cpu);
607         pp_params.dev       = c->pdev;
608         pp_params.dma_dir   = rq->buff.map_dir;
609
610         /* page_pool can be used even when there is no rq->xdp_prog,
611          * given page_pool does not handle DMA mapping there is no
612          * required state to clear. And page_pool gracefully handle
613          * elevated refcnt.
614          */
615         rq->page_pool = page_pool_create(&pp_params);
616         if (IS_ERR(rq->page_pool)) {
617                 err = PTR_ERR(rq->page_pool);
618                 rq->page_pool = NULL;
619                 goto err_free;
620         }
621         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
622                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
623         if (err)
624                 goto err_free;
625
626         for (i = 0; i < wq_sz; i++) {
627                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
628                         struct mlx5e_rx_wqe_ll *wqe =
629                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
630                         u32 byte_count =
631                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
632                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
633
634                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
635                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
636                         wqe->data[0].lkey = rq->mkey_be;
637                 } else {
638                         struct mlx5e_rx_wqe_cyc *wqe =
639                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
640                         int f;
641
642                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
643                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
644                                         MLX5_HW_START_PADDING;
645
646                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
647                                 wqe->data[f].lkey = rq->mkey_be;
648                         }
649                         /* check if num_frags is not a pow of two */
650                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
651                                 wqe->data[f].byte_count = 0;
652                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
653                                 wqe->data[f].addr = 0;
654                         }
655                 }
656         }
657
658         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
659
660         switch (params->rx_cq_moderation.cq_period_mode) {
661         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
662                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
663                 break;
664         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
665         default:
666                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
667         }
668
669         rq->page_cache.head = 0;
670         rq->page_cache.tail = 0;
671
672         return 0;
673
674 err_free:
675         switch (rq->wq_type) {
676         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
677                 kvfree(rq->mpwqe.info);
678                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
679                 break;
680         default: /* MLX5_WQ_TYPE_CYCLIC */
681                 kvfree(rq->wqe.frags);
682                 mlx5e_free_di_list(rq);
683         }
684
685 err_rq_wq_destroy:
686         if (rq->xdp_prog)
687                 bpf_prog_put(rq->xdp_prog);
688         xdp_rxq_info_unreg(&rq->xdp_rxq);
689         if (rq->page_pool)
690                 page_pool_destroy(rq->page_pool);
691         mlx5_wq_destroy(&rq->wq_ctrl);
692
693         return err;
694 }
695
696 static void mlx5e_free_rq(struct mlx5e_rq *rq)
697 {
698         int i;
699
700         if (rq->xdp_prog)
701                 bpf_prog_put(rq->xdp_prog);
702
703         xdp_rxq_info_unreg(&rq->xdp_rxq);
704         if (rq->page_pool)
705                 page_pool_destroy(rq->page_pool);
706
707         switch (rq->wq_type) {
708         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
709                 kvfree(rq->mpwqe.info);
710                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
711                 break;
712         default: /* MLX5_WQ_TYPE_CYCLIC */
713                 kvfree(rq->wqe.frags);
714                 mlx5e_free_di_list(rq);
715         }
716
717         for (i = rq->page_cache.head; i != rq->page_cache.tail;
718              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
719                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
720
721                 mlx5e_page_release(rq, dma_info, false);
722         }
723         mlx5_wq_destroy(&rq->wq_ctrl);
724 }
725
726 static int mlx5e_create_rq(struct mlx5e_rq *rq,
727                            struct mlx5e_rq_param *param)
728 {
729         struct mlx5_core_dev *mdev = rq->mdev;
730
731         void *in;
732         void *rqc;
733         void *wq;
734         int inlen;
735         int err;
736
737         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
738                 sizeof(u64) * rq->wq_ctrl.buf.npages;
739         in = kvzalloc(inlen, GFP_KERNEL);
740         if (!in)
741                 return -ENOMEM;
742
743         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
744         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
745
746         memcpy(rqc, param->rqc, sizeof(param->rqc));
747
748         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
749         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
750         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
751                                                 MLX5_ADAPTER_PAGE_SHIFT);
752         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
753
754         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
755                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
756
757         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
758
759         kvfree(in);
760
761         return err;
762 }
763
764 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
765                                  int next_state)
766 {
767         struct mlx5_core_dev *mdev = rq->mdev;
768
769         void *in;
770         void *rqc;
771         int inlen;
772         int err;
773
774         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
775         in = kvzalloc(inlen, GFP_KERNEL);
776         if (!in)
777                 return -ENOMEM;
778
779         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
780
781         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
782         MLX5_SET(rqc, rqc, state, next_state);
783
784         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
785
786         kvfree(in);
787
788         return err;
789 }
790
791 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
792 {
793         struct mlx5e_channel *c = rq->channel;
794         struct mlx5e_priv *priv = c->priv;
795         struct mlx5_core_dev *mdev = priv->mdev;
796
797         void *in;
798         void *rqc;
799         int inlen;
800         int err;
801
802         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
803         in = kvzalloc(inlen, GFP_KERNEL);
804         if (!in)
805                 return -ENOMEM;
806
807         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
808
809         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
810         MLX5_SET64(modify_rq_in, in, modify_bitmask,
811                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
812         MLX5_SET(rqc, rqc, scatter_fcs, enable);
813         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
814
815         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
816
817         kvfree(in);
818
819         return err;
820 }
821
822 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
823 {
824         struct mlx5e_channel *c = rq->channel;
825         struct mlx5_core_dev *mdev = c->mdev;
826         void *in;
827         void *rqc;
828         int inlen;
829         int err;
830
831         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
832         in = kvzalloc(inlen, GFP_KERNEL);
833         if (!in)
834                 return -ENOMEM;
835
836         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
837
838         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
839         MLX5_SET64(modify_rq_in, in, modify_bitmask,
840                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
841         MLX5_SET(rqc, rqc, vsd, vsd);
842         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
843
844         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
845
846         kvfree(in);
847
848         return err;
849 }
850
851 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
852 {
853         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
854 }
855
856 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
857 {
858         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
859         struct mlx5e_channel *c = rq->channel;
860
861         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
862
863         do {
864                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
865                         return 0;
866
867                 msleep(20);
868         } while (time_before(jiffies, exp_time));
869
870         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
871                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
872
873         return -ETIMEDOUT;
874 }
875
876 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
877 {
878         __be16 wqe_ix_be;
879         u16 wqe_ix;
880
881         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
882                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
883
884                 /* UMR WQE (if in progress) is always at wq->head */
885                 if (rq->mpwqe.umr_in_progress)
886                         rq->dealloc_wqe(rq, wq->head);
887
888                 while (!mlx5_wq_ll_is_empty(wq)) {
889                         struct mlx5e_rx_wqe_ll *wqe;
890
891                         wqe_ix_be = *wq->tail_next;
892                         wqe_ix    = be16_to_cpu(wqe_ix_be);
893                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
894                         rq->dealloc_wqe(rq, wqe_ix);
895                         mlx5_wq_ll_pop(wq, wqe_ix_be,
896                                        &wqe->next.next_wqe_index);
897                 }
898         } else {
899                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
900
901                 while (!mlx5_wq_cyc_is_empty(wq)) {
902                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
903                         rq->dealloc_wqe(rq, wqe_ix);
904                         mlx5_wq_cyc_pop(wq);
905                 }
906         }
907
908 }
909
910 static int mlx5e_open_rq(struct mlx5e_channel *c,
911                          struct mlx5e_params *params,
912                          struct mlx5e_rq_param *param,
913                          struct mlx5e_rq *rq)
914 {
915         int err;
916
917         err = mlx5e_alloc_rq(c, params, param, rq);
918         if (err)
919                 return err;
920
921         err = mlx5e_create_rq(rq, param);
922         if (err)
923                 goto err_free_rq;
924
925         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
926         if (err)
927                 goto err_destroy_rq;
928
929         if (params->rx_dim_enabled)
930                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
931
932         if (params->pflags & MLX5E_PFLAG_RX_NO_CSUM_COMPLETE)
933                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
934
935         return 0;
936
937 err_destroy_rq:
938         mlx5e_destroy_rq(rq);
939 err_free_rq:
940         mlx5e_free_rq(rq);
941
942         return err;
943 }
944
945 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
946 {
947         struct mlx5e_icosq *sq = &rq->channel->icosq;
948         struct mlx5_wq_cyc *wq = &sq->wq;
949         struct mlx5e_tx_wqe *nopwqe;
950
951         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
952
953         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
954         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
955         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
956         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
957 }
958
959 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
960 {
961         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
962         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
963 }
964
965 static void mlx5e_close_rq(struct mlx5e_rq *rq)
966 {
967         cancel_work_sync(&rq->dim.work);
968         mlx5e_destroy_rq(rq);
969         mlx5e_free_rx_descs(rq);
970         mlx5e_free_rq(rq);
971 }
972
973 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
974 {
975         kvfree(sq->db.xdpi);
976 }
977
978 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
979 {
980         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
981
982         sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)),
983                                     GFP_KERNEL, numa);
984         if (!sq->db.xdpi) {
985                 mlx5e_free_xdpsq_db(sq);
986                 return -ENOMEM;
987         }
988
989         return 0;
990 }
991
992 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
993                              struct mlx5e_params *params,
994                              struct mlx5e_sq_param *param,
995                              struct mlx5e_xdpsq *sq,
996                              bool is_redirect)
997 {
998         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
999         struct mlx5_core_dev *mdev = c->mdev;
1000         struct mlx5_wq_cyc *wq = &sq->wq;
1001         int err;
1002
1003         sq->pdev      = c->pdev;
1004         sq->mkey_be   = c->mkey_be;
1005         sq->channel   = c;
1006         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1007         sq->min_inline_mode = params->tx_min_inline_mode;
1008         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1009         sq->stats     = is_redirect ?
1010                 &c->priv->channel_stats[c->ix].xdpsq :
1011                 &c->priv->channel_stats[c->ix].rq_xdpsq;
1012
1013         param->wq.db_numa_node = cpu_to_node(c->cpu);
1014         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1015         if (err)
1016                 return err;
1017         wq->db = &wq->db[MLX5_SND_DBR];
1018
1019         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1020         if (err)
1021                 goto err_sq_wq_destroy;
1022
1023         return 0;
1024
1025 err_sq_wq_destroy:
1026         mlx5_wq_destroy(&sq->wq_ctrl);
1027
1028         return err;
1029 }
1030
1031 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1032 {
1033         mlx5e_free_xdpsq_db(sq);
1034         mlx5_wq_destroy(&sq->wq_ctrl);
1035 }
1036
1037 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1038 {
1039         kvfree(sq->db.ico_wqe);
1040 }
1041
1042 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1043 {
1044         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1045
1046         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1047                                                   sizeof(*sq->db.ico_wqe)),
1048                                        GFP_KERNEL, numa);
1049         if (!sq->db.ico_wqe)
1050                 return -ENOMEM;
1051
1052         return 0;
1053 }
1054
1055 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1056                              struct mlx5e_sq_param *param,
1057                              struct mlx5e_icosq *sq)
1058 {
1059         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1060         struct mlx5_core_dev *mdev = c->mdev;
1061         struct mlx5_wq_cyc *wq = &sq->wq;
1062         int err;
1063
1064         sq->channel   = c;
1065         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1066
1067         param->wq.db_numa_node = cpu_to_node(c->cpu);
1068         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1069         if (err)
1070                 return err;
1071         wq->db = &wq->db[MLX5_SND_DBR];
1072
1073         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1074         if (err)
1075                 goto err_sq_wq_destroy;
1076
1077         return 0;
1078
1079 err_sq_wq_destroy:
1080         mlx5_wq_destroy(&sq->wq_ctrl);
1081
1082         return err;
1083 }
1084
1085 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1086 {
1087         mlx5e_free_icosq_db(sq);
1088         mlx5_wq_destroy(&sq->wq_ctrl);
1089 }
1090
1091 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1092 {
1093         kvfree(sq->db.wqe_info);
1094         kvfree(sq->db.dma_fifo);
1095 }
1096
1097 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1098 {
1099         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1100         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1101
1102         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1103                                                    sizeof(*sq->db.dma_fifo)),
1104                                         GFP_KERNEL, numa);
1105         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1106                                                    sizeof(*sq->db.wqe_info)),
1107                                         GFP_KERNEL, numa);
1108         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1109                 mlx5e_free_txqsq_db(sq);
1110                 return -ENOMEM;
1111         }
1112
1113         sq->dma_fifo_mask = df_sz - 1;
1114
1115         return 0;
1116 }
1117
1118 static void mlx5e_sq_recover(struct work_struct *work);
1119 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1120                              int txq_ix,
1121                              struct mlx5e_params *params,
1122                              struct mlx5e_sq_param *param,
1123                              struct mlx5e_txqsq *sq,
1124                              int tc)
1125 {
1126         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1127         struct mlx5_core_dev *mdev = c->mdev;
1128         struct mlx5_wq_cyc *wq = &sq->wq;
1129         int err;
1130
1131         sq->pdev      = c->pdev;
1132         sq->tstamp    = c->tstamp;
1133         sq->clock     = &mdev->clock;
1134         sq->mkey_be   = c->mkey_be;
1135         sq->channel   = c;
1136         sq->txq_ix    = txq_ix;
1137         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1138         sq->min_inline_mode = params->tx_min_inline_mode;
1139         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1140         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1141         if (MLX5_IPSEC_DEV(c->priv->mdev))
1142                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1143         if (mlx5_accel_is_tls_device(c->priv->mdev))
1144                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1145
1146         param->wq.db_numa_node = cpu_to_node(c->cpu);
1147         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1148         if (err)
1149                 return err;
1150         wq->db    = &wq->db[MLX5_SND_DBR];
1151
1152         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1153         if (err)
1154                 goto err_sq_wq_destroy;
1155
1156         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1157         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1158
1159         return 0;
1160
1161 err_sq_wq_destroy:
1162         mlx5_wq_destroy(&sq->wq_ctrl);
1163
1164         return err;
1165 }
1166
1167 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1168 {
1169         mlx5e_free_txqsq_db(sq);
1170         mlx5_wq_destroy(&sq->wq_ctrl);
1171 }
1172
1173 struct mlx5e_create_sq_param {
1174         struct mlx5_wq_ctrl        *wq_ctrl;
1175         u32                         cqn;
1176         u32                         tisn;
1177         u8                          tis_lst_sz;
1178         u8                          min_inline_mode;
1179 };
1180
1181 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1182                            struct mlx5e_sq_param *param,
1183                            struct mlx5e_create_sq_param *csp,
1184                            u32 *sqn)
1185 {
1186         void *in;
1187         void *sqc;
1188         void *wq;
1189         int inlen;
1190         int err;
1191
1192         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1193                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1194         in = kvzalloc(inlen, GFP_KERNEL);
1195         if (!in)
1196                 return -ENOMEM;
1197
1198         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1199         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1200
1201         memcpy(sqc, param->sqc, sizeof(param->sqc));
1202         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1203         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1204         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1205
1206         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1207                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1208
1209         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1210         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1211
1212         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1213         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1214         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1215                                           MLX5_ADAPTER_PAGE_SHIFT);
1216         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1217
1218         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1219                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1220
1221         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1222
1223         kvfree(in);
1224
1225         return err;
1226 }
1227
1228 struct mlx5e_modify_sq_param {
1229         int curr_state;
1230         int next_state;
1231         bool rl_update;
1232         int rl_index;
1233 };
1234
1235 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1236                            struct mlx5e_modify_sq_param *p)
1237 {
1238         void *in;
1239         void *sqc;
1240         int inlen;
1241         int err;
1242
1243         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1244         in = kvzalloc(inlen, GFP_KERNEL);
1245         if (!in)
1246                 return -ENOMEM;
1247
1248         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1249
1250         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1251         MLX5_SET(sqc, sqc, state, p->next_state);
1252         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1253                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1254                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1255         }
1256
1257         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1258
1259         kvfree(in);
1260
1261         return err;
1262 }
1263
1264 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1265 {
1266         mlx5_core_destroy_sq(mdev, sqn);
1267 }
1268
1269 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1270                                struct mlx5e_sq_param *param,
1271                                struct mlx5e_create_sq_param *csp,
1272                                u32 *sqn)
1273 {
1274         struct mlx5e_modify_sq_param msp = {0};
1275         int err;
1276
1277         err = mlx5e_create_sq(mdev, param, csp, sqn);
1278         if (err)
1279                 return err;
1280
1281         msp.curr_state = MLX5_SQC_STATE_RST;
1282         msp.next_state = MLX5_SQC_STATE_RDY;
1283         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1284         if (err)
1285                 mlx5e_destroy_sq(mdev, *sqn);
1286
1287         return err;
1288 }
1289
1290 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1291                                 struct mlx5e_txqsq *sq, u32 rate);
1292
1293 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1294                             u32 tisn,
1295                             int txq_ix,
1296                             struct mlx5e_params *params,
1297                             struct mlx5e_sq_param *param,
1298                             struct mlx5e_txqsq *sq,
1299                             int tc)
1300 {
1301         struct mlx5e_create_sq_param csp = {};
1302         u32 tx_rate;
1303         int err;
1304
1305         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1306         if (err)
1307                 return err;
1308
1309         csp.tisn            = tisn;
1310         csp.tis_lst_sz      = 1;
1311         csp.cqn             = sq->cq.mcq.cqn;
1312         csp.wq_ctrl         = &sq->wq_ctrl;
1313         csp.min_inline_mode = sq->min_inline_mode;
1314         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1315         if (err)
1316                 goto err_free_txqsq;
1317
1318         tx_rate = c->priv->tx_rates[sq->txq_ix];
1319         if (tx_rate)
1320                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1321
1322         if (params->tx_dim_enabled)
1323                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1324
1325         return 0;
1326
1327 err_free_txqsq:
1328         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1329         mlx5e_free_txqsq(sq);
1330
1331         return err;
1332 }
1333
1334 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1335 {
1336         WARN_ONCE(sq->cc != sq->pc,
1337                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1338                   sq->sqn, sq->cc, sq->pc);
1339         sq->cc = 0;
1340         sq->dma_fifo_cc = 0;
1341         sq->pc = 0;
1342 }
1343
1344 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1345 {
1346         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1347         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1348         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1349         netdev_tx_reset_queue(sq->txq);
1350         netif_tx_start_queue(sq->txq);
1351 }
1352
1353 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1354 {
1355         __netif_tx_lock_bh(txq);
1356         netif_tx_stop_queue(txq);
1357         __netif_tx_unlock_bh(txq);
1358 }
1359
1360 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1361 {
1362         struct mlx5e_channel *c = sq->channel;
1363         struct mlx5_wq_cyc *wq = &sq->wq;
1364
1365         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1366         /* prevent netif_tx_wake_queue */
1367         napi_synchronize(&c->napi);
1368
1369         netif_tx_disable_queue(sq->txq);
1370
1371         /* last doorbell out, godspeed .. */
1372         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1373                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1374                 struct mlx5e_tx_wqe *nop;
1375
1376                 sq->db.wqe_info[pi].skb = NULL;
1377                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1378                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1379         }
1380 }
1381
1382 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1383 {
1384         struct mlx5e_channel *c = sq->channel;
1385         struct mlx5_core_dev *mdev = c->mdev;
1386         struct mlx5_rate_limit rl = {0};
1387
1388         mlx5e_destroy_sq(mdev, sq->sqn);
1389         if (sq->rate_limit) {
1390                 rl.rate = sq->rate_limit;
1391                 mlx5_rl_remove_rate(mdev, &rl);
1392         }
1393         mlx5e_free_txqsq_descs(sq);
1394         mlx5e_free_txqsq(sq);
1395 }
1396
1397 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1398 {
1399         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1400
1401         while (time_before(jiffies, exp_time)) {
1402                 if (sq->cc == sq->pc)
1403                         return 0;
1404
1405                 msleep(20);
1406         }
1407
1408         netdev_err(sq->channel->netdev,
1409                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1410                    sq->sqn, sq->cc, sq->pc);
1411
1412         return -ETIMEDOUT;
1413 }
1414
1415 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1416 {
1417         struct mlx5_core_dev *mdev = sq->channel->mdev;
1418         struct net_device *dev = sq->channel->netdev;
1419         struct mlx5e_modify_sq_param msp = {0};
1420         int err;
1421
1422         msp.curr_state = curr_state;
1423         msp.next_state = MLX5_SQC_STATE_RST;
1424
1425         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1426         if (err) {
1427                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1428                 return err;
1429         }
1430
1431         memset(&msp, 0, sizeof(msp));
1432         msp.curr_state = MLX5_SQC_STATE_RST;
1433         msp.next_state = MLX5_SQC_STATE_RDY;
1434
1435         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1436         if (err) {
1437                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1438                 return err;
1439         }
1440
1441         return 0;
1442 }
1443
1444 static void mlx5e_sq_recover(struct work_struct *work)
1445 {
1446         struct mlx5e_txqsq_recover *recover =
1447                 container_of(work, struct mlx5e_txqsq_recover,
1448                              recover_work);
1449         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1450                                               recover);
1451         struct mlx5_core_dev *mdev = sq->channel->mdev;
1452         struct net_device *dev = sq->channel->netdev;
1453         u8 state;
1454         int err;
1455
1456         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1457         if (err) {
1458                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1459                            sq->sqn, err);
1460                 return;
1461         }
1462
1463         if (state != MLX5_RQC_STATE_ERR) {
1464                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1465                 return;
1466         }
1467
1468         netif_tx_disable_queue(sq->txq);
1469
1470         if (mlx5e_wait_for_sq_flush(sq))
1471                 return;
1472
1473         /* If the interval between two consecutive recovers per SQ is too
1474          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1475          * If we reached this state, there is probably a bug that needs to be
1476          * fixed. let's keep the queue close and let tx timeout cleanup.
1477          */
1478         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1479             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1480                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1481                            sq->sqn);
1482                 return;
1483         }
1484
1485         /* At this point, no new packets will arrive from the stack as TXQ is
1486          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1487          * pending WQEs.  SQ can safely reset the SQ.
1488          */
1489         if (mlx5e_sq_to_ready(sq, state))
1490                 return;
1491
1492         mlx5e_reset_txqsq_cc_pc(sq);
1493         sq->stats->recover++;
1494         recover->last_recover = jiffies;
1495         mlx5e_activate_txqsq(sq);
1496 }
1497
1498 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1499                             struct mlx5e_params *params,
1500                             struct mlx5e_sq_param *param,
1501                             struct mlx5e_icosq *sq)
1502 {
1503         struct mlx5e_create_sq_param csp = {};
1504         int err;
1505
1506         err = mlx5e_alloc_icosq(c, param, sq);
1507         if (err)
1508                 return err;
1509
1510         csp.cqn             = sq->cq.mcq.cqn;
1511         csp.wq_ctrl         = &sq->wq_ctrl;
1512         csp.min_inline_mode = params->tx_min_inline_mode;
1513         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1514         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1515         if (err)
1516                 goto err_free_icosq;
1517
1518         return 0;
1519
1520 err_free_icosq:
1521         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1522         mlx5e_free_icosq(sq);
1523
1524         return err;
1525 }
1526
1527 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1528 {
1529         struct mlx5e_channel *c = sq->channel;
1530
1531         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1532         napi_synchronize(&c->napi);
1533
1534         mlx5e_destroy_sq(c->mdev, sq->sqn);
1535         mlx5e_free_icosq(sq);
1536 }
1537
1538 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1539                             struct mlx5e_params *params,
1540                             struct mlx5e_sq_param *param,
1541                             struct mlx5e_xdpsq *sq,
1542                             bool is_redirect)
1543 {
1544         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1545         struct mlx5e_create_sq_param csp = {};
1546         unsigned int inline_hdr_sz = 0;
1547         int err;
1548         int i;
1549
1550         err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1551         if (err)
1552                 return err;
1553
1554         csp.tis_lst_sz      = 1;
1555         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1556         csp.cqn             = sq->cq.mcq.cqn;
1557         csp.wq_ctrl         = &sq->wq_ctrl;
1558         csp.min_inline_mode = sq->min_inline_mode;
1559         if (is_redirect)
1560                 set_bit(MLX5E_SQ_STATE_REDIRECT, &sq->state);
1561         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1562         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1563         if (err)
1564                 goto err_free_xdpsq;
1565
1566         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1567                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1568                 ds_cnt++;
1569         }
1570
1571         /* Pre initialize fixed WQE fields */
1572         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1573                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1574                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1575                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1576                 struct mlx5_wqe_data_seg *dseg;
1577
1578                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1579                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1580
1581                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1582                 dseg->lkey = sq->mkey_be;
1583         }
1584
1585         return 0;
1586
1587 err_free_xdpsq:
1588         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1589         mlx5e_free_xdpsq(sq);
1590
1591         return err;
1592 }
1593
1594 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1595 {
1596         struct mlx5e_channel *c = sq->channel;
1597
1598         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1599         napi_synchronize(&c->napi);
1600
1601         mlx5e_destroy_sq(c->mdev, sq->sqn);
1602         mlx5e_free_xdpsq_descs(sq);
1603         mlx5e_free_xdpsq(sq);
1604 }
1605
1606 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1607                                  struct mlx5e_cq_param *param,
1608                                  struct mlx5e_cq *cq)
1609 {
1610         struct mlx5_core_cq *mcq = &cq->mcq;
1611         int eqn_not_used;
1612         unsigned int irqn;
1613         int err;
1614         u32 i;
1615
1616         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1617                                &cq->wq_ctrl);
1618         if (err)
1619                 return err;
1620
1621         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1622
1623         mcq->cqe_sz     = 64;
1624         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1625         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1626         *mcq->set_ci_db = 0;
1627         *mcq->arm_db    = 0;
1628         mcq->vector     = param->eq_ix;
1629         mcq->comp       = mlx5e_completion_event;
1630         mcq->event      = mlx5e_cq_error_event;
1631         mcq->irqn       = irqn;
1632
1633         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1634                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1635
1636                 cqe->op_own = 0xf1;
1637         }
1638
1639         cq->mdev = mdev;
1640
1641         return 0;
1642 }
1643
1644 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1645                           struct mlx5e_cq_param *param,
1646                           struct mlx5e_cq *cq)
1647 {
1648         struct mlx5_core_dev *mdev = c->priv->mdev;
1649         int err;
1650
1651         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1652         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1653         param->eq_ix   = c->ix;
1654
1655         err = mlx5e_alloc_cq_common(mdev, param, cq);
1656
1657         cq->napi    = &c->napi;
1658         cq->channel = c;
1659
1660         return err;
1661 }
1662
1663 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1664 {
1665         mlx5_wq_destroy(&cq->wq_ctrl);
1666 }
1667
1668 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1669 {
1670         struct mlx5_core_dev *mdev = cq->mdev;
1671         struct mlx5_core_cq *mcq = &cq->mcq;
1672
1673         void *in;
1674         void *cqc;
1675         int inlen;
1676         unsigned int irqn_not_used;
1677         int eqn;
1678         int err;
1679
1680         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1681                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1682         in = kvzalloc(inlen, GFP_KERNEL);
1683         if (!in)
1684                 return -ENOMEM;
1685
1686         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1687
1688         memcpy(cqc, param->cqc, sizeof(param->cqc));
1689
1690         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1691                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1692
1693         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1694
1695         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1696         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1697         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1698         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1699                                             MLX5_ADAPTER_PAGE_SHIFT);
1700         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1701
1702         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1703
1704         kvfree(in);
1705
1706         if (err)
1707                 return err;
1708
1709         mlx5e_cq_arm(cq);
1710
1711         return 0;
1712 }
1713
1714 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1715 {
1716         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1717 }
1718
1719 static int mlx5e_open_cq(struct mlx5e_channel *c,
1720                          struct net_dim_cq_moder moder,
1721                          struct mlx5e_cq_param *param,
1722                          struct mlx5e_cq *cq)
1723 {
1724         struct mlx5_core_dev *mdev = c->mdev;
1725         int err;
1726
1727         err = mlx5e_alloc_cq(c, param, cq);
1728         if (err)
1729                 return err;
1730
1731         err = mlx5e_create_cq(cq, param);
1732         if (err)
1733                 goto err_free_cq;
1734
1735         if (MLX5_CAP_GEN(mdev, cq_moderation))
1736                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1737         return 0;
1738
1739 err_free_cq:
1740         mlx5e_free_cq(cq);
1741
1742         return err;
1743 }
1744
1745 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1746 {
1747         mlx5e_destroy_cq(cq);
1748         mlx5e_free_cq(cq);
1749 }
1750
1751 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1752 {
1753         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1754 }
1755
1756 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1757                              struct mlx5e_params *params,
1758                              struct mlx5e_channel_param *cparam)
1759 {
1760         int err;
1761         int tc;
1762
1763         for (tc = 0; tc < c->num_tc; tc++) {
1764                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1765                                     &cparam->tx_cq, &c->sq[tc].cq);
1766                 if (err)
1767                         goto err_close_tx_cqs;
1768         }
1769
1770         return 0;
1771
1772 err_close_tx_cqs:
1773         for (tc--; tc >= 0; tc--)
1774                 mlx5e_close_cq(&c->sq[tc].cq);
1775
1776         return err;
1777 }
1778
1779 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1780 {
1781         int tc;
1782
1783         for (tc = 0; tc < c->num_tc; tc++)
1784                 mlx5e_close_cq(&c->sq[tc].cq);
1785 }
1786
1787 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1788                           struct mlx5e_params *params,
1789                           struct mlx5e_channel_param *cparam)
1790 {
1791         struct mlx5e_priv *priv = c->priv;
1792         int err, tc, max_nch = priv->profile->max_nch(priv->mdev);
1793
1794         for (tc = 0; tc < params->num_tc; tc++) {
1795                 int txq_ix = c->ix + tc * max_nch;
1796
1797                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1798                                        params, &cparam->sq, &c->sq[tc], tc);
1799                 if (err)
1800                         goto err_close_sqs;
1801         }
1802
1803         return 0;
1804
1805 err_close_sqs:
1806         for (tc--; tc >= 0; tc--)
1807                 mlx5e_close_txqsq(&c->sq[tc]);
1808
1809         return err;
1810 }
1811
1812 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1813 {
1814         int tc;
1815
1816         for (tc = 0; tc < c->num_tc; tc++)
1817                 mlx5e_close_txqsq(&c->sq[tc]);
1818 }
1819
1820 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1821                                 struct mlx5e_txqsq *sq, u32 rate)
1822 {
1823         struct mlx5e_priv *priv = netdev_priv(dev);
1824         struct mlx5_core_dev *mdev = priv->mdev;
1825         struct mlx5e_modify_sq_param msp = {0};
1826         struct mlx5_rate_limit rl = {0};
1827         u16 rl_index = 0;
1828         int err;
1829
1830         if (rate == sq->rate_limit)
1831                 /* nothing to do */
1832                 return 0;
1833
1834         if (sq->rate_limit) {
1835                 rl.rate = sq->rate_limit;
1836                 /* remove current rl index to free space to next ones */
1837                 mlx5_rl_remove_rate(mdev, &rl);
1838         }
1839
1840         sq->rate_limit = 0;
1841
1842         if (rate) {
1843                 rl.rate = rate;
1844                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1845                 if (err) {
1846                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1847                                    rate, err);
1848                         return err;
1849                 }
1850         }
1851
1852         msp.curr_state = MLX5_SQC_STATE_RDY;
1853         msp.next_state = MLX5_SQC_STATE_RDY;
1854         msp.rl_index   = rl_index;
1855         msp.rl_update  = true;
1856         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1857         if (err) {
1858                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1859                            rate, err);
1860                 /* remove the rate from the table */
1861                 if (rate)
1862                         mlx5_rl_remove_rate(mdev, &rl);
1863                 return err;
1864         }
1865
1866         sq->rate_limit = rate;
1867         return 0;
1868 }
1869
1870 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1871 {
1872         struct mlx5e_priv *priv = netdev_priv(dev);
1873         struct mlx5_core_dev *mdev = priv->mdev;
1874         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1875         int err = 0;
1876
1877         if (!mlx5_rl_is_supported(mdev)) {
1878                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1879                 return -EINVAL;
1880         }
1881
1882         /* rate is given in Mb/sec, HW config is in Kb/sec */
1883         rate = rate << 10;
1884
1885         /* Check whether rate in valid range, 0 is always valid */
1886         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1887                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1888                 return -ERANGE;
1889         }
1890
1891         mutex_lock(&priv->state_lock);
1892         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1893                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1894         if (!err)
1895                 priv->tx_rates[index] = rate;
1896         mutex_unlock(&priv->state_lock);
1897
1898         return err;
1899 }
1900
1901 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1902                               struct mlx5e_params *params,
1903                               struct mlx5e_channel_param *cparam,
1904                               struct mlx5e_channel **cp)
1905 {
1906         struct net_dim_cq_moder icocq_moder = {0, 0};
1907         struct net_device *netdev = priv->netdev;
1908         int cpu = mlx5e_get_cpu(priv, ix);
1909         struct mlx5e_channel *c;
1910         unsigned int irq;
1911         int err;
1912         int eqn;
1913
1914         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1915         if (!c)
1916                 return -ENOMEM;
1917
1918         c->priv     = priv;
1919         c->mdev     = priv->mdev;
1920         c->tstamp   = &priv->tstamp;
1921         c->ix       = ix;
1922         c->cpu      = cpu;
1923         c->pdev     = &priv->mdev->pdev->dev;
1924         c->netdev   = priv->netdev;
1925         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1926         c->num_tc   = params->num_tc;
1927         c->xdp      = !!params->xdp_prog;
1928         c->stats    = &priv->channel_stats[ix].ch;
1929
1930         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1931         c->irq_desc = irq_to_desc(irq);
1932
1933         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1934
1935         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1936         if (err)
1937                 goto err_napi_del;
1938
1939         err = mlx5e_open_tx_cqs(c, params, cparam);
1940         if (err)
1941                 goto err_close_icosq_cq;
1942
1943         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1944         if (err)
1945                 goto err_close_tx_cqs;
1946
1947         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1948         if (err)
1949                 goto err_close_xdp_tx_cqs;
1950
1951         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1952         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1953                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1954         if (err)
1955                 goto err_close_rx_cq;
1956
1957         napi_enable(&c->napi);
1958
1959         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1960         if (err)
1961                 goto err_disable_napi;
1962
1963         err = mlx5e_open_sqs(c, params, cparam);
1964         if (err)
1965                 goto err_close_icosq;
1966
1967         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1968         if (err)
1969                 goto err_close_sqs;
1970
1971         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1972         if (err)
1973                 goto err_close_xdp_sq;
1974
1975         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1976         if (err)
1977                 goto err_close_rq;
1978
1979         *cp = c;
1980
1981         return 0;
1982
1983 err_close_rq:
1984         mlx5e_close_rq(&c->rq);
1985
1986 err_close_xdp_sq:
1987         if (c->xdp)
1988                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1989
1990 err_close_sqs:
1991         mlx5e_close_sqs(c);
1992
1993 err_close_icosq:
1994         mlx5e_close_icosq(&c->icosq);
1995
1996 err_disable_napi:
1997         napi_disable(&c->napi);
1998         if (c->xdp)
1999                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2000
2001 err_close_rx_cq:
2002         mlx5e_close_cq(&c->rq.cq);
2003
2004 err_close_xdp_tx_cqs:
2005         mlx5e_close_cq(&c->xdpsq.cq);
2006
2007 err_close_tx_cqs:
2008         mlx5e_close_tx_cqs(c);
2009
2010 err_close_icosq_cq:
2011         mlx5e_close_cq(&c->icosq.cq);
2012
2013 err_napi_del:
2014         netif_napi_del(&c->napi);
2015         kvfree(c);
2016
2017         return err;
2018 }
2019
2020 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2021 {
2022         int tc;
2023
2024         for (tc = 0; tc < c->num_tc; tc++)
2025                 mlx5e_activate_txqsq(&c->sq[tc]);
2026         mlx5e_activate_rq(&c->rq);
2027         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
2028 }
2029
2030 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2031 {
2032         int tc;
2033
2034         mlx5e_deactivate_rq(&c->rq);
2035         for (tc = 0; tc < c->num_tc; tc++)
2036                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2037 }
2038
2039 static void mlx5e_close_channel(struct mlx5e_channel *c)
2040 {
2041         mlx5e_close_xdpsq(&c->xdpsq);
2042         mlx5e_close_rq(&c->rq);
2043         if (c->xdp)
2044                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2045         mlx5e_close_sqs(c);
2046         mlx5e_close_icosq(&c->icosq);
2047         napi_disable(&c->napi);
2048         if (c->xdp)
2049                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2050         mlx5e_close_cq(&c->rq.cq);
2051         mlx5e_close_cq(&c->xdpsq.cq);
2052         mlx5e_close_tx_cqs(c);
2053         mlx5e_close_cq(&c->icosq.cq);
2054         netif_napi_del(&c->napi);
2055
2056         kvfree(c);
2057 }
2058
2059 #define DEFAULT_FRAG_SIZE (2048)
2060
2061 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2062                                       struct mlx5e_params *params,
2063                                       struct mlx5e_rq_frags_info *info)
2064 {
2065         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2066         int frag_size_max = DEFAULT_FRAG_SIZE;
2067         u32 buf_size = 0;
2068         int i;
2069
2070 #ifdef CONFIG_MLX5_EN_IPSEC
2071         if (MLX5_IPSEC_DEV(mdev))
2072                 byte_count += MLX5E_METADATA_ETHER_LEN;
2073 #endif
2074
2075         if (mlx5e_rx_is_linear_skb(mdev, params)) {
2076                 int frag_stride;
2077
2078                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2079                 frag_stride = roundup_pow_of_two(frag_stride);
2080
2081                 info->arr[0].frag_size = byte_count;
2082                 info->arr[0].frag_stride = frag_stride;
2083                 info->num_frags = 1;
2084                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2085                 goto out;
2086         }
2087
2088         if (byte_count > PAGE_SIZE +
2089             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2090                 frag_size_max = PAGE_SIZE;
2091
2092         i = 0;
2093         while (buf_size < byte_count) {
2094                 int frag_size = byte_count - buf_size;
2095
2096                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2097                         frag_size = min(frag_size, frag_size_max);
2098
2099                 info->arr[i].frag_size = frag_size;
2100                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2101
2102                 buf_size += frag_size;
2103                 i++;
2104         }
2105         info->num_frags = i;
2106         /* number of different wqes sharing a page */
2107         info->wqe_bulk = 1 + (info->num_frags % 2);
2108
2109 out:
2110         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2111         info->log_num_frags = order_base_2(info->num_frags);
2112 }
2113
2114 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2115 {
2116         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2117
2118         switch (wq_type) {
2119         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2120                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2121                 break;
2122         default: /* MLX5_WQ_TYPE_CYCLIC */
2123                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2124         }
2125
2126         return order_base_2(sz);
2127 }
2128
2129 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2130                                  struct mlx5e_params *params,
2131                                  struct mlx5e_rq_param *param)
2132 {
2133         struct mlx5_core_dev *mdev = priv->mdev;
2134         void *rqc = param->rqc;
2135         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2136         int ndsegs = 1;
2137
2138         switch (params->rq_wq_type) {
2139         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2140                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2141                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2142                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2143                 MLX5_SET(wq, wq, log_wqe_stride_size,
2144                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2145                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2146                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2147                 break;
2148         default: /* MLX5_WQ_TYPE_CYCLIC */
2149                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2150                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2151                 ndsegs = param->frags_info.num_frags;
2152         }
2153
2154         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2155         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2156         MLX5_SET(wq, wq, log_wq_stride,
2157                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2158         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2159         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2160         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2161         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2162
2163         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2164 }
2165
2166 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2167                                       struct mlx5e_rq_param *param)
2168 {
2169         struct mlx5_core_dev *mdev = priv->mdev;
2170         void *rqc = param->rqc;
2171         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2172
2173         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2174         MLX5_SET(wq, wq, log_wq_stride,
2175                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2176         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2177
2178         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2179 }
2180
2181 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2182                                         struct mlx5e_sq_param *param)
2183 {
2184         void *sqc = param->sqc;
2185         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2186
2187         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2188         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2189
2190         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2191 }
2192
2193 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2194                                  struct mlx5e_params *params,
2195                                  struct mlx5e_sq_param *param)
2196 {
2197         void *sqc = param->sqc;
2198         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2199
2200         mlx5e_build_sq_param_common(priv, param);
2201         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2202         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2203 }
2204
2205 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2206                                         struct mlx5e_cq_param *param)
2207 {
2208         void *cqc = param->cqc;
2209
2210         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2211 }
2212
2213 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2214                                     struct mlx5e_params *params,
2215                                     struct mlx5e_cq_param *param)
2216 {
2217         struct mlx5_core_dev *mdev = priv->mdev;
2218         void *cqc = param->cqc;
2219         u8 log_cq_size;
2220
2221         switch (params->rq_wq_type) {
2222         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2223                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2224                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2225                 break;
2226         default: /* MLX5_WQ_TYPE_CYCLIC */
2227                 log_cq_size = params->log_rq_mtu_frames;
2228         }
2229
2230         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2231         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2232                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2233                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2234         }
2235
2236         mlx5e_build_common_cq_param(priv, param);
2237         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2238 }
2239
2240 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2241                                     struct mlx5e_params *params,
2242                                     struct mlx5e_cq_param *param)
2243 {
2244         void *cqc = param->cqc;
2245
2246         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2247
2248         mlx5e_build_common_cq_param(priv, param);
2249         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2250 }
2251
2252 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2253                                      u8 log_wq_size,
2254                                      struct mlx5e_cq_param *param)
2255 {
2256         void *cqc = param->cqc;
2257
2258         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2259
2260         mlx5e_build_common_cq_param(priv, param);
2261
2262         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2263 }
2264
2265 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2266                                     u8 log_wq_size,
2267                                     struct mlx5e_sq_param *param)
2268 {
2269         void *sqc = param->sqc;
2270         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2271
2272         mlx5e_build_sq_param_common(priv, param);
2273
2274         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2275         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2276 }
2277
2278 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2279                                     struct mlx5e_params *params,
2280                                     struct mlx5e_sq_param *param)
2281 {
2282         void *sqc = param->sqc;
2283         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2284
2285         mlx5e_build_sq_param_common(priv, param);
2286         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2287 }
2288
2289 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2290                                       struct mlx5e_params *params,
2291                                       struct mlx5e_channel_param *cparam)
2292 {
2293         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2294
2295         mlx5e_build_rq_param(priv, params, &cparam->rq);
2296         mlx5e_build_sq_param(priv, params, &cparam->sq);
2297         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2298         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2299         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2300         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2301         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2302 }
2303
2304 int mlx5e_open_channels(struct mlx5e_priv *priv,
2305                         struct mlx5e_channels *chs)
2306 {
2307         struct mlx5e_channel_param *cparam;
2308         int err = -ENOMEM;
2309         int i;
2310
2311         chs->num = chs->params.num_channels;
2312
2313         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2314         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2315         if (!chs->c || !cparam)
2316                 goto err_free;
2317
2318         mlx5e_build_channel_param(priv, &chs->params, cparam);
2319         for (i = 0; i < chs->num; i++) {
2320                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2321                 if (err)
2322                         goto err_close_channels;
2323         }
2324
2325         kvfree(cparam);
2326         return 0;
2327
2328 err_close_channels:
2329         for (i--; i >= 0; i--)
2330                 mlx5e_close_channel(chs->c[i]);
2331
2332 err_free:
2333         kfree(chs->c);
2334         kvfree(cparam);
2335         chs->num = 0;
2336         return err;
2337 }
2338
2339 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2340 {
2341         int i;
2342
2343         for (i = 0; i < chs->num; i++)
2344                 mlx5e_activate_channel(chs->c[i]);
2345 }
2346
2347 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2348 {
2349         int err = 0;
2350         int i;
2351
2352         for (i = 0; i < chs->num; i++)
2353                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2354                                                   err ? 0 : 20000);
2355
2356         return err ? -ETIMEDOUT : 0;
2357 }
2358
2359 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2360 {
2361         int i;
2362
2363         for (i = 0; i < chs->num; i++)
2364                 mlx5e_deactivate_channel(chs->c[i]);
2365 }
2366
2367 void mlx5e_close_channels(struct mlx5e_channels *chs)
2368 {
2369         int i;
2370
2371         for (i = 0; i < chs->num; i++)
2372                 mlx5e_close_channel(chs->c[i]);
2373
2374         kfree(chs->c);
2375         chs->num = 0;
2376 }
2377
2378 static int
2379 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2380 {
2381         struct mlx5_core_dev *mdev = priv->mdev;
2382         void *rqtc;
2383         int inlen;
2384         int err;
2385         u32 *in;
2386         int i;
2387
2388         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2389         in = kvzalloc(inlen, GFP_KERNEL);
2390         if (!in)
2391                 return -ENOMEM;
2392
2393         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2394
2395         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2396         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2397
2398         for (i = 0; i < sz; i++)
2399                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2400
2401         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2402         if (!err)
2403                 rqt->enabled = true;
2404
2405         kvfree(in);
2406         return err;
2407 }
2408
2409 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2410 {
2411         rqt->enabled = false;
2412         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2413 }
2414
2415 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2416 {
2417         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2418         int err;
2419
2420         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2421         if (err)
2422                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2423         return err;
2424 }
2425
2426 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2427 {
2428         struct mlx5e_rqt *rqt;
2429         int err;
2430         int ix;
2431
2432         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2433                 rqt = &priv->direct_tir[ix].rqt;
2434                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2435                 if (err)
2436                         goto err_destroy_rqts;
2437         }
2438
2439         return 0;
2440
2441 err_destroy_rqts:
2442         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2443         for (ix--; ix >= 0; ix--)
2444                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2445
2446         return err;
2447 }
2448
2449 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2450 {
2451         int i;
2452
2453         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2454                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2455 }
2456
2457 static int mlx5e_rx_hash_fn(int hfunc)
2458 {
2459         return (hfunc == ETH_RSS_HASH_TOP) ?
2460                MLX5_RX_HASH_FN_TOEPLITZ :
2461                MLX5_RX_HASH_FN_INVERTED_XOR8;
2462 }
2463
2464 int mlx5e_bits_invert(unsigned long a, int size)
2465 {
2466         int inv = 0;
2467         int i;
2468
2469         for (i = 0; i < size; i++)
2470                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2471
2472         return inv;
2473 }
2474
2475 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2476                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2477 {
2478         int i;
2479
2480         for (i = 0; i < sz; i++) {
2481                 u32 rqn;
2482
2483                 if (rrp.is_rss) {
2484                         int ix = i;
2485
2486                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2487                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2488
2489                         ix = priv->channels.params.indirection_rqt[ix];
2490                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2491                 } else {
2492                         rqn = rrp.rqn;
2493                 }
2494                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2495         }
2496 }
2497
2498 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2499                        struct mlx5e_redirect_rqt_param rrp)
2500 {
2501         struct mlx5_core_dev *mdev = priv->mdev;
2502         void *rqtc;
2503         int inlen;
2504         u32 *in;
2505         int err;
2506
2507         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2508         in = kvzalloc(inlen, GFP_KERNEL);
2509         if (!in)
2510                 return -ENOMEM;
2511
2512         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2513
2514         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2515         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2516         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2517         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2518
2519         kvfree(in);
2520         return err;
2521 }
2522
2523 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2524                                 struct mlx5e_redirect_rqt_param rrp)
2525 {
2526         if (!rrp.is_rss)
2527                 return rrp.rqn;
2528
2529         if (ix >= rrp.rss.channels->num)
2530                 return priv->drop_rq.rqn;
2531
2532         return rrp.rss.channels->c[ix]->rq.rqn;
2533 }
2534
2535 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2536                                 struct mlx5e_redirect_rqt_param rrp)
2537 {
2538         u32 rqtn;
2539         int ix;
2540
2541         if (priv->indir_rqt.enabled) {
2542                 /* RSS RQ table */
2543                 rqtn = priv->indir_rqt.rqtn;
2544                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2545         }
2546
2547         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2548                 struct mlx5e_redirect_rqt_param direct_rrp = {
2549                         .is_rss = false,
2550                         {
2551                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2552                         },
2553                 };
2554
2555                 /* Direct RQ Tables */
2556                 if (!priv->direct_tir[ix].rqt.enabled)
2557                         continue;
2558
2559                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2560                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2561         }
2562 }
2563
2564 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2565                                             struct mlx5e_channels *chs)
2566 {
2567         struct mlx5e_redirect_rqt_param rrp = {
2568                 .is_rss        = true,
2569                 {
2570                         .rss = {
2571                                 .channels  = chs,
2572                                 .hfunc     = chs->params.rss_hfunc,
2573                         }
2574                 },
2575         };
2576
2577         mlx5e_redirect_rqts(priv, rrp);
2578 }
2579
2580 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2581 {
2582         struct mlx5e_redirect_rqt_param drop_rrp = {
2583                 .is_rss = false,
2584                 {
2585                         .rqn = priv->drop_rq.rqn,
2586                 },
2587         };
2588
2589         mlx5e_redirect_rqts(priv, drop_rrp);
2590 }
2591
2592 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2593 {
2594         if (!params->lro_en)
2595                 return;
2596
2597 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2598
2599         MLX5_SET(tirc, tirc, lro_enable_mask,
2600                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2601                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2602         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2603                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2604         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2605 }
2606
2607 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2608                                     enum mlx5e_traffic_types tt,
2609                                     void *tirc, bool inner)
2610 {
2611         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2612                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2613
2614 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2615                                  MLX5_HASH_FIELD_SEL_DST_IP)
2616
2617 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2618                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2619                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2620                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2621
2622 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2623                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2624                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2625
2626         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2627         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2628                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2629                                              rx_hash_toeplitz_key);
2630                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2631                                                rx_hash_toeplitz_key);
2632
2633                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2634                 memcpy(rss_key, params->toeplitz_hash_key, len);
2635         }
2636
2637         switch (tt) {
2638         case MLX5E_TT_IPV4_TCP:
2639                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2640                          MLX5_L3_PROT_TYPE_IPV4);
2641                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2642                          MLX5_L4_PROT_TYPE_TCP);
2643                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2644                          MLX5_HASH_IP_L4PORTS);
2645                 break;
2646
2647         case MLX5E_TT_IPV6_TCP:
2648                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2649                          MLX5_L3_PROT_TYPE_IPV6);
2650                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2651                          MLX5_L4_PROT_TYPE_TCP);
2652                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2653                          MLX5_HASH_IP_L4PORTS);
2654                 break;
2655
2656         case MLX5E_TT_IPV4_UDP:
2657                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2658                          MLX5_L3_PROT_TYPE_IPV4);
2659                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2660                          MLX5_L4_PROT_TYPE_UDP);
2661                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2662                          MLX5_HASH_IP_L4PORTS);
2663                 break;
2664
2665         case MLX5E_TT_IPV6_UDP:
2666                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2667                          MLX5_L3_PROT_TYPE_IPV6);
2668                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2669                          MLX5_L4_PROT_TYPE_UDP);
2670                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2671                          MLX5_HASH_IP_L4PORTS);
2672                 break;
2673
2674         case MLX5E_TT_IPV4_IPSEC_AH:
2675                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2676                          MLX5_L3_PROT_TYPE_IPV4);
2677                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2678                          MLX5_HASH_IP_IPSEC_SPI);
2679                 break;
2680
2681         case MLX5E_TT_IPV6_IPSEC_AH:
2682                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2683                          MLX5_L3_PROT_TYPE_IPV6);
2684                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2685                          MLX5_HASH_IP_IPSEC_SPI);
2686                 break;
2687
2688         case MLX5E_TT_IPV4_IPSEC_ESP:
2689                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2690                          MLX5_L3_PROT_TYPE_IPV4);
2691                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2692                          MLX5_HASH_IP_IPSEC_SPI);
2693                 break;
2694
2695         case MLX5E_TT_IPV6_IPSEC_ESP:
2696                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2697                          MLX5_L3_PROT_TYPE_IPV6);
2698                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2699                          MLX5_HASH_IP_IPSEC_SPI);
2700                 break;
2701
2702         case MLX5E_TT_IPV4:
2703                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2704                          MLX5_L3_PROT_TYPE_IPV4);
2705                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2706                          MLX5_HASH_IP);
2707                 break;
2708
2709         case MLX5E_TT_IPV6:
2710                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2711                          MLX5_L3_PROT_TYPE_IPV6);
2712                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2713                          MLX5_HASH_IP);
2714                 break;
2715         default:
2716                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2717         }
2718 }
2719
2720 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2721 {
2722         struct mlx5_core_dev *mdev = priv->mdev;
2723
2724         void *in;
2725         void *tirc;
2726         int inlen;
2727         int err;
2728         int tt;
2729         int ix;
2730
2731         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2732         in = kvzalloc(inlen, GFP_KERNEL);
2733         if (!in)
2734                 return -ENOMEM;
2735
2736         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2737         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2738
2739         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2740
2741         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2742                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2743                                            inlen);
2744                 if (err)
2745                         goto free_in;
2746         }
2747
2748         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2749                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2750                                            in, inlen);
2751                 if (err)
2752                         goto free_in;
2753         }
2754
2755 free_in:
2756         kvfree(in);
2757
2758         return err;
2759 }
2760
2761 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2762                                             enum mlx5e_traffic_types tt,
2763                                             u32 *tirc)
2764 {
2765         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2766
2767         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2768
2769         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2770         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2771         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2772
2773         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2774 }
2775
2776 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2777                          struct mlx5e_params *params, u16 mtu)
2778 {
2779         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2780         int err;
2781
2782         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2783         if (err)
2784                 return err;
2785
2786         /* Update vport context MTU */
2787         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2788         return 0;
2789 }
2790
2791 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2792                             struct mlx5e_params *params, u16 *mtu)
2793 {
2794         u16 hw_mtu = 0;
2795         int err;
2796
2797         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2798         if (err || !hw_mtu) /* fallback to port oper mtu */
2799                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2800
2801         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2802 }
2803
2804 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2805 {
2806         struct mlx5e_params *params = &priv->channels.params;
2807         struct net_device *netdev = priv->netdev;
2808         struct mlx5_core_dev *mdev = priv->mdev;
2809         u16 mtu;
2810         int err;
2811
2812         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2813         if (err)
2814                 return err;
2815
2816         mlx5e_query_mtu(mdev, params, &mtu);
2817         if (mtu != params->sw_mtu)
2818                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2819                             __func__, mtu, params->sw_mtu);
2820
2821         params->sw_mtu = mtu;
2822         return 0;
2823 }
2824
2825 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2826 {
2827         struct mlx5e_priv *priv = netdev_priv(netdev);
2828         int nch = priv->channels.params.num_channels;
2829         int ntc = priv->channels.params.num_tc;
2830         int tc;
2831
2832         netdev_reset_tc(netdev);
2833
2834         if (ntc == 1)
2835                 return;
2836
2837         netdev_set_num_tc(netdev, ntc);
2838
2839         /* Map netdev TCs to offset 0
2840          * We have our own UP to TXQ mapping for QoS
2841          */
2842         for (tc = 0; tc < ntc; tc++)
2843                 netdev_set_tc_queue(netdev, tc, nch, 0);
2844 }
2845
2846 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2847 {
2848         int max_nch = priv->profile->max_nch(priv->mdev);
2849         int i, tc;
2850
2851         for (i = 0; i < max_nch; i++)
2852                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2853                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2854 }
2855
2856 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2857 {
2858         struct mlx5e_channel *c;
2859         struct mlx5e_txqsq *sq;
2860         int i, tc;
2861
2862         for (i = 0; i < priv->channels.num; i++) {
2863                 c = priv->channels.c[i];
2864                 for (tc = 0; tc < c->num_tc; tc++) {
2865                         sq = &c->sq[tc];
2866                         priv->txq2sq[sq->txq_ix] = sq;
2867                 }
2868         }
2869 }
2870
2871 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2872 {
2873         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2874         struct net_device *netdev = priv->netdev;
2875
2876         mlx5e_netdev_set_tcs(netdev);
2877         netif_set_real_num_tx_queues(netdev, num_txqs);
2878         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2879
2880         mlx5e_build_tx2sq_maps(priv);
2881         mlx5e_activate_channels(&priv->channels);
2882         netif_tx_start_all_queues(priv->netdev);
2883
2884         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2885                 mlx5e_add_sqs_fwd_rules(priv);
2886
2887         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2888         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2889 }
2890
2891 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2892 {
2893         mlx5e_redirect_rqts_to_drop(priv);
2894
2895         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2896                 mlx5e_remove_sqs_fwd_rules(priv);
2897
2898         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2899          * polling for inactive tx queues.
2900          */
2901         netif_tx_stop_all_queues(priv->netdev);
2902         netif_tx_disable(priv->netdev);
2903         mlx5e_deactivate_channels(&priv->channels);
2904 }
2905
2906 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2907                                 struct mlx5e_channels *new_chs,
2908                                 mlx5e_fp_hw_modify hw_modify)
2909 {
2910         struct net_device *netdev = priv->netdev;
2911         int new_num_txqs;
2912         int carrier_ok;
2913         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2914
2915         carrier_ok = netif_carrier_ok(netdev);
2916         netif_carrier_off(netdev);
2917
2918         if (new_num_txqs < netdev->real_num_tx_queues)
2919                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2920
2921         mlx5e_deactivate_priv_channels(priv);
2922         mlx5e_close_channels(&priv->channels);
2923
2924         priv->channels = *new_chs;
2925
2926         /* New channels are ready to roll, modify HW settings if needed */
2927         if (hw_modify)
2928                 hw_modify(priv);
2929
2930         mlx5e_refresh_tirs(priv, false);
2931         mlx5e_activate_priv_channels(priv);
2932
2933         /* return carrier back if needed */
2934         if (carrier_ok)
2935                 netif_carrier_on(netdev);
2936 }
2937
2938 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2939 {
2940         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2941         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2942 }
2943
2944 int mlx5e_open_locked(struct net_device *netdev)
2945 {
2946         struct mlx5e_priv *priv = netdev_priv(netdev);
2947         int err;
2948
2949         set_bit(MLX5E_STATE_OPENED, &priv->state);
2950
2951         err = mlx5e_open_channels(priv, &priv->channels);
2952         if (err)
2953                 goto err_clear_state_opened_flag;
2954
2955         mlx5e_refresh_tirs(priv, false);
2956         mlx5e_activate_priv_channels(priv);
2957         if (priv->profile->update_carrier)
2958                 priv->profile->update_carrier(priv);
2959
2960         if (priv->profile->update_stats)
2961                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2962
2963         return 0;
2964
2965 err_clear_state_opened_flag:
2966         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2967         return err;
2968 }
2969
2970 int mlx5e_open(struct net_device *netdev)
2971 {
2972         struct mlx5e_priv *priv = netdev_priv(netdev);
2973         int err;
2974
2975         mutex_lock(&priv->state_lock);
2976         err = mlx5e_open_locked(netdev);
2977         if (!err)
2978                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2979         mutex_unlock(&priv->state_lock);
2980
2981         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
2982                 udp_tunnel_get_rx_info(netdev);
2983
2984         return err;
2985 }
2986
2987 int mlx5e_close_locked(struct net_device *netdev)
2988 {
2989         struct mlx5e_priv *priv = netdev_priv(netdev);
2990
2991         /* May already be CLOSED in case a previous configuration operation
2992          * (e.g RX/TX queue size change) that involves close&open failed.
2993          */
2994         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2995                 return 0;
2996
2997         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2998
2999         netif_carrier_off(priv->netdev);
3000         mlx5e_deactivate_priv_channels(priv);
3001         mlx5e_close_channels(&priv->channels);
3002
3003         return 0;
3004 }
3005
3006 int mlx5e_close(struct net_device *netdev)
3007 {
3008         struct mlx5e_priv *priv = netdev_priv(netdev);
3009         int err;
3010
3011         if (!netif_device_present(netdev))
3012                 return -ENODEV;
3013
3014         mutex_lock(&priv->state_lock);
3015         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3016         err = mlx5e_close_locked(netdev);
3017         mutex_unlock(&priv->state_lock);
3018
3019         return err;
3020 }
3021
3022 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3023                                struct mlx5e_rq *rq,
3024                                struct mlx5e_rq_param *param)
3025 {
3026         void *rqc = param->rqc;
3027         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3028         int err;
3029
3030         param->wq.db_numa_node = param->wq.buf_numa_node;
3031
3032         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3033                                  &rq->wq_ctrl);
3034         if (err)
3035                 return err;
3036
3037         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3038         xdp_rxq_info_unused(&rq->xdp_rxq);
3039
3040         rq->mdev = mdev;
3041
3042         return 0;
3043 }
3044
3045 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3046                                struct mlx5e_cq *cq,
3047                                struct mlx5e_cq_param *param)
3048 {
3049         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3050         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
3051
3052         return mlx5e_alloc_cq_common(mdev, param, cq);
3053 }
3054
3055 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3056                        struct mlx5e_rq *drop_rq)
3057 {
3058         struct mlx5_core_dev *mdev = priv->mdev;
3059         struct mlx5e_cq_param cq_param = {};
3060         struct mlx5e_rq_param rq_param = {};
3061         struct mlx5e_cq *cq = &drop_rq->cq;
3062         int err;
3063
3064         mlx5e_build_drop_rq_param(priv, &rq_param);
3065
3066         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3067         if (err)
3068                 return err;
3069
3070         err = mlx5e_create_cq(cq, &cq_param);
3071         if (err)
3072                 goto err_free_cq;
3073
3074         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3075         if (err)
3076                 goto err_destroy_cq;
3077
3078         err = mlx5e_create_rq(drop_rq, &rq_param);
3079         if (err)
3080                 goto err_free_rq;
3081
3082         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);