drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include "eswitch.h"
  39 #include "en.h"
  40 #include "en_tc.h"
  41 #include "en_rep.h"
  42 #include "en_accel/ipsec.h"
  43 #include "en_accel/ipsec_rxtx.h"
  44 #include "accel/ipsec.h"
  45 #include "vxlan.h"
  46
  47 struct mlx5e_rq_param {
  48         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  49         struct mlx5_wq_param    wq;
  50 };
  51
  52 struct mlx5e_sq_param {
  53         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  54         struct mlx5_wq_param       wq;
  55 };
  56
  57 struct mlx5e_cq_param {
  58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  59         struct mlx5_wq_param       wq;
  60         u16                        eq_ix;
  61         u8                         cq_period_mode;
  62 };
  63
  64 struct mlx5e_channel_param {
  65         struct mlx5e_rq_param      rq;
  66         struct mlx5e_sq_param      sq;
  67         struct mlx5e_sq_param      xdp_sq;
  68         struct mlx5e_sq_param      icosq;
  69         struct mlx5e_cq_param      rx_cq;
  70         struct mlx5e_cq_param      tx_cq;
  71         struct mlx5e_cq_param      icosq_cq;
  72 };
  73
  74 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  75 {
  76         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  77                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  78                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  79         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  80         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  81
  82         if (!striding_rq_umr)
  83                 return false;
  84         if (!inline_umr) {
  85                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  86                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  87                 return false;
  88         }
  89         return true;
  90 }
  91
  92 static u32 mlx5e_mpwqe_get_linear_frag_sz(struct mlx5e_params *params)
  93 {
  94         if (!params->xdp_prog) {
  95                 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
  96                 u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN;
  97
  98                 return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu);
  99         }
 100
 101         return PAGE_SIZE;
 102 }
 103
 104 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 105 {
 106         u32 linear_frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
 107
 108         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 109 }
 110
 111 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 112                                          struct mlx5e_params *params)
 113 {
 114         u32 frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
 115         s8 signed_log_num_strides_param;
 116         u8 log_num_strides;
 117
 118         if (params->lro_en || frag_sz > PAGE_SIZE)
 119                 return false;
 120
 121         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 122                 return true;
 123
 124         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 125         signed_log_num_strides_param =
 126                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 127
 128         return signed_log_num_strides_param >= 0;
 129 }
 130
 131 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 132 {
 133         if (params->log_rq_mtu_frames <
 134             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 135                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 136
 137         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 138 }
 139
 140 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 141                                           struct mlx5e_params *params)
 142 {
 143         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 144                 return order_base_2(mlx5e_mpwqe_get_linear_frag_sz(params));
 145
 146         return MLX5E_MPWQE_STRIDE_SZ(mdev,
 147                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 148 }
 149
 150 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 151                                           struct mlx5e_params *params)
 152 {
 153         return MLX5_MPWRQ_LOG_WQE_SZ -
 154                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 155 }
 156
 157 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 158                                  struct mlx5e_params *params)
 159 {
 160         u16 linear_rq_headroom = params->xdp_prog ?
 161                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 162
 163         linear_rq_headroom += NET_IP_ALIGN;
 164
 165         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)
 166                 return linear_rq_headroom;
 167
 168         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 169                 return linear_rq_headroom;
 170
 171         return 0;
 172 }
 173
 174 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 175                                struct mlx5e_params *params)
 176 {
 177         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 178         params->log_rq_mtu_frames = is_kdump_kernel() ?
 179                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 180                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 181         switch (params->rq_wq_type) {
 182         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 183                 break;
 184         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 185                 /* Extra room needed for build_skb */
 186                 params->lro_wqe_sz -= mlx5e_get_rq_headroom(mdev, params) +
 187                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 188         }
 189
 190         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 191                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 192                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 193                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 194                        BIT(params->log_rq_mtu_frames),
 195                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 196                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 197 }
 198
 199 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 200                                 struct mlx5e_params *params)
 201 {
 202         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 203                 !params->xdp_prog && !MLX5_IPSEC_DEV(mdev);
 204 }
 205
 206 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 207 {
 208         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 209                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 210                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 211                 MLX5_WQ_TYPE_LINKED_LIST;
 212 }
 213
 214 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 215 {
 216         struct mlx5_core_dev *mdev = priv->mdev;
 217         u8 port_state;
 218
 219         port_state = mlx5_query_vport_state(mdev,
 220                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
 221                                             0);
 222
 223         if (port_state == VPORT_STATE_UP) {
 224                 netdev_info(priv->netdev, "Link up\n");
 225                 netif_carrier_on(priv->netdev);
 226         } else {
 227                 netdev_info(priv->netdev, "Link down\n");
 228                 netif_carrier_off(priv->netdev);
 229         }
 230 }
 231
 232 static void mlx5e_update_carrier_work(struct work_struct *work)
 233 {
 234         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 235                                                update_carrier_work);
 236
 237         mutex_lock(&priv->state_lock);
 238         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 239                 if (priv->profile->update_carrier)
 240                         priv->profile->update_carrier(priv);
 241         mutex_unlock(&priv->state_lock);
 242 }
 243
 244 void mlx5e_update_stats(struct mlx5e_priv *priv)
 245 {
 246         int i;
 247
 248         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 249                 if (mlx5e_stats_grps[i].update_stats)
 250                         mlx5e_stats_grps[i].update_stats(priv);
 251 }
 252
 253 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 254 {
 255         int i;
 256
 257         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 258                 if (mlx5e_stats_grps[i].update_stats_mask &
 259                     MLX5E_NDO_UPDATE_STATS)
 260                         mlx5e_stats_grps[i].update_stats(priv);
 261 }
 262
 263 void mlx5e_update_stats_work(struct work_struct *work)
 264 {
 265         struct delayed_work *dwork = to_delayed_work(work);
 266         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 267                                                update_stats_work);
 268         mutex_lock(&priv->state_lock);
 269         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 270                 priv->profile->update_stats(priv);
 271                 queue_delayed_work(priv->wq, dwork,
 272                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 273         }
 274         mutex_unlock(&priv->state_lock);
 275 }
 276
 277 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 278                               enum mlx5_dev_event event, unsigned long param)
 279 {
 280         struct mlx5e_priv *priv = vpriv;
 281
 282         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 283                 return;
 284
 285         switch (event) {
 286         case MLX5_DEV_EVENT_PORT_UP:
 287         case MLX5_DEV_EVENT_PORT_DOWN:
 288                 queue_work(priv->wq, &priv->update_carrier_work);
 289                 break;
 290         default:
 291                 break;
 292         }
 293 }
 294
 295 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 296 {
 297         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 298 }
 299
 300 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 301 {
 302         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 303         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 304 }
 305
 306 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 307                                        struct mlx5e_icosq *sq,
 308                                        struct mlx5e_umr_wqe *wqe,
 309                                        u16 ix)
 310 {
 311         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 312         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 313         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 314         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 315
 316         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 317                                       ds_cnt);
 318         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 319         cseg->imm       = rq->mkey_be;
 320
 321         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 322         ucseg->xlt_octowords =
 323                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 324         ucseg->bsf_octowords =
 325                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 326         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 327 }
 328
 329 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 330                                      struct mlx5e_channel *c)
 331 {
 332         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 333         int i;
 334
 335         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 336                                       GFP_KERNEL, cpu_to_node(c->cpu));
 337         if (!rq->mpwqe.info)
 338                 return -ENOMEM;
 339
 340         for (i = 0; i < wq_sz; i++) {
 341                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 342
 343                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 344         }
 345
 346         return 0;
 347 }
 348
 349 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 350                                  u64 npages, u8 page_shift,
 351                                  struct mlx5_core_mkey *umr_mkey)
 352 {
 353         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 354         void *mkc;
 355         u32 *in;
 356         int err;
 357
 358         in = kvzalloc(inlen, GFP_KERNEL);
 359         if (!in)
 360                 return -ENOMEM;
 361
 362         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 363
 364         MLX5_SET(mkc, mkc, free, 1);
 365         MLX5_SET(mkc, mkc, umr_en, 1);
 366         MLX5_SET(mkc, mkc, lw, 1);
 367         MLX5_SET(mkc, mkc, lr, 1);
 368         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
 369
 370         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 371         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 372         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 373         MLX5_SET(mkc, mkc, translations_octword_size,
 374                  MLX5_MTT_OCTW(npages));
 375         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 376
 377         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 378
 379         kvfree(in);
 380         return err;
 381 }
 382
 383 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 384 {
 385         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
 386
 387         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 388 }
 389
 390 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 391                           struct mlx5e_params *params,
 392                           struct mlx5e_rq_param *rqp,
 393                           struct mlx5e_rq *rq)
 394 {
 395         struct mlx5_core_dev *mdev = c->mdev;
 396         void *rqc = rqp->rqc;
 397         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 398         u32 byte_count;
 399         int npages;
 400         int wq_sz;
 401         int err;
 402         int i;
 403
 404         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 405
 406         err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
 407                                 &rq->wq_ctrl);
 408         if (err)
 409                 return err;
 410
 411         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 412
 413         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 414
 415         rq->wq_type = params->rq_wq_type;
 416         rq->pdev    = c->pdev;
 417         rq->netdev  = c->netdev;
 418         rq->tstamp  = c->tstamp;
 419         rq->clock   = &mdev->clock;
 420         rq->channel = c;
 421         rq->ix      = c->ix;
 422         rq->mdev    = mdev;
 423         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 424
 425         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 426         if (IS_ERR(rq->xdp_prog)) {
 427                 err = PTR_ERR(rq->xdp_prog);
 428                 rq->xdp_prog = NULL;
 429                 goto err_rq_wq_destroy;
 430         }
 431
 432         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 433         if (err < 0)
 434                 goto err_rq_wq_destroy;
 435
 436         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 437         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 438
 439         switch (rq->wq_type) {
 440         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 441                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 442                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 443
 444                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 445 #ifdef CONFIG_MLX5_EN_IPSEC
 446                 if (MLX5_IPSEC_DEV(mdev)) {
 447                         err = -EINVAL;
 448                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 449                         goto err_rq_wq_destroy;
 450                 }
 451 #endif
 452                 if (!rq->handle_rx_cqe) {
 453                         err = -EINVAL;
 454                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 455                         goto err_rq_wq_destroy;
 456                 }
 457
 458                 rq->mpwqe.skb_from_cqe_mpwrq =
 459                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 460                         mlx5e_skb_from_cqe_mpwrq_linear :
 461                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 462                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 463                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 464
 465                 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 466
 467                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 468                 if (err)
 469                         goto err_rq_wq_destroy;
 470                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 471
 472                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 473                 if (err)
 474                         goto err_destroy_umr_mkey;
 475                 break;
 476         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 477                 rq->wqe.frag_info =
 478                         kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
 479                                      GFP_KERNEL, cpu_to_node(c->cpu));
 480                 if (!rq->wqe.frag_info) {
 481                         err = -ENOMEM;
 482                         goto err_rq_wq_destroy;
 483                 }
 484                 rq->post_wqes = mlx5e_post_rx_wqes;
 485                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 486
 487 #ifdef CONFIG_MLX5_EN_IPSEC
 488                 if (c->priv->ipsec)
 489                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 490                 else
 491 #endif
 492                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 493                 if (!rq->handle_rx_cqe) {
 494                         kfree(rq->wqe.frag_info);
 495                         err = -EINVAL;
 496                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 497                         goto err_rq_wq_destroy;
 498                 }
 499
 500                 byte_count = params->lro_en  ?
 501                                 params->lro_wqe_sz :
 502                                 MLX5E_SW2HW_MTU(params, params->sw_mtu);
 503 #ifdef CONFIG_MLX5_EN_IPSEC
 504                 if (MLX5_IPSEC_DEV(mdev))
 505                         byte_count += MLX5E_METADATA_ETHER_LEN;
 506 #endif
 507                 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
 508
 509                 /* calc the required page order */
 510                 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
 511                 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
 512                 rq->buff.page_order = order_base_2(npages);
 513
 514                 byte_count |= MLX5_HW_START_PADDING;
 515                 rq->mkey_be = c->mkey_be;
 516         }
 517
 518         for (i = 0; i < wq_sz; i++) {
 519                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 520
 521                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 522                         u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
 523
 524                         wqe->data.addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 525                 }
 526
 527                 wqe->data.byte_count = cpu_to_be32(byte_count);
 528                 wqe->data.lkey = rq->mkey_be;
 529         }
 530
 531         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 532
 533         switch (params->rx_cq_moderation.cq_period_mode) {
 534         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 535                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 536                 break;
 537         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 538         default:
 539                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 540         }
 541
 542         rq->page_cache.head = 0;
 543         rq->page_cache.tail = 0;
 544
 545         return 0;
 546
 547 err_destroy_umr_mkey:
 548         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 549
 550 err_rq_wq_destroy:
 551         if (rq->xdp_prog)
 552                 bpf_prog_put(rq->xdp_prog);
 553         xdp_rxq_info_unreg(&rq->xdp_rxq);
 554         mlx5_wq_destroy(&rq->wq_ctrl);
 555
 556         return err;
 557 }
 558
 559 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 560 {
 561         int i;
 562
 563         if (rq->xdp_prog)
 564                 bpf_prog_put(rq->xdp_prog);
 565
 566         xdp_rxq_info_unreg(&rq->xdp_rxq);
 567
 568         switch (rq->wq_type) {
 569         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 570                 kfree(rq->mpwqe.info);
 571                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 572                 break;
 573         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 574                 kfree(rq->wqe.frag_info);
 575         }
 576
 577         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 578              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 579                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 580
 581                 mlx5e_page_release(rq, dma_info, false);
 582         }
 583         mlx5_wq_destroy(&rq->wq_ctrl);
 584 }
 585
 586 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 587                            struct mlx5e_rq_param *param)
 588 {
 589         struct mlx5_core_dev *mdev = rq->mdev;
 590
 591         void *in;
 592         void *rqc;
 593         void *wq;
 594         int inlen;
 595         int err;
 596
 597         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 598                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 599         in = kvzalloc(inlen, GFP_KERNEL);
 600         if (!in)
 601                 return -ENOMEM;
 602
 603         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 604         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 605
 606         memcpy(rqc, param->rqc, sizeof(param->rqc));
 607
 608         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 609         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 610         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 611                                                 MLX5_ADAPTER_PAGE_SHIFT);
 612         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 613
 614         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 615                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 616
 617         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 618
 619         kvfree(in);
 620
 621         return err;
 622 }
 623
 624 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 625                                  int next_state)
 626 {
 627         struct mlx5_core_dev *mdev = rq->mdev;
 628
 629         void *in;
 630         void *rqc;
 631         int inlen;
 632         int err;
 633
 634         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 635         in = kvzalloc(inlen, GFP_KERNEL);
 636         if (!in)
 637                 return -ENOMEM;
 638
 639         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 640
 641         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 642         MLX5_SET(rqc, rqc, state, next_state);
 643
 644         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 645
 646         kvfree(in);
 647
 648         return err;
 649 }
 650
 651 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 652 {
 653         struct mlx5e_channel *c = rq->channel;
 654         struct mlx5e_priv *priv = c->priv;
 655         struct mlx5_core_dev *mdev = priv->mdev;
 656
 657         void *in;
 658         void *rqc;
 659         int inlen;
 660         int err;
 661
 662         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 663         in = kvzalloc(inlen, GFP_KERNEL);
 664         if (!in)
 665                 return -ENOMEM;
 666
 667         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 668
 669         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 670         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 671                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 672         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 673         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 674
 675         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 676
 677         kvfree(in);
 678
 679         return err;
 680 }
 681
 682 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 683 {
 684         struct mlx5e_channel *c = rq->channel;
 685         struct mlx5_core_dev *mdev = c->mdev;
 686         void *in;
 687         void *rqc;
 688         int inlen;
 689         int err;
 690
 691         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 692         in = kvzalloc(inlen, GFP_KERNEL);
 693         if (!in)
 694                 return -ENOMEM;
 695
 696         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 697
 698         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 699         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 700                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 701         MLX5_SET(rqc, rqc, vsd, vsd);
 702         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 703
 704         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 705
 706         kvfree(in);
 707
 708         return err;
 709 }
 710
 711 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 712 {
 713         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 714 }
 715
 716 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 717 {
 718         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 719         struct mlx5e_channel *c = rq->channel;
 720
 721         struct mlx5_wq_ll *wq = &rq->wq;
 722         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
 723
 724         while (time_before(jiffies, exp_time)) {
 725                 if (wq->cur_sz >= min_wqes)
 726                         return 0;
 727
 728                 msleep(20);
 729         }
 730
 731         netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 732                     rq->rqn, wq->cur_sz, min_wqes);
 733         return -ETIMEDOUT;
 734 }
 735
 736 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 737 {
 738         struct mlx5_wq_ll *wq = &rq->wq;
 739         struct mlx5e_rx_wqe *wqe;
 740         __be16 wqe_ix_be;
 741         u16 wqe_ix;
 742
 743         /* UMR WQE (if in progress) is always at wq->head */
 744         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
 745             rq->mpwqe.umr_in_progress)
 746                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 747
 748         while (!mlx5_wq_ll_is_empty(wq)) {
 749                 wqe_ix_be = *wq->tail_next;
 750                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 751                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 752                 rq->dealloc_wqe(rq, wqe_ix);
 753                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 754                                &wqe->next.next_wqe_index);
 755         }
 756
 757         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
 758                 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
 759                  * but yet to be re-posted.
 760                  */
 761                 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 762
 763                 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
 764                         rq->dealloc_wqe(rq, wqe_ix);
 765         }
 766 }
 767
 768 static int mlx5e_open_rq(struct mlx5e_channel *c,
 769                          struct mlx5e_params *params,
 770                          struct mlx5e_rq_param *param,
 771                          struct mlx5e_rq *rq)
 772 {
 773         int err;
 774
 775         err = mlx5e_alloc_rq(c, params, param, rq);
 776         if (err)
 777                 return err;
 778
 779         err = mlx5e_create_rq(rq, param);
 780         if (err)
 781                 goto err_free_rq;
 782
 783         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 784         if (err)
 785                 goto err_destroy_rq;
 786
 787         if (params->rx_dim_enabled)
 788                 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
 789
 790         return 0;
 791
 792 err_destroy_rq:
 793         mlx5e_destroy_rq(rq);
 794 err_free_rq:
 795         mlx5e_free_rq(rq);
 796
 797         return err;
 798 }
 799
 800 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 801 {
 802         struct mlx5e_icosq *sq = &rq->channel->icosq;
 803         u16 pi = sq->pc & sq->wq.sz_m1;
 804         struct mlx5e_tx_wqe *nopwqe;
 805
 806         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 807         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 808         nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
 809         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 810 }
 811
 812 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 813 {
 814         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 815         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 816 }
 817
 818 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 819 {
 820         cancel_work_sync(&rq->dim.work);
 821         mlx5e_destroy_rq(rq);
 822         mlx5e_free_rx_descs(rq);
 823         mlx5e_free_rq(rq);
 824 }
 825
 826 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 827 {
 828         kfree(sq->db.di);
 829 }
 830
 831 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 832 {
 833         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 834
 835         sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
 836                                      GFP_KERNEL, numa);
 837         if (!sq->db.di) {
 838                 mlx5e_free_xdpsq_db(sq);
 839                 return -ENOMEM;
 840         }
 841
 842         return 0;
 843 }
 844
 845 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 846                              struct mlx5e_params *params,
 847                              struct mlx5e_sq_param *param,
 848                              struct mlx5e_xdpsq *sq)
 849 {
 850         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 851         struct mlx5_core_dev *mdev = c->mdev;
 852         int err;
 853
 854         sq->pdev      = c->pdev;
 855         sq->mkey_be   = c->mkey_be;
 856         sq->channel   = c;
 857         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 858         sq->min_inline_mode = params->tx_min_inline_mode;
 859
 860         param->wq.db_numa_node = cpu_to_node(c->cpu);
 861         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 862         if (err)
 863                 return err;
 864         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 865
 866         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 867         if (err)
 868                 goto err_sq_wq_destroy;
 869
 870         return 0;
 871
 872 err_sq_wq_destroy:
 873         mlx5_wq_destroy(&sq->wq_ctrl);
 874
 875         return err;
 876 }
 877
 878 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
 879 {
 880         mlx5e_free_xdpsq_db(sq);
 881         mlx5_wq_destroy(&sq->wq_ctrl);
 882 }
 883
 884 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
 885 {
 886         kfree(sq->db.ico_wqe);
 887 }
 888
 889 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
 890 {
 891         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 892
 893         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 894                                       GFP_KERNEL, numa);
 895         if (!sq->db.ico_wqe)
 896                 return -ENOMEM;
 897
 898         return 0;
 899 }
 900
 901 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
 902                              struct mlx5e_sq_param *param,
 903                              struct mlx5e_icosq *sq)
 904 {
 905         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 906         struct mlx5_core_dev *mdev = c->mdev;
 907         int err;
 908
 909         sq->channel   = c;
 910         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 911
 912         param->wq.db_numa_node = cpu_to_node(c->cpu);
 913         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 914         if (err)
 915                 return err;
 916         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 917
 918         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
 919         if (err)
 920                 goto err_sq_wq_destroy;
 921
 922         sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
 923
 924         return 0;
 925
 926 err_sq_wq_destroy:
 927         mlx5_wq_destroy(&sq->wq_ctrl);
 928
 929         return err;
 930 }
 931
 932 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
 933 {
 934         mlx5e_free_icosq_db(sq);
 935         mlx5_wq_destroy(&sq->wq_ctrl);
 936 }
 937
 938 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
 939 {
 940         kfree(sq->db.wqe_info);
 941         kfree(sq->db.dma_fifo);
 942 }
 943
 944 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
 945 {
 946         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 947         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 948
 949         sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
 950                                            GFP_KERNEL, numa);
 951         sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
 952                                            GFP_KERNEL, numa);
 953         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
 954                 mlx5e_free_txqsq_db(sq);
 955                 return -ENOMEM;
 956         }
 957
 958         sq->dma_fifo_mask = df_sz - 1;
 959
 960         return 0;
 961 }
 962
 963 static void mlx5e_sq_recover(struct work_struct *work);
 964 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
 965                              int txq_ix,
 966                              struct mlx5e_params *params,
 967                              struct mlx5e_sq_param *param,
 968                              struct mlx5e_txqsq *sq)
 969 {
 970         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 971         struct mlx5_core_dev *mdev = c->mdev;
 972         int err;
 973
 974         sq->pdev      = c->pdev;
 975         sq->tstamp    = c->tstamp;
 976         sq->clock     = &mdev->clock;
 977         sq->mkey_be   = c->mkey_be;
 978         sq->channel   = c;
 979         sq->txq_ix    = txq_ix;
 980         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 981         sq->min_inline_mode = params->tx_min_inline_mode;
 982         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
 983         if (MLX5_IPSEC_DEV(c->priv->mdev))
 984                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
 985
 986         param->wq.db_numa_node = cpu_to_node(c->cpu);
 987         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 988         if (err)
 989                 return err;
 990         sq->wq.db    = &sq->wq.db[MLX5_SND_DBR];
 991
 992         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
 993         if (err)
 994                 goto err_sq_wq_destroy;
 995
 996         sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 997
 998         return 0;
 999
1000 err_sq_wq_destroy:
1001         mlx5_wq_destroy(&sq->wq_ctrl);
1002
1003         return err;
1004 }
1005
1006 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1007 {
1008         mlx5e_free_txqsq_db(sq);
1009         mlx5_wq_destroy(&sq->wq_ctrl);
1010 }
1011
1012 struct mlx5e_create_sq_param {
1013         struct mlx5_wq_ctrl        *wq_ctrl;
1014         u32                         cqn;
1015         u32                         tisn;
1016         u8                          tis_lst_sz;
1017         u8                          min_inline_mode;
1018 };
1019
1020 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1021                            struct mlx5e_sq_param *param,
1022                            struct mlx5e_create_sq_param *csp,
1023                            u32 *sqn)
1024 {
1025         void *in;
1026         void *sqc;
1027         void *wq;
1028         int inlen;
1029         int err;
1030
1031         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1032                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1033         in = kvzalloc(inlen, GFP_KERNEL);
1034         if (!in)
1035                 return -ENOMEM;
1036
1037         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1038         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1039
1040         memcpy(sqc, param->sqc, sizeof(param->sqc));
1041         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1042         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1043         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1044
1045         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1046                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1047
1048         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1049         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1050
1051         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1052         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1053         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1054                                           MLX5_ADAPTER_PAGE_SHIFT);
1055         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1056
1057         mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1058
1059         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1060
1061         kvfree(in);
1062
1063         return err;
1064 }
1065
1066 struct mlx5e_modify_sq_param {
1067         int curr_state;
1068         int next_state;
1069         bool rl_update;
1070         int rl_index;
1071 };
1072
1073 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1074                            struct mlx5e_modify_sq_param *p)
1075 {
1076         void *in;
1077         void *sqc;
1078         int inlen;
1079         int err;
1080
1081         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1082         in = kvzalloc(inlen, GFP_KERNEL);
1083         if (!in)
1084                 return -ENOMEM;
1085
1086         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1087
1088         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1089         MLX5_SET(sqc, sqc, state, p->next_state);
1090         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1091                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1092                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1093         }
1094
1095         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1096
1097         kvfree(in);
1098
1099         return err;
1100 }
1101
1102 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1103 {
1104         mlx5_core_destroy_sq(mdev, sqn);
1105 }
1106
1107 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1108                                struct mlx5e_sq_param *param,
1109                                struct mlx5e_create_sq_param *csp,
1110                                u32 *sqn)
1111 {
1112         struct mlx5e_modify_sq_param msp = {0};
1113         int err;
1114
1115         err = mlx5e_create_sq(mdev, param, csp, sqn);
1116         if (err)
1117                 return err;
1118
1119         msp.curr_state = MLX5_SQC_STATE_RST;
1120         msp.next_state = MLX5_SQC_STATE_RDY;
1121         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1122         if (err)
1123                 mlx5e_destroy_sq(mdev, *sqn);
1124
1125         return err;
1126 }
1127
1128 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1129                                 struct mlx5e_txqsq *sq, u32 rate);
1130
1131 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1132                             u32 tisn,
1133                             int txq_ix,
1134                             struct mlx5e_params *params,
1135                             struct mlx5e_sq_param *param,
1136                             struct mlx5e_txqsq *sq)
1137 {
1138         struct mlx5e_create_sq_param csp = {};
1139         u32 tx_rate;
1140         int err;
1141
1142         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1143         if (err)
1144                 return err;
1145
1146         csp.tisn            = tisn;
1147         csp.tis_lst_sz      = 1;
1148         csp.cqn             = sq->cq.mcq.cqn;
1149         csp.wq_ctrl         = &sq->wq_ctrl;
1150         csp.min_inline_mode = sq->min_inline_mode;
1151         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1152         if (err)
1153                 goto err_free_txqsq;
1154
1155         tx_rate = c->priv->tx_rates[sq->txq_ix];
1156         if (tx_rate)
1157                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1158
1159         return 0;
1160
1161 err_free_txqsq:
1162         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1163         mlx5e_free_txqsq(sq);
1164
1165         return err;
1166 }
1167
1168 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1169 {
1170         WARN_ONCE(sq->cc != sq->pc,
1171                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1172                   sq->sqn, sq->cc, sq->pc);
1173         sq->cc = 0;
1174         sq->dma_fifo_cc = 0;
1175         sq->pc = 0;
1176 }
1177
1178 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1179 {
1180         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1181         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1182         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1183         netdev_tx_reset_queue(sq->txq);
1184         netif_tx_start_queue(sq->txq);
1185 }
1186
1187 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1188 {
1189         __netif_tx_lock_bh(txq);
1190         netif_tx_stop_queue(txq);
1191         __netif_tx_unlock_bh(txq);
1192 }
1193
1194 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1195 {
1196         struct mlx5e_channel *c = sq->channel;
1197
1198         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1199         /* prevent netif_tx_wake_queue */
1200         napi_synchronize(&c->napi);
1201
1202         netif_tx_disable_queue(sq->txq);
1203
1204         /* last doorbell out, godspeed .. */
1205         if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1206                 struct mlx5e_tx_wqe *nop;
1207
1208                 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1209                 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1210                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1211         }
1212 }
1213
1214 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1215 {
1216         struct mlx5e_channel *c = sq->channel;
1217         struct mlx5_core_dev *mdev = c->mdev;
1218
1219         mlx5e_destroy_sq(mdev, sq->sqn);
1220         if (sq->rate_limit)
1221                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1222         mlx5e_free_txqsq_descs(sq);
1223         mlx5e_free_txqsq(sq);
1224 }
1225
1226 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1227 {
1228         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1229
1230         while (time_before(jiffies, exp_time)) {
1231                 if (sq->cc == sq->pc)
1232                         return 0;
1233
1234                 msleep(20);
1235         }
1236
1237         netdev_err(sq->channel->netdev,
1238                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1239                    sq->sqn, sq->cc, sq->pc);
1240
1241         return -ETIMEDOUT;
1242 }
1243
1244 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1245 {
1246         struct mlx5_core_dev *mdev = sq->channel->mdev;
1247         struct net_device *dev = sq->channel->netdev;
1248         struct mlx5e_modify_sq_param msp = {0};
1249         int err;
1250
1251         msp.curr_state = curr_state;
1252         msp.next_state = MLX5_SQC_STATE_RST;
1253
1254         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1255         if (err) {
1256                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1257                 return err;
1258         }
1259
1260         memset(&msp, 0, sizeof(msp));
1261         msp.curr_state = MLX5_SQC_STATE_RST;
1262         msp.next_state = MLX5_SQC_STATE_RDY;
1263
1264         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1265         if (err) {
1266                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1267                 return err;
1268         }
1269
1270         return 0;
1271 }
1272
1273 static void mlx5e_sq_recover(struct work_struct *work)
1274 {
1275         struct mlx5e_txqsq_recover *recover =
1276                 container_of(work, struct mlx5e_txqsq_recover,
1277                              recover_work);
1278         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1279                                               recover);
1280         struct mlx5_core_dev *mdev = sq->channel->mdev;
1281         struct net_device *dev = sq->channel->netdev;
1282         u8 state;
1283         int err;
1284
1285         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1286         if (err) {
1287                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1288                            sq->sqn, err);
1289                 return;
1290         }
1291
1292         if (state != MLX5_RQC_STATE_ERR) {
1293                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1294                 return;
1295         }
1296
1297         netif_tx_disable_queue(sq->txq);
1298
1299         if (mlx5e_wait_for_sq_flush(sq))
1300                 return;
1301
1302         /* If the interval between two consecutive recovers per SQ is too
1303          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1304          * If we reached this state, there is probably a bug that needs to be
1305          * fixed. let's keep the queue close and let tx timeout cleanup.
1306          */
1307         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1308             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1309                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1310                            sq->sqn);
1311                 return;
1312         }
1313
1314         /* At this point, no new packets will arrive from the stack as TXQ is
1315          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1316          * pending WQEs.  SQ can safely reset the SQ.
1317          */
1318         if (mlx5e_sq_to_ready(sq, state))
1319                 return;
1320
1321         mlx5e_reset_txqsq_cc_pc(sq);
1322         sq->stats.recover++;
1323         recover->last_recover = jiffies;
1324         mlx5e_activate_txqsq(sq);
1325 }
1326
1327 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1328                             struct mlx5e_params *params,
1329                             struct mlx5e_sq_param *param,
1330                             struct mlx5e_icosq *sq)
1331 {
1332         struct mlx5e_create_sq_param csp = {};
1333         int err;
1334
1335         err = mlx5e_alloc_icosq(c, param, sq);
1336         if (err)
1337                 return err;
1338
1339         csp.cqn             = sq->cq.mcq.cqn;
1340         csp.wq_ctrl         = &sq->wq_ctrl;
1341         csp.min_inline_mode = params->tx_min_inline_mode;
1342         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1343         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1344         if (err)
1345                 goto err_free_icosq;
1346
1347         return 0;
1348
1349 err_free_icosq:
1350         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1351         mlx5e_free_icosq(sq);
1352
1353         return err;
1354 }
1355
1356 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1357 {
1358         struct mlx5e_channel *c = sq->channel;
1359
1360         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1361         napi_synchronize(&c->napi);
1362
1363         mlx5e_destroy_sq(c->mdev, sq->sqn);
1364         mlx5e_free_icosq(sq);
1365 }
1366
1367 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1368                             struct mlx5e_params *params,
1369                             struct mlx5e_sq_param *param,
1370                             struct mlx5e_xdpsq *sq)
1371 {
1372         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1373         struct mlx5e_create_sq_param csp = {};
1374         unsigned int inline_hdr_sz = 0;
1375         int err;
1376         int i;
1377
1378         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1379         if (err)
1380                 return err;
1381
1382         csp.tis_lst_sz      = 1;
1383         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1384         csp.cqn             = sq->cq.mcq.cqn;
1385         csp.wq_ctrl         = &sq->wq_ctrl;
1386         csp.min_inline_mode = sq->min_inline_mode;
1387         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1388         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1389         if (err)
1390                 goto err_free_xdpsq;
1391
1392         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1393                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1394                 ds_cnt++;
1395         }
1396
1397         /* Pre initialize fixed WQE fields */
1398         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1399                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1400                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1401                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1402                 struct mlx5_wqe_data_seg *dseg;
1403
1404                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1405                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1406
1407                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1408                 dseg->lkey = sq->mkey_be;
1409         }
1410
1411         return 0;
1412
1413 err_free_xdpsq:
1414         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1415         mlx5e_free_xdpsq(sq);
1416
1417         return err;
1418 }
1419
1420 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1421 {
1422         struct mlx5e_channel *c = sq->channel;
1423
1424         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1425         napi_synchronize(&c->napi);
1426
1427         mlx5e_destroy_sq(c->mdev, sq->sqn);
1428         mlx5e_free_xdpsq_descs(sq);
1429         mlx5e_free_xdpsq(sq);
1430 }
1431
1432 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1433                                  struct mlx5e_cq_param *param,
1434                                  struct mlx5e_cq *cq)
1435 {
1436         struct mlx5_core_cq *mcq = &cq->mcq;
1437         int eqn_not_used;
1438         unsigned int irqn;
1439         int err;
1440         u32 i;
1441
1442         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1443                                &cq->wq_ctrl);
1444         if (err)
1445                 return err;
1446
1447         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1448
1449         mcq->cqe_sz     = 64;
1450         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1451         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1452         *mcq->set_ci_db = 0;
1453         *mcq->arm_db    = 0;
1454         mcq->vector     = param->eq_ix;
1455         mcq->comp       = mlx5e_completion_event;
1456         mcq->event      = mlx5e_cq_error_event;
1457         mcq->irqn       = irqn;
1458
1459         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1460                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1461
1462                 cqe->op_own = 0xf1;
1463         }
1464
1465         cq->mdev = mdev;
1466
1467         return 0;
1468 }
1469
1470 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1471                           struct mlx5e_cq_param *param,
1472                           struct mlx5e_cq *cq)
1473 {
1474         struct mlx5_core_dev *mdev = c->priv->mdev;
1475         int err;
1476
1477         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1478         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1479         param->eq_ix   = c->ix;
1480
1481         err = mlx5e_alloc_cq_common(mdev, param, cq);
1482
1483         cq->napi    = &c->napi;
1484         cq->channel = c;
1485
1486         return err;
1487 }
1488
1489 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1490 {
1491         mlx5_cqwq_destroy(&cq->wq_ctrl);
1492 }
1493
1494 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1495 {
1496         struct mlx5_core_dev *mdev = cq->mdev;
1497         struct mlx5_core_cq *mcq = &cq->mcq;
1498
1499         void *in;
1500         void *cqc;
1501         int inlen;
1502         unsigned int irqn_not_used;
1503         int eqn;
1504         int err;
1505
1506         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1507                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1508         in = kvzalloc(inlen, GFP_KERNEL);
1509         if (!in)
1510                 return -ENOMEM;
1511
1512         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1513
1514         memcpy(cqc, param->cqc, sizeof(param->cqc));
1515
1516         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1517                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1518
1519         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1520
1521         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1522         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1523         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1524         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1525                                             MLX5_ADAPTER_PAGE_SHIFT);
1526         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1527
1528         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1529
1530         kvfree(in);
1531
1532         if (err)
1533                 return err;
1534
1535         mlx5e_cq_arm(cq);
1536
1537         return 0;
1538 }
1539
1540 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1541 {
1542         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1543 }
1544
1545 static int mlx5e_open_cq(struct mlx5e_channel *c,
1546                          struct net_dim_cq_moder moder,
1547                          struct mlx5e_cq_param *param,
1548                          struct mlx5e_cq *cq)
1549 {
1550         struct mlx5_core_dev *mdev = c->mdev;
1551         int err;
1552
1553         err = mlx5e_alloc_cq(c, param, cq);
1554         if (err)
1555                 return err;
1556
1557         err = mlx5e_create_cq(cq, param);
1558         if (err)
1559                 goto err_free_cq;
1560
1561         if (MLX5_CAP_GEN(mdev, cq_moderation))
1562                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1563         return 0;
1564
1565 err_free_cq:
1566         mlx5e_free_cq(cq);
1567
1568         return err;
1569 }
1570
1571 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1572 {
1573         mlx5e_destroy_cq(cq);
1574         mlx5e_free_cq(cq);
1575 }
1576
1577 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1578 {
1579         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1580 }
1581
1582 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1583                              struct mlx5e_params *params,
1584                              struct mlx5e_channel_param *cparam)
1585 {
1586         int err;
1587         int tc;
1588
1589         for (tc = 0; tc < c->num_tc; tc++) {
1590                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1591                                     &cparam->tx_cq, &c->sq[tc].cq);
1592                 if (err)
1593                         goto err_close_tx_cqs;
1594         }
1595
1596         return 0;
1597
1598 err_close_tx_cqs:
1599         for (tc--; tc >= 0; tc--)
1600                 mlx5e_close_cq(&c->sq[tc].cq);
1601
1602         return err;
1603 }
1604
1605 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1606 {
1607         int tc;
1608
1609         for (tc = 0; tc < c->num_tc; tc++)
1610                 mlx5e_close_cq(&c->sq[tc].cq);
1611 }
1612
1613 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1614                           struct mlx5e_params *params,
1615                           struct mlx5e_channel_param *cparam)
1616 {
1617         int err;
1618         int tc;
1619
1620         for (tc = 0; tc < params->num_tc; tc++) {
1621                 int txq_ix = c->ix + tc * params->num_channels;
1622
1623                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1624                                        params, &cparam->sq, &c->sq[tc]);
1625                 if (err)
1626                         goto err_close_sqs;
1627         }
1628
1629         return 0;
1630
1631 err_close_sqs:
1632         for (tc--; tc >= 0; tc--)
1633                 mlx5e_close_txqsq(&c->sq[tc]);
1634
1635         return err;
1636 }
1637
1638 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1639 {
1640         int tc;
1641
1642         for (tc = 0; tc < c->num_tc; tc++)
1643                 mlx5e_close_txqsq(&c->sq[tc]);
1644 }
1645
1646 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1647                                 struct mlx5e_txqsq *sq, u32 rate)
1648 {
1649         struct mlx5e_priv *priv = netdev_priv(dev);
1650         struct mlx5_core_dev *mdev = priv->mdev;
1651         struct mlx5e_modify_sq_param msp = {0};
1652         u16 rl_index = 0;
1653         int err;
1654
1655         if (rate == sq->rate_limit)
1656                 /* nothing to do */
1657                 return 0;
1658
1659         if (sq->rate_limit)
1660                 /* remove current rl index to free space to next ones */
1661                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1662
1663         sq->rate_limit = 0;
1664
1665         if (rate) {
1666                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1667                 if (err) {
1668                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1669                                    rate, err);
1670                         return err;
1671                 }
1672         }
1673
1674         msp.curr_state = MLX5_SQC_STATE_RDY;
1675         msp.next_state = MLX5_SQC_STATE_RDY;
1676         msp.rl_index   = rl_index;
1677         msp.rl_update  = true;
1678         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1679         if (err) {
1680                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1681                            rate, err);
1682                 /* remove the rate from the table */
1683                 if (rate)
1684                         mlx5_rl_remove_rate(mdev, rate);
1685                 return err;
1686         }
1687
1688         sq->rate_limit = rate;
1689         return 0;
1690 }
1691
1692 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1693 {
1694         struct mlx5e_priv *priv = netdev_priv(dev);
1695         struct mlx5_core_dev *mdev = priv->mdev;
1696         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1697         int err = 0;
1698
1699         if (!mlx5_rl_is_supported(mdev)) {
1700                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1701                 return -EINVAL;
1702         }
1703
1704         /* rate is given in Mb/sec, HW config is in Kb/sec */
1705         rate = rate << 10;
1706
1707         /* Check whether rate in valid range, 0 is always valid */
1708         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1709                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1710                 return -ERANGE;
1711         }
1712
1713         mutex_lock(&priv->state_lock);
1714         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1715                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1716         if (!err)
1717                 priv->tx_rates[index] = rate;
1718         mutex_unlock(&priv->state_lock);
1719
1720         return err;
1721 }
1722
1723 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1724                               struct mlx5e_params *params,
1725                               struct mlx5e_channel_param *cparam,
1726                               struct mlx5e_channel **cp)
1727 {
1728         struct net_dim_cq_moder icocq_moder = {0, 0};
1729         struct net_device *netdev = priv->netdev;
1730         int cpu = mlx5e_get_cpu(priv, ix);
1731         struct mlx5e_channel *c;
1732         unsigned int irq;
1733         int err;
1734         int eqn;
1735
1736         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1737         if (!c)
1738                 return -ENOMEM;
1739
1740         c->priv     = priv;
1741         c->mdev     = priv->mdev;
1742         c->tstamp   = &priv->tstamp;
1743         c->ix       = ix;
1744         c->cpu      = cpu;
1745         c->pdev     = &priv->mdev->pdev->dev;
1746         c->netdev   = priv->netdev;
1747         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1748         c->num_tc   = params->num_tc;
1749         c->xdp      = !!params->xdp_prog;
1750
1751         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1752         c->irq_desc = irq_to_desc(irq);
1753
1754         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1755
1756         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1757         if (err)
1758                 goto err_napi_del;
1759
1760         err = mlx5e_open_tx_cqs(c, params, cparam);
1761         if (err)
1762                 goto err_close_icosq_cq;
1763
1764         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1765         if (err)
1766                 goto err_close_tx_cqs;
1767
1768         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1769         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1770                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1771         if (err)
1772                 goto err_close_rx_cq;
1773
1774         napi_enable(&c->napi);
1775
1776         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1777         if (err)
1778                 goto err_disable_napi;
1779
1780         err = mlx5e_open_sqs(c, params, cparam);
1781         if (err)
1782                 goto err_close_icosq;
1783
1784         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1785         if (err)
1786                 goto err_close_sqs;
1787
1788         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1789         if (err)
1790                 goto err_close_xdp_sq;
1791
1792         *cp = c;
1793
1794         return 0;
1795 err_close_xdp_sq:
1796         if (c->xdp)
1797                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1798
1799 err_close_sqs:
1800         mlx5e_close_sqs(c);
1801
1802 err_close_icosq:
1803         mlx5e_close_icosq(&c->icosq);
1804
1805 err_disable_napi:
1806         napi_disable(&c->napi);
1807         if (c->xdp)
1808                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1809
1810 err_close_rx_cq:
1811         mlx5e_close_cq(&c->rq.cq);
1812
1813 err_close_tx_cqs:
1814         mlx5e_close_tx_cqs(c);
1815
1816 err_close_icosq_cq:
1817         mlx5e_close_cq(&c->icosq.cq);
1818
1819 err_napi_del:
1820         netif_napi_del(&c->napi);
1821         kfree(c);
1822
1823         return err;
1824 }
1825
1826 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1827 {
1828         int tc;
1829
1830         for (tc = 0; tc < c->num_tc; tc++)
1831                 mlx5e_activate_txqsq(&c->sq[tc]);
1832         mlx5e_activate_rq(&c->rq);
1833         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1834 }
1835
1836 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1837 {
1838         int tc;
1839
1840         mlx5e_deactivate_rq(&c->rq);
1841         for (tc = 0; tc < c->num_tc; tc++)
1842                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1843 }
1844
1845 static void mlx5e_close_channel(struct mlx5e_channel *c)
1846 {
1847         mlx5e_close_rq(&c->rq);
1848         if (c->xdp)
1849                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1850         mlx5e_close_sqs(c);
1851         mlx5e_close_icosq(&c->icosq);
1852         napi_disable(&c->napi);
1853         if (c->xdp)
1854                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1855         mlx5e_close_cq(&c->rq.cq);
1856         mlx5e_close_tx_cqs(c);
1857         mlx5e_close_cq(&c->icosq.cq);
1858         netif_napi_del(&c->napi);
1859
1860         kfree(c);
1861 }
1862
1863 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1864                                  struct mlx5e_params *params,
1865                                  struct mlx5e_rq_param *param)
1866 {
1867         struct mlx5_core_dev *mdev = priv->mdev;
1868         void *rqc = param->rqc;
1869         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1870
1871         switch (params->rq_wq_type) {
1872         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1873                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1874                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
1875                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
1876                 MLX5_SET(wq, wq, log_wqe_stride_size,
1877                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
1878                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
1879                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1880                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
1881                 break;
1882         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1883                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1884                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
1885         }
1886
1887         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1888         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1889         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
1890         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1891         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
1892         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
1893
1894         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1895         param->wq.linear = 1;
1896 }
1897
1898 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
1899                                       struct mlx5e_rq_param *param)
1900 {
1901         struct mlx5_core_dev *mdev = priv->mdev;
1902         void *rqc = param->rqc;
1903         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1904
1905         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1906         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1907         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
1908
1909         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1910 }
1911
1912 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1913                                         struct mlx5e_sq_param *param)
1914 {
1915         void *sqc = param->sqc;
1916         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1917
1918         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1919         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1920
1921         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1922 }
1923
1924 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1925                                  struct mlx5e_params *params,
1926                                  struct mlx5e_sq_param *param)
1927 {
1928         void *sqc = param->sqc;
1929         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1930
1931         mlx5e_build_sq_param_common(priv, param);
1932         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1933         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1934 }
1935
1936 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1937                                         struct mlx5e_cq_param *param)
1938 {
1939         void *cqc = param->cqc;
1940
1941         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1942 }
1943
1944 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1945                                     struct mlx5e_params *params,
1946                                     struct mlx5e_cq_param *param)
1947 {
1948         struct mlx5_core_dev *mdev = priv->mdev;
1949         void *cqc = param->cqc;
1950         u8 log_cq_size;
1951
1952         switch (params->rq_wq_type) {
1953         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1954                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
1955                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
1956                 break;
1957         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1958                 log_cq_size = params->log_rq_mtu_frames;
1959         }
1960
1961         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1962         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1963                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1964                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1965         }
1966
1967         mlx5e_build_common_cq_param(priv, param);
1968         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
1969 }
1970
1971 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1972                                     struct mlx5e_params *params,
1973                                     struct mlx5e_cq_param *param)
1974 {
1975         void *cqc = param->cqc;
1976
1977         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1978
1979         mlx5e_build_common_cq_param(priv, param);
1980         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
1981 }
1982
1983 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1984                                      u8 log_wq_size,
1985                                      struct mlx5e_cq_param *param)
1986 {
1987         void *cqc = param->cqc;
1988
1989         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1990
1991         mlx5e_build_common_cq_param(priv, param);
1992
1993         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1994 }
1995
1996 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1997                                     u8 log_wq_size,
1998                                     struct mlx5e_sq_param *param)
1999 {
2000         void *sqc = param->sqc;
2001         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2002
2003         mlx5e_build_sq_param_common(priv, param);
2004
2005         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2006         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2007 }
2008
2009 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2010                                     struct mlx5e_params *params,
2011                                     struct mlx5e_sq_param *param)
2012 {
2013         void *sqc = param->sqc;
2014         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2015
2016         mlx5e_build_sq_param_common(priv, param);
2017         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2018 }
2019
2020 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2021                                       struct mlx5e_params *params,
2022                                       struct mlx5e_channel_param *cparam)
2023 {
2024         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2025
2026         mlx5e_build_rq_param(priv, params, &cparam->rq);
2027         mlx5e_build_sq_param(priv, params, &cparam->sq);
2028         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2029         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2030         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2031         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2032         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2033 }
2034
2035 int mlx5e_open_channels(struct mlx5e_priv *priv,
2036                         struct mlx5e_channels *chs)
2037 {
2038         struct mlx5e_channel_param *cparam;
2039         int err = -ENOMEM;
2040         int i;
2041
2042         chs->num = chs->params.num_channels;
2043
2044         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2045         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2046         if (!chs->c || !cparam)
2047                 goto err_free;
2048
2049         mlx5e_build_channel_param(priv, &chs->params, cparam);
2050         for (i = 0; i < chs->num; i++) {
2051                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2052                 if (err)
2053                         goto err_close_channels;
2054         }
2055
2056         kfree(cparam);
2057         return 0;
2058
2059 err_close_channels:
2060         for (i--; i >= 0; i--)
2061                 mlx5e_close_channel(chs->c[i]);
2062
2063 err_free:
2064         kfree(chs->c);
2065         kfree(cparam);
2066         chs->num = 0;
2067         return err;
2068 }
2069
2070 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2071 {
2072         int i;
2073
2074         for (i = 0; i < chs->num; i++)
2075                 mlx5e_activate_channel(chs->c[i]);
2076 }
2077
2078 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2079 {
2080         int err = 0;
2081         int i;
2082
2083         for (i = 0; i < chs->num; i++) {
2084                 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2085                 if (err)
2086                         break;
2087         }
2088
2089         return err;
2090 }
2091
2092 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2093 {
2094         int i;
2095
2096         for (i = 0; i < chs->num; i++)
2097                 mlx5e_deactivate_channel(chs->c[i]);
2098 }
2099
2100 void mlx5e_close_channels(struct mlx5e_channels *chs)
2101 {
2102         int i;
2103
2104         for (i = 0; i < chs->num; i++)
2105                 mlx5e_close_channel(chs->c[i]);
2106
2107         kfree(chs->c);
2108         chs->num = 0;
2109 }
2110
2111 static int
2112 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2113 {
2114         struct mlx5_core_dev *mdev = priv->mdev;
2115         void *rqtc;
2116         int inlen;
2117         int err;
2118         u32 *in;
2119         int i;
2120
2121         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2122         in = kvzalloc(inlen, GFP_KERNEL);
2123         if (!in)
2124                 return -ENOMEM;
2125
2126         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2127
2128         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2129         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2130
2131         for (i = 0; i < sz; i++)
2132                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2133
2134         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2135         if (!err)
2136                 rqt->enabled = true;
2137
2138         kvfree(in);
2139         return err;
2140 }
2141
2142 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2143 {
2144         rqt->enabled = false;
2145         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2146 }
2147
2148 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2149 {
2150         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2151         int err;
2152
2153         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2154         if (err)
2155                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2156         return err;
2157 }
2158
2159 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2160 {
2161         struct mlx5e_rqt *rqt;
2162         int err;
2163         int ix;
2164
2165         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2166                 rqt = &priv->direct_tir[ix].rqt;
2167                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2168                 if (err)
2169                         goto err_destroy_rqts;
2170         }
2171
2172         return 0;
2173
2174 err_destroy_rqts:
2175         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2176         for (ix--; ix >= 0; ix--)
2177                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2178
2179         return err;
2180 }
2181
2182 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2183 {
2184         int i;
2185
2186         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2187                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2188 }
2189
2190 static int mlx5e_rx_hash_fn(int hfunc)
2191 {
2192         return (hfunc == ETH_RSS_HASH_TOP) ?
2193                MLX5_RX_HASH_FN_TOEPLITZ :
2194                MLX5_RX_HASH_FN_INVERTED_XOR8;
2195 }
2196
2197 int mlx5e_bits_invert(unsigned long a, int size)
2198 {
2199         int inv = 0;
2200         int i;
2201
2202         for (i = 0; i < size; i++)
2203                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2204
2205         return inv;
2206 }
2207
2208 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2209                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2210 {
2211         int i;
2212
2213         for (i = 0; i < sz; i++) {
2214                 u32 rqn;
2215
2216                 if (rrp.is_rss) {
2217                         int ix = i;
2218
2219                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2220                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2221
2222                         ix = priv->channels.params.indirection_rqt[ix];
2223                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2224                 } else {
2225                         rqn = rrp.rqn;
2226                 }
2227                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2228         }
2229 }
2230
2231 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2232                        struct mlx5e_redirect_rqt_param rrp)
2233 {
2234         struct mlx5_core_dev *mdev = priv->mdev;
2235         void *rqtc;
2236         int inlen;
2237         u32 *in;
2238         int err;
2239
2240         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2241         in = kvzalloc(inlen, GFP_KERNEL);
2242         if (!in)
2243                 return -ENOMEM;
2244
2245         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2246
2247         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2248         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2249         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2250         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2251
2252         kvfree(in);
2253         return err;
2254 }
2255
2256 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2257                                 struct mlx5e_redirect_rqt_param rrp)
2258 {
2259         if (!rrp.is_rss)
2260                 return rrp.rqn;
2261
2262         if (ix >= rrp.rss.channels->num)
2263                 return priv->drop_rq.rqn;
2264
2265         return rrp.rss.channels->c[ix]->rq.rqn;
2266 }
2267
2268 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2269                                 struct mlx5e_redirect_rqt_param rrp)
2270 {
2271         u32 rqtn;
2272         int ix;
2273
2274         if (priv->indir_rqt.enabled) {
2275                 /* RSS RQ table */
2276                 rqtn = priv->indir_rqt.rqtn;
2277                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2278         }
2279
2280         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2281                 struct mlx5e_redirect_rqt_param direct_rrp = {
2282                         .is_rss = false,
2283                         {
2284                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2285                         },
2286                 };
2287
2288                 /* Direct RQ Tables */
2289                 if (!priv->direct_tir[ix].rqt.enabled)
2290                         continue;
2291
2292                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2293                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2294         }
2295 }
2296
2297 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2298                                             struct mlx5e_channels *chs)
2299 {
2300         struct mlx5e_redirect_rqt_param rrp = {
2301                 .is_rss        = true,
2302                 {
2303                         .rss = {
2304                                 .channels  = chs,
2305                                 .hfunc     = chs->params.rss_hfunc,
2306                         }
2307                 },
2308         };
2309
2310         mlx5e_redirect_rqts(priv, rrp);
2311 }
2312
2313 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2314 {
2315         struct mlx5e_redirect_rqt_param drop_rrp = {
2316                 .is_rss = false,
2317                 {
2318                         .rqn = priv->drop_rq.rqn,
2319                 },
2320         };
2321
2322         mlx5e_redirect_rqts(priv, drop_rrp);
2323 }
2324
2325 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2326 {
2327         if (!params->lro_en)
2328                 return;
2329
2330 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2331
2332         MLX5_SET(tirc, tirc, lro_enable_mask,
2333                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2334                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2335         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2336                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2337         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2338 }
2339
2340 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2341                                     enum mlx5e_traffic_types tt,
2342                                     void *tirc, bool inner)
2343 {
2344         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2345                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2346
2347 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2348                                  MLX5_HASH_FIELD_SEL_DST_IP)
2349
2350 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2351                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2352                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2353                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2354
2355 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2356                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2357                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2358
2359         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2360         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2361                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2362                                              rx_hash_toeplitz_key);
2363                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2364                                                rx_hash_toeplitz_key);
2365
2366                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2367                 memcpy(rss_key, params->toeplitz_hash_key, len);
2368         }
2369
2370         switch (tt) {
2371         case MLX5E_TT_IPV4_TCP:
2372                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2373                          MLX5_L3_PROT_TYPE_IPV4);
2374                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2375                          MLX5_L4_PROT_TYPE_TCP);
2376                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2377                          MLX5_HASH_IP_L4PORTS);
2378                 break;
2379
2380         case MLX5E_TT_IPV6_TCP:
2381                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2382                          MLX5_L3_PROT_TYPE_IPV6);
2383                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2384                          MLX5_L4_PROT_TYPE_TCP);
2385                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2386                          MLX5_HASH_IP_L4PORTS);
2387                 break;
2388
2389         case MLX5E_TT_IPV4_UDP:
2390                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2391                          MLX5_L3_PROT_TYPE_IPV4);
2392                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2393                          MLX5_L4_PROT_TYPE_UDP);
2394                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2395                          MLX5_HASH_IP_L4PORTS);
2396                 break;
2397
2398         case MLX5E_TT_IPV6_UDP:
2399                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2400                          MLX5_L3_PROT_TYPE_IPV6);
2401                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2402                          MLX5_L4_PROT_TYPE_UDP);
2403                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2404                          MLX5_HASH_IP_L4PORTS);
2405                 break;
2406
2407         case MLX5E_TT_IPV4_IPSEC_AH:
2408                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2409                          MLX5_L3_PROT_TYPE_IPV4);
2410                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2411                          MLX5_HASH_IP_IPSEC_SPI);
2412                 break;
2413
2414         case MLX5E_TT_IPV6_IPSEC_AH:
2415                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2416                          MLX5_L3_PROT_TYPE_IPV6);
2417                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2418                          MLX5_HASH_IP_IPSEC_SPI);
2419                 break;
2420
2421         case MLX5E_TT_IPV4_IPSEC_ESP:
2422                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2423                          MLX5_L3_PROT_TYPE_IPV4);
2424                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2425                          MLX5_HASH_IP_IPSEC_SPI);
2426                 break;
2427
2428         case MLX5E_TT_IPV6_IPSEC_ESP:
2429                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2430                          MLX5_L3_PROT_TYPE_IPV6);
2431                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2432                          MLX5_HASH_IP_IPSEC_SPI);
2433                 break;
2434
2435         case MLX5E_TT_IPV4:
2436                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2437                          MLX5_L3_PROT_TYPE_IPV4);
2438                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2439                          MLX5_HASH_IP);
2440                 break;
2441
2442         case MLX5E_TT_IPV6:
2443                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2444                          MLX5_L3_PROT_TYPE_IPV6);
2445                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2446                          MLX5_HASH_IP);
2447                 break;
2448         default:
2449                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2450         }
2451 }
2452
2453 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2454 {
2455         struct mlx5_core_dev *mdev = priv->mdev;
2456
2457         void *in;
2458         void *tirc;
2459         int inlen;
2460         int err;
2461         int tt;
2462         int ix;
2463
2464         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2465         in = kvzalloc(inlen, GFP_KERNEL);
2466         if (!in)
2467                 return -ENOMEM;
2468
2469         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2470         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2471
2472         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2473
2474         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2475                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2476                                            inlen);
2477                 if (err)
2478                         goto free_in;
2479         }
2480
2481         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2482                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2483                                            in, inlen);
2484                 if (err)
2485                         goto free_in;
2486         }
2487
2488 free_in:
2489         kvfree(in);
2490
2491         return err;
2492 }
2493
2494 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2495                                             enum mlx5e_traffic_types tt,
2496                                             u32 *tirc)
2497 {
2498         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2499
2500         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2501
2502         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2503         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2504         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2505
2506         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2507 }
2508
2509 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2510                          struct mlx5e_params *params, u16 mtu)
2511 {
2512         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2513         int err;
2514
2515         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2516         if (err)
2517                 return err;
2518
2519         /* Update vport context MTU */
2520         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2521         return 0;
2522 }
2523
2524 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2525                             struct mlx5e_params *params, u16 *mtu)
2526 {
2527         u16 hw_mtu = 0;
2528         int err;
2529
2530         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2531         if (err || !hw_mtu) /* fallback to port oper mtu */
2532                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2533
2534         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2535 }
2536
2537 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2538 {
2539         struct mlx5e_params *params = &priv->channels.params;
2540         struct net_device *netdev = priv->netdev;
2541         struct mlx5_core_dev *mdev = priv->mdev;
2542         u16 mtu;
2543         int err;
2544
2545         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2546         if (err)
2547                 return err;
2548
2549         mlx5e_query_mtu(mdev, params, &mtu);
2550         if (mtu != params->sw_mtu)
2551                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2552                             __func__, mtu, params->sw_mtu);
2553
2554         params->sw_mtu = mtu;
2555         return 0;
2556 }
2557
2558 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2559 {
2560         struct mlx5e_priv *priv = netdev_priv(netdev);
2561         int nch = priv->channels.params.num_channels;
2562         int ntc = priv->channels.params.num_tc;
2563         int tc;
2564
2565         netdev_reset_tc(netdev);
2566
2567         if (ntc == 1)
2568                 return;
2569
2570         netdev_set_num_tc(netdev, ntc);
2571
2572         /* Map netdev TCs to offset 0
2573          * We have our own UP to TXQ mapping for QoS
2574          */
2575         for (tc = 0; tc < ntc; tc++)
2576                 netdev_set_tc_queue(netdev, tc, nch, 0);
2577 }
2578
2579 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2580 {
2581         struct mlx5e_channel *c;
2582         struct mlx5e_txqsq *sq;
2583         int i, tc;
2584
2585         for (i = 0; i < priv->channels.num; i++)
2586                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2587                         priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2588
2589         for (i = 0; i < priv->channels.num; i++) {
2590                 c = priv->channels.c[i];
2591                 for (tc = 0; tc < c->num_tc; tc++) {
2592                         sq = &c->sq[tc];
2593                         priv->txq2sq[sq->txq_ix] = sq;
2594                 }
2595         }
2596 }
2597
2598 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2599 {
2600         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2601         struct net_device *netdev = priv->netdev;
2602
2603         mlx5e_netdev_set_tcs(netdev);
2604         netif_set_real_num_tx_queues(netdev, num_txqs);
2605         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2606
2607         mlx5e_build_channels_tx_maps(priv);
2608         mlx5e_activate_channels(&priv->channels);
2609         netif_tx_start_all_queues(priv->netdev);
2610
2611         if (MLX5_VPORT_MANAGER(priv->mdev))
2612                 mlx5e_add_sqs_fwd_rules(priv);
2613
2614         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2615         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2616 }
2617
2618 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2619 {
2620         mlx5e_redirect_rqts_to_drop(priv);
2621
2622         if (MLX5_VPORT_MANAGER(priv->mdev))
2623                 mlx5e_remove_sqs_fwd_rules(priv);
2624
2625         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2626          * polling for inactive tx queues.
2627          */
2628         netif_tx_stop_all_queues(priv->netdev);
2629         netif_tx_disable(priv->netdev);
2630         mlx5e_deactivate_channels(&priv->channels);
2631 }
2632
2633 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2634                                 struct mlx5e_channels *new_chs,
2635                                 mlx5e_fp_hw_modify hw_modify)
2636 {
2637         struct net_device *netdev = priv->netdev;
2638         int new_num_txqs;
2639         int carrier_ok;
2640         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2641
2642         carrier_ok = netif_carrier_ok(netdev);
2643         netif_carrier_off(netdev);
2644
2645         if (new_num_txqs < netdev->real_num_tx_queues)
2646                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2647
2648         mlx5e_deactivate_priv_channels(priv);
2649         mlx5e_close_channels(&priv->channels);
2650
2651         priv->channels = *new_chs;
2652
2653         /* New channels are ready to roll, modify HW settings if needed */
2654         if (hw_modify)
2655                 hw_modify(priv);
2656
2657         mlx5e_refresh_tirs(priv, false);
2658         mlx5e_activate_priv_channels(priv);
2659
2660         /* return carrier back if needed */
2661         if (carrier_ok)
2662                 netif_carrier_on(netdev);
2663 }
2664
2665 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2666 {
2667         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2668         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2669 }
2670
2671 int mlx5e_open_locked(struct net_device *netdev)
2672 {
2673         struct mlx5e_priv *priv = netdev_priv(netdev);
2674         int err;
2675
2676         set_bit(MLX5E_STATE_OPENED, &priv->state);
2677
2678         err = mlx5e_open_channels(priv, &priv->channels);
2679         if (err)
2680                 goto err_clear_state_opened_flag;
2681
2682         mlx5e_refresh_tirs(priv, false);
2683         mlx5e_activate_priv_channels(priv);
2684         if (priv->profile->update_carrier)
2685                 priv->profile->update_carrier(priv);
2686
2687         if (priv->profile->update_stats)
2688                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2689
2690         return 0;
2691
2692 err_clear_state_opened_flag:
2693         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2694         return err;
2695 }
2696
2697 int mlx5e_open(struct net_device *netdev)
2698 {
2699         struct mlx5e_priv *priv = netdev_priv(netdev);
2700         int err;
2701
2702         mutex_lock(&priv->state_lock);
2703         err = mlx5e_open_locked(netdev);
2704         if (!err)
2705                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2706         mutex_unlock(&priv->state_lock);
2707
2708         return err;
2709 }
2710
2711 int mlx5e_close_locked(struct net_device *netdev)
2712 {
2713         struct mlx5e_priv *priv = netdev_priv(netdev);
2714
2715         /* May already be CLOSED in case a previous configuration operation
2716          * (e.g RX/TX queue size change) that involves close&open failed.
2717          */
2718         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2719                 return 0;
2720
2721         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2722
2723         netif_carrier_off(priv->netdev);
2724         mlx5e_deactivate_priv_channels(priv);
2725         mlx5e_close_channels(&priv->channels);
2726
2727         return 0;
2728 }
2729
2730 int mlx5e_close(struct net_device *netdev)
2731 {
2732         struct mlx5e_priv *priv = netdev_priv(netdev);
2733         int err;
2734
2735         if (!netif_device_present(netdev))
2736                 return -ENODEV;
2737
2738         mutex_lock(&priv->state_lock);
2739         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2740         err = mlx5e_close_locked(netdev);
2741         mutex_unlock(&priv->state_lock);
2742
2743         return err;
2744 }
2745
2746 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2747                                struct mlx5e_rq *rq,
2748                                struct mlx5e_rq_param *param)
2749 {
2750         void *rqc = param->rqc;
2751         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2752         int err;
2753
2754         param->wq.db_numa_node = param->wq.buf_numa_node;
2755
2756         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2757                                 &rq->wq_ctrl);
2758         if (err)
2759                 return err;
2760
2761         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2762         xdp_rxq_info_unused(&rq->xdp_rxq);
2763
2764         rq->mdev = mdev;
2765
2766         return 0;
2767 }
2768
2769 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2770                                struct mlx5e_cq *cq,
2771                                struct mlx5e_cq_param *param)
2772 {
2773         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2774         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
2775
2776         return mlx5e_alloc_cq_common(mdev, param, cq);
2777 }
2778
2779 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2780                               struct mlx5e_rq *drop_rq)
2781 {
2782         struct mlx5_core_dev *mdev = priv->mdev;
2783         struct mlx5e_cq_param cq_param = {};
2784         struct mlx5e_rq_param rq_param = {};
2785         struct mlx5e_cq *cq = &drop_rq->cq;
2786         int err;
2787
2788         mlx5e_build_drop_rq_param(priv, &rq_param);
2789
2790         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2791         if (err)
2792                 return err;
2793
2794         err = mlx5e_create_cq(cq, &cq_param);
2795         if (err)
2796                 goto err_free_cq;
2797
2798         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2799         if (err)
2800                 goto err_destroy_cq;
2801
2802         err = mlx5e_create_rq(drop_rq, &rq_param);
2803         if (err)
2804                 goto err_free_rq;
2805
2806         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2807         if (err)
2808                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2809
2810         return 0;
2811
2812 err_free_rq:
2813         mlx5e_free_rq(drop_rq);
2814
2815 err_destroy_cq:
2816         mlx5e_destroy_cq(cq);
2817
2818 err_free_cq:
2819         mlx5e_free_cq(cq);
2820
2821         return err;
2822 }
2823
2824 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2825 {
2826         mlx5e_destroy_rq(drop_rq);
2827         mlx5e_free_rq(drop_rq);
2828         mlx5e_destroy_cq(&drop_rq->cq);
2829         mlx5e_free_cq(&drop_rq->cq);
2830 }
2831
2832 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2833                      u32 underlay_qpn, u32 *tisn)
2834 {
2835         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2836         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2837
2838         MLX5_SET(tisc, tisc, prio, tc << 1);
2839         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2840         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2841
2842         if (mlx5_lag_is_lacp_owner(mdev))
2843                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2844
2845         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2846 }
2847
2848 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2849 {
2850         mlx5_core_destroy_tis(mdev, tisn);
2851 }
2852
2853 int mlx5e_create_tises(struct mlx5e_priv *priv)
2854 {
2855         int err;
2856         int tc;
2857
2858         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2859                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2860                 if (err)
2861                         goto err_close_tises;
2862         }
2863
2864         return 0;
2865
2866 err_close_tises:
2867         for (tc--; tc >= 0; tc--)
2868                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2869
2870         return err;
2871 }
2872
2873 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2874 {
2875         int tc;
2876
2877         for (tc = 0; tc < priv->profile->max_tc; tc++)
2878                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2879 }
2880
2881 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2882                                       enum mlx5e_traffic_types tt,
2883                                       u32 *tirc)
2884 {
2885         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2886
2887         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2888
2889         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2890         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2891         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2892 }
2893
2894 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2895 {
2896         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2897
2898         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2899
2900         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2901         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2902         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2903 }
2904
2905 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2906 {
2907         struct mlx5e_tir *tir;
2908         void *tirc;
2909         int inlen;
2910         int i = 0;
2911         int err;
2912         u32 *in;
2913         int tt;
2914
2915         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2916         in = kvzalloc(inlen, GFP_KERNEL);
2917         if (!in)
2918                 return -ENOMEM;
2919
2920         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2921                 memset(in, 0, inlen);
2922                 tir = &priv->indir_tir[tt];
2923                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2924                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2925                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2926                 if (err) {
2927                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2928                         goto err_destroy_inner_tirs;
2929                 }
2930         }
2931
2932         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2933                 goto out;
2934
2935         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2936                 memset(in, 0, inlen);
2937                 tir = &priv->inner_indir_tir[i];
2938                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2939                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2940                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2941                 if (err) {
2942                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2943                         goto err_destroy_inner_tirs;
2944                 }
2945         }
2946
2947 out:
2948         kvfree(in);
2949
2950         return 0;
2951
2952 err_destroy_inner_tirs:
2953         for (i--; i >= 0; i--)
2954                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2955
2956         for (tt--; tt >= 0; tt--)
2957                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2958
2959         kvfree(in);
2960
2961         return err;
2962 }
2963
2964 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2965 {
2966         int nch = priv->profile->max_nch(priv->mdev);
2967         struct mlx5e_tir *tir;
2968         void *tirc;
2969         int inlen;
2970         int err;
2971         u32 *in;
2972         int ix;
2973
2974         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2975         in = kvzalloc(inlen, GFP_KERNEL);
2976         if (!in)
2977                 return -ENOMEM;
2978
2979         for (ix = 0; ix < nch; ix++) {
2980                 memset(in, 0, inlen);
2981                 tir = &priv->direct_tir[ix];
2982                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2983                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2984                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2985                 if (err)
2986                         goto err_destroy_ch_tirs;
2987         }
2988
2989         kvfree(in);
2990
2991         return 0;
2992
2993 err_destroy_ch_tirs:
2994         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
2995         for (ix--; ix >= 0; ix--)
2996                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2997
2998         kvfree(in);
2999
3000         return err;
3001 }
3002
3003 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3004 {
3005         int i;
3006
3007         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3008                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3009
3010         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3011                 return;
3012
3013         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3014                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3015 }
3016
3017 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3018 {
3019         int nch = priv->profile->max_nch(priv->mdev);
3020         int i;
3021
3022         for (i = 0; i < nch; i++)
3023                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3024 }
3025
3026 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3027 {
3028         int err = 0;
3029         int i;
3030
3031         for (i = 0; i < chs->num; i++) {
3032                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3033                 if (err)
3034                         return err;
3035         }
3036
3037         return 0;
3038 }
3039
3040 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3041 {
3042         int err = 0;
3043         int i;
3044
3045         for (i = 0; i < chs->num; i++) {
3046                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3047                 if (err)
3048                         return err;
3049         }
3050
3051         return 0;
3052 }
3053
3054 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3055                                  struct tc_mqprio_qopt *mqprio)
3056 {
3057         struct mlx5e_priv *priv = netdev_priv(netdev);
3058         struct mlx5e_channels new_channels = {};
3059         u8 tc = mqprio->num_tc;
3060         int err = 0;
3061
3062         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3063
3064         if (tc && tc != MLX5E_MAX_NUM_TC)
3065                 return -EINVAL;
3066
3067         mutex_lock(&priv->state_lock);
3068
3069         new_channels.params = priv->channels.params;
3070         new_channels.params.num_tc = tc ? tc : 1;
3071
3072         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3073                 priv->channels.params = new_channels.params;
3074                 goto out;
3075         }
3076
3077         err = mlx5e_open_channels(priv, &new_channels);
3078         if (err)
3079                 goto out;
3080
3081         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3082 out:
3083         mutex_unlock(&priv->state_lock);
3084         return err;
3085 }
3086
3087 #ifdef CONFIG_MLX5_ESWITCH
3088 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3089                                      struct tc_cls_flower_offload *cls_flower)
3090 {
3091         switch (cls_flower->command) {
3092         case TC_CLSFLOWER_REPLACE:
3093                 return mlx5e_configure_flower(priv, cls_flower);
3094         case TC_CLSFLOWER_DESTROY:
3095                 return mlx5e_delete_flower(priv, cls_flower);
3096         case TC_CLSFLOWER_STATS:
3097                 return mlx5e_stats_flower(priv, cls_flower);
3098         default:
3099                 return -EOPNOTSUPP;
3100         }
3101 }
3102
3103 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3104                             void *cb_priv)
3105 {
3106         struct mlx5e_priv *priv = cb_priv;
3107
3108  &n