drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include "eswitch.h"
  39 #include "en.h"
  40 #include "en_tc.h"
  41 #include "en_rep.h"
  42 #include "en_accel/ipsec.h"
  43 #include "en_accel/ipsec_rxtx.h"
  44 #include "accel/ipsec.h"
  45 #include "vxlan.h"
  46
  47 struct mlx5e_rq_param {
  48         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  49         struct mlx5_wq_param    wq;
  50 };
  51
  52 struct mlx5e_sq_param {
  53         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  54         struct mlx5_wq_param       wq;
  55 };
  56
  57 struct mlx5e_cq_param {
  58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  59         struct mlx5_wq_param       wq;
  60         u16                        eq_ix;
  61         u8                         cq_period_mode;
  62 };
  63
  64 struct mlx5e_channel_param {
  65         struct mlx5e_rq_param      rq;
  66         struct mlx5e_sq_param      sq;
  67         struct mlx5e_sq_param      xdp_sq;
  68         struct mlx5e_sq_param      icosq;
  69         struct mlx5e_cq_param      rx_cq;
  70         struct mlx5e_cq_param      tx_cq;
  71         struct mlx5e_cq_param      icosq_cq;
  72 };
  73
  74 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  75 {
  76         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  77                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  78                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  79         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  80         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  81
  82         if (!striding_rq_umr)
  83                 return false;
  84         if (!inline_umr) {
  85                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  86                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  87                 return false;
  88         }
  89         return true;
  90 }
  91
  92 static u32 mlx5e_mpwqe_get_linear_frag_sz(struct mlx5e_params *params)
  93 {
  94         if (!params->xdp_prog) {
  95                 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
  96                 u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN;
  97
  98                 return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu);
  99         }
 100
 101         return PAGE_SIZE;
 102 }
 103
 104 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 105 {
 106         u32 linear_frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
 107
 108         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 109 }
 110
 111 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 112                                          struct mlx5e_params *params)
 113 {
 114         u32 frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
 115         s8 signed_log_num_strides_param;
 116         u8 log_num_strides;
 117
 118         if (params->lro_en || frag_sz > PAGE_SIZE)
 119                 return false;
 120
 121         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 122                 return true;
 123
 124         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 125         signed_log_num_strides_param =
 126                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 127
 128         return signed_log_num_strides_param >= 0;
 129 }
 130
 131 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 132 {
 133         if (params->log_rq_mtu_frames <
 134             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 135                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 136
 137         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 138 }
 139
 140 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 141                                           struct mlx5e_params *params)
 142 {
 143         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 144                 return order_base_2(mlx5e_mpwqe_get_linear_frag_sz(params));
 145
 146         return MLX5E_MPWQE_STRIDE_SZ(mdev,
 147                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 148 }
 149
 150 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 151                                           struct mlx5e_params *params)
 152 {
 153         return MLX5_MPWRQ_LOG_WQE_SZ -
 154                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 155 }
 156
 157 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 158                                  struct mlx5e_params *params)
 159 {
 160         u16 linear_rq_headroom = params->xdp_prog ?
 161                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 162
 163         linear_rq_headroom += NET_IP_ALIGN;
 164
 165         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)
 166                 return linear_rq_headroom;
 167
 168         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 169                 return linear_rq_headroom;
 170
 171         return 0;
 172 }
 173
 174 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 175                                struct mlx5e_params *params)
 176 {
 177         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 178         params->log_rq_mtu_frames = is_kdump_kernel() ?
 179                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 180                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 181         switch (params->rq_wq_type) {
 182         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 183                 break;
 184         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 185                 /* Extra room needed for build_skb */
 186                 params->lro_wqe_sz -= mlx5e_get_rq_headroom(mdev, params) +
 187                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 188         }
 189
 190         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 191                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 192                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 193                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 194                        BIT(params->log_rq_mtu_frames),
 195                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 196                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 197 }
 198
 199 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 200                                 struct mlx5e_params *params)
 201 {
 202         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 203                 !MLX5_IPSEC_DEV(mdev) &&
 204                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 205 }
 206
 207 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 208 {
 209         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 210                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 211                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 212                 MLX5_WQ_TYPE_LINKED_LIST;
 213 }
 214
 215 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 216 {
 217         struct mlx5_core_dev *mdev = priv->mdev;
 218         u8 port_state;
 219
 220         port_state = mlx5_query_vport_state(mdev,
 221                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
 222                                             0);
 223
 224         if (port_state == VPORT_STATE_UP) {
 225                 netdev_info(priv->netdev, "Link up\n");
 226                 netif_carrier_on(priv->netdev);
 227         } else {
 228                 netdev_info(priv->netdev, "Link down\n");
 229                 netif_carrier_off(priv->netdev);
 230         }
 231 }
 232
 233 static void mlx5e_update_carrier_work(struct work_struct *work)
 234 {
 235         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 236                                                update_carrier_work);
 237
 238         mutex_lock(&priv->state_lock);
 239         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 240                 if (priv->profile->update_carrier)
 241                         priv->profile->update_carrier(priv);
 242         mutex_unlock(&priv->state_lock);
 243 }
 244
 245 void mlx5e_update_stats(struct mlx5e_priv *priv)
 246 {
 247         int i;
 248
 249         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 250                 if (mlx5e_stats_grps[i].update_stats)
 251                         mlx5e_stats_grps[i].update_stats(priv);
 252 }
 253
 254 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 255 {
 256         int i;
 257
 258         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 259                 if (mlx5e_stats_grps[i].update_stats_mask &
 260                     MLX5E_NDO_UPDATE_STATS)
 261                         mlx5e_stats_grps[i].update_stats(priv);
 262 }
 263
 264 void mlx5e_update_stats_work(struct work_struct *work)
 265 {
 266         struct delayed_work *dwork = to_delayed_work(work);
 267         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 268                                                update_stats_work);
 269         mutex_lock(&priv->state_lock);
 270         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 271                 priv->profile->update_stats(priv);
 272                 queue_delayed_work(priv->wq, dwork,
 273                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 274         }
 275         mutex_unlock(&priv->state_lock);
 276 }
 277
 278 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 279                               enum mlx5_dev_event event, unsigned long param)
 280 {
 281         struct mlx5e_priv *priv = vpriv;
 282
 283         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 284                 return;
 285
 286         switch (event) {
 287         case MLX5_DEV_EVENT_PORT_UP:
 288         case MLX5_DEV_EVENT_PORT_DOWN:
 289                 queue_work(priv->wq, &priv->update_carrier_work);
 290                 break;
 291         default:
 292                 break;
 293         }
 294 }
 295
 296 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 297 {
 298         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 299 }
 300
 301 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 302 {
 303         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 304         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 305 }
 306
 307 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 308                                        struct mlx5e_icosq *sq,
 309                                        struct mlx5e_umr_wqe *wqe,
 310                                        u16 ix)
 311 {
 312         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 313         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 314         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 315         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 316
 317         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 318                                       ds_cnt);
 319         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 320         cseg->imm       = rq->mkey_be;
 321
 322         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 323         ucseg->xlt_octowords =
 324                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 325         ucseg->bsf_octowords =
 326                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 327         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 328 }
 329
 330 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 331                                      struct mlx5e_channel *c)
 332 {
 333         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 334         int i;
 335
 336         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 337                                       GFP_KERNEL, cpu_to_node(c->cpu));
 338         if (!rq->mpwqe.info)
 339                 return -ENOMEM;
 340
 341         for (i = 0; i < wq_sz; i++) {
 342                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 343
 344                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 345         }
 346
 347         return 0;
 348 }
 349
 350 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 351                                  u64 npages, u8 page_shift,
 352                                  struct mlx5_core_mkey *umr_mkey)
 353 {
 354         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 355         void *mkc;
 356         u32 *in;
 357         int err;
 358
 359         in = kvzalloc(inlen, GFP_KERNEL);
 360         if (!in)
 361                 return -ENOMEM;
 362
 363         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 364
 365         MLX5_SET(mkc, mkc, free, 1);
 366         MLX5_SET(mkc, mkc, umr_en, 1);
 367         MLX5_SET(mkc, mkc, lw, 1);
 368         MLX5_SET(mkc, mkc, lr, 1);
 369         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
 370
 371         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 372         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 373         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 374         MLX5_SET(mkc, mkc, translations_octword_size,
 375                  MLX5_MTT_OCTW(npages));
 376         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 377
 378         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 379
 380         kvfree(in);
 381         return err;
 382 }
 383
 384 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 385 {
 386         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
 387
 388         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 389 }
 390
 391 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 392                           struct mlx5e_params *params,
 393                           struct mlx5e_rq_param *rqp,
 394                           struct mlx5e_rq *rq)
 395 {
 396         struct mlx5_core_dev *mdev = c->mdev;
 397         void *rqc = rqp->rqc;
 398         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 399         u32 byte_count;
 400         int npages;
 401         int wq_sz;
 402         int err;
 403         int i;
 404
 405         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 406
 407         err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
 408                                 &rq->wq_ctrl);
 409         if (err)
 410                 return err;
 411
 412         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 413
 414         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 415
 416         rq->wq_type = params->rq_wq_type;
 417         rq->pdev    = c->pdev;
 418         rq->netdev  = c->netdev;
 419         rq->tstamp  = c->tstamp;
 420         rq->clock   = &mdev->clock;
 421         rq->channel = c;
 422         rq->ix      = c->ix;
 423         rq->mdev    = mdev;
 424         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 425
 426         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 427         if (IS_ERR(rq->xdp_prog)) {
 428                 err = PTR_ERR(rq->xdp_prog);
 429                 rq->xdp_prog = NULL;
 430                 goto err_rq_wq_destroy;
 431         }
 432
 433         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 434         if (err < 0)
 435                 goto err_rq_wq_destroy;
 436
 437         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 438         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 439
 440         switch (rq->wq_type) {
 441         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 442                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 443                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 444
 445                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 446 #ifdef CONFIG_MLX5_EN_IPSEC
 447                 if (MLX5_IPSEC_DEV(mdev)) {
 448                         err = -EINVAL;
 449                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 450                         goto err_rq_wq_destroy;
 451                 }
 452 #endif
 453                 if (!rq->handle_rx_cqe) {
 454                         err = -EINVAL;
 455                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 456                         goto err_rq_wq_destroy;
 457                 }
 458
 459                 rq->mpwqe.skb_from_cqe_mpwrq =
 460                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 461                         mlx5e_skb_from_cqe_mpwrq_linear :
 462                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 463                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 464                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 465
 466                 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 467
 468                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 469                 if (err)
 470                         goto err_rq_wq_destroy;
 471                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 472
 473                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 474                 if (err)
 475                         goto err_destroy_umr_mkey;
 476                 break;
 477         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 478                 rq->wqe.frag_info =
 479                         kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
 480                                      GFP_KERNEL, cpu_to_node(c->cpu));
 481                 if (!rq->wqe.frag_info) {
 482                         err = -ENOMEM;
 483                         goto err_rq_wq_destroy;
 484                 }
 485                 rq->post_wqes = mlx5e_post_rx_wqes;
 486                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 487
 488 #ifdef CONFIG_MLX5_EN_IPSEC
 489                 if (c->priv->ipsec)
 490                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 491                 else
 492 #endif
 493                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 494                 if (!rq->handle_rx_cqe) {
 495                         kfree(rq->wqe.frag_info);
 496                         err = -EINVAL;
 497                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 498                         goto err_rq_wq_destroy;
 499                 }
 500
 501                 byte_count = params->lro_en  ?
 502                                 params->lro_wqe_sz :
 503                                 MLX5E_SW2HW_MTU(params, params->sw_mtu);
 504 #ifdef CONFIG_MLX5_EN_IPSEC
 505                 if (MLX5_IPSEC_DEV(mdev))
 506                         byte_count += MLX5E_METADATA_ETHER_LEN;
 507 #endif
 508                 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
 509
 510                 /* calc the required page order */
 511                 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
 512                 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
 513                 rq->buff.page_order = order_base_2(npages);
 514
 515                 byte_count |= MLX5_HW_START_PADDING;
 516                 rq->mkey_be = c->mkey_be;
 517         }
 518
 519         for (i = 0; i < wq_sz; i++) {
 520                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 521
 522                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 523                         u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
 524
 525                         wqe->data.addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 526                 }
 527
 528                 wqe->data.byte_count = cpu_to_be32(byte_count);
 529                 wqe->data.lkey = rq->mkey_be;
 530         }
 531
 532         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 533
 534         switch (params->rx_cq_moderation.cq_period_mode) {
 535         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 536                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 537                 break;
 538         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 539         default:
 540                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 541         }
 542
 543         rq->page_cache.head = 0;
 544         rq->page_cache.tail = 0;
 545
 546         return 0;
 547
 548 err_destroy_umr_mkey:
 549         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 550
 551 err_rq_wq_destroy:
 552         if (rq->xdp_prog)
 553                 bpf_prog_put(rq->xdp_prog);
 554         xdp_rxq_info_unreg(&rq->xdp_rxq);
 555         mlx5_wq_destroy(&rq->wq_ctrl);
 556
 557         return err;
 558 }
 559
 560 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 561 {
 562         int i;
 563
 564         if (rq->xdp_prog)
 565                 bpf_prog_put(rq->xdp_prog);
 566
 567         xdp_rxq_info_unreg(&rq->xdp_rxq);
 568
 569         switch (rq->wq_type) {
 570         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 571                 kfree(rq->mpwqe.info);
 572                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 573                 break;
 574         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 575                 kfree(rq->wqe.frag_info);
 576         }
 577
 578         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 579              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 580                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 581
 582                 mlx5e_page_release(rq, dma_info, false);
 583         }
 584         mlx5_wq_destroy(&rq->wq_ctrl);
 585 }
 586
 587 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 588                            struct mlx5e_rq_param *param)
 589 {
 590         struct mlx5_core_dev *mdev = rq->mdev;
 591
 592         void *in;
 593         void *rqc;
 594         void *wq;
 595         int inlen;
 596         int err;
 597
 598         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 599                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 600         in = kvzalloc(inlen, GFP_KERNEL);
 601         if (!in)
 602                 return -ENOMEM;
 603
 604         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 605         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 606
 607         memcpy(rqc, param->rqc, sizeof(param->rqc));
 608
 609         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 610         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 611         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 612                                                 MLX5_ADAPTER_PAGE_SHIFT);
 613         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 614
 615         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 616                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 617
 618         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 619
 620         kvfree(in);
 621
 622         return err;
 623 }
 624
 625 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 626                                  int next_state)
 627 {
 628         struct mlx5_core_dev *mdev = rq->mdev;
 629
 630         void *in;
 631         void *rqc;
 632         int inlen;
 633         int err;
 634
 635         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 636         in = kvzalloc(inlen, GFP_KERNEL);
 637         if (!in)
 638                 return -ENOMEM;
 639
 640         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 641
 642         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 643         MLX5_SET(rqc, rqc, state, next_state);
 644
 645         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 646
 647         kvfree(in);
 648
 649         return err;
 650 }
 651
 652 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 653 {
 654         struct mlx5e_channel *c = rq->channel;
 655         struct mlx5e_priv *priv = c->priv;
 656         struct mlx5_core_dev *mdev = priv->mdev;
 657
 658         void *in;
 659         void *rqc;
 660         int inlen;
 661         int err;
 662
 663         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 664         in = kvzalloc(inlen, GFP_KERNEL);
 665         if (!in)
 666                 return -ENOMEM;
 667
 668         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 669
 670         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 671         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 672                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 673         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 674         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 675
 676         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 677
 678         kvfree(in);
 679
 680         return err;
 681 }
 682
 683 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 684 {
 685         struct mlx5e_channel *c = rq->channel;
 686         struct mlx5_core_dev *mdev = c->mdev;
 687         void *in;
 688         void *rqc;
 689         int inlen;
 690         int err;
 691
 692         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 693         in = kvzalloc(inlen, GFP_KERNEL);
 694         if (!in)
 695                 return -ENOMEM;
 696
 697         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 698
 699         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 700         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 701                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 702         MLX5_SET(rqc, rqc, vsd, vsd);
 703         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 704
 705         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 706
 707         kvfree(in);
 708
 709         return err;
 710 }
 711
 712 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 713 {
 714         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 715 }
 716
 717 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 718 {
 719         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 720         struct mlx5e_channel *c = rq->channel;
 721
 722         struct mlx5_wq_ll *wq = &rq->wq;
 723         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
 724
 725         while (time_before(jiffies, exp_time)) {
 726                 if (wq->cur_sz >= min_wqes)
 727                         return 0;
 728
 729                 msleep(20);
 730         }
 731
 732         netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 733                     rq->rqn, wq->cur_sz, min_wqes);
 734         return -ETIMEDOUT;
 735 }
 736
 737 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 738 {
 739         struct mlx5_wq_ll *wq = &rq->wq;
 740         struct mlx5e_rx_wqe *wqe;
 741         __be16 wqe_ix_be;
 742         u16 wqe_ix;
 743
 744         /* UMR WQE (if in progress) is always at wq->head */
 745         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
 746             rq->mpwqe.umr_in_progress)
 747                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 748
 749         while (!mlx5_wq_ll_is_empty(wq)) {
 750                 wqe_ix_be = *wq->tail_next;
 751                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 752                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 753                 rq->dealloc_wqe(rq, wqe_ix);
 754                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 755                                &wqe->next.next_wqe_index);
 756         }
 757
 758         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
 759                 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
 760                  * but yet to be re-posted.
 761                  */
 762                 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 763
 764                 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
 765                         rq->dealloc_wqe(rq, wqe_ix);
 766         }
 767 }
 768
 769 static int mlx5e_open_rq(struct mlx5e_channel *c,
 770                          struct mlx5e_params *params,
 771                          struct mlx5e_rq_param *param,
 772                          struct mlx5e_rq *rq)
 773 {
 774         int err;
 775
 776         err = mlx5e_alloc_rq(c, params, param, rq);
 777         if (err)
 778                 return err;
 779
 780         err = mlx5e_create_rq(rq, param);
 781         if (err)
 782                 goto err_free_rq;
 783
 784         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 785         if (err)
 786                 goto err_destroy_rq;
 787
 788         if (params->rx_dim_enabled)
 789                 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
 790
 791         return 0;
 792
 793 err_destroy_rq:
 794         mlx5e_destroy_rq(rq);
 795 err_free_rq:
 796         mlx5e_free_rq(rq);
 797
 798         return err;
 799 }
 800
 801 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 802 {
 803         struct mlx5e_icosq *sq = &rq->channel->icosq;
 804         u16 pi = sq->pc & sq->wq.sz_m1;
 805         struct mlx5e_tx_wqe *nopwqe;
 806
 807         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 808         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 809         nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
 810         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 811 }
 812
 813 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 814 {
 815         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 816         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 817 }
 818
 819 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 820 {
 821         cancel_work_sync(&rq->dim.work);
 822         mlx5e_destroy_rq(rq);
 823         mlx5e_free_rx_descs(rq);
 824         mlx5e_free_rq(rq);
 825 }
 826
 827 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 828 {
 829         kfree(sq->db.di);
 830 }
 831
 832 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 833 {
 834         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 835
 836         sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
 837                                      GFP_KERNEL, numa);
 838         if (!sq->db.di) {
 839                 mlx5e_free_xdpsq_db(sq);
 840                 return -ENOMEM;
 841         }
 842
 843         return 0;
 844 }
 845
 846 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 847                              struct mlx5e_params *params,
 848                              struct mlx5e_sq_param *param,
 849                              struct mlx5e_xdpsq *sq)
 850 {
 851         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 852         struct mlx5_core_dev *mdev = c->mdev;
 853         int err;
 854
 855         sq->pdev      = c->pdev;
 856         sq->mkey_be   = c->mkey_be;
 857         sq->channel   = c;
 858         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 859         sq->min_inline_mode = params->tx_min_inline_mode;
 860
 861         param->wq.db_numa_node = cpu_to_node(c->cpu);
 862         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 863         if (err)
 864                 return err;
 865         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 866
 867         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 868         if (err)
 869                 goto err_sq_wq_destroy;
 870
 871         return 0;
 872
 873 err_sq_wq_destroy:
 874         mlx5_wq_destroy(&sq->wq_ctrl);
 875
 876         return err;
 877 }
 878
 879 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
 880 {
 881         mlx5e_free_xdpsq_db(sq);
 882         mlx5_wq_destroy(&sq->wq_ctrl);
 883 }
 884
 885 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
 886 {
 887         kfree(sq->db.ico_wqe);
 888 }
 889
 890 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
 891 {
 892         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 893
 894         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 895                                       GFP_KERNEL, numa);
 896         if (!sq->db.ico_wqe)
 897                 return -ENOMEM;
 898
 899         return 0;
 900 }
 901
 902 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
 903                              struct mlx5e_sq_param *param,
 904                              struct mlx5e_icosq *sq)
 905 {
 906         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 907         struct mlx5_core_dev *mdev = c->mdev;
 908         int err;
 909
 910         sq->channel   = c;
 911         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 912
 913         param->wq.db_numa_node = cpu_to_node(c->cpu);
 914         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 915         if (err)
 916                 return err;
 917         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 918
 919         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
 920         if (err)
 921                 goto err_sq_wq_destroy;
 922
 923         sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
 924
 925         return 0;
 926
 927 err_sq_wq_destroy:
 928         mlx5_wq_destroy(&sq->wq_ctrl);
 929
 930         return err;
 931 }
 932
 933 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
 934 {
 935         mlx5e_free_icosq_db(sq);
 936         mlx5_wq_destroy(&sq->wq_ctrl);
 937 }
 938
 939 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
 940 {
 941         kfree(sq->db.wqe_info);
 942         kfree(sq->db.dma_fifo);
 943 }
 944
 945 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
 946 {
 947         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 948         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 949
 950         sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
 951                                            GFP_KERNEL, numa);
 952         sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
 953                                            GFP_KERNEL, numa);
 954         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
 955                 mlx5e_free_txqsq_db(sq);
 956                 return -ENOMEM;
 957         }
 958
 959         sq->dma_fifo_mask = df_sz - 1;
 960
 961         return 0;
 962 }
 963
 964 static void mlx5e_sq_recover(struct work_struct *work);
 965 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
 966                              int txq_ix,
 967                              struct mlx5e_params *params,
 968                              struct mlx5e_sq_param *param,
 969                              struct mlx5e_txqsq *sq)
 970 {
 971         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 972         struct mlx5_core_dev *mdev = c->mdev;
 973         int err;
 974
 975         sq->pdev      = c->pdev;
 976         sq->tstamp    = c->tstamp;
 977         sq->clock     = &mdev->clock;
 978         sq->mkey_be   = c->mkey_be;
 979         sq->channel   = c;
 980         sq->txq_ix    = txq_ix;
 981         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 982         sq->min_inline_mode = params->tx_min_inline_mode;
 983         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
 984         if (MLX5_IPSEC_DEV(c->priv->mdev))
 985                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
 986
 987         param->wq.db_numa_node = cpu_to_node(c->cpu);
 988         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 989         if (err)
 990                 return err;
 991         sq->wq.db    = &sq->wq.db[MLX5_SND_DBR];
 992
 993         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
 994         if (err)
 995                 goto err_sq_wq_destroy;
 996
 997         sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 998
 999         return 0;
1000
1001 err_sq_wq_destroy:
1002         mlx5_wq_destroy(&sq->wq_ctrl);
1003
1004         return err;
1005 }
1006
1007 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1008 {
1009         mlx5e_free_txqsq_db(sq);
1010         mlx5_wq_destroy(&sq->wq_ctrl);
1011 }
1012
1013 struct mlx5e_create_sq_param {
1014         struct mlx5_wq_ctrl        *wq_ctrl;
1015         u32                         cqn;
1016         u32                         tisn;
1017         u8                          tis_lst_sz;
1018         u8                          min_inline_mode;
1019 };
1020
1021 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1022                            struct mlx5e_sq_param *param,
1023                            struct mlx5e_create_sq_param *csp,
1024                            u32 *sqn)
1025 {
1026         void *in;
1027         void *sqc;
1028         void *wq;
1029         int inlen;
1030         int err;
1031
1032         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1033                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1034         in = kvzalloc(inlen, GFP_KERNEL);
1035         if (!in)
1036                 return -ENOMEM;
1037
1038         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1039         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1040
1041         memcpy(sqc, param->sqc, sizeof(param->sqc));
1042         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1043         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1044         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1045
1046         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1047                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1048
1049         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1050         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1051
1052         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1053         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1054         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1055                                           MLX5_ADAPTER_PAGE_SHIFT);
1056         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1057
1058         mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1059
1060         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1061
1062         kvfree(in);
1063
1064         return err;
1065 }
1066
1067 struct mlx5e_modify_sq_param {
1068         int curr_state;
1069         int next_state;
1070         bool rl_update;
1071         int rl_index;
1072 };
1073
1074 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1075                            struct mlx5e_modify_sq_param *p)
1076 {
1077         void *in;
1078         void *sqc;
1079         int inlen;
1080         int err;
1081
1082         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1083         in = kvzalloc(inlen, GFP_KERNEL);
1084         if (!in)
1085                 return -ENOMEM;
1086
1087         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1088
1089         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1090         MLX5_SET(sqc, sqc, state, p->next_state);
1091         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1092                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1093                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1094         }
1095
1096         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1097
1098         kvfree(in);
1099
1100         return err;
1101 }
1102
1103 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1104 {
1105         mlx5_core_destroy_sq(mdev, sqn);
1106 }
1107
1108 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1109                                struct mlx5e_sq_param *param,
1110                                struct mlx5e_create_sq_param *csp,
1111                                u32 *sqn)
1112 {
1113         struct mlx5e_modify_sq_param msp = {0};
1114         int err;
1115
1116         err = mlx5e_create_sq(mdev, param, csp, sqn);
1117         if (err)
1118                 return err;
1119
1120         msp.curr_state = MLX5_SQC_STATE_RST;
1121         msp.next_state = MLX5_SQC_STATE_RDY;
1122         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1123         if (err)
1124                 mlx5e_destroy_sq(mdev, *sqn);
1125
1126         return err;
1127 }
1128
1129 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1130                                 struct mlx5e_txqsq *sq, u32 rate);
1131
1132 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1133                             u32 tisn,
1134                             int txq_ix,
1135                             struct mlx5e_params *params,
1136                             struct mlx5e_sq_param *param,
1137                             struct mlx5e_txqsq *sq)
1138 {
1139         struct mlx5e_create_sq_param csp = {};
1140         u32 tx_rate;
1141         int err;
1142
1143         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1144         if (err)
1145                 return err;
1146
1147         csp.tisn            = tisn;
1148         csp.tis_lst_sz      = 1;
1149         csp.cqn             = sq->cq.mcq.cqn;
1150         csp.wq_ctrl         = &sq->wq_ctrl;
1151         csp.min_inline_mode = sq->min_inline_mode;
1152         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1153         if (err)
1154                 goto err_free_txqsq;
1155
1156         tx_rate = c->priv->tx_rates[sq->txq_ix];
1157         if (tx_rate)
1158                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1159
1160         return 0;
1161
1162 err_free_txqsq:
1163         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1164         mlx5e_free_txqsq(sq);
1165
1166         return err;
1167 }
1168
1169 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1170 {
1171         WARN_ONCE(sq->cc != sq->pc,
1172                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1173                   sq->sqn, sq->cc, sq->pc);
1174         sq->cc = 0;
1175         sq->dma_fifo_cc = 0;
1176         sq->pc = 0;
1177 }
1178
1179 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1180 {
1181         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1182         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1183         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1184         netdev_tx_reset_queue(sq->txq);
1185         netif_tx_start_queue(sq->txq);
1186 }
1187
1188 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1189 {
1190         __netif_tx_lock_bh(txq);
1191         netif_tx_stop_queue(txq);
1192         __netif_tx_unlock_bh(txq);
1193 }
1194
1195 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1196 {
1197         struct mlx5e_channel *c = sq->channel;
1198
1199         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1200         /* prevent netif_tx_wake_queue */
1201         napi_synchronize(&c->napi);
1202
1203         netif_tx_disable_queue(sq->txq);
1204
1205         /* last doorbell out, godspeed .. */
1206         if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1207                 struct mlx5e_tx_wqe *nop;
1208
1209                 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1210                 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1211                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1212         }
1213 }
1214
1215 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1216 {
1217         struct mlx5e_channel *c = sq->channel;
1218         struct mlx5_core_dev *mdev = c->mdev;
1219
1220         mlx5e_destroy_sq(mdev, sq->sqn);
1221         if (sq->rate_limit)
1222                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1223         mlx5e_free_txqsq_descs(sq);
1224         mlx5e_free_txqsq(sq);
1225 }
1226
1227 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1228 {
1229         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1230
1231         while (time_before(jiffies, exp_time)) {
1232                 if (sq->cc == sq->pc)
1233                         return 0;
1234
1235                 msleep(20);
1236         }
1237
1238         netdev_err(sq->channel->netdev,
1239                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1240                    sq->sqn, sq->cc, sq->pc);
1241
1242         return -ETIMEDOUT;
1243 }
1244
1245 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1246 {
1247         struct mlx5_core_dev *mdev = sq->channel->mdev;
1248         struct net_device *dev = sq->channel->netdev;
1249         struct mlx5e_modify_sq_param msp = {0};
1250         int err;
1251
1252         msp.curr_state = curr_state;
1253         msp.next_state = MLX5_SQC_STATE_RST;
1254
1255         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1256         if (err) {
1257                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1258                 return err;
1259         }
1260
1261         memset(&msp, 0, sizeof(msp));
1262         msp.curr_state = MLX5_SQC_STATE_RST;
1263         msp.next_state = MLX5_SQC_STATE_RDY;
1264
1265         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1266         if (err) {
1267                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1268                 return err;
1269         }
1270
1271         return 0;
1272 }
1273
1274 static void mlx5e_sq_recover(struct work_struct *work)
1275 {
1276         struct mlx5e_txqsq_recover *recover =
1277                 container_of(work, struct mlx5e_txqsq_recover,
1278                              recover_work);
1279         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1280                                               recover);
1281         struct mlx5_core_dev *mdev = sq->channel->mdev;
1282         struct net_device *dev = sq->channel->netdev;
1283         u8 state;
1284         int err;
1285
1286         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1287         if (err) {
1288                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1289                            sq->sqn, err);
1290                 return;
1291         }
1292
1293         if (state != MLX5_RQC_STATE_ERR) {
1294                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1295                 return;
1296         }
1297
1298         netif_tx_disable_queue(sq->txq);
1299
1300         if (mlx5e_wait_for_sq_flush(sq))
1301                 return;
1302
1303         /* If the interval between two consecutive recovers per SQ is too
1304          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1305          * If we reached this state, there is probably a bug that needs to be
1306          * fixed. let's keep the queue close and let tx timeout cleanup.
1307          */
1308         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1309             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1310                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1311                            sq->sqn);
1312                 return;
1313         }
1314
1315         /* At this point, no new packets will arrive from the stack as TXQ is
1316          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1317          * pending WQEs.  SQ can safely reset the SQ.
1318          */
1319         if (mlx5e_sq_to_ready(sq, state))
1320                 return;
1321
1322         mlx5e_reset_txqsq_cc_pc(sq);
1323         sq->stats.recover++;
1324         recover->last_recover = jiffies;
1325         mlx5e_activate_txqsq(sq);
1326 }
1327
1328 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1329                             struct mlx5e_params *params,
1330                             struct mlx5e_sq_param *param,
1331                             struct mlx5e_icosq *sq)
1332 {
1333         struct mlx5e_create_sq_param csp = {};
1334         int err;
1335
1336         err = mlx5e_alloc_icosq(c, param, sq);
1337         if (err)
1338                 return err;
1339
1340         csp.cqn             = sq->cq.mcq.cqn;
1341         csp.wq_ctrl         = &sq->wq_ctrl;
1342         csp.min_inline_mode = params->tx_min_inline_mode;
1343         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1344         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1345         if (err)
1346                 goto err_free_icosq;
1347
1348         return 0;
1349
1350 err_free_icosq:
1351         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1352         mlx5e_free_icosq(sq);
1353
1354         return err;
1355 }
1356
1357 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1358 {
1359         struct mlx5e_channel *c = sq->channel;
1360
1361         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1362         napi_synchronize(&c->napi);
1363
1364         mlx5e_destroy_sq(c->mdev, sq->sqn);
1365         mlx5e_free_icosq(sq);
1366 }
1367
1368 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1369                             struct mlx5e_params *params,
1370                             struct mlx5e_sq_param *param,
1371                             struct mlx5e_xdpsq *sq)
1372 {
1373         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1374         struct mlx5e_create_sq_param csp = {};
1375         unsigned int inline_hdr_sz = 0;
1376         int err;
1377         int i;
1378
1379         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1380         if (err)
1381                 return err;
1382
1383         csp.tis_lst_sz      = 1;
1384         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1385         csp.cqn             = sq->cq.mcq.cqn;
1386         csp.wq_ctrl         = &sq->wq_ctrl;
1387         csp.min_inline_mode = sq->min_inline_mode;
1388         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1389         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1390         if (err)
1391                 goto err_free_xdpsq;
1392
1393         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1394                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1395                 ds_cnt++;
1396         }
1397
1398         /* Pre initialize fixed WQE fields */
1399         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1400                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1401                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1402                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1403                 struct mlx5_wqe_data_seg *dseg;
1404
1405                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1406                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1407
1408                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1409                 dseg->lkey = sq->mkey_be;
1410         }
1411
1412         return 0;
1413
1414 err_free_xdpsq:
1415         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1416         mlx5e_free_xdpsq(sq);
1417
1418         return err;
1419 }
1420
1421 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1422 {
1423         struct mlx5e_channel *c = sq->channel;
1424
1425         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1426         napi_synchronize(&c->napi);
1427
1428         mlx5e_destroy_sq(c->mdev, sq->sqn);
1429         mlx5e_free_xdpsq_descs(sq);
1430         mlx5e_free_xdpsq(sq);
1431 }
1432
1433 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1434                                  struct mlx5e_cq_param *param,
1435                                  struct mlx5e_cq *cq)
1436 {
1437         struct mlx5_core_cq *mcq = &cq->mcq;
1438         int eqn_not_used;
1439         unsigned int irqn;
1440         int err;
1441         u32 i;
1442
1443         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1444                                &cq->wq_ctrl);
1445         if (err)
1446                 return err;
1447
1448         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1449
1450         mcq->cqe_sz     = 64;
1451         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1452         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1453         *mcq->set_ci_db = 0;
1454         *mcq->arm_db    = 0;
1455         mcq->vector     = param->eq_ix;
1456         mcq->comp       = mlx5e_completion_event;
1457         mcq->event      = mlx5e_cq_error_event;
1458         mcq->irqn       = irqn;
1459
1460         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1461                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1462
1463                 cqe->op_own = 0xf1;
1464         }
1465
1466         cq->mdev = mdev;
1467
1468         return 0;
1469 }
1470
1471 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1472                           struct mlx5e_cq_param *param,
1473                           struct mlx5e_cq *cq)
1474 {
1475         struct mlx5_core_dev *mdev = c->priv->mdev;
1476         int err;
1477
1478         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1479         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1480         param->eq_ix   = c->ix;
1481
1482         err = mlx5e_alloc_cq_common(mdev, param, cq);
1483
1484         cq->napi    = &c->napi;
1485         cq->channel = c;
1486
1487         return err;
1488 }
1489
1490 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1491 {
1492         mlx5_cqwq_destroy(&cq->wq_ctrl);
1493 }
1494
1495 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1496 {
1497         struct mlx5_core_dev *mdev = cq->mdev;
1498         struct mlx5_core_cq *mcq = &cq->mcq;
1499
1500         void *in;
1501         void *cqc;
1502         int inlen;
1503         unsigned int irqn_not_used;
1504         int eqn;
1505         int err;
1506
1507         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1508                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1509         in = kvzalloc(inlen, GFP_KERNEL);
1510         if (!in)
1511                 return -ENOMEM;
1512
1513         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1514
1515         memcpy(cqc, param->cqc, sizeof(param->cqc));
1516
1517         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1518                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1519
1520         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1521
1522         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1523         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1524         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1525         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1526                                             MLX5_ADAPTER_PAGE_SHIFT);
1527         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1528
1529         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1530
1531         kvfree(in);
1532
1533         if (err)
1534                 return err;
1535
1536         mlx5e_cq_arm(cq);
1537
1538         return 0;
1539 }
1540
1541 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1542 {
1543         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1544 }
1545
1546 static int mlx5e_open_cq(struct mlx5e_channel *c,
1547                          struct net_dim_cq_moder moder,
1548                          struct mlx5e_cq_param *param,
1549                          struct mlx5e_cq *cq)
1550 {
1551         struct mlx5_core_dev *mdev = c->mdev;
1552         int err;
1553
1554         err = mlx5e_alloc_cq(c, param, cq);
1555         if (err)
1556                 return err;
1557
1558         err = mlx5e_create_cq(cq, param);
1559         if (err)
1560                 goto err_free_cq;
1561
1562         if (MLX5_CAP_GEN(mdev, cq_moderation))
1563                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1564         return 0;
1565
1566 err_free_cq:
1567         mlx5e_free_cq(cq);
1568
1569         return err;
1570 }
1571
1572 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1573 {
1574         mlx5e_destroy_cq(cq);
1575         mlx5e_free_cq(cq);
1576 }
1577
1578 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1579 {
1580         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1581 }
1582
1583 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1584                              struct mlx5e_params *params,
1585                              struct mlx5e_channel_param *cparam)
1586 {
1587         int err;
1588         int tc;
1589
1590         for (tc = 0; tc < c->num_tc; tc++) {
1591                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1592                                     &cparam->tx_cq, &c->sq[tc].cq);
1593                 if (err)
1594                         goto err_close_tx_cqs;
1595         }
1596
1597         return 0;
1598
1599 err_close_tx_cqs:
1600         for (tc--; tc >= 0; tc--)
1601                 mlx5e_close_cq(&c->sq[tc].cq);
1602
1603         return err;
1604 }
1605
1606 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1607 {
1608         int tc;
1609
1610         for (tc = 0; tc < c->num_tc; tc++)
1611                 mlx5e_close_cq(&c->sq[tc].cq);
1612 }
1613
1614 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1615                           struct mlx5e_params *params,
1616                           struct mlx5e_channel_param *cparam)
1617 {
1618         int err;
1619         int tc;
1620
1621         for (tc = 0; tc < params->num_tc; tc++) {
1622                 int txq_ix = c->ix + tc * params->num_channels;
1623
1624                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1625                                        params, &cparam->sq, &c->sq[tc]);
1626                 if (err)
1627                         goto err_close_sqs;
1628         }
1629
1630         return 0;
1631
1632 err_close_sqs:
1633         for (tc--; tc >= 0; tc--)
1634                 mlx5e_close_txqsq(&c->sq[tc]);
1635
1636         return err;
1637 }
1638
1639 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1640 {
1641         int tc;
1642
1643         for (tc = 0; tc < c->num_tc; tc++)
1644                 mlx5e_close_txqsq(&c->sq[tc]);
1645 }
1646
1647 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1648                                 struct mlx5e_txqsq *sq, u32 rate)
1649 {
1650         struct mlx5e_priv *priv = netdev_priv(dev);
1651         struct mlx5_core_dev *mdev = priv->mdev;
1652         struct mlx5e_modify_sq_param msp = {0};
1653         u16 rl_index = 0;
1654         int err;
1655
1656         if (rate == sq->rate_limit)
1657                 /* nothing to do */
1658                 return 0;
1659
1660         if (sq->rate_limit)
1661                 /* remove current rl index to free space to next ones */
1662                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1663
1664         sq->rate_limit = 0;
1665
1666         if (rate) {
1667                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1668                 if (err) {
1669                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1670                                    rate, err);
1671                         return err;
1672                 }
1673         }
1674
1675         msp.curr_state = MLX5_SQC_STATE_RDY;
1676         msp.next_state = MLX5_SQC_STATE_RDY;
1677         msp.rl_index   = rl_index;
1678         msp.rl_update  = true;
1679         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1680         if (err) {
1681                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1682                            rate, err);
1683                 /* remove the rate from the table */
1684                 if (rate)
1685                         mlx5_rl_remove_rate(mdev, rate);
1686                 return err;
1687         }
1688
1689         sq->rate_limit = rate;
1690         return 0;
1691 }
1692
1693 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1694 {
1695         struct mlx5e_priv *priv = netdev_priv(dev);
1696         struct mlx5_core_dev *mdev = priv->mdev;
1697         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1698         int err = 0;
1699
1700         if (!mlx5_rl_is_supported(mdev)) {
1701                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1702                 return -EINVAL;
1703         }
1704
1705         /* rate is given in Mb/sec, HW config is in Kb/sec */
1706         rate = rate << 10;
1707
1708         /* Check whether rate in valid range, 0 is always valid */
1709         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1710                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1711                 return -ERANGE;
1712         }
1713
1714         mutex_lock(&priv->state_lock);
1715         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1716                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1717         if (!err)
1718                 priv->tx_rates[index] = rate;
1719         mutex_unlock(&priv->state_lock);
1720
1721         return err;
1722 }
1723
1724 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1725                               struct mlx5e_params *params,
1726                               struct mlx5e_channel_param *cparam,
1727                               struct mlx5e_channel **cp)
1728 {
1729         struct net_dim_cq_moder icocq_moder = {0, 0};
1730         struct net_device *netdev = priv->netdev;
1731         int cpu = mlx5e_get_cpu(priv, ix);
1732         struct mlx5e_channel *c;
1733         unsigned int irq;
1734         int err;
1735         int eqn;
1736
1737         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1738         if (!c)
1739                 return -ENOMEM;
1740
1741         c->priv     = priv;
1742         c->mdev     = priv->mdev;
1743         c->tstamp   = &priv->tstamp;
1744         c->ix       = ix;
1745         c->cpu      = cpu;
1746         c->pdev     = &priv->mdev->pdev->dev;
1747         c->netdev   = priv->netdev;
1748         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1749         c->num_tc   = params->num_tc;
1750         c->xdp      = !!params->xdp_prog;
1751
1752         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1753         c->irq_desc = irq_to_desc(irq);
1754
1755         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1756
1757         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1758         if (err)
1759                 goto err_napi_del;
1760
1761         err = mlx5e_open_tx_cqs(c, params, cparam);
1762         if (err)
1763                 goto err_close_icosq_cq;
1764
1765         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1766         if (err)
1767                 goto err_close_tx_cqs;
1768
1769         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1770         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1771                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1772         if (err)
1773                 goto err_close_rx_cq;
1774
1775         napi_enable(&c->napi);
1776
1777         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1778         if (err)
1779                 goto err_disable_napi;
1780
1781         err = mlx5e_open_sqs(c, params, cparam);
1782         if (err)
1783                 goto err_close_icosq;
1784
1785         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1786         if (err)
1787                 goto err_close_sqs;
1788
1789         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1790         if (err)
1791                 goto err_close_xdp_sq;
1792
1793         *cp = c;
1794
1795         return 0;
1796 err_close_xdp_sq:
1797         if (c->xdp)
1798                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1799
1800 err_close_sqs:
1801         mlx5e_close_sqs(c);
1802
1803 err_close_icosq:
1804         mlx5e_close_icosq(&c->icosq);
1805
1806 err_disable_napi:
1807         napi_disable(&c->napi);
1808         if (c->xdp)
1809                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1810
1811 err_close_rx_cq:
1812         mlx5e_close_cq(&c->rq.cq);
1813
1814 err_close_tx_cqs:
1815         mlx5e_close_tx_cqs(c);
1816
1817 err_close_icosq_cq:
1818         mlx5e_close_cq(&c->icosq.cq);
1819
1820 err_napi_del:
1821         netif_napi_del(&c->napi);
1822         kfree(c);
1823
1824         return err;
1825 }
1826
1827 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1828 {
1829         int tc;
1830
1831         for (tc = 0; tc < c->num_tc; tc++)
1832                 mlx5e_activate_txqsq(&c->sq[tc]);
1833         mlx5e_activate_rq(&c->rq);
1834         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1835 }
1836
1837 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1838 {
1839         int tc;
1840
1841         mlx5e_deactivate_rq(&c->rq);
1842         for (tc = 0; tc < c->num_tc; tc++)
1843                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1844 }
1845
1846 static void mlx5e_close_channel(struct mlx5e_channel *c)
1847 {
1848         mlx5e_close_rq(&c->rq);
1849         if (c->xdp)
1850                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1851         mlx5e_close_sqs(c);
1852         mlx5e_close_icosq(&c->icosq);
1853         napi_disable(&c->napi);
1854         if (c->xdp)
1855                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1856         mlx5e_close_cq(&c->rq.cq);
1857         mlx5e_close_tx_cqs(c);
1858         mlx5e_close_cq(&c->icosq.cq);
1859         netif_napi_del(&c->napi);
1860
1861         kfree(c);
1862 }
1863
1864 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1865                                  struct mlx5e_params *params,
1866                                  struct mlx5e_rq_param *param)
1867 {
1868         struct mlx5_core_dev *mdev = priv->mdev;
1869         void *rqc = param->rqc;
1870         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1871
1872         switch (params->rq_wq_type) {
1873         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1874                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1875                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
1876                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
1877                 MLX5_SET(wq, wq, log_wqe_stride_size,
1878                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
1879                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
1880                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1881                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
1882                 break;
1883         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1884                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1885                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
1886         }
1887
1888         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1889         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1890         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
1891         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1892         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
1893         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
1894
1895         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1896         param->wq.linear = 1;
1897 }
1898
1899 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
1900                                       struct mlx5e_rq_param *param)
1901 {
1902         struct mlx5_core_dev *mdev = priv->mdev;
1903         void *rqc = param->rqc;
1904         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1905
1906         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1907         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1908         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
1909
1910         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1911 }
1912
1913 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1914                                         struct mlx5e_sq_param *param)
1915 {
1916         void *sqc = param->sqc;
1917         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1918
1919         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1920         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1921
1922         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1923 }
1924
1925 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1926                                  struct mlx5e_params *params,
1927                                  struct mlx5e_sq_param *param)
1928 {
1929         void *sqc = param->sqc;
1930         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1931
1932         mlx5e_build_sq_param_common(priv, param);
1933         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1934         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1935 }
1936
1937 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1938                                         struct mlx5e_cq_param *param)
1939 {
1940         void *cqc = param->cqc;
1941
1942         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1943 }
1944
1945 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1946                                     struct mlx5e_params *params,
1947                                     struct mlx5e_cq_param *param)
1948 {
1949         struct mlx5_core_dev *mdev = priv->mdev;
1950         void *cqc = param->cqc;
1951         u8 log_cq_size;
1952
1953         switch (params->rq_wq_type) {
1954         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1955                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
1956                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
1957                 break;
1958         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1959                 log_cq_size = params->log_rq_mtu_frames;
1960         }
1961
1962         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1963         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1964                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1965                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1966         }
1967
1968         mlx5e_build_common_cq_param(priv, param);
1969         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
1970 }
1971
1972 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1973                                     struct mlx5e_params *params,
1974                                     struct mlx5e_cq_param *param)
1975 {
1976         void *cqc = param->cqc;
1977
1978         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1979
1980         mlx5e_build_common_cq_param(priv, param);
1981         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
1982 }
1983
1984 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1985                                      u8 log_wq_size,
1986                                      struct mlx5e_cq_param *param)
1987 {
1988         void *cqc = param->cqc;
1989
1990         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1991
1992         mlx5e_build_common_cq_param(priv, param);
1993
1994         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1995 }
1996
1997 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1998                                     u8 log_wq_size,
1999                                     struct mlx5e_sq_param *param)
2000 {
2001         void *sqc = param->sqc;
2002         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2003
2004         mlx5e_build_sq_param_common(priv, param);
2005
2006         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2007         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2008 }
2009
2010 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2011                                     struct mlx5e_params *params,
2012                                     struct mlx5e_sq_param *param)
2013 {
2014         void *sqc = param->sqc;
2015         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2016
2017         mlx5e_build_sq_param_common(priv, param);
2018         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2019 }
2020
2021 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2022                                       struct mlx5e_params *params,
2023                                       struct mlx5e_channel_param *cparam)
2024 {
2025         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2026
2027         mlx5e_build_rq_param(priv, params, &cparam->rq);
2028         mlx5e_build_sq_param(priv, params, &cparam->sq);
2029         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2030         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2031         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2032         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2033         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2034 }
2035
2036 int mlx5e_open_channels(struct mlx5e_priv *priv,
2037                         struct mlx5e_channels *chs)
2038 {
2039         struct mlx5e_channel_param *cparam;
2040         int err = -ENOMEM;
2041         int i;
2042
2043         chs->num = chs->params.num_channels;
2044
2045         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2046         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2047         if (!chs->c || !cparam)
2048                 goto err_free;
2049
2050         mlx5e_build_channel_param(priv, &chs->params, cparam);
2051         for (i = 0; i < chs->num; i++) {
2052                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2053                 if (err)
2054                         goto err_close_channels;
2055         }
2056
2057         kfree(cparam);
2058         return 0;
2059
2060 err_close_channels:
2061         for (i--; i >= 0; i--)
2062                 mlx5e_close_channel(chs->c[i]);
2063
2064 err_free:
2065         kfree(chs->c);
2066         kfree(cparam);
2067         chs->num = 0;
2068         return err;
2069 }
2070
2071 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2072 {
2073         int i;
2074
2075         for (i = 0; i < chs->num; i++)
2076                 mlx5e_activate_channel(chs->c[i]);
2077 }
2078
2079 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2080 {
2081         int err = 0;
2082         int i;
2083
2084         for (i = 0; i < chs->num; i++) {
2085                 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2086                 if (err)
2087                         break;
2088         }
2089
2090         return err;
2091 }
2092
2093 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2094 {
2095         int i;
2096
2097         for (i = 0; i < chs->num; i++)
2098                 mlx5e_deactivate_channel(chs->c[i]);
2099 }
2100
2101 void mlx5e_close_channels(struct mlx5e_channels *chs)
2102 {
2103         int i;
2104
2105         for (i = 0; i < chs->num; i++)
2106                 mlx5e_close_channel(chs->c[i]);
2107
2108         kfree(chs->c);
2109         chs->num = 0;
2110 }
2111
2112 static int
2113 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2114 {
2115         struct mlx5_core_dev *mdev = priv->mdev;
2116         void *rqtc;
2117         int inlen;
2118         int err;
2119         u32 *in;
2120         int i;
2121
2122         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2123         in = kvzalloc(inlen, GFP_KERNEL);
2124         if (!in)
2125                 return -ENOMEM;
2126
2127         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2128
2129         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2130         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2131
2132         for (i = 0; i < sz; i++)
2133                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2134
2135         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2136         if (!err)
2137                 rqt->enabled = true;
2138
2139         kvfree(in);
2140         return err;
2141 }
2142
2143 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2144 {
2145         rqt->enabled = false;
2146         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2147 }
2148
2149 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2150 {
2151         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2152         int err;
2153
2154         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2155         if (err)
2156                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2157         return err;
2158 }
2159
2160 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2161 {
2162         struct mlx5e_rqt *rqt;
2163         int err;
2164         int ix;
2165
2166         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2167                 rqt = &priv->direct_tir[ix].rqt;
2168                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2169                 if (err)
2170                         goto err_destroy_rqts;
2171         }
2172
2173         return 0;
2174
2175 err_destroy_rqts:
2176         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2177         for (ix--; ix >= 0; ix--)
2178                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2179
2180         return err;
2181 }
2182
2183 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2184 {
2185         int i;
2186
2187         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2188                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2189 }
2190
2191 static int mlx5e_rx_hash_fn(int hfunc)
2192 {
2193         return (hfunc == ETH_RSS_HASH_TOP) ?
2194                MLX5_RX_HASH_FN_TOEPLITZ :
2195                MLX5_RX_HASH_FN_INVERTED_XOR8;
2196 }
2197
2198 int mlx5e_bits_invert(unsigned long a, int size)
2199 {
2200         int inv = 0;
2201         int i;
2202
2203         for (i = 0; i < size; i++)
2204                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2205
2206         return inv;
2207 }
2208
2209 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2210                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2211 {
2212         int i;
2213
2214         for (i = 0; i < sz; i++) {
2215                 u32 rqn;
2216
2217                 if (rrp.is_rss) {
2218                         int ix = i;
2219
2220                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2221                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2222
2223                         ix = priv->channels.params.indirection_rqt[ix];
2224                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2225                 } else {
2226                         rqn = rrp.rqn;
2227                 }
2228                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2229         }
2230 }
2231
2232 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2233                        struct mlx5e_redirect_rqt_param rrp)
2234 {
2235         struct mlx5_core_dev *mdev = priv->mdev;
2236         void *rqtc;
2237         int inlen;
2238         u32 *in;
2239         int err;
2240
2241         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2242         in = kvzalloc(inlen, GFP_KERNEL);
2243         if (!in)
2244                 return -ENOMEM;
2245
2246         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2247
2248         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2249         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2250         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2251         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2252
2253         kvfree(in);
2254         return err;
2255 }
2256
2257 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2258                                 struct mlx5e_redirect_rqt_param rrp)
2259 {
2260         if (!rrp.is_rss)
2261                 return rrp.rqn;
2262
2263         if (ix >= rrp.rss.channels->num)
2264                 return priv->drop_rq.rqn;
2265
2266         return rrp.rss.channels->c[ix]->rq.rqn;
2267 }
2268
2269 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2270                                 struct mlx5e_redirect_rqt_param rrp)
2271 {
2272         u32 rqtn;
2273         int ix;
2274
2275         if (priv->indir_rqt.enabled) {
2276                 /* RSS RQ table */
2277                 rqtn = priv->indir_rqt.rqtn;
2278                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2279         }
2280
2281         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2282                 struct mlx5e_redirect_rqt_param direct_rrp = {
2283                         .is_rss = false,
2284                         {
2285                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2286                         },
2287                 };
2288
2289                 /* Direct RQ Tables */
2290                 if (!priv->direct_tir[ix].rqt.enabled)
2291                         continue;
2292
2293                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2294                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2295         }
2296 }
2297
2298 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2299                                             struct mlx5e_channels *chs)
2300 {
2301         struct mlx5e_redirect_rqt_param rrp = {
2302                 .is_rss        = true,
2303                 {
2304                         .rss = {
2305                                 .channels  = chs,
2306                                 .hfunc     = chs->params.rss_hfunc,
2307                         }
2308                 },
2309         };
2310
2311         mlx5e_redirect_rqts(priv, rrp);
2312 }
2313
2314 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2315 {
2316         struct mlx5e_redirect_rqt_param drop_rrp = {
2317                 .is_rss = false,
2318                 {
2319                         .rqn = priv->drop_rq.rqn,
2320                 },
2321         };
2322
2323         mlx5e_redirect_rqts(priv, drop_rrp);
2324 }
2325
2326 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2327 {
2328         if (!params->lro_en)
2329                 return;
2330
2331 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2332
2333         MLX5_SET(tirc, tirc, lro_enable_mask,
2334                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2335                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2336         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2337                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2338         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2339 }
2340
2341 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2342                                     enum mlx5e_traffic_types tt,
2343                                     void *tirc, bool inner)
2344 {
2345         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2346                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2347
2348 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2349                                  MLX5_HASH_FIELD_SEL_DST_IP)
2350
2351 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2352                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2353                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2354                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2355
2356 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2357                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2358                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2359
2360         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2361         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2362                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2363                                              rx_hash_toeplitz_key);
2364                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2365                                                rx_hash_toeplitz_key);
2366
2367                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2368                 memcpy(rss_key, params->toeplitz_hash_key, len);
2369         }
2370
2371         switch (tt) {
2372         case MLX5E_TT_IPV4_TCP:
2373                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2374                          MLX5_L3_PROT_TYPE_IPV4);
2375                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2376                          MLX5_L4_PROT_TYPE_TCP);
2377                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2378                          MLX5_HASH_IP_L4PORTS);
2379                 break;
2380
2381         case MLX5E_TT_IPV6_TCP:
2382                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2383                          MLX5_L3_PROT_TYPE_IPV6);
2384                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2385                          MLX5_L4_PROT_TYPE_TCP);
2386                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2387                          MLX5_HASH_IP_L4PORTS);
2388                 break;
2389
2390         case MLX5E_TT_IPV4_UDP:
2391                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2392                          MLX5_L3_PROT_TYPE_IPV4);
2393                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2394                          MLX5_L4_PROT_TYPE_UDP);
2395                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2396                          MLX5_HASH_IP_L4PORTS);
2397                 break;
2398
2399         case MLX5E_TT_IPV6_UDP:
2400                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2401                          MLX5_L3_PROT_TYPE_IPV6);
2402                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2403                          MLX5_L4_PROT_TYPE_UDP);
2404                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2405                          MLX5_HASH_IP_L4PORTS);
2406                 break;
2407
2408         case MLX5E_TT_IPV4_IPSEC_AH:
2409                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2410                          MLX5_L3_PROT_TYPE_IPV4);
2411                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2412                          MLX5_HASH_IP_IPSEC_SPI);
2413                 break;
2414
2415         case MLX5E_TT_IPV6_IPSEC_AH:
2416                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2417                          MLX5_L3_PROT_TYPE_IPV6);
2418                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2419                          MLX5_HASH_IP_IPSEC_SPI);
2420                 break;
2421
2422         case MLX5E_TT_IPV4_IPSEC_ESP:
2423                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2424                          MLX5_L3_PROT_TYPE_IPV4);
2425                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2426                          MLX5_HASH_IP_IPSEC_SPI);
2427                 break;
2428
2429         case MLX5E_TT_IPV6_IPSEC_ESP:
2430                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2431                          MLX5_L3_PROT_TYPE_IPV6);
2432                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2433                          MLX5_HASH_IP_IPSEC_SPI);
2434                 break;
2435
2436         case MLX5E_TT_IPV4:
2437                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2438                          MLX5_L3_PROT_TYPE_IPV4);
2439                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2440                          MLX5_HASH_IP);
2441                 break;
2442
2443         case MLX5E_TT_IPV6:
2444                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2445                          MLX5_L3_PROT_TYPE_IPV6);
2446                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2447                          MLX5_HASH_IP);
2448                 break;
2449         default:
2450                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2451         }
2452 }
2453
2454 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2455 {
2456         struct mlx5_core_dev *mdev = priv->mdev;
2457
2458         void *in;
2459         void *tirc;
2460         int inlen;
2461         int err;
2462         int tt;
2463         int ix;
2464
2465         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2466         in = kvzalloc(inlen, GFP_KERNEL);
2467         if (!in)
2468                 return -ENOMEM;
2469
2470         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2471         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2472
2473         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2474
2475         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2476                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2477                                            inlen);
2478                 if (err)
2479                         goto free_in;
2480         }
2481
2482         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2483                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2484                                            in, inlen);
2485                 if (err)
2486                         goto free_in;
2487         }
2488
2489 free_in:
2490         kvfree(in);
2491
2492         return err;
2493 }
2494
2495 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2496                                             enum mlx5e_traffic_types tt,
2497                                             u32 *tirc)
2498 {
2499         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2500
2501         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2502
2503         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2504         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2505         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2506
2507         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2508 }
2509
2510 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2511                          struct mlx5e_params *params, u16 mtu)
2512 {
2513         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2514         int err;
2515
2516         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2517         if (err)
2518                 return err;
2519
2520         /* Update vport context MTU */
2521         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2522         return 0;
2523 }
2524
2525 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2526                             struct mlx5e_params *params, u16 *mtu)
2527 {
2528         u16 hw_mtu = 0;
2529         int err;
2530
2531         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2532         if (err || !hw_mtu) /* fallback to port oper mtu */
2533                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2534
2535         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2536 }
2537
2538 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2539 {
2540         struct mlx5e_params *params = &priv->channels.params;
2541         struct net_device *netdev = priv->netdev;
2542         struct mlx5_core_dev *mdev = priv->mdev;
2543         u16 mtu;
2544         int err;
2545
2546         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2547         if (err)
2548                 return err;
2549
2550         mlx5e_query_mtu(mdev, params, &mtu);
2551         if (mtu != params->sw_mtu)
2552                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2553                             __func__, mtu, params->sw_mtu);
2554
2555         params->sw_mtu = mtu;
2556         return 0;
2557 }
2558
2559 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2560 {
2561         struct mlx5e_priv *priv = netdev_priv(netdev);
2562         int nch = priv->channels.params.num_channels;
2563         int ntc = priv->channels.params.num_tc;
2564         int tc;
2565
2566         netdev_reset_tc(netdev);
2567
2568         if (ntc == 1)
2569                 return;
2570
2571         netdev_set_num_tc(netdev, ntc);
2572
2573         /* Map netdev TCs to offset 0
2574          * We have our own UP to TXQ mapping for QoS
2575          */
2576         for (tc = 0; tc < ntc; tc++)
2577                 netdev_set_tc_queue(netdev, tc, nch, 0);
2578 }
2579
2580 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2581 {
2582         struct mlx5e_channel *c;
2583         struct mlx5e_txqsq *sq;
2584         int i, tc;
2585
2586         for (i = 0; i < priv->channels.num; i++)
2587                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2588                         priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2589
2590         for (i = 0; i < priv->channels.num; i++) {
2591                 c = priv->channels.c[i];
2592                 for (tc = 0; tc < c->num_tc; tc++) {
2593                         sq = &c->sq[tc];
2594                         priv->txq2sq[sq->txq_ix] = sq;
2595                 }
2596         }
2597 }
2598
2599 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2600 {
2601         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2602         struct net_device *netdev = priv->netdev;
2603
2604         mlx5e_netdev_set_tcs(netdev);
2605         netif_set_real_num_tx_queues(netdev, num_txqs);
2606         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2607
2608         mlx5e_build_channels_tx_maps(priv);
2609         mlx5e_activate_channels(&priv->channels);
2610         netif_tx_start_all_queues(priv->netdev);
2611
2612         if (MLX5_VPORT_MANAGER(priv->mdev))
2613                 mlx5e_add_sqs_fwd_rules(priv);
2614
2615         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2616         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2617 }
2618
2619 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2620 {
2621         mlx5e_redirect_rqts_to_drop(priv);
2622
2623         if (MLX5_VPORT_MANAGER(priv->mdev))
2624                 mlx5e_remove_sqs_fwd_rules(priv);
2625
2626         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2627          * polling for inactive tx queues.
2628          */
2629         netif_tx_stop_all_queues(priv->netdev);
2630         netif_tx_disable(priv->netdev);
2631         mlx5e_deactivate_channels(&priv->channels);
2632 }
2633
2634 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2635                                 struct mlx5e_channels *new_chs,
2636                                 mlx5e_fp_hw_modify hw_modify)
2637 {
2638         struct net_device *netdev = priv->netdev;
2639         int new_num_txqs;
2640         int carrier_ok;
2641         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2642
2643         carrier_ok = netif_carrier_ok(netdev);
2644         netif_carrier_off(netdev);
2645
2646         if (new_num_txqs < netdev->real_num_tx_queues)
2647                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2648
2649         mlx5e_deactivate_priv_channels(priv);
2650         mlx5e_close_channels(&priv->channels);
2651
2652         priv->channels = *new_chs;
2653
2654         /* New channels are ready to roll, modify HW settings if needed */
2655         if (hw_modify)
2656                 hw_modify(priv);
2657
2658         mlx5e_refresh_tirs(priv, false);
2659         mlx5e_activate_priv_channels(priv);
2660
2661         /* return carrier back if needed */
2662         if (carrier_ok)
2663                 netif_carrier_on(netdev);
2664 }
2665
2666 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2667 {
2668         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2669         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2670 }
2671
2672 int mlx5e_open_locked(struct net_device *netdev)
2673 {
2674         struct mlx5e_priv *priv = netdev_priv(netdev);
2675         int err;
2676
2677         set_bit(MLX5E_STATE_OPENED, &priv->state);
2678
2679         err = mlx5e_open_channels(priv, &priv->channels);
2680         if (err)
2681                 goto err_clear_state_opened_flag;
2682
2683         mlx5e_refresh_tirs(priv, false);
2684         mlx5e_activate_priv_channels(priv);
2685         if (priv->profile->update_carrier)
2686                 priv->profile->update_carrier(priv);
2687
2688         if (priv->profile->update_stats)
2689                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2690
2691         return 0;
2692
2693 err_clear_state_opened_flag:
2694         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2695         return err;
2696 }
2697
2698 int mlx5e_open(struct net_device *netdev)
2699 {
2700         struct mlx5e_priv *priv = netdev_priv(netdev);
2701         int err;
2702
2703         mutex_lock(&priv->state_lock);
2704         err = mlx5e_open_locked(netdev);
2705         if (!err)
2706                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2707         mutex_unlock(&priv->state_lock);
2708
2709         return err;
2710 }
2711
2712 int mlx5e_close_locked(struct net_device *netdev)
2713 {
2714         struct mlx5e_priv *priv = netdev_priv(netdev);
2715
2716         /* May already be CLOSED in case a previous configuration operation
2717          * (e.g RX/TX queue size change) that involves close&open failed.
2718          */
2719         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2720                 return 0;
2721
2722         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2723
2724         netif_carrier_off(priv->netdev);
2725         mlx5e_deactivate_priv_channels(priv);
2726         mlx5e_close_channels(&priv->channels);
2727
2728         return 0;
2729 }
2730
2731 int mlx5e_close(struct net_device *netdev)
2732 {
2733         struct mlx5e_priv *priv = netdev_priv(netdev);
2734         int err;
2735
2736         if (!netif_device_present(netdev))
2737                 return -ENODEV;
2738
2739         mutex_lock(&priv->state_lock);
2740         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2741         err = mlx5e_close_locked(netdev);
2742         mutex_unlock(&priv->state_lock);
2743
2744         return err;
2745 }
2746
2747 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2748                                struct mlx5e_rq *rq,
2749                                struct mlx5e_rq_param *param)
2750 {
2751         void *rqc = param->rqc;
2752         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2753         int err;
2754
2755         param->wq.db_numa_node = param->wq.buf_numa_node;
2756
2757         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2758                                 &rq->wq_ctrl);
2759         if (err)
2760                 return err;
2761
2762         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2763         xdp_rxq_info_unused(&rq->xdp_rxq);
2764
2765         rq->mdev = mdev;
2766
2767         return 0;
2768 }
2769
2770 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2771                                struct mlx5e_cq *cq,
2772                                struct mlx5e_cq_param *param)
2773 {
2774         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2775         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
2776
2777         return mlx5e_alloc_cq_common(mdev, param, cq);
2778 }
2779
2780 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2781                               struct mlx5e_rq *drop_rq)
2782 {
2783         struct mlx5_core_dev *mdev = priv->mdev;
2784         struct mlx5e_cq_param cq_param = {};
2785         struct mlx5e_rq_param rq_param = {};
2786         struct mlx5e_cq *cq = &drop_rq->cq;
2787         int err;
2788
2789         mlx5e_build_drop_rq_param(priv, &rq_param);
2790
2791         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2792         if (err)
2793                 return err;
2794
2795         err = mlx5e_create_cq(cq, &cq_param);
2796         if (err)
2797                 goto err_free_cq;
2798
2799         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2800         if (err)
2801                 goto err_destroy_cq;
2802
2803         err = mlx5e_create_rq(drop_rq, &rq_param);
2804         if (err)
2805                 goto err_free_rq;
2806
2807         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2808         if (err)
2809                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2810
2811         return 0;
2812
2813 err_free_rq:
2814         mlx5e_free_rq(drop_rq);
2815
2816 err_destroy_cq:
2817         mlx5e_destroy_cq(cq);
2818
2819 err_free_cq:
2820         mlx5e_free_cq(cq);
2821
2822         return err;
2823 }
2824
2825 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2826 {
2827         mlx5e_destroy_rq(drop_rq);
2828         mlx5e_free_rq(drop_rq);
2829         mlx5e_destroy_cq(&drop_rq->cq);
2830         mlx5e_free_cq(&drop_rq->cq);
2831 }
2832
2833 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2834                      u32 underlay_qpn, u32 *tisn)
2835 {
2836         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2837         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2838
2839         MLX5_SET(tisc, tisc, prio, tc << 1);
2840         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2841         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2842
2843         if (mlx5_lag_is_lacp_owner(mdev))
2844                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2845
2846         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2847 }
2848
2849 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2850 {
2851         mlx5_core_destroy_tis(mdev, tisn);
2852 }
2853
2854 int mlx5e_create_tises(struct mlx5e_priv *priv)
2855 {
2856         int err;
2857         int tc;
2858
2859         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2860                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2861                 if (err)
2862                         goto err_close_tises;
2863         }
2864
2865         return 0;
2866
2867 err_close_tises:
2868         for (tc--; tc >= 0; tc--)
2869                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2870
2871         return err;
2872 }
2873
2874 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2875 {
2876         int tc;
2877
2878         for (tc = 0; tc < priv->profile->max_tc; tc++)
2879                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2880 }
2881
2882 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2883                                       enum mlx5e_traffic_types tt,
2884                                       u32 *tirc)
2885 {
2886         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2887
2888         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2889
2890         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2891         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2892         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2893 }
2894
2895 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2896 {
2897         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2898
2899         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2900
2901         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2902         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2903         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2904 }
2905
2906 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2907 {
2908         struct mlx5e_tir *tir;
2909         void *tirc;
2910         int inlen;
2911         int i = 0;
2912         int err;
2913         u32 *in;
2914         int tt;
2915
2916         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2917         in = kvzalloc(inlen, GFP_KERNEL);
2918         if (!in)
2919                 return -ENOMEM;
2920
2921         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2922                 memset(in, 0, inlen);
2923                 tir = &priv->indir_tir[tt];
2924                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2925                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2926                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2927                 if (err) {
2928                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2929                         goto err_destroy_inner_tirs;
2930                 }
2931         }
2932
2933         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2934                 goto out;
2935
2936         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2937                 memset(in, 0, inlen);
2938                 tir = &priv->inner_indir_tir[i];
2939                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2940                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2941                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2942                 if (err) {
2943                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2944                         goto err_destroy_inner_tirs;
2945                 }
2946         }
2947
2948 out:
2949         kvfree(in);
2950
2951         return 0;
2952
2953 err_destroy_inner_tirs:
2954         for (i--; i >= 0; i--)
2955                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2956
2957         for (tt--; tt >= 0; tt--)
2958                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2959
2960         kvfree(in);
2961
2962         return err;
2963 }
2964
2965 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2966 {
2967         int nch = priv->profile->max_nch(priv->mdev);
2968         struct mlx5e_tir *tir;
2969         void *tirc;
2970         int inlen;
2971         int err;
2972         u32 *in;
2973         int ix;
2974
2975         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2976         in = kvzalloc(inlen, GFP_KERNEL);
2977         if (!in)
2978                 return -ENOMEM;
2979
2980         for (ix = 0; ix < nch; ix++) {
2981                 memset(in, 0, inlen);
2982                 tir = &priv->direct_tir[ix];
2983                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2984                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2985                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2986                 if (err)
2987                         goto err_destroy_ch_tirs;
2988         }
2989
2990         kvfree(in);
2991
2992         return 0;
2993
2994 err_destroy_ch_tirs:
2995         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
2996         for (ix--; ix >= 0; ix--)
2997                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2998
2999         kvfree(in);
3000
3001         return err;
3002 }
3003
3004 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3005 {
3006         int i;
3007
3008         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3009                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3010
3011         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3012                 return;
3013
3014         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3015                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3016 }
3017
3018 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3019 {
3020         int nch = priv->profile->max_nch(priv->mdev);
3021         int i;
3022
3023         for (i = 0; i < nch; i++)
3024                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3025 }
3026
3027 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3028 {
3029         int err = 0;
3030         int i;
3031
3032         for (i = 0; i < chs->num; i++) {
3033                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3034                 if (err)
3035                         return err;
3036         }
3037
3038         return 0;
3039 }
3040
3041 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3042 {
3043         int err = 0;
3044         int i;
3045
3046         for (i = 0; i < chs->num; i++) {
3047                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3048                 if (err)
3049                         return err;
3050         }
3051
3052         return 0;
3053 }
3054
3055 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3056                                  struct tc_mqprio_qopt *mqprio)
3057 {
3058         struct mlx5e_priv *priv = netdev_priv(netdev);
3059         struct mlx5e_channels new_channels = {};
3060         u8 tc = mqprio->num_tc;
3061         int err = 0;
3062
3063         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3064
3065         if (tc && tc != MLX5E_MAX_NUM_TC)
3066                 return -EINVAL;
3067
3068         mutex_lock(&priv->state_lock);
3069
3070         new_channels.params = priv->channels.params;
3071         new_channels.params.num_tc = tc ? tc : 1;
3072
3073         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3074                 priv->channels.params = new_channels.params;
3075                 goto out;
3076         }
3077
3078         err = mlx5e_open_channels(priv, &new_channels);
3079         if (err)
3080                 goto out;
3081
3082         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3083 out:
3084         mutex_unlock(&priv->state_lock);
3085         return err;
3086 }
3087
3088 #ifdef CONFIG_MLX5_ESWITCH
3089 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3090                                      struct tc_cls_flower_offload *cls_flower)
3091 {
3092         switch (cls_flower->command) {
3093         case TC_CLSFLOWER_REPLACE:
3094                 return mlx5e_configure_flower(priv, cls_flower);
3095         case TC_CLSFLOWER_DESTROY:
3096                 return mlx5e_delete_flower(priv, cls_flower);
3097         case TC_CLSFLOWER_STATS:
3098                 return mlx5e_stats_flower(priv, cls_flower);
3099         default:
3100                 return -EOPNOTSUPP;
3101         }
3102 }
3103
3104 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3105                             void *cb_priv)
3106 {
3107         struct mlx5e_priv *priv = cb_priv;