9cc321a3acdfe7a3d53d9e6e1accece790b8e98f
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/mlx5/flow_table.h>
34 #include "en.h"
35
36 struct mlx5e_rq_param {
37         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
38         struct mlx5_wq_param       wq;
39 };
40
41 struct mlx5e_sq_param {
42         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
43         struct mlx5_wq_param       wq;
44 };
45
46 struct mlx5e_cq_param {
47         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
48         struct mlx5_wq_param       wq;
49         u16                        eq_ix;
50 };
51
52 struct mlx5e_channel_param {
53         struct mlx5e_rq_param      rq;
54         struct mlx5e_sq_param      sq;
55         struct mlx5e_cq_param      rx_cq;
56         struct mlx5e_cq_param      tx_cq;
57 };
58
59 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
60 {
61         struct mlx5_core_dev *mdev = priv->mdev;
62         u8 port_state;
63
64         port_state = mlx5_query_vport_state(mdev,
65                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
66
67         if (port_state == VPORT_STATE_UP)
68                 netif_carrier_on(priv->netdev);
69         else
70                 netif_carrier_off(priv->netdev);
71 }
72
73 static void mlx5e_update_carrier_work(struct work_struct *work)
74 {
75         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
76                                                update_carrier_work);
77
78         mutex_lock(&priv->state_lock);
79         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
80                 mlx5e_update_carrier(priv);
81         mutex_unlock(&priv->state_lock);
82 }
83
84 void mlx5e_update_stats(struct mlx5e_priv *priv)
85 {
86         struct mlx5_core_dev *mdev = priv->mdev;
87         struct mlx5e_vport_stats *s = &priv->stats.vport;
88         struct mlx5e_rq_stats *rq_stats;
89         struct mlx5e_sq_stats *sq_stats;
90         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
91         u32 *out;
92         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
93         u64 tx_offload_none;
94         int i, j;
95
96         out = mlx5_vzalloc(outlen);
97         if (!out)
98                 return;
99
100         /* Collect firts the SW counters and then HW for consistency */
101         s->tso_packets          = 0;
102         s->tso_bytes            = 0;
103         s->tx_queue_stopped     = 0;
104         s->tx_queue_wake        = 0;
105         s->tx_queue_dropped     = 0;
106         tx_offload_none         = 0;
107         s->lro_packets          = 0;
108         s->lro_bytes            = 0;
109         s->rx_csum_none         = 0;
110         s->rx_wqe_err           = 0;
111         for (i = 0; i < priv->params.num_channels; i++) {
112                 rq_stats = &priv->channel[i]->rq.stats;
113
114                 s->lro_packets  += rq_stats->lro_packets;
115                 s->lro_bytes    += rq_stats->lro_bytes;
116                 s->rx_csum_none += rq_stats->csum_none;
117                 s->rx_wqe_err   += rq_stats->wqe_err;
118
119                 for (j = 0; j < priv->num_tc; j++) {
120                         sq_stats = &priv->channel[i]->sq[j].stats;
121
122                         s->tso_packets          += sq_stats->tso_packets;
123                         s->tso_bytes            += sq_stats->tso_bytes;
124                         s->tx_queue_stopped     += sq_stats->stopped;
125                         s->tx_queue_wake        += sq_stats->wake;
126                         s->tx_queue_dropped     += sq_stats->dropped;
127                         tx_offload_none         += sq_stats->csum_offload_none;
128                 }
129         }
130
131         /* HW counters */
132         memset(in, 0, sizeof(in));
133
134         MLX5_SET(query_vport_counter_in, in, opcode,
135                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
136         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
137         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
138
139         memset(out, 0, outlen);
140
141         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
142                 goto free_out;
143
144 #define MLX5_GET_CTR(p, x) \
145         MLX5_GET64(query_vport_counter_out, p, x)
146
147         s->rx_error_packets     =
148                 MLX5_GET_CTR(out, received_errors.packets);
149         s->rx_error_bytes       =
150                 MLX5_GET_CTR(out, received_errors.octets);
151         s->tx_error_packets     =
152                 MLX5_GET_CTR(out, transmit_errors.packets);
153         s->tx_error_bytes       =
154                 MLX5_GET_CTR(out, transmit_errors.octets);
155
156         s->rx_unicast_packets   =
157                 MLX5_GET_CTR(out, received_eth_unicast.packets);
158         s->rx_unicast_bytes     =
159                 MLX5_GET_CTR(out, received_eth_unicast.octets);
160         s->tx_unicast_packets   =
161                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
162         s->tx_unicast_bytes     =
163                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
164
165         s->rx_multicast_packets =
166                 MLX5_GET_CTR(out, received_eth_multicast.packets);
167         s->rx_multicast_bytes   =
168                 MLX5_GET_CTR(out, received_eth_multicast.octets);
169         s->tx_multicast_packets =
170                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
171         s->tx_multicast_bytes   =
172                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
173
174         s->rx_broadcast_packets =
175                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
176         s->rx_broadcast_bytes   =
177                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
178         s->tx_broadcast_packets =
179                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
180         s->tx_broadcast_bytes   =
181                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
182
183         s->rx_packets =
184                 s->rx_unicast_packets +
185                 s->rx_multicast_packets +
186                 s->rx_broadcast_packets;
187         s->rx_bytes =
188                 s->rx_unicast_bytes +
189                 s->rx_multicast_bytes +
190                 s->rx_broadcast_bytes;
191         s->tx_packets =
192                 s->tx_unicast_packets +
193                 s->tx_multicast_packets +
194                 s->tx_broadcast_packets;
195         s->tx_bytes =
196                 s->tx_unicast_bytes +
197                 s->tx_multicast_bytes +
198                 s->tx_broadcast_bytes;
199
200         /* Update calculated offload counters */
201         s->tx_csum_offload = s->tx_packets - tx_offload_none;
202         s->rx_csum_good    = s->rx_packets - s->rx_csum_none;
203
204 free_out:
205         kvfree(out);
206 }
207
208 static void mlx5e_update_stats_work(struct work_struct *work)
209 {
210         struct delayed_work *dwork = to_delayed_work(work);
211         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
212                                                update_stats_work);
213         mutex_lock(&priv->state_lock);
214         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
215                 mlx5e_update_stats(priv);
216                 schedule_delayed_work(dwork,
217                                       msecs_to_jiffies(
218                                               MLX5E_UPDATE_STATS_INTERVAL));
219         }
220         mutex_unlock(&priv->state_lock);
221 }
222
223 static void __mlx5e_async_event(struct mlx5e_priv *priv,
224                                 enum mlx5_dev_event event)
225 {
226         switch (event) {
227         case MLX5_DEV_EVENT_PORT_UP:
228         case MLX5_DEV_EVENT_PORT_DOWN:
229                 schedule_work(&priv->update_carrier_work);
230                 break;
231
232         default:
233                 break;
234         }
235 }
236
237 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
238                               enum mlx5_dev_event event, unsigned long param)
239 {
240         struct mlx5e_priv *priv = vpriv;
241
242         spin_lock(&priv->async_events_spinlock);
243         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
244                 __mlx5e_async_event(priv, event);
245         spin_unlock(&priv->async_events_spinlock);
246 }
247
248 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
249 {
250         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
251 }
252
253 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
254 {
255         spin_lock_irq(&priv->async_events_spinlock);
256         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
257         spin_unlock_irq(&priv->async_events_spinlock);
258 }
259
260 static void mlx5e_send_nop(struct mlx5e_sq *sq)
261 {
262         struct mlx5_wq_cyc                *wq  = &sq->wq;
263
264         u16 pi = sq->pc & wq->sz_m1;
265         struct mlx5e_tx_wqe              *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
266
267         struct mlx5_wqe_ctrl_seg         *cseg = &wqe->ctrl;
268
269         memset(cseg, 0, sizeof(*cseg));
270
271         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);
272         cseg->qpn_ds           = cpu_to_be32((sq->sqn << 8) | 0x01);
273         cseg->fm_ce_se         = MLX5_WQE_CTRL_CQ_UPDATE;
274
275         sq->skb[pi] = NULL;
276         sq->pc++;
277         mlx5e_tx_notify_hw(sq, wqe);
278 }
279
280 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
281 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
282
283 static int mlx5e_create_rq(struct mlx5e_channel *c,
284                            struct mlx5e_rq_param *param,
285                            struct mlx5e_rq *rq)
286 {
287         struct mlx5e_priv *priv = c->priv;
288         struct mlx5_core_dev *mdev = priv->mdev;
289         void *rqc = param->rqc;
290         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
291         int wq_sz;
292         int err;
293         int i;
294
295         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
296                                 &rq->wq_ctrl);
297         if (err)
298                 return err;
299
300         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
301
302         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
303         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
304                                cpu_to_node(c->cpu));
305         if (!rq->skb) {
306                 err = -ENOMEM;
307                 goto err_rq_wq_destroy;
308         }
309
310         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
311                                              MLX5E_SW2HW_MTU(priv->netdev->mtu);
312         rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
313
314         for (i = 0; i < wq_sz; i++) {
315                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
316                 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
317
318                 wqe->data.lkey       = c->mkey_be;
319                 wqe->data.byte_count =
320                         cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
321         }
322
323         rq->pdev    = c->pdev;
324         rq->netdev  = c->netdev;
325         rq->channel = c;
326         rq->ix      = c->ix;
327
328         return 0;
329
330 err_rq_wq_destroy:
331         mlx5_wq_destroy(&rq->wq_ctrl);
332
333         return err;
334 }
335
336 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
337 {
338         kfree(rq->skb);
339         mlx5_wq_destroy(&rq->wq_ctrl);
340 }
341
342 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
343 {
344         struct mlx5e_channel *c = rq->channel;
345         struct mlx5e_priv *priv = c->priv;
346         struct mlx5_core_dev *mdev = priv->mdev;
347
348         void *in;
349         void *rqc;
350         void *wq;
351         int inlen;
352         int err;
353
354         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
355                 sizeof(u64) * rq->wq_ctrl.buf.npages;
356         in = mlx5_vzalloc(inlen);
357         if (!in)
358                 return -ENOMEM;
359
360         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
361         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
362
363         memcpy(rqc, param->rqc, sizeof(param->rqc));
364
365         MLX5_SET(rqc,  rqc, cqn,                c->rq.cq.mcq.cqn);
366         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
367         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
368         MLX5_SET(wq,   wq,  wq_type,            MLX5_WQ_TYPE_LINKED_LIST);
369         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
370                                                 PAGE_SHIFT);
371         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
372
373         mlx5_fill_page_array(&rq->wq_ctrl.buf,
374                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
375
376         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
377
378         kvfree(in);
379
380         return err;
381 }
382
383 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
384 {
385         struct mlx5e_channel *c = rq->channel;
386         struct mlx5e_priv *priv = c->priv;
387         struct mlx5_core_dev *mdev = priv->mdev;
388
389         void *in;
390         void *rqc;
391         int inlen;
392         int err;
393
394         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
395         in = mlx5_vzalloc(inlen);
396         if (!in)
397                 return -ENOMEM;
398
399         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
400
401         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
402         MLX5_SET(rqc, rqc, state, next_state);
403
404         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
405
406         kvfree(in);
407
408         return err;
409 }
410
411 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
412 {
413         struct mlx5e_channel *c = rq->channel;
414         struct mlx5e_priv *priv = c->priv;
415         struct mlx5_core_dev *mdev = priv->mdev;
416
417         mlx5_core_destroy_rq(mdev, rq->rqn);
418 }
419
420 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
421 {
422         struct mlx5e_channel *c = rq->channel;
423         struct mlx5e_priv *priv = c->priv;
424         struct mlx5_wq_ll *wq = &rq->wq;
425         int i;
426
427         for (i = 0; i < 1000; i++) {
428                 if (wq->cur_sz >= priv->params.min_rx_wqes)
429                         return 0;
430
431                 msleep(20);
432         }
433
434         return -ETIMEDOUT;
435 }
436
437 static int mlx5e_open_rq(struct mlx5e_channel *c,
438                          struct mlx5e_rq_param *param,
439                          struct mlx5e_rq *rq)
440 {
441         int err;
442
443         err = mlx5e_create_rq(c, param, rq);
444         if (err)
445                 return err;
446
447         err = mlx5e_enable_rq(rq, param);
448         if (err)
449                 goto err_destroy_rq;
450
451         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
452         if (err)
453                 goto err_disable_rq;
454
455         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
456         mlx5e_send_nop(&c->sq[0]); /* trigger mlx5e_post_rx_wqes() */
457
458         return 0;
459
460 err_disable_rq:
461         mlx5e_disable_rq(rq);
462 err_destroy_rq:
463         mlx5e_destroy_rq(rq);
464
465         return err;
466 }
467
468 static void mlx5e_close_rq(struct mlx5e_rq *rq)
469 {
470         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
471         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
472
473         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
474         while (!mlx5_wq_ll_is_empty(&rq->wq))
475                 msleep(20);
476
477         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
478         napi_synchronize(&rq->channel->napi);
479
480         mlx5e_disable_rq(rq);
481         mlx5e_destroy_rq(rq);
482 }
483
484 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
485 {
486         kfree(sq->dma_fifo);
487         kfree(sq->skb);
488 }
489
490 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
491 {
492         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
493         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
494
495         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
496         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
497                                     numa);
498
499         if (!sq->skb || !sq->dma_fifo) {
500                 mlx5e_free_sq_db(sq);
501                 return -ENOMEM;
502         }
503
504         sq->dma_fifo_mask = df_sz - 1;
505
506         return 0;
507 }
508
509 static int mlx5e_create_sq(struct mlx5e_channel *c,
510                            int tc,
511                            struct mlx5e_sq_param *param,
512                            struct mlx5e_sq *sq)
513 {
514         struct mlx5e_priv *priv = c->priv;
515         struct mlx5_core_dev *mdev = priv->mdev;
516
517         void *sqc = param->sqc;
518         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
519         int err;
520
521         err = mlx5_alloc_map_uar(mdev, &sq->uar);
522         if (err)
523                 return err;
524
525         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
526                                  &sq->wq_ctrl);
527         if (err)
528                 goto err_unmap_free_uar;
529
530         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
531         sq->uar_map     = sq->uar.map;
532         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
533
534         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
535         if (err)
536                 goto err_sq_wq_destroy;
537
538         sq->txq = netdev_get_tx_queue(priv->netdev,
539                                       c->ix + tc * priv->params.num_channels);
540
541         sq->pdev    = c->pdev;
542         sq->mkey_be = c->mkey_be;
543         sq->channel = c;
544         sq->tc      = tc;
545
546         return 0;
547
548 err_sq_wq_destroy:
549         mlx5_wq_destroy(&sq->wq_ctrl);
550
551 err_unmap_free_uar:
552         mlx5_unmap_free_uar(mdev, &sq->uar);
553
554         return err;
555 }
556
557 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
558 {
559         struct mlx5e_channel *c = sq->channel;
560         struct mlx5e_priv *priv = c->priv;
561
562         mlx5e_free_sq_db(sq);
563         mlx5_wq_destroy(&sq->wq_ctrl);
564         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
565 }
566
567 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
568 {
569         struct mlx5e_channel *c = sq->channel;
570         struct mlx5e_priv *priv = c->priv;
571         struct mlx5_core_dev *mdev = priv->mdev;
572
573         void *in;
574         void *sqc;
575         void *wq;
576         int inlen;
577         int err;
578
579         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
580                 sizeof(u64) * sq->wq_ctrl.buf.npages;
581         in = mlx5_vzalloc(inlen);
582         if (!in)
583                 return -ENOMEM;
584
585         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
586         wq = MLX5_ADDR_OF(sqc, sqc, wq);
587
588         memcpy(sqc, param->sqc, sizeof(param->sqc));
589
590         MLX5_SET(sqc,  sqc, user_index,         sq->tc);
591         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
592         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
593         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
594         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
595         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
596
597         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
598         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
599         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
600                                           PAGE_SHIFT);
601         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
602
603         mlx5_fill_page_array(&sq->wq_ctrl.buf,
604                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
605
606         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
607
608         kvfree(in);
609
610         return err;
611 }
612
613 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
614 {
615         struct mlx5e_channel *c = sq->channel;
616         struct mlx5e_priv *priv = c->priv;
617         struct mlx5_core_dev *mdev = priv->mdev;
618
619         void *in;
620         void *sqc;
621         int inlen;
622         int err;
623
624         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
625         in = mlx5_vzalloc(inlen);
626         if (!in)
627                 return -ENOMEM;
628
629         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
630
631         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
632         MLX5_SET(sqc, sqc, state, next_state);
633
634         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
635
636         kvfree(in);
637
638         return err;
639 }
640
641 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
642 {
643         struct mlx5e_channel *c = sq->channel;
644         struct mlx5e_priv *priv = c->priv;
645         struct mlx5_core_dev *mdev = priv->mdev;
646
647         mlx5_core_destroy_sq(mdev, sq->sqn);
648 }
649
650 static int mlx5e_open_sq(struct mlx5e_channel *c,
651                          int tc,
652                          struct mlx5e_sq_param *param,
653                          struct mlx5e_sq *sq)
654 {
655         int err;
656
657         err = mlx5e_create_sq(c, tc, param, sq);
658         if (err)
659                 return err;
660
661         err = mlx5e_enable_sq(sq, param);
662         if (err)
663                 goto err_destroy_sq;
664
665         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
666         if (err)
667                 goto err_disable_sq;
668
669         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
670         netdev_tx_reset_queue(sq->txq);
671         netif_tx_start_queue(sq->txq);
672
673         return 0;
674
675 err_disable_sq:
676         mlx5e_disable_sq(sq);
677 err_destroy_sq:
678         mlx5e_destroy_sq(sq);
679
680         return err;
681 }
682
683 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
684 {
685         __netif_tx_lock_bh(txq);
686         netif_tx_stop_queue(txq);
687         __netif_tx_unlock_bh(txq);
688 }
689
690 static void mlx5e_close_sq(struct mlx5e_sq *sq)
691 {
692         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
693         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
694         netif_tx_disable_queue(sq->txq);
695
696         /* ensure hw is notified of all pending wqes */
697         if (mlx5e_sq_has_room_for(sq, 1))
698                 mlx5e_send_nop(sq);
699
700         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
701         while (sq->cc != sq->pc) /* wait till sq is empty */
702                 msleep(20);
703
704         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
705         napi_synchronize(&sq->channel->napi);
706
707         mlx5e_disable_sq(sq);
708         mlx5e_destroy_sq(sq);
709 }
710
711 static int mlx5e_create_cq(struct mlx5e_channel *c,
712                            struct mlx5e_cq_param *param,
713                            struct mlx5e_cq *cq)
714 {
715         struct mlx5e_priv *priv = c->priv;
716         struct mlx5_core_dev *mdev = priv->mdev;
717         struct mlx5_core_cq *mcq = &cq->mcq;
718         int eqn_not_used;
719         int irqn;
720         int err;
721         u32 i;
722
723         param->wq.numa = cpu_to_node(c->cpu);
724         param->eq_ix   = c->ix;
725
726         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
727                                &cq->wq_ctrl);
728         if (err)
729                 return err;
730
731         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
732
733         cq->napi        = &c->napi;
734
735         mcq->cqe_sz     = 64;
736         mcq->set_ci_db  = cq->wq_ctrl.db.db;
737         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
738         *mcq->set_ci_db = 0;
739         *mcq->arm_db    = 0;
740         mcq->vector     = param->eq_ix;
741         mcq->comp       = mlx5e_completion_event;
742         mcq->event      = mlx5e_cq_error_event;
743         mcq->irqn       = irqn;
744         mcq->uar        = &priv->cq_uar;
745
746         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
747                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
748
749                 cqe->op_own = 0xf1;
750         }
751
752         cq->channel = c;
753
754         return 0;
755 }
756
757 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
758 {
759         mlx5_wq_destroy(&cq->wq_ctrl);
760 }
761
762 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
763 {
764         struct mlx5e_channel *c = cq->channel;
765         struct mlx5e_priv *priv = c->priv;
766         struct mlx5_core_dev *mdev = priv->mdev;
767         struct mlx5_core_cq *mcq = &cq->mcq;
768
769         void *in;
770         void *cqc;
771         int inlen;
772         int irqn_not_used;
773         int eqn;
774         int err;
775
776         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
777                 sizeof(u64) * cq->wq_ctrl.buf.npages;
778         in = mlx5_vzalloc(inlen);
779         if (!in)
780                 return -ENOMEM;
781
782         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
783
784         memcpy(cqc, param->cqc, sizeof(param->cqc));
785
786         mlx5_fill_page_array(&cq->wq_ctrl.buf,
787                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
788
789         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
790
791         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
792         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
793         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
794                                             PAGE_SHIFT);
795         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
796
797         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
798
799         kvfree(in);
800
801         if (err)
802                 return err;
803
804         mlx5e_cq_arm(cq);
805
806         return 0;
807 }
808
809 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
810 {
811         struct mlx5e_channel *c = cq->channel;
812         struct mlx5e_priv *priv = c->priv;
813         struct mlx5_core_dev *mdev = priv->mdev;
814
815         mlx5_core_destroy_cq(mdev, &cq->mcq);
816 }
817
818 static int mlx5e_open_cq(struct mlx5e_channel *c,
819                          struct mlx5e_cq_param *param,
820                          struct mlx5e_cq *cq,
821                          u16 moderation_usecs,
822                          u16 moderation_frames)
823 {
824         int err;
825         struct mlx5e_priv *priv = c->priv;
826         struct mlx5_core_dev *mdev = priv->mdev;
827
828         err = mlx5e_create_cq(c, param, cq);
829         if (err)
830                 return err;
831
832         err = mlx5e_enable_cq(cq, param);
833         if (err)
834                 goto err_destroy_cq;
835
836         err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
837                                              moderation_usecs,
838                                              moderation_frames);
839         if (err)
840                 goto err_destroy_cq;
841
842         return 0;
843
844 err_destroy_cq:
845         mlx5e_destroy_cq(cq);
846
847         return err;
848 }
849
850 static void mlx5e_close_cq(struct mlx5e_cq *cq)
851 {
852         mlx5e_disable_cq(cq);
853         mlx5e_destroy_cq(cq);
854 }
855
856 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
857 {
858         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
859 }
860
861 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
862                              struct mlx5e_channel_param *cparam)
863 {
864         struct mlx5e_priv *priv = c->priv;
865         int err;
866         int tc;
867
868         for (tc = 0; tc < c->num_tc; tc++) {
869                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
870                                     priv->params.tx_cq_moderation_usec,
871                                     priv->params.tx_cq_moderation_pkts);
872                 if (err)
873                         goto err_close_tx_cqs;
874
875                 c->sq[tc].cq.sqrq = &c->sq[tc];
876         }
877
878         return 0;
879
880 err_close_tx_cqs:
881         for (tc--; tc >= 0; tc--)
882                 mlx5e_close_cq(&c->sq[tc].cq);
883
884         return err;
885 }
886
887 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
888 {
889         int tc;
890
891         for (tc = 0; tc < c->num_tc; tc++)
892                 mlx5e_close_cq(&c->sq[tc].cq);
893 }
894
895 static int mlx5e_open_sqs(struct mlx5e_channel *c,
896                           struct mlx5e_channel_param *cparam)
897 {
898         int err;
899         int tc;
900
901         for (tc = 0; tc < c->num_tc; tc++) {
902                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
903                 if (err)
904                         goto err_close_sqs;
905         }
906
907         return 0;
908
909 err_close_sqs:
910         for (tc--; tc >= 0; tc--)
911                 mlx5e_close_sq(&c->sq[tc]);
912
913         return err;
914 }
915
916 static void mlx5e_close_sqs(struct mlx5e_channel *c)
917 {
918         int tc;
919
920         for (tc = 0; tc < c->num_tc; tc++)
921                 mlx5e_close_sq(&c->sq[tc]);
922 }
923
924 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
925                               struct mlx5e_channel_param *cparam,
926                               struct mlx5e_channel **cp)
927 {
928         struct net_device *netdev = priv->netdev;
929         int cpu = mlx5e_get_cpu(priv, ix);
930         struct mlx5e_channel *c;
931         int err;
932
933         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
934         if (!c)
935                 return -ENOMEM;
936
937         c->priv     = priv;
938         c->ix       = ix;
939         c->cpu      = cpu;
940         c->pdev     = &priv->mdev->pdev->dev;
941         c->netdev   = priv->netdev;
942         c->mkey_be  = cpu_to_be32(priv->mr.key);
943         c->num_tc   = priv->num_tc;
944
945         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
946
947         err = mlx5e_open_tx_cqs(c, cparam);
948         if (err)
949                 goto err_napi_del;
950
951         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
952                             priv->params.rx_cq_moderation_usec,
953                             priv->params.rx_cq_moderation_pkts);
954         if (err)
955                 goto err_close_tx_cqs;
956         c->rq.cq.sqrq = &c->rq;
957
958         napi_enable(&c->napi);
959
960         err = mlx5e_open_sqs(c, cparam);
961         if (err)
962                 goto err_disable_napi;
963
964         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
965         if (err)
966                 goto err_close_sqs;
967
968         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
969         *cp = c;
970
971         return 0;
972
973 err_close_sqs:
974         mlx5e_close_sqs(c);
975
976 err_disable_napi:
977         napi_disable(&c->napi);
978         mlx5e_close_cq(&c->rq.cq);
979
980 err_close_tx_cqs:
981         mlx5e_close_tx_cqs(c);
982
983 err_napi_del:
984         netif_napi_del(&c->napi);
985         kfree(c);
986
987         return err;
988 }
989
990 static void mlx5e_close_channel(struct mlx5e_channel *c)
991 {
992         mlx5e_close_rq(&c->rq);
993         mlx5e_close_sqs(c);
994         napi_disable(&c->napi);
995         mlx5e_close_cq(&c->rq.cq);
996         mlx5e_close_tx_cqs(c);
997         netif_napi_del(&c->napi);
998         kfree(c);
999 }
1000
1001 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1002                                  struct mlx5e_rq_param *param)
1003 {
1004         void *rqc = param->rqc;
1005         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1006
1007         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
1008         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1009         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1010         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1011         MLX5_SET(wq, wq, pd,               priv->pdn);
1012
1013         param->wq.numa   = dev_to_node(&priv->mdev->pdev->dev);
1014         param->wq.linear = 1;
1015 }
1016
1017 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1018                                  struct mlx5e_sq_param *param)
1019 {
1020         void *sqc = param->sqc;
1021         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1022
1023         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1024         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1025         MLX5_SET(wq, wq, pd,            priv->pdn);
1026
1027         param->wq.numa = dev_to_node(&priv->mdev->pdev->dev);
1028 }
1029
1030 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1031                                         struct mlx5e_cq_param *param)
1032 {
1033         void *cqc = param->cqc;
1034
1035         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1036 }
1037
1038 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1039                                     struct mlx5e_cq_param *param)
1040 {
1041         void *cqc = param->cqc;
1042
1043         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1044
1045         mlx5e_build_common_cq_param(priv, param);
1046 }
1047
1048 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1049                                     struct mlx5e_cq_param *param)
1050 {
1051         void *cqc = param->cqc;
1052
1053         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1054
1055         mlx5e_build_common_cq_param(priv, param);
1056 }
1057
1058 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1059                                       struct mlx5e_channel_param *cparam)
1060 {
1061         memset(cparam, 0, sizeof(*cparam));
1062
1063         mlx5e_build_rq_param(priv, &cparam->rq);
1064         mlx5e_build_sq_param(priv, &cparam->sq);
1065         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1066         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1067 }
1068
1069 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1070 {
1071         struct mlx5e_channel_param cparam;
1072         int err;
1073         int i;
1074         int j;
1075
1076         priv->channel = kcalloc(priv->params.num_channels,
1077                                 sizeof(struct mlx5e_channel *), GFP_KERNEL);
1078         if (!priv->channel)
1079                 return -ENOMEM;
1080
1081         mlx5e_build_channel_param(priv, &cparam);
1082         for (i = 0; i < priv->params.num_channels; i++) {
1083                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1084                 if (err)
1085                         goto err_close_channels;
1086         }
1087
1088         for (j = 0; j < priv->params.num_channels; j++) {
1089                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1090                 if (err)
1091                         goto err_close_channels;
1092         }
1093
1094         return 0;
1095
1096 err_close_channels:
1097         for (i--; i >= 0; i--)
1098                 mlx5e_close_channel(priv->channel[i]);
1099
1100         kfree(priv->channel);
1101
1102         return err;
1103 }
1104
1105 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1106 {
1107         int i;
1108
1109         for (i = 0; i < priv->params.num_channels; i++)
1110                 mlx5e_close_channel(priv->channel[i]);
1111
1112         kfree(priv->channel);
1113 }
1114
1115 static int mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1116 {
1117         struct mlx5_core_dev *mdev = priv->mdev;
1118         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1119         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1120
1121         memset(in, 0, sizeof(in));
1122
1123         MLX5_SET(tisc, tisc, prio,  tc);
1124
1125         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1126 }
1127
1128 static void mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1129 {
1130         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1131 }
1132
1133 static int mlx5e_open_tises(struct mlx5e_priv *priv)
1134 {
1135         int num_tc = priv->num_tc;
1136         int err;
1137         int tc;
1138
1139         for (tc = 0; tc < num_tc; tc++) {
1140                 err = mlx5e_open_tis(priv, tc);
1141                 if (err)
1142                         goto err_close_tises;
1143         }
1144
1145         return 0;
1146
1147 err_close_tises:
1148         for (tc--; tc >= 0; tc--)
1149                 mlx5e_close_tis(priv, tc);
1150
1151         return err;
1152 }
1153
1154 static void mlx5e_close_tises(struct mlx5e_priv *priv)
1155 {
1156         int num_tc = priv->num_tc;
1157         int tc;
1158
1159         for (tc = 0; tc < num_tc; tc++)
1160                 mlx5e_close_tis(priv, tc);
1161 }
1162
1163 static int mlx5e_open_rqt(struct mlx5e_priv *priv)
1164 {
1165         struct mlx5_core_dev *mdev = priv->mdev;
1166         u32 *in;
1167         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1168         void *rqtc;
1169         int inlen;
1170         int err;
1171         int sz;
1172         int i;
1173
1174         sz = 1 << priv->params.rx_hash_log_tbl_sz;
1175
1176         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1177         in = mlx5_vzalloc(inlen);
1178         if (!in)
1179                 return -ENOMEM;
1180
1181         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1182
1183         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1184         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1185
1186         for (i = 0; i < sz; i++) {
1187                 int ix = i % priv->params.num_channels;
1188
1189                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1190         }
1191
1192         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1193
1194         memset(out, 0, sizeof(out));
1195         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1196         if (!err)
1197                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1198
1199         kvfree(in);
1200
1201         return err;
1202 }
1203
1204 static void mlx5e_close_rqt(struct mlx5e_priv *priv)
1205 {
1206         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1207         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1208
1209         memset(in, 0, sizeof(in));
1210
1211         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1212         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1213
1214         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1215                                    sizeof(out));
1216 }
1217
1218 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1219 {
1220         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1221
1222 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1223
1224 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1225                           MLX5_HASH_FIELD_SEL_DST_IP)
1226
1227 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1228                           MLX5_HASH_FIELD_SEL_DST_IP   |\
1229                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
1230                           MLX5_HASH_FIELD_SEL_L4_DPORT)
1231
1232         if (priv->params.lro_en) {
1233                 MLX5_SET(tirc, tirc, lro_enable_mask,
1234                          MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1235                          MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1236                 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1237                          (priv->params.lro_wqe_sz -
1238                           ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1239                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1240                          MLX5_CAP_ETH(priv->mdev,
1241                                       lro_timer_supported_periods[3]));
1242         }
1243
1244         switch (tt) {
1245         case MLX5E_TT_ANY:
1246                 MLX5_SET(tirc, tirc, disp_type,
1247                          MLX5_TIRC_DISP_TYPE_DIRECT);
1248                 MLX5_SET(tirc, tirc, inline_rqn,
1249                          priv->channel[0]->rq.rqn);
1250                 break;
1251         default:
1252                 MLX5_SET(tirc, tirc, disp_type,
1253                          MLX5_TIRC_DISP_TYPE_INDIRECT);
1254                 MLX5_SET(tirc, tirc, indirect_table,
1255                          priv->rqtn);
1256                 MLX5_SET(tirc, tirc, rx_hash_fn,
1257                          MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
1258                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1259                 netdev_rss_key_fill(MLX5_ADDR_OF(tirc, tirc,
1260                                                  rx_hash_toeplitz_key),
1261                                     MLX5_FLD_SZ_BYTES(tirc,
1262                                                       rx_hash_toeplitz_key));
1263                 break;
1264         }
1265
1266         switch (tt) {
1267         case MLX5E_TT_IPV4_TCP:
1268                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1269                          MLX5_L3_PROT_TYPE_IPV4);
1270                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1271                          MLX5_L4_PROT_TYPE_TCP);
1272                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1273                          MLX5_HASH_ALL);
1274                 break;
1275
1276         case MLX5E_TT_IPV6_TCP:
1277                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1278                          MLX5_L3_PROT_TYPE_IPV6);
1279                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1280                          MLX5_L4_PROT_TYPE_TCP);
1281                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1282                          MLX5_HASH_ALL);
1283                 break;
1284
1285         case MLX5E_TT_IPV4_UDP:
1286                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1287                          MLX5_L3_PROT_TYPE_IPV4);
1288                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1289                          MLX5_L4_PROT_TYPE_UDP);
1290                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1291                          MLX5_HASH_ALL);
1292                 break;
1293
1294         case MLX5E_TT_IPV6_UDP:
1295                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1296                          MLX5_L3_PROT_TYPE_IPV6);
1297                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1298                          MLX5_L4_PROT_TYPE_UDP);
1299                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1300                          MLX5_HASH_ALL);
1301                 break;
1302
1303         case MLX5E_TT_IPV4:
1304                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1305                          MLX5_L3_PROT_TYPE_IPV4);
1306                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1307                          MLX5_HASH_IP);
1308                 break;
1309
1310         case MLX5E_TT_IPV6:
1311                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1312                          MLX5_L3_PROT_TYPE_IPV6);
1313                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1314                          MLX5_HASH_IP);
1315                 break;
1316         }
1317 }
1318
1319 static int mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
1320 {
1321         struct mlx5_core_dev *mdev = priv->mdev;
1322         u32 *in;
1323         void *tirc;
1324         int inlen;
1325         int err;
1326
1327         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1328         in = mlx5_vzalloc(inlen);
1329         if (!in)
1330                 return -ENOMEM;
1331
1332         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1333
1334         mlx5e_build_tir_ctx(priv, tirc, tt);
1335
1336         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1337
1338         kvfree(in);
1339
1340         return err;
1341 }
1342
1343 static void mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
1344 {
1345         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1346 }
1347
1348 static int mlx5e_open_tirs(struct mlx5e_priv *priv)
1349 {
1350         int err;
1351         int i;
1352
1353         for (i = 0; i < MLX5E_NUM_TT; i++) {
1354                 err = mlx5e_open_tir(priv, i);
1355                 if (err)
1356                         goto err_close_tirs;
1357         }
1358
1359         return 0;
1360
1361 err_close_tirs:
1362         for (i--; i >= 0; i--)
1363                 mlx5e_close_tir(priv, i);
1364
1365         return err;
1366 }
1367
1368 static void mlx5e_close_tirs(struct mlx5e_priv *priv)
1369 {
1370         int i;
1371
1372         for (i = 0; i < MLX5E_NUM_TT; i++)
1373                 mlx5e_close_tir(priv, i);
1374 }
1375
1376 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1377 {
1378         struct mlx5e_priv *priv = netdev_priv(netdev);
1379         struct mlx5_core_dev *mdev = priv->mdev;
1380         int hw_mtu;
1381         int err;
1382
1383         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1384         if (err)
1385                 return err;
1386
1387         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1388
1389         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1390                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1391                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1392
1393         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1394         return 0;
1395 }
1396
1397 int mlx5e_open_locked(struct net_device *netdev)
1398 {
1399         struct mlx5e_priv *priv = netdev_priv(netdev);
1400         int num_txqs;
1401         int err;
1402
1403         num_txqs = roundup_pow_of_two(priv->params.num_channels) *
1404                    priv->params.num_tc;
1405         netif_set_real_num_tx_queues(netdev, num_txqs);
1406         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1407
1408         err = mlx5e_set_dev_port_mtu(netdev);
1409         if (err)
1410                 return err;
1411
1412         err = mlx5e_open_tises(priv);
1413         if (err) {
1414                 netdev_err(netdev, "%s: mlx5e_open_tises failed, %d\n",
1415                            __func__, err);
1416                 return err;
1417         }
1418
1419         err = mlx5e_open_channels(priv);
1420         if (err) {
1421                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1422                            __func__, err);
1423                 goto err_close_tises;
1424         }
1425
1426         err = mlx5e_open_rqt(priv);
1427         if (err) {
1428                 netdev_err(netdev, "%s: mlx5e_open_rqt failed, %d\n",
1429                            __func__, err);
1430                 goto err_close_channels;
1431         }
1432
1433         err = mlx5e_open_tirs(priv);
1434         if (err) {
1435                 netdev_err(netdev, "%s: mlx5e_open_tir failed, %d\n",
1436                            __func__, err);
1437                 goto err_close_rqls;
1438         }
1439
1440         err = mlx5e_open_flow_table(priv);
1441         if (err) {
1442                 netdev_err(netdev, "%s: mlx5e_open_flow_table failed, %d\n",
1443                            __func__, err);
1444                 goto err_close_tirs;
1445         }
1446
1447         err = mlx5e_add_all_vlan_rules(priv);
1448         if (err) {
1449                 netdev_err(netdev, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
1450                            __func__, err);
1451                 goto err_close_flow_table;
1452         }
1453
1454         mlx5e_init_eth_addr(priv);
1455
1456         set_bit(MLX5E_STATE_OPENED, &priv->state);
1457
1458         mlx5e_update_carrier(priv);
1459         mlx5e_set_rx_mode_core(priv);
1460
1461         schedule_delayed_work(&priv->update_stats_work, 0);
1462         return 0;
1463
1464 err_close_flow_table:
1465         mlx5e_close_flow_table(priv);
1466
1467 err_close_tirs:
1468         mlx5e_close_tirs(priv);
1469
1470 err_close_rqls:
1471         mlx5e_close_rqt(priv);
1472
1473 err_close_channels:
1474         mlx5e_close_channels(priv);
1475
1476 err_close_tises:
1477         mlx5e_close_tises(priv);
1478
1479         return err;
1480 }
1481
1482 static int mlx5e_open(struct net_device *netdev)
1483 {
1484         struct mlx5e_priv *priv = netdev_priv(netdev);
1485         int err;
1486
1487         mutex_lock(&priv->state_lock);
1488         err = mlx5e_open_locked(netdev);
1489         mutex_unlock(&priv->state_lock);
1490
1491         return err;
1492 }
1493
1494 int mlx5e_close_locked(struct net_device *netdev)
1495 {
1496         struct mlx5e_priv *priv = netdev_priv(netdev);
1497
1498         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1499
1500         mlx5e_set_rx_mode_core(priv);
1501         mlx5e_del_all_vlan_rules(priv);
1502         netif_carrier_off(priv->netdev);
1503         mlx5e_close_flow_table(priv);
1504         mlx5e_close_tirs(priv);
1505         mlx5e_close_rqt(priv);
1506         mlx5e_close_channels(priv);
1507         mlx5e_close_tises(priv);
1508
1509         return 0;
1510 }
1511
1512 static int mlx5e_close(struct net_device *netdev)
1513 {
1514         struct mlx5e_priv *priv = netdev_priv(netdev);
1515         int err;
1516
1517         mutex_lock(&priv->state_lock);
1518         err = mlx5e_close_locked(netdev);
1519         mutex_unlock(&priv->state_lock);
1520
1521         return err;
1522 }
1523
1524 int mlx5e_update_priv_params(struct mlx5e_priv *priv,
1525                              struct mlx5e_params *new_params)
1526 {
1527         int err = 0;
1528         int was_opened;
1529
1530         WARN_ON(!mutex_is_locked(&priv->state_lock));
1531
1532         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1533         if (was_opened)
1534                 mlx5e_close_locked(priv->netdev);
1535
1536         priv->params = *new_params;
1537
1538         if (was_opened)
1539                 err = mlx5e_open_locked(priv->netdev);
1540
1541         return err;
1542 }
1543
1544 static struct rtnl_link_stats64 *
1545 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1546 {
1547         struct mlx5e_priv *priv = netdev_priv(dev);
1548         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1549
1550         stats->rx_packets = vstats->rx_packets;
1551         stats->rx_bytes   = vstats->rx_bytes;
1552         stats->tx_packets = vstats->tx_packets;
1553         stats->tx_bytes   = vstats->tx_bytes;
1554         stats->multicast  = vstats->rx_multicast_packets +
1555                             vstats->tx_multicast_packets;
1556         stats->tx_errors  = vstats->tx_error_packets;
1557         stats->rx_errors  = vstats->rx_error_packets;
1558         stats->tx_dropped = vstats->tx_queue_dropped;
1559         stats->rx_crc_errors = 0;
1560         stats->rx_length_errors = 0;
1561
1562         return stats;
1563 }
1564
1565 static void mlx5e_set_rx_mode(struct net_device *dev)
1566 {
1567         struct mlx5e_priv *priv = netdev_priv(dev);
1568
1569         schedule_work(&priv->set_rx_mode_work);
1570 }
1571
1572 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1573 {
1574         struct mlx5e_priv *priv = netdev_priv(netdev);
1575         struct sockaddr *saddr = addr;
1576
1577         if (!is_valid_ether_addr(saddr->sa_data))
1578                 return -EADDRNOTAVAIL;
1579
1580         netif_addr_lock_bh(netdev);
1581         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1582         netif_addr_unlock_bh(netdev);
1583
1584         schedule_work(&priv->set_rx_mode_work);
1585
1586         return 0;
1587 }
1588
1589 static int mlx5e_set_features(struct net_device *netdev,
1590                               netdev_features_t features)
1591 {
1592         struct mlx5e_priv *priv = netdev_priv(netdev);
1593         netdev_features_t changes = features ^ netdev->features;
1594         struct mlx5e_params new_params;
1595         bool update_params = false;
1596
1597         mutex_lock(&priv->state_lock);
1598         new_params = priv->params;
1599
1600         if (changes & NETIF_F_LRO) {
1601                 new_params.lro_en = !!(features & NETIF_F_LRO);
1602                 update_params = true;
1603         }
1604
1605         if (update_params)
1606                 mlx5e_update_priv_params(priv, &new_params);
1607
1608         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1609                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1610                         mlx5e_enable_vlan_filter(priv);
1611                 else
1612                         mlx5e_disable_vlan_filter(priv);
1613         }
1614
1615         mutex_unlock(&priv->state_lock);
1616
1617         return 0;
1618 }
1619
1620 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1621 {
1622         struct mlx5e_priv *priv = netdev_priv(netdev);
1623         struct mlx5_core_dev *mdev = priv->mdev;
1624         int max_mtu;
1625         int err;
1626
1627         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1628
1629         if (new_mtu > max_mtu) {
1630                 netdev_err(netdev,
1631                            "%s: Bad MTU (%d) > (%d) Max\n",
1632                            __func__, new_mtu, max_mtu);
1633                 return -EINVAL;
1634         }
1635
1636         mutex_lock(&priv->state_lock);
1637         netdev->mtu = new_mtu;
1638         err = mlx5e_update_priv_params(priv, &priv->params);
1639         mutex_unlock(&priv->state_lock);
1640
1641         return err;
1642 }
1643
1644 static struct net_device_ops mlx5e_netdev_ops = {
1645         .ndo_open                = mlx5e_open,
1646         .ndo_stop                = mlx5e_close,
1647         .ndo_start_xmit          = mlx5e_xmit,
1648         .ndo_get_stats64         = mlx5e_get_stats,
1649         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
1650         .ndo_set_mac_address     = mlx5e_set_mac,
1651         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
1652         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
1653         .ndo_set_features        = mlx5e_set_features,
1654         .ndo_change_mtu          = mlx5e_change_mtu,
1655 };
1656
1657 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1658 {
1659         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1660                 return -ENOTSUPP;
1661         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1662             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1663             !MLX5_CAP_ETH(mdev, csum_cap) ||
1664             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1665             !MLX5_CAP_ETH(mdev, vlan_cap) ||
1666             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap)) {
1667                 mlx5_core_warn(mdev,
1668                                "Not creating net device, some required device capabilities are missing\n");
1669                 return -ENOTSUPP;
1670         }
1671         return 0;
1672 }
1673
1674 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1675                                     struct net_device *netdev,
1676                                     int num_comp_vectors)
1677 {
1678         struct mlx5e_priv *priv = netdev_priv(netdev);
1679
1680         priv->params.log_sq_size           =
1681                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1682         priv->params.log_rq_size           =
1683                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
1684         priv->params.rx_cq_moderation_usec =
1685                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
1686         priv->params.rx_cq_moderation_pkts =
1687                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
1688         priv->params.tx_cq_moderation_usec =
1689                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
1690         priv->params.tx_cq_moderation_pkts =
1691                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
1692         priv->params.min_rx_wqes           =
1693                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
1694         priv->params.rx_hash_log_tbl_sz    =
1695                 (order_base_2(num_comp_vectors) >
1696                  MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
1697                 order_base_2(num_comp_vectors)           :
1698                 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
1699         priv->params.num_tc                = 1;
1700         priv->params.default_vlan_prio     = 0;
1701
1702         priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap);
1703         priv->params.lro_wqe_sz            =
1704                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
1705
1706         priv->mdev                         = mdev;
1707         priv->netdev                       = netdev;
1708         priv->params.num_channels          = num_comp_vectors;
1709         priv->order_base_2_num_channels    = order_base_2(num_comp_vectors);
1710         priv->queue_mapping_channel_mask   =
1711                 roundup_pow_of_two(num_comp_vectors) - 1;
1712         priv->num_tc                       = priv->params.num_tc;
1713         priv->default_vlan_prio            = priv->params.default_vlan_prio;
1714
1715         spin_lock_init(&priv->async_events_spinlock);
1716         mutex_init(&priv->state_lock);
1717
1718         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
1719         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
1720         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
1721 }
1722
1723 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
1724 {
1725         struct mlx5e_priv *priv = netdev_priv(netdev);
1726
1727         mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
1728 }
1729
1730 static void mlx5e_build_netdev(struct net_device *netdev)
1731 {
1732         struct mlx5e_priv *priv = netdev_priv(netdev);
1733         struct mlx5_core_dev *mdev = priv->mdev;
1734
1735         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
1736
1737         if (priv->num_tc > 1) {
1738                 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
1739                 mlx5e_netdev_ops.ndo_start_xmit   = mlx5e_xmit_multi_tc;
1740         }
1741
1742         netdev->netdev_ops        = &mlx5e_netdev_ops;
1743         netdev->watchdog_timeo    = 15 * HZ;
1744
1745         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
1746
1747         netdev->vlan_features    |= NETIF_F_IP_CSUM;
1748         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
1749         netdev->vlan_features    |= NETIF_F_GRO;
1750         netdev->vlan_features    |= NETIF_F_TSO;
1751         netdev->vlan_features    |= NETIF_F_TSO6;
1752         netdev->vlan_features    |= NETIF_F_RXCSUM;
1753         netdev->vlan_features    |= NETIF_F_RXHASH;
1754
1755         if (!!MLX5_CAP_ETH(mdev, lro_cap))
1756                 netdev->vlan_features    |= NETIF_F_LRO;
1757
1758         netdev->hw_features       = netdev->vlan_features;
1759         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
1760         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
1761
1762         netdev->features          = netdev->hw_features;
1763         if (!priv->params.lro_en)
1764                 netdev->features  &= ~NETIF_F_LRO;
1765
1766         netdev->features         |= NETIF_F_HIGHDMA;
1767
1768         netdev->priv_flags       |= IFF_UNICAST_FLT;
1769
1770         mlx5e_set_netdev_dev_addr(netdev);
1771 }
1772
1773 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
1774                              struct mlx5_core_mr *mr)
1775 {
1776         struct mlx5_core_dev *mdev = priv->mdev;
1777         struct mlx5_create_mkey_mbox_in *in;
1778         int err;
1779
1780         in = mlx5_vzalloc(sizeof(*in));
1781         if (!in)
1782                 return -ENOMEM;
1783
1784         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
1785                         MLX5_PERM_LOCAL_READ  |
1786                         MLX5_ACCESS_MODE_PA;
1787         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
1788         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1789
1790         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
1791                                     NULL);
1792
1793         kvfree(in);
1794
1795         return err;
1796 }
1797
1798 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
1799 {
1800         struct net_device *netdev;
1801         struct mlx5e_priv *priv;
1802         int ncv = mdev->priv.eq_table.num_comp_vectors;
1803         int err;
1804
1805         if (mlx5e_check_required_hca_cap(mdev))
1806                 return NULL;
1807
1808         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
1809                                     roundup_pow_of_two(ncv) * MLX5E_MAX_NUM_TC,
1810                                     ncv);
1811         if (!netdev) {
1812                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
1813                 return NULL;
1814         }
1815
1816         mlx5e_build_netdev_priv(mdev, netdev, ncv);
1817         mlx5e_build_netdev(netdev);
1818
1819         netif_carrier_off(netdev);
1820
1821         priv = netdev_priv(netdev);
1822
1823         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
1824         if (err) {
1825                 netdev_err(netdev, "%s: mlx5_alloc_map_uar failed, %d\n",
1826                            __func__, err);
1827                 goto err_free_netdev;
1828         }
1829
1830         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
1831         if (err) {
1832                 netdev_err(netdev, "%s: mlx5_core_alloc_pd failed, %d\n",
1833                            __func__, err);
1834                 goto err_unmap_free_uar;
1835         }
1836
1837         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
1838         if (err) {
1839                 netdev_err(netdev, "%s: mlx5e_create_mkey failed, %d\n",
1840                            __func__, err);
1841                 goto err_dealloc_pd;
1842         }
1843
1844         err = register_netdev(netdev);
1845         if (err) {
1846                 netdev_err(netdev, "%s: register_netdev failed, %d\n",
1847                            __func__, err);
1848                 goto err_destroy_mkey;
1849         }
1850
1851         mlx5e_enable_async_events(priv);
1852
1853         return priv;
1854
1855 err_destroy_mkey:
1856         mlx5_core_destroy_mkey(mdev, &priv->mr);
1857
1858 err_dealloc_pd:
1859         mlx5_core_dealloc_pd(mdev, priv->pdn);
1860
1861 err_unmap_free_uar:
1862         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
1863
1864 err_free_netdev:
1865         free_netdev(netdev);
1866
1867         return NULL;
1868 }
1869
1870 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
1871 {
1872         struct mlx5e_priv *priv = vpriv;
1873         struct net_device *netdev = priv->netdev;
1874
1875         unregister_netdev(netdev);
1876         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
1877         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
1878         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
1879         mlx5e_disable_async_events(priv);
1880         flush_scheduled_work();
1881         free_netdev(netdev);
1882 }
1883
1884 static void *mlx5e_get_netdev(void *vpriv)
1885 {
1886         struct mlx5e_priv *priv = vpriv;
1887
1888         return priv->netdev;
1889 }
1890
1891 static struct mlx5_interface mlx5e_interface = {
1892         .add       = mlx5e_create_netdev,
1893         .remove    = mlx5e_destroy_netdev,
1894         .event     = mlx5e_async_event,
1895         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
1896         .get_dev   = mlx5e_get_netdev,
1897 };
1898
1899 void mlx5e_init(void)
1900 {
1901         mlx5_register_interface(&mlx5e_interface);
1902 }
1903
1904 void mlx5e_cleanup(void)
1905 {
1906         mlx5_unregister_interface(&mlx5e_interface);
1907 }