drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include <net/page_pool.h>
  39 #include "eswitch.h"
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "en_rep.h"
  43 #include "en_accel/ipsec.h"
  44 #include "en_accel/ipsec_rxtx.h"
  45 #include "en_accel/tls.h"
  46 #include "accel/ipsec.h"
  47 #include "accel/tls.h"
  48 #include "lib/vxlan.h"
  49 #include "lib/clock.h"
  50 #include "en/port.h"
  51 #include "en/xdp.h"
  52 #include "lib/eq.h"
  53 #include "en/monitor_stats.h"
  54
  55 struct mlx5e_rq_param {
  56         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  57         struct mlx5_wq_param    wq;
  58         struct mlx5e_rq_frags_info frags_info;
  59 };
  60
  61 struct mlx5e_sq_param {
  62         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  63         struct mlx5_wq_param       wq;
  64         bool                       is_mpw;
  65 };
  66
  67 struct mlx5e_cq_param {
  68         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  69         struct mlx5_wq_param       wq;
  70         u16                        eq_ix;
  71         u8                         cq_period_mode;
  72 };
  73
  74 struct mlx5e_channel_param {
  75         struct mlx5e_rq_param      rq;
  76         struct mlx5e_sq_param      sq;
  77         struct mlx5e_sq_param      xdp_sq;
  78         struct mlx5e_sq_param      icosq;
  79         struct mlx5e_cq_param      rx_cq;
  80         struct mlx5e_cq_param      tx_cq;
  81         struct mlx5e_cq_param      icosq_cq;
  82 };
  83
  84 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  85 {
  86         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  87                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  88                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  89         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  90         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  91
  92         if (!striding_rq_umr)
  93                 return false;
  94         if (!inline_umr) {
  95                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  96                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  97                 return false;
  98         }
  99         return true;
 100 }
 101
 102 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
 103 {
 104         u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 105         u16 linear_rq_headroom = params->xdp_prog ?
 106                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 107         u32 frag_sz;
 108
 109         linear_rq_headroom += NET_IP_ALIGN;
 110
 111         frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
 112
 113         if (params->xdp_prog && frag_sz < PAGE_SIZE)
 114                 frag_sz = PAGE_SIZE;
 115
 116         return frag_sz;
 117 }
 118
 119 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 120 {
 121         u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 122
 123         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 124 }
 125
 126 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
 127                                    struct mlx5e_params *params)
 128 {
 129         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 130
 131         return !params->lro_en && frag_sz <= PAGE_SIZE;
 132 }
 133
 134 #define MLX5_MAX_MPWQE_LOG_WQE_STRIDE_SZ ((BIT(__mlx5_bit_sz(wq, log_wqe_stride_size)) - 1) + \
 135                                           MLX5_MPWQE_LOG_STRIDE_SZ_BASE)
 136 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 137                                          struct mlx5e_params *params)
 138 {
 139         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 140         s8 signed_log_num_strides_param;
 141         u8 log_num_strides;
 142
 143         if (!mlx5e_rx_is_linear_skb(mdev, params))
 144                 return false;
 145
 146         if (order_base_2(frag_sz) > MLX5_MAX_MPWQE_LOG_WQE_STRIDE_SZ)
 147                 return false;
 148
 149         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 150                 return true;
 151
 152         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 153         signed_log_num_strides_param =
 154                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 155
 156         return signed_log_num_strides_param >= 0;
 157 }
 158
 159 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 160 {
 161         if (params->log_rq_mtu_frames <
 162             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 163                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 164
 165         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 166 }
 167
 168 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 169                                           struct mlx5e_params *params)
 170 {
 171         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 172                 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
 173
 174         return MLX5E_MPWQE_STRIDE_SZ(mdev,
 175                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 176 }
 177
 178 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 179                                           struct mlx5e_params *params)
 180 {
 181         return MLX5_MPWRQ_LOG_WQE_SZ -
 182                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 183 }
 184
 185 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 186                                  struct mlx5e_params *params)
 187 {
 188         u16 linear_rq_headroom = params->xdp_prog ?
 189                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 190         bool is_linear_skb;
 191
 192         linear_rq_headroom += NET_IP_ALIGN;
 193
 194         is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
 195                 mlx5e_rx_is_linear_skb(mdev, params) :
 196                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
 197
 198         return is_linear_skb ? linear_rq_headroom : 0;
 199 }
 200
 201 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 202                                struct mlx5e_params *params)
 203 {
 204         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 205         params->log_rq_mtu_frames = is_kdump_kernel() ?
 206                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 207                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 208
 209         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 210                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 211                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 212                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 213                        BIT(params->log_rq_mtu_frames),
 214                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 215                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 216 }
 217
 218 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 219                                 struct mlx5e_params *params)
 220 {
 221         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 222                 !MLX5_IPSEC_DEV(mdev) &&
 223                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 224 }
 225
 226 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 227 {
 228         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 229                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 230                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 231                 MLX5_WQ_TYPE_CYCLIC;
 232 }
 233
 234 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 235 {
 236         struct mlx5_core_dev *mdev = priv->mdev;
 237         u8 port_state;
 238
 239         port_state = mlx5_query_vport_state(mdev,
 240                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 241                                             0);
 242
 243         if (port_state == VPORT_STATE_UP) {
 244                 netdev_info(priv->netdev, "Link up\n");
 245                 netif_carrier_on(priv->netdev);
 246         } else {
 247                 netdev_info(priv->netdev, "Link down\n");
 248                 netif_carrier_off(priv->netdev);
 249         }
 250 }
 251
 252 static void mlx5e_update_carrier_work(struct work_struct *work)
 253 {
 254         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 255                                                update_carrier_work);
 256
 257         mutex_lock(&priv->state_lock);
 258         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 259                 if (priv->profile->update_carrier)
 260                         priv->profile->update_carrier(priv);
 261         mutex_unlock(&priv->state_lock);
 262 }
 263
 264 void mlx5e_update_stats(struct mlx5e_priv *priv)
 265 {
 266         int i;
 267
 268         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 269                 if (mlx5e_stats_grps[i].update_stats)
 270                         mlx5e_stats_grps[i].update_stats(priv);
 271 }
 272
 273 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 274 {
 275         int i;
 276
 277         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 278                 if (mlx5e_stats_grps[i].update_stats_mask &
 279                     MLX5E_NDO_UPDATE_STATS)
 280                         mlx5e_stats_grps[i].update_stats(priv);
 281 }
 282
 283 static void mlx5e_update_stats_work(struct work_struct *work)
 284 {
 285         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 286                                                update_stats_work);
 287
 288         mutex_lock(&priv->state_lock);
 289         priv->profile->update_stats(priv);
 290         mutex_unlock(&priv->state_lock);
 291 }
 292
 293 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 294 {
 295         if (!priv->profile->update_stats)
 296                 return;
 297
 298         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 299                 return;
 300
 301         queue_work(priv->wq, &priv->update_stats_work);
 302 }
 303
 304 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 305 {
 306         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 307         struct mlx5_eqe   *eqe = data;
 308
 309         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 310                 return NOTIFY_DONE;
 311
 312         switch (eqe->sub_type) {
 313         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 314         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 315                 queue_work(priv->wq, &priv->update_carrier_work);
 316                 break;
 317         default:
 318                 return NOTIFY_DONE;
 319         }
 320
 321         return NOTIFY_OK;
 322 }
 323
 324 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 325 {
 326         priv->events_nb.notifier_call = async_event;
 327         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 328 }
 329
 330 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 331 {
 332         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 333 }
 334
 335 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 336                                        struct mlx5e_icosq *sq,
 337                                        struct mlx5e_umr_wqe *wqe)
 338 {
 339         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 340         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 341         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 342
 343         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 344                                       ds_cnt);
 345         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 346         cseg->imm       = rq->mkey_be;
 347
 348         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 349         ucseg->xlt_octowords =
 350                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 351         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 352 }
 353
 354 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 355 {
 356         switch (rq->wq_type) {
 357         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 358                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 359         default:
 360                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 361         }
 362 }
 363
 364 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 365 {
 366         switch (rq->wq_type) {
 367         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 368                 return rq->mpwqe.wq.cur_sz;
 369         default:
 370                 return rq->wqe.wq.cur_sz;
 371         }
 372 }
 373
 374 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 375                                      struct mlx5e_channel *c)
 376 {
 377         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 378
 379         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 380                                                   sizeof(*rq->mpwqe.info)),
 381                                        GFP_KERNEL, cpu_to_node(c->cpu));
 382         if (!rq->mpwqe.info)
 383                 return -ENOMEM;
 384
 385         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 386
 387         return 0;
 388 }
 389
 390 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 391                                  u64 npages, u8 page_shift,
 392                                  struct mlx5_core_mkey *umr_mkey)
 393 {
 394         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 395         void *mkc;
 396         u32 *in;
 397         int err;
 398
 399         in = kvzalloc(inlen, GFP_KERNEL);
 400         if (!in)
 401                 return -ENOMEM;
 402
 403         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 404
 405         MLX5_SET(mkc, mkc, free, 1);
 406         MLX5_SET(mkc, mkc, umr_en, 1);
 407         MLX5_SET(mkc, mkc, lw, 1);
 408         MLX5_SET(mkc, mkc, lr, 1);
 409         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 410
 411         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 412         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 413         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 414         MLX5_SET(mkc, mkc, translations_octword_size,
 415                  MLX5_MTT_OCTW(npages));
 416         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 417
 418         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 419
 420         kvfree(in);
 421         return err;
 422 }
 423
 424 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 425 {
 426         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 427
 428         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 429 }
 430
 431 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 432 {
 433         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 434 }
 435
 436 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 437 {
 438         struct mlx5e_wqe_frag_info next_frag, *prev;
 439         int i;
 440
 441         next_frag.di = &rq->wqe.di[0];
 442         next_frag.offset = 0;
 443         prev = NULL;
 444
 445         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 446                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 447                 struct mlx5e_wqe_frag_info *frag =
 448                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 449                 int f;
 450
 451                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 452                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 453                                 next_frag.di++;
 454                                 next_frag.offset = 0;
 455                                 if (prev)
 456                                         prev->last_in_page = true;
 457                         }
 458                         *frag = next_frag;
 459
 460                         /* prepare next */
 461                         next_frag.offset += frag_info[f].frag_stride;
 462                         prev = frag;
 463                 }
 464         }
 465
 466         if (prev)
 467                 prev->last_in_page = true;
 468 }
 469
 470 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 471                               struct mlx5e_params *params,
 472                               int wq_sz, int cpu)
 473 {
 474         int len = wq_sz << rq->wqe.info.log_num_frags;
 475
 476         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 477                                    GFP_KERNEL, cpu_to_node(cpu));
 478         if (!rq->wqe.di)
 479                 return -ENOMEM;
 480
 481         mlx5e_init_frags_partition(rq);
 482
 483         return 0;
 484 }
 485
 486 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 487 {
 488         kvfree(rq->wqe.di);
 489 }
 490
 491 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 492                           struct mlx5e_params *params,
 493                           struct mlx5e_rq_param *rqp,
 494                           struct mlx5e_rq *rq)
 495 {
 496         struct page_pool_params pp_params = { 0 };
 497         struct mlx5_core_dev *mdev = c->mdev;
 498         void *rqc = rqp->rqc;
 499         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 500         u32 pool_size;
 501         int wq_sz;
 502         int err;
 503         int i;
 504
 505         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 506
 507         rq->wq_type = params->rq_wq_type;
 508         rq->pdev    = c->pdev;
 509         rq->netdev  = c->netdev;
 510         rq->tstamp  = c->tstamp;
 511         rq->clock   = &mdev->clock;
 512         rq->channel = c;
 513         rq->ix      = c->ix;
 514         rq->mdev    = mdev;
 515         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 516         rq->stats   = &c->priv->channel_stats[c->ix].rq;
 517
 518         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 519         if (IS_ERR(rq->xdp_prog)) {
 520                 err = PTR_ERR(rq->xdp_prog);
 521                 rq->xdp_prog = NULL;
 522                 goto err_rq_wq_destroy;
 523         }
 524
 525         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 526         if (err < 0)
 527                 goto err_rq_wq_destroy;
 528
 529         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 530         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 531         pool_size = 1 << params->log_rq_mtu_frames;
 532
 533         switch (rq->wq_type) {
 534         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 535                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 536                                         &rq->wq_ctrl);
 537                 if (err)
 538                         return err;
 539
 540                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 541
 542                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 543
 544                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 545
 546                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 547                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 548
 549                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 550 #ifdef CONFIG_MLX5_EN_IPSEC
 551                 if (MLX5_IPSEC_DEV(mdev)) {
 552                         err = -EINVAL;
 553                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 554                         goto err_rq_wq_destroy;
 555                 }
 556 #endif
 557                 if (!rq->handle_rx_cqe) {
 558                         err = -EINVAL;
 559                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 560                         goto err_rq_wq_destroy;
 561                 }
 562
 563                 rq->mpwqe.skb_from_cqe_mpwrq =
 564                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 565                         mlx5e_skb_from_cqe_mpwrq_linear :
 566                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 567                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 568                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 569
 570                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 571                 if (err)
 572                         goto err_rq_wq_destroy;
 573                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 574
 575                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 576                 if (err)
 577                         goto err_free;
 578                 break;
 579         default: /* MLX5_WQ_TYPE_CYCLIC */
 580                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 581                                          &rq->wq_ctrl);
 582                 if (err)
 583                         return err;
 584
 585                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 586
 587                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 588
 589                 rq->wqe.info = rqp->frags_info;
 590                 rq->wqe.frags =
 591                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 592                                         (wq_sz << rq->wqe.info.log_num_frags)),
 593                                       GFP_KERNEL, cpu_to_node(c->cpu));
 594                 if (!rq->wqe.frags) {
 595                         err = -ENOMEM;
 596                         goto err_free;
 597                 }
 598
 599                 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
 600                 if (err)
 601                         goto err_free;
 602                 rq->post_wqes = mlx5e_post_rx_wqes;
 603                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 604
 605 #ifdef CONFIG_MLX5_EN_IPSEC
 606                 if (c->priv->ipsec)
 607                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 608                 else
 609 #endif
 610                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 611                 if (!rq->handle_rx_cqe) {
 612                         err = -EINVAL;
 613                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 614                         goto err_free;
 615                 }
 616
 617                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
 618                         mlx5e_skb_from_cqe_linear :
 619                         mlx5e_skb_from_cqe_nonlinear;
 620                 rq->mkey_be = c->mkey_be;
 621         }
 622
 623         /* Create a page_pool and register it with rxq */
 624         pp_params.order     = 0;
 625         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 626         pp_params.pool_size = pool_size;
 627         pp_params.nid       = cpu_to_node(c->cpu);
 628         pp_params.dev       = c->pdev;
 629         pp_params.dma_dir   = rq->buff.map_dir;
 630
 631         /* page_pool can be used even when there is no rq->xdp_prog,
 632          * given page_pool does not handle DMA mapping there is no
 633          * required state to clear. And page_pool gracefully handle
 634          * elevated refcnt.
 635          */
 636         rq->page_pool = page_pool_create(&pp_params);
 637         if (IS_ERR(rq->page_pool)) {
 638                 err = PTR_ERR(rq->page_pool);
 639                 rq->page_pool = NULL;
 640                 goto err_free;
 641         }
 642         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 643                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 644         if (err)
 645                 goto err_free;
 646
 647         for (i = 0; i < wq_sz; i++) {
 648                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 649                         struct mlx5e_rx_wqe_ll *wqe =
 650                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 651                         u32 byte_count =
 652                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 653                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 654
 655                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 656                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 657                         wqe->data[0].lkey = rq->mkey_be;
 658                 } else {
 659                         struct mlx5e_rx_wqe_cyc *wqe =
 660                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 661                         int f;
 662
 663                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 664                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 665                                         MLX5_HW_START_PADDING;
 666
 667                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 668                                 wqe->data[f].lkey = rq->mkey_be;
 669                         }
 670                         /* check if num_frags is not a pow of two */
 671                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 672                                 wqe->data[f].byte_count = 0;
 673                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 674                                 wqe->data[f].addr = 0;
 675                         }
 676                 }
 677         }
 678
 679         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 680
 681         switch (params->rx_cq_moderation.cq_period_mode) {
 682         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 683                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 684                 break;
 685         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 686         default:
 687                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 688         }
 689
 690         rq->page_cache.head = 0;
 691         rq->page_cache.tail = 0;
 692
 693         return 0;
 694
 695 err_free:
 696         switch (rq->wq_type) {
 697         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 698                 kvfree(rq->mpwqe.info);
 699                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 700                 break;
 701         default: /* MLX5_WQ_TYPE_CYCLIC */
 702                 kvfree(rq->wqe.frags);
 703                 mlx5e_free_di_list(rq);
 704         }
 705
 706 err_rq_wq_destroy:
 707         if (rq->xdp_prog)
 708                 bpf_prog_put(rq->xdp_prog);
 709         xdp_rxq_info_unreg(&rq->xdp_rxq);
 710         if (rq->page_pool)
 711                 page_pool_destroy(rq->page_pool);
 712         mlx5_wq_destroy(&rq->wq_ctrl);
 713
 714         return err;
 715 }
 716
 717 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 718 {
 719         int i;
 720
 721         if (rq->xdp_prog)
 722                 bpf_prog_put(rq->xdp_prog);
 723
 724         xdp_rxq_info_unreg(&rq->xdp_rxq);
 725         if (rq->page_pool)
 726                 page_pool_destroy(rq->page_pool);
 727
 728         switch (rq->wq_type) {
 729         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 730                 kvfree(rq->mpwqe.info);
 731                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 732                 break;
 733         default: /* MLX5_WQ_TYPE_CYCLIC */
 734                 kvfree(rq->wqe.frags);
 735                 mlx5e_free_di_list(rq);
 736         }
 737
 738         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 739              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 740                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 741
 742                 mlx5e_page_release(rq, dma_info, false);
 743         }
 744         mlx5_wq_destroy(&rq->wq_ctrl);
 745 }
 746
 747 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 748                            struct mlx5e_rq_param *param)
 749 {
 750         struct mlx5_core_dev *mdev = rq->mdev;
 751
 752         void *in;
 753         void *rqc;
 754         void *wq;
 755         int inlen;
 756         int err;
 757
 758         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 759                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 760         in = kvzalloc(inlen, GFP_KERNEL);
 761         if (!in)
 762                 return -ENOMEM;
 763
 764         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 765         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 766
 767         memcpy(rqc, param->rqc, sizeof(param->rqc));
 768
 769         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 770         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 771         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 772                                                 MLX5_ADAPTER_PAGE_SHIFT);
 773         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 774
 775         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 776                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 777
 778         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 779
 780         kvfree(in);
 781
 782         return err;
 783 }
 784
 785 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 786                                  int next_state)
 787 {
 788         struct mlx5_core_dev *mdev = rq->mdev;
 789
 790         void *in;
 791         void *rqc;
 792         int inlen;
 793         int err;
 794
 795         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 796         in = kvzalloc(inlen, GFP_KERNEL);
 797         if (!in)
 798                 return -ENOMEM;
 799
 800         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 801
 802         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 803         MLX5_SET(rqc, rqc, state, next_state);
 804
 805         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 806
 807         kvfree(in);
 808
 809         return err;
 810 }
 811
 812 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 813 {
 814         struct mlx5e_channel *c = rq->channel;
 815         struct mlx5e_priv *priv = c->priv;
 816         struct mlx5_core_dev *mdev = priv->mdev;
 817
 818         void *in;
 819         void *rqc;
 820         int inlen;
 821         int err;
 822
 823         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 824         in = kvzalloc(inlen, GFP_KERNEL);
 825         if (!in)
 826                 return -ENOMEM;
 827
 828         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 829
 830         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 831         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 832                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 833         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 834         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 835
 836         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 837
 838         kvfree(in);
 839
 840         return err;
 841 }
 842
 843 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 844 {
 845         struct mlx5e_channel *c = rq->channel;
 846         struct mlx5_core_dev *mdev = c->mdev;
 847         void *in;
 848         void *rqc;
 849         int inlen;
 850         int err;
 851
 852         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 853         in = kvzalloc(inlen, GFP_KERNEL);
 854         if (!in)
 855                 return -ENOMEM;
 856
 857         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 858
 859         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 860         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 861                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 862         MLX5_SET(rqc, rqc, vsd, vsd);
 863         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 864
 865         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 866
 867         kvfree(in);
 868
 869         return err;
 870 }
 871
 872 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 873 {
 874         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 875 }
 876
 877 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 878 {
 879         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 880         struct mlx5e_channel *c = rq->channel;
 881
 882         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 883
 884         do {
 885                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 886                         return 0;
 887
 888                 msleep(20);
 889         } while (time_before(jiffies, exp_time));
 890
 891         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 892                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 893
 894         return -ETIMEDOUT;
 895 }
 896
 897 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 898 {
 899         __be16 wqe_ix_be;
 900         u16 wqe_ix;
 901
 902         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 903                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 904
 905                 /* UMR WQE (if in progress) is always at wq->head */
 906                 if (rq->mpwqe.umr_in_progress)
 907                         rq->dealloc_wqe(rq, wq->head);
 908
 909                 while (!mlx5_wq_ll_is_empty(wq)) {
 910                         struct mlx5e_rx_wqe_ll *wqe;
 911
 912                         wqe_ix_be = *wq->tail_next;
 913                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 914                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 915                         rq->dealloc_wqe(rq, wqe_ix);
 916                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 917                                        &wqe->next.next_wqe_index);
 918                 }
 919         } else {
 920                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 921
 922                 while (!mlx5_wq_cyc_is_empty(wq)) {
 923                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 924                         rq->dealloc_wqe(rq, wqe_ix);
 925                         mlx5_wq_cyc_pop(wq);
 926                 }
 927         }
 928
 929 }
 930
 931 static int mlx5e_open_rq(struct mlx5e_channel *c,
 932                          struct mlx5e_params *params,
 933                          struct mlx5e_rq_param *param,
 934                          struct mlx5e_rq *rq)
 935 {
 936         int err;
 937
 938         err = mlx5e_alloc_rq(c, params, param, rq);
 939         if (err)
 940                 return err;
 941
 942         err = mlx5e_create_rq(rq, param);
 943         if (err)
 944                 goto err_free_rq;
 945
 946         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 947         if (err)
 948                 goto err_destroy_rq;
 949
 950         if (params->rx_dim_enabled)
 951                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 952
 953         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE))
 954                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 955
 956         return 0;
 957
 958 err_destroy_rq:
 959         mlx5e_destroy_rq(rq);
 960 err_free_rq:
 961         mlx5e_free_rq(rq);
 962
 963         return err;
 964 }
 965
 966 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 967 {
 968         struct mlx5e_icosq *sq = &rq->channel->icosq;
 969         struct mlx5_wq_cyc *wq = &sq->wq;
 970         struct mlx5e_tx_wqe *nopwqe;
 971
 972         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 973
 974         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 975         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 976         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 977         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 978 }
 979
 980 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 981 {
 982         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 983         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 984 }
 985
 986 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 987 {
 988         cancel_work_sync(&rq->dim.work);
 989         mlx5e_destroy_rq(rq);
 990         mlx5e_free_rx_descs(rq);
 991         mlx5e_free_rq(rq);
 992 }
 993
 994 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 995 {
 996         kvfree(sq->db.xdpi_fifo.xi);
 997         kvfree(sq->db.wqe_info);
 998 }
 999
1000 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1001 {
1002         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1003         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
1004         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1005
1006         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
1007                                       GFP_KERNEL, numa);
1008         if (!xdpi_fifo->xi)
1009                 return -ENOMEM;
1010
1011         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
1012         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
1013         xdpi_fifo->mask = dsegs_per_wq - 1;
1014
1015         return 0;
1016 }
1017
1018 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1019 {
1020         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1021         int err;
1022
1023         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
1024                                         GFP_KERNEL, numa);
1025         if (!sq->db.wqe_info)
1026                 return -ENOMEM;
1027
1028         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1029         if (err) {
1030                 mlx5e_free_xdpsq_db(sq);
1031                 return err;
1032         }
1033
1034         return 0;
1035 }
1036
1037 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1038                              struct mlx5e_params *params,
1039                              struct mlx5e_sq_param *param,
1040                              struct mlx5e_xdpsq *sq,
1041                              bool is_redirect)
1042 {
1043         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1044         struct mlx5_core_dev *mdev = c->mdev;
1045         struct mlx5_wq_cyc *wq = &sq->wq;
1046         int err;
1047
1048         sq->pdev      = c->pdev;
1049         sq->mkey_be   = c->mkey_be;
1050         sq->channel   = c;
1051         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1052         sq->min_inline_mode = params->tx_min_inline_mode;
1053         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1054         sq->stats     = is_redirect ?
1055                 &c->priv->channel_stats[c->ix].xdpsq :
1056                 &c->priv->channel_stats[c->ix].rq_xdpsq;
1057
1058         param->wq.db_numa_node = cpu_to_node(c->cpu);
1059         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1060         if (err)
1061                 return err;
1062         wq->db = &wq->db[MLX5_SND_DBR];
1063
1064         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1065         if (err)
1066                 goto err_sq_wq_destroy;
1067
1068         return 0;
1069
1070 err_sq_wq_destroy:
1071         mlx5_wq_destroy(&sq->wq_ctrl);
1072
1073         return err;
1074 }
1075
1076 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1077 {
1078         mlx5e_free_xdpsq_db(sq);
1079         mlx5_wq_destroy(&sq->wq_ctrl);
1080 }
1081
1082 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1083 {
1084         kvfree(sq->db.ico_wqe);
1085 }
1086
1087 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1088 {
1089         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1090
1091         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1092                                                   sizeof(*sq->db.ico_wqe)),
1093                                        GFP_KERNEL, numa);
1094         if (!sq->db.ico_wqe)
1095                 return -ENOMEM;
1096
1097         return 0;
1098 }
1099
1100 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1101                              struct mlx5e_sq_param *param,
1102                              struct mlx5e_icosq *sq)
1103 {
1104         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1105         struct mlx5_core_dev *mdev = c->mdev;
1106         struct mlx5_wq_cyc *wq = &sq->wq;
1107         int err;
1108
1109         sq->channel   = c;
1110         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1111
1112         param->wq.db_numa_node = cpu_to_node(c->cpu);
1113         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1114         if (err)
1115                 return err;
1116         wq->db = &wq->db[MLX5_SND_DBR];
1117
1118         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1119         if (err)
1120                 goto err_sq_wq_destroy;
1121
1122         return 0;
1123
1124 err_sq_wq_destroy:
1125         mlx5_wq_destroy(&sq->wq_ctrl);
1126
1127         return err;
1128 }
1129
1130 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1131 {
1132         mlx5e_free_icosq_db(sq);
1133         mlx5_wq_destroy(&sq->wq_ctrl);
1134 }
1135
1136 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1137 {
1138         kvfree(sq->db.wqe_info);
1139         kvfree(sq->db.dma_fifo);
1140 }
1141
1142 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1143 {
1144         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1145         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1146
1147         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1148                                                    sizeof(*sq->db.dma_fifo)),
1149                                         GFP_KERNEL, numa);
1150         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1151                                                    sizeof(*sq->db.wqe_info)),
1152                                         GFP_KERNEL, numa);
1153         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1154                 mlx5e_free_txqsq_db(sq);
1155                 return -ENOMEM;
1156         }
1157
1158         sq->dma_fifo_mask = df_sz - 1;
1159
1160         return 0;
1161 }
1162
1163 static void mlx5e_sq_recover(struct work_struct *work);
1164 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1165                              int txq_ix,
1166                              struct mlx5e_params *params,
1167                              struct mlx5e_sq_param *param,
1168                              struct mlx5e_txqsq *sq,
1169                              int tc)
1170 {
1171         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1172         struct mlx5_core_dev *mdev = c->mdev;
1173         struct mlx5_wq_cyc *wq = &sq->wq;
1174         int err;
1175
1176         sq->pdev      = c->pdev;
1177         sq->tstamp    = c->tstamp;
1178         sq->clock     = &mdev->clock;
1179         sq->mkey_be   = c->mkey_be;
1180         sq->channel   = c;
1181         sq->txq_ix    = txq_ix;
1182         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1183         sq->min_inline_mode = params->tx_min_inline_mode;
1184         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1185         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1186         if (MLX5_IPSEC_DEV(c->priv->mdev))
1187                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1188         if (mlx5_accel_is_tls_device(c->priv->mdev))
1189                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1190
1191         param->wq.db_numa_node = cpu_to_node(c->cpu);
1192         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1193         if (err)
1194                 return err;
1195         wq->db    = &wq->db[MLX5_SND_DBR];
1196
1197         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1198         if (err)
1199                 goto err_sq_wq_destroy;
1200
1201         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1202         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1203
1204         return 0;
1205
1206 err_sq_wq_destroy:
1207         mlx5_wq_destroy(&sq->wq_ctrl);
1208
1209         return err;
1210 }
1211
1212 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1213 {
1214         mlx5e_free_txqsq_db(sq);
1215         mlx5_wq_destroy(&sq->wq_ctrl);
1216 }
1217
1218 struct mlx5e_create_sq_param {
1219         struct mlx5_wq_ctrl        *wq_ctrl;
1220         u32                         cqn;
1221         u32                         tisn;
1222         u8                          tis_lst_sz;
1223         u8                          min_inline_mode;
1224 };
1225
1226 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1227                            struct mlx5e_sq_param *param,
1228                            struct mlx5e_create_sq_param *csp,
1229                            u32 *sqn)
1230 {
1231         void *in;
1232         void *sqc;
1233         void *wq;
1234         int inlen;
1235         int err;
1236
1237         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1238                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1239         in = kvzalloc(inlen, GFP_KERNEL);
1240         if (!in)
1241                 return -ENOMEM;
1242
1243         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1244         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1245
1246         memcpy(sqc, param->sqc, sizeof(param->sqc));
1247         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1248         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1249         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1250
1251         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1252                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1253
1254         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1255         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1256
1257         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1258         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1259         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1260                                           MLX5_ADAPTER_PAGE_SHIFT);
1261         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1262
1263         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1264                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1265
1266         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1267
1268         kvfree(in);
1269
1270         return err;
1271 }
1272
1273 struct mlx5e_modify_sq_param {
1274         int curr_state;
1275         int next_state;
1276         bool rl_update;
1277         int rl_index;
1278 };
1279
1280 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1281                            struct mlx5e_modify_sq_param *p)
1282 {
1283         void *in;
1284         void *sqc;
1285         int inlen;
1286         int err;
1287
1288         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1289         in = kvzalloc(inlen, GFP_KERNEL);
1290         if (!in)
1291                 return -ENOMEM;
1292
1293         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1294
1295         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1296         MLX5_SET(sqc, sqc, state, p->next_state);
1297         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1298                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1299                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1300         }
1301
1302         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1303
1304         kvfree(in);
1305
1306         return err;
1307 }
1308
1309 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1310 {
1311         mlx5_core_destroy_sq(mdev, sqn);
1312 }
1313
1314 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1315                                struct mlx5e_sq_param *param,
1316                                struct mlx5e_create_sq_param *csp,
1317                                u32 *sqn)
1318 {
1319         struct mlx5e_modify_sq_param msp = {0};
1320         int err;
1321
1322         err = mlx5e_create_sq(mdev, param, csp, sqn);
1323         if (err)
1324                 return err;
1325
1326         msp.curr_state = MLX5_SQC_STATE_RST;
1327         msp.next_state = MLX5_SQC_STATE_RDY;
1328         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1329         if (err)
1330                 mlx5e_destroy_sq(mdev, *sqn);
1331
1332         return err;
1333 }
1334
1335 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1336                                 struct mlx5e_txqsq *sq, u32 rate);
1337
1338 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1339                             u32 tisn,
1340                             int txq_ix,
1341                             struct mlx5e_params *params,
1342                             struct mlx5e_sq_param *param,
1343                             struct mlx5e_txqsq *sq,
1344                             int tc)
1345 {
1346         struct mlx5e_create_sq_param csp = {};
1347         u32 tx_rate;
1348         int err;
1349
1350         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1351         if (err)
1352                 return err;
1353
1354         csp.tisn            = tisn;
1355         csp.tis_lst_sz      = 1;
1356         csp.cqn             = sq->cq.mcq.cqn;
1357         csp.wq_ctrl         = &sq->wq_ctrl;
1358         csp.min_inline_mode = sq->min_inline_mode;
1359         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1360         if (err)
1361                 goto err_free_txqsq;
1362
1363         tx_rate = c->priv->tx_rates[sq->txq_ix];
1364         if (tx_rate)
1365                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1366
1367         if (params->tx_dim_enabled)
1368                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1369
1370         return 0;
1371
1372 err_free_txqsq:
1373         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1374         mlx5e_free_txqsq(sq);
1375
1376         return err;
1377 }
1378
1379 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1380 {
1381         WARN_ONCE(sq->cc != sq->pc,
1382                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1383                   sq->sqn, sq->cc, sq->pc);
1384         sq->cc = 0;
1385         sq->dma_fifo_cc = 0;
1386         sq->pc = 0;
1387 }
1388
1389 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1390 {
1391         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1392         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1393         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1394         netdev_tx_reset_queue(sq->txq);
1395         netif_tx_start_queue(sq->txq);
1396 }
1397
1398 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1399 {
1400         __netif_tx_lock_bh(txq);
1401         netif_tx_stop_queue(txq);
1402         __netif_tx_unlock_bh(txq);
1403 }
1404
1405 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1406 {
1407         struct mlx5e_channel *c = sq->channel;
1408         struct mlx5_wq_cyc *wq = &sq->wq;
1409
1410         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1411         /* prevent netif_tx_wake_queue */
1412         napi_synchronize(&c->napi);
1413
1414         netif_tx_disable_queue(sq->txq);
1415
1416         /* last doorbell out, godspeed .. */
1417         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1418                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1419                 struct mlx5e_tx_wqe *nop;
1420
1421                 sq->db.wqe_info[pi].skb = NULL;
1422                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1423                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1424         }
1425 }
1426
1427 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1428 {
1429         struct mlx5e_channel *c = sq->channel;
1430         struct mlx5_core_dev *mdev = c->mdev;
1431         struct mlx5_rate_limit rl = {0};
1432
1433         cancel_work_sync(&sq->dim.work);
1434         mlx5e_destroy_sq(mdev, sq->sqn);
1435         if (sq->rate_limit) {
1436                 rl.rate = sq->rate_limit;
1437                 mlx5_rl_remove_rate(mdev, &rl);
1438         }
1439         mlx5e_free_txqsq_descs(sq);
1440         mlx5e_free_txqsq(sq);
1441 }
1442
1443 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1444 {
1445         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1446
1447         while (time_before(jiffies, exp_time)) {
1448                 if (sq->cc == sq->pc)
1449                         return 0;
1450
1451                 msleep(20);
1452         }
1453
1454         netdev_err(sq->channel->netdev,
1455                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1456                    sq->sqn, sq->cc, sq->pc);
1457
1458         return -ETIMEDOUT;
1459 }
1460
1461 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1462 {
1463         struct mlx5_core_dev *mdev = sq->channel->mdev;
1464         struct net_device *dev = sq->channel->netdev;
1465         struct mlx5e_modify_sq_param msp = {0};
1466         int err;
1467
1468         msp.curr_state = curr_state;
1469         msp.next_state = MLX5_SQC_STATE_RST;
1470
1471         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1472         if (err) {
1473                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1474                 return err;
1475         }
1476
1477         memset(&msp, 0, sizeof(msp));
1478         msp.curr_state = MLX5_SQC_STATE_RST;
1479         msp.next_state = MLX5_SQC_STATE_RDY;
1480
1481         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1482         if (err) {
1483                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1484                 return err;
1485         }
1486
1487         return 0;
1488 }
1489
1490 static void mlx5e_sq_recover(struct work_struct *work)
1491 {
1492         struct mlx5e_txqsq_recover *recover =
1493                 container_of(work, struct mlx5e_txqsq_recover,
1494                              recover_work);
1495         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1496                                               recover);
1497         struct mlx5_core_dev *mdev = sq->channel->mdev;
1498         struct net_device *dev = sq->channel->netdev;
1499         u8 state;
1500         int err;
1501
1502         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1503         if (err) {
1504                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1505                            sq->sqn, err);
1506                 return;
1507         }
1508
1509         if (state != MLX5_RQC_STATE_ERR) {
1510                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1511                 return;
1512         }
1513
1514         netif_tx_disable_queue(sq->txq);
1515
1516         if (mlx5e_wait_for_sq_flush(sq))
1517                 return;
1518
1519         /* If the interval between two consecutive recovers per SQ is too
1520          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1521          * If we reached this state, there is probably a bug that needs to be
1522          * fixed. let's keep the queue close and let tx timeout cleanup.
1523          */
1524         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1525             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1526                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1527                            sq->sqn);
1528                 return;
1529         }
1530
1531         /* At this point, no new packets will arrive from the stack as TXQ is
1532          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1533          * pending WQEs.  SQ can safely reset the SQ.
1534          */
1535         if (mlx5e_sq_to_ready(sq, state))
1536                 return;
1537
1538         mlx5e_reset_txqsq_cc_pc(sq);
1539         sq->stats->recover++;
1540         recover->last_recover = jiffies;
1541         mlx5e_activate_txqsq(sq);
1542 }
1543
1544 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1545                             struct mlx5e_params *params,
1546                             struct mlx5e_sq_param *param,
1547                             struct mlx5e_icosq *sq)
1548 {
1549         struct mlx5e_create_sq_param csp = {};
1550         int err;
1551
1552         err = mlx5e_alloc_icosq(c, param, sq);
1553         if (err)
1554                 return err;
1555
1556         csp.cqn             = sq->cq.mcq.cqn;
1557         csp.wq_ctrl         = &sq->wq_ctrl;
1558         csp.min_inline_mode = params->tx_min_inline_mode;
1559         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1560         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1561         if (err)
1562                 goto err_free_icosq;
1563
1564         return 0;
1565
1566 err_free_icosq:
1567         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1568         mlx5e_free_icosq(sq);
1569
1570         return err;
1571 }
1572
1573 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1574 {
1575         struct mlx5e_channel *c = sq->channel;
1576
1577         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1578         napi_synchronize(&c->napi);
1579
1580         mlx5e_destroy_sq(c->mdev, sq->sqn);
1581         mlx5e_free_icosq(sq);
1582 }
1583
1584 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1585                             struct mlx5e_params *params,
1586                             struct mlx5e_sq_param *param,
1587                             struct mlx5e_xdpsq *sq,
1588                             bool is_redirect)
1589 {
1590         struct mlx5e_create_sq_param csp = {};
1591         int err;
1592
1593         err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1594         if (err)
1595                 return err;
1596
1597         csp.tis_lst_sz      = 1;
1598         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1599         csp.cqn             = sq->cq.mcq.cqn;
1600         csp.wq_ctrl         = &sq->wq_ctrl;
1601         csp.min_inline_mode = sq->min_inline_mode;
1602         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1603         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1604         if (err)
1605                 goto err_free_xdpsq;
1606
1607         mlx5e_set_xmit_fp(sq, param->is_mpw);
1608
1609         if (!param->is_mpw) {
1610                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1611                 unsigned int inline_hdr_sz = 0;
1612                 int i;
1613
1614                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1615                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1616                         ds_cnt++;
1617                 }
1618
1619                 /* Pre initialize fixed WQE fields */
1620                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1621                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1622                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1623                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1624                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1625                         struct mlx5_wqe_data_seg *dseg;
1626
1627                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1628                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1629
1630                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1631                         dseg->lkey = sq->mkey_be;
1632
1633                         wi->num_wqebbs = 1;
1634                         wi->num_ds     = 1;
1635                 }
1636         }
1637
1638         return 0;
1639
1640 err_free_xdpsq:
1641         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1642         mlx5e_free_xdpsq(sq);
1643
1644         return err;
1645 }
1646
1647 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq)
1648 {
1649         struct mlx5e_channel *c = sq->channel;
1650
1651         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1652         napi_synchronize(&c->napi);
1653
1654         mlx5e_destroy_sq(c->mdev, sq->sqn);
1655         mlx5e_free_xdpsq_descs(sq, rq);
1656         mlx5e_free_xdpsq(sq);
1657 }
1658
1659 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1660                                  struct mlx5e_cq_param *param,
1661                                  struct mlx5e_cq *cq)
1662 {
1663         struct mlx5_core_cq *mcq = &cq->mcq;
1664         int eqn_not_used;
1665         unsigned int irqn;
1666         int err;
1667         u32 i;
1668
1669         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1670         if (err)
1671                 return err;
1672
1673         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1674                                &cq->wq_ctrl);
1675         if (err)
1676                 return err;
1677
1678         mcq->cqe_sz     = 64;
1679         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1680         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1681         *mcq->set_ci_db = 0;
1682         *mcq->arm_db    = 0;
1683         mcq->vector     = param->eq_ix;
1684         mcq->comp       = mlx5e_completion_event;
1685         mcq->event      = mlx5e_cq_error_event;
1686         mcq->irqn       = irqn;
1687
1688         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1689                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1690
1691                 cqe->op_own = 0xf1;
1692         }
1693
1694         cq->mdev = mdev;
1695
1696         return 0;
1697 }
1698
1699 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1700                           struct mlx5e_cq_param *param,
1701                           struct mlx5e_cq *cq)
1702 {
1703         struct mlx5_core_dev *mdev = c->priv->mdev;
1704         int err;
1705
1706         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1707         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1708         param->eq_ix   = c->ix;
1709
1710         err = mlx5e_alloc_cq_common(mdev, param, cq);
1711
1712         cq->napi    = &c->napi;
1713         cq->channel = c;
1714
1715         return err;
1716 }
1717
1718 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1719 {
1720         mlx5_wq_destroy(&cq->wq_ctrl);
1721 }
1722
1723 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1724 {
1725         struct mlx5_core_dev *mdev = cq->mdev;
1726         struct mlx5_core_cq *mcq = &cq->mcq;
1727
1728         void *in;
1729         void *cqc;
1730         int inlen;
1731         unsigned int irqn_not_used;
1732         int eqn;
1733         int err;
1734
1735         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1736         if (err)
1737                 return err;
1738
1739         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1740                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1741         in = kvzalloc(inlen, GFP_KERNEL);
1742         if (!in)
1743                 return -ENOMEM;
1744
1745         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1746
1747         memcpy(cqc, param->cqc, sizeof(param->cqc));
1748
1749         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1750                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1751
1752         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1753         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1754         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1755         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1756                                             MLX5_ADAPTER_PAGE_SHIFT);
1757         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1758
1759         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1760
1761         kvfree(in);
1762
1763         if (err)
1764                 return err;
1765
1766         mlx5e_cq_arm(cq);
1767
1768         return 0;
1769 }
1770
1771 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1772 {
1773         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1774 }
1775
1776 static int mlx5e_open_cq(struct mlx5e_channel *c,
1777                          struct net_dim_cq_moder moder,
1778                          struct mlx5e_cq_param *param,
1779                          struct mlx5e_cq *cq)
1780 {
1781         struct mlx5_core_dev *mdev = c->mdev;
1782         int err;
1783
1784         err = mlx5e_alloc_cq(c, param, cq);
1785         if (err)
1786                 return err;
1787
1788         err = mlx5e_create_cq(cq, param);
1789         if (err)
1790                 goto err_free_cq;
1791
1792         if (MLX5_CAP_GEN(mdev, cq_moderation))
1793                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1794         return 0;
1795
1796 err_free_cq:
1797         mlx5e_free_cq(cq);
1798
1799         return err;
1800 }
1801
1802 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1803 {
1804         mlx5e_destroy_cq(cq);
1805         mlx5e_free_cq(cq);
1806 }
1807
1808 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1809                              struct mlx5e_params *params,
1810                              struct mlx5e_channel_param *cparam)
1811 {
1812         int err;
1813         int tc;
1814
1815         for (tc = 0; tc < c->num_tc; tc++) {
1816                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1817                                     &cparam->tx_cq, &c->sq[tc].cq);
1818                 if (err)
1819                         goto err_close_tx_cqs;
1820         }
1821
1822         return 0;
1823
1824 err_close_tx_cqs:
1825         for (tc--; tc >= 0; tc--)
1826                 mlx5e_close_cq(&c->sq[tc].cq);
1827
1828         return err;
1829 }
1830
1831 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1832 {
1833         int tc;
1834
1835         for (tc = 0; tc < c->num_tc; tc++)
1836                 mlx5e_close_cq(&c->sq[tc].cq);
1837 }
1838
1839 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1840                           struct mlx5e_params *params,
1841                           struct mlx5e_channel_param *cparam)
1842 {
1843         struct mlx5e_priv *priv = c->priv;
1844         int err, tc, max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1845
1846         for (tc = 0; tc < params->num_tc; tc++) {
1847                 int txq_ix = c->ix + tc * max_nch;
1848
1849                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1850                                        params, &cparam->sq, &c->sq[tc], tc);
1851                 if (err)
1852                         goto err_close_sqs;
1853         }
1854
1855         return 0;
1856
1857 err_close_sqs:
1858         for (tc--; tc >= 0; tc--)
1859                 mlx5e_close_txqsq(&c->sq[tc]);
1860
1861         return err;
1862 }
1863
1864 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1865 {
1866         int tc;
1867
1868         for (tc = 0; tc < c->num_tc; tc++)
1869                 mlx5e_close_txqsq(&c->sq[tc]);
1870 }
1871
1872 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1873                                 struct mlx5e_txqsq *sq, u32 rate)
1874 {
1875         struct mlx5e_priv *priv = netdev_priv(dev);
1876         struct mlx5_core_dev *mdev = priv->mdev;
1877         struct mlx5e_modify_sq_param msp = {0};
1878         struct mlx5_rate_limit rl = {0};
1879         u16 rl_index = 0;
1880         int err;
1881
1882         if (rate == sq->rate_limit)
1883                 /* nothing to do */
1884                 return 0;
1885
1886         if (sq->rate_limit) {
1887                 rl.rate = sq->rate_limit;
1888                 /* remove current rl index to free space to next ones */
1889                 mlx5_rl_remove_rate(mdev, &rl);
1890         }
1891
1892         sq->rate_limit = 0;
1893
1894         if (rate) {
1895                 rl.rate = rate;
1896                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1897                 if (err) {
1898                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1899                                    rate, err);
1900                         return err;
1901                 }
1902         }
1903
1904         msp.curr_state = MLX5_SQC_STATE_RDY;
1905         msp.next_state = MLX5_SQC_STATE_RDY;
1906         msp.rl_index   = rl_index;
1907         msp.rl_update  = true;
1908         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1909         if (err) {
1910                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1911                            rate, err);
1912                 /* remove the rate from the table */
1913                 if (rate)
1914                         mlx5_rl_remove_rate(mdev, &rl);
1915                 return err;
1916         }
1917
1918         sq->rate_limit = rate;
1919         return 0;
1920 }
1921
1922 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1923 {
1924         struct mlx5e_priv *priv = netdev_priv(dev);
1925         struct mlx5_core_dev *mdev = priv->mdev;
1926         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1927         int err = 0;
1928
1929         if (!mlx5_rl_is_supported(mdev)) {
1930                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1931                 return -EINVAL;
1932         }
1933
1934         /* rate is given in Mb/sec, HW config is in Kb/sec */
1935         rate = rate << 10;
1936
1937         /* Check whether rate in valid range, 0 is always valid */
1938         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1939                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1940                 return -ERANGE;
1941         }
1942
1943         mutex_lock(&priv->state_lock);
1944         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1945                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1946         if (!err)
1947                 priv->tx_rates[index] = rate;
1948         mutex_unlock(&priv->state_lock);
1949
1950         return err;
1951 }
1952
1953 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1954                               struct mlx5e_params *params,
1955                               struct mlx5e_channel_param *cparam,
1956                               struct mlx5e_channel **cp)
1957 {
1958         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1959         struct net_dim_cq_moder icocq_moder = {0, 0};
1960         struct net_device *netdev = priv->netdev;
1961         struct mlx5e_channel *c;
1962         unsigned int irq;
1963         int err;
1964         int eqn;
1965
1966         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1967         if (err)
1968                 return err;
1969
1970         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1971         if (!c)
1972                 return -ENOMEM;
1973
1974         c->priv     = priv;
1975         c->mdev     = priv->mdev;
1976         c->tstamp   = &priv->tstamp;
1977         c->ix       = ix;
1978         c->cpu      = cpu;
1979         c->pdev     = &priv->mdev->pdev->dev;
1980         c->netdev   = priv->netdev;
1981         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1982         c->num_tc   = params->num_tc;
1983         c->xdp      = !!params->xdp_prog;
1984         c->stats    = &priv->channel_stats[ix].ch;
1985
1986         c->irq_desc = irq_to_desc(irq);
1987
1988         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1989
1990         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1991         if (err)
1992                 goto err_napi_del;
1993
1994         err = mlx5e_open_tx_cqs(c, params, cparam);
1995         if (err)
1996                 goto err_close_icosq_cq;
1997
1998         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1999         if (err)
2000                 goto err_close_tx_cqs;
2001
2002         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
2003         if (err)
2004                 goto err_close_xdp_tx_cqs;
2005
2006         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
2007         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
2008                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
2009         if (err)
2010                 goto err_close_rx_cq;
2011
2012         napi_enable(&c->napi);
2013
2014         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
2015         if (err)
2016                 goto err_disable_napi;
2017
2018         err = mlx5e_open_sqs(c, params, cparam);
2019         if (err)
2020                 goto err_close_icosq;
2021
2022         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
2023         if (err)
2024                 goto err_close_sqs;
2025
2026         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
2027         if (err)
2028                 goto err_close_xdp_sq;
2029
2030         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
2031         if (err)
2032                 goto err_close_rq;
2033
2034         *cp = c;
2035
2036         return 0;
2037
2038 err_close_rq:
2039         mlx5e_close_rq(&c->rq);
2040
2041 err_close_xdp_sq:
2042         if (c->xdp)
2043                 mlx5e_close_xdpsq(&c->rq.xdpsq, &c->rq);
2044
2045 err_close_sqs:
2046         mlx5e_close_sqs(c);
2047
2048 err_close_icosq:
2049         mlx5e_close_icosq(&c->icosq);
2050
2051 err_disable_napi:
2052         napi_disable(&c->napi);
2053         if (c->xdp)
2054                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2055
2056 err_close_rx_cq:
2057         mlx5e_close_cq(&c->rq.cq);
2058
2059 err_close_xdp_tx_cqs:
2060         mlx5e_close_cq(&c->xdpsq.cq);
2061
2062 err_close_tx_cqs:
2063         mlx5e_close_tx_cqs(c);
2064
2065 err_close_icosq_cq:
2066         mlx5e_close_cq(&c->icosq.cq);
2067
2068 err_napi_del:
2069         netif_napi_del(&c->napi);
2070         kvfree(c);
2071
2072         return err;
2073 }
2074
2075 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2076 {
2077         int tc;
2078
2079         for (tc = 0; tc < c->num_tc; tc++)
2080                 mlx5e_activate_txqsq(&c->sq[tc]);
2081         mlx5e_activate_rq(&c->rq);
2082         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
2083 }
2084
2085 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2086 {
2087         int tc;
2088
2089         mlx5e_deactivate_rq(&c->rq);
2090         for (tc = 0; tc < c->num_tc; tc++)
2091                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2092 }
2093
2094 static void mlx5e_close_channel(struct mlx5e_channel *c)
2095 {
2096         mlx5e_close_xdpsq(&c->xdpsq, NULL);
2097         mlx5e_close_rq(&c->rq);
2098         if (c->xdp)
2099                 mlx5e_close_xdpsq(&c->rq.xdpsq, &c->rq);
2100         mlx5e_close_sqs(c);
2101         mlx5e_close_icosq(&c->icosq);
2102         napi_disable(&c->napi);
2103         if (c->xdp)
2104                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2105         mlx5e_close_cq(&c->rq.cq);
2106         mlx5e_close_cq(&c->xdpsq.cq);
2107         mlx5e_close_tx_cqs(c);
2108         mlx5e_close_cq(&c->icosq.cq);
2109         netif_napi_del(&c->napi);
2110
2111         kvfree(c);
2112 }
2113
2114 #define DEFAULT_FRAG_SIZE (2048)
2115
2116 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2117                                       struct mlx5e_params *params,
2118                                       struct mlx5e_rq_frags_info *info)
2119 {
2120         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2121         int frag_size_max = DEFAULT_FRAG_SIZE;
2122         u32 buf_size = 0;
2123         int i;
2124
2125 #ifdef CONFIG_MLX5_EN_IPSEC
2126         if (MLX5_IPSEC_DEV(mdev))
2127                 byte_count += MLX5E_METADATA_ETHER_LEN;
2128 #endif
2129
2130         if (mlx5e_rx_is_linear_skb(mdev, params)) {
2131                 int frag_stride;
2132
2133                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2134                 frag_stride = roundup_pow_of_two(frag_stride);
2135
2136                 info->arr[0].frag_size = byte_count;
2137                 info->arr[0].frag_stride = frag_stride;
2138                 info->num_frags = 1;
2139                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2140                 goto out;
2141         }
2142
2143         if (byte_count > PAGE_SIZE +
2144             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2145                 frag_size_max = PAGE_SIZE;
2146
2147         i = 0;
2148         while (buf_size < byte_count) {
2149                 int frag_size = byte_count - buf_size;
2150
2151                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2152                         frag_size = min(frag_size, frag_size_max);
2153
2154                 info->arr[i].frag_size = frag_size;
2155                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2156
2157                 buf_size += frag_size;
2158                 i++;
2159         }
2160         info->num_frags = i;
2161         /* number of different wqes sharing a page */
2162         info->wqe_bulk = 1 + (info->num_frags % 2);
2163
2164 out:
2165         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2166         info->log_num_frags = order_base_2(info->num_frags);
2167 }
2168
2169 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2170 {
2171         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2172
2173         switch (wq_type) {
2174         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2175                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2176                 break;
2177         default: /* MLX5_WQ_TYPE_CYCLIC */
2178                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2179         }
2180
2181         return order_base_2(sz);
2182 }
2183
2184 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2185                                  struct mlx5e_params *params,
2186                                  struct mlx5e_rq_param *param)
2187 {
2188         struct mlx5_core_dev *mdev = priv->mdev;
2189         void *rqc = param->rqc;
2190         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2191         int ndsegs = 1;
2192
2193         switch (params->rq_wq_type) {
2194         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2195                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2196                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2197                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2198                 MLX5_SET(wq, wq, log_wqe_stride_size,
2199                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2200                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2201                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2202                 break;
2203         default: /* MLX5_WQ_TYPE_CYCLIC */
2204                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2205                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2206                 ndsegs = param->frags_info.num_frags;
2207         }
2208
2209         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2210         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2211         MLX5_SET(wq, wq, log_wq_stride,
2212                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2213         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2214         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2215         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2216         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2217
2218         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2219 }
2220
2221 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2222                                       struct mlx5e_rq_param *param)
2223 {
2224         struct mlx5_core_dev *mdev = priv->mdev;
2225         void *rqc = param->rqc;
2226         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2227
2228         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2229         MLX5_SET(wq, wq, log_wq_stride,
2230                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2231         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2232
2233         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2234 }
2235
2236 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2237                                         struct mlx5e_sq_param *param)
2238 {
2239         void *sqc = param->sqc;
2240         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2241
2242         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2243         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2244
2245         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2246 }
2247
2248 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2249                                  struct mlx5e_params *params,
2250                                  struct mlx5e_sq_param *param)
2251 {
2252         void *sqc = param->sqc;
2253         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2254
2255         mlx5e_build_sq_param_common(priv, param);
2256         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2257         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2258 }
2259
2260 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2261                                         struct mlx5e_cq_param *param)
2262 {
2263         void *cqc = param->cqc;
2264
2265         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2266         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2267                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2268 }
2269
2270 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2271                                     struct mlx5e_params *params,
2272                                     struct mlx5e_cq_param *param)
2273 {
2274         struct mlx5_core_dev *mdev = priv->mdev;
2275         void *cqc = param->cqc;
2276         u8 log_cq_size;
2277
2278         switch (params->rq_wq_type) {
2279         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2280                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2281                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2282                 break;
2283         default: /* MLX5_WQ_TYPE_CYCLIC */
2284                 log_cq_size = params->log_rq_mtu_frames;
2285         }
2286
2287         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2288         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2289                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2290                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2291         }
2292
2293         mlx5e_build_common_cq_param(priv, param);
2294         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2295 }
2296
2297 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2298                                     struct mlx5e_params *params,
2299                                     struct mlx5e_cq_param *param)
2300 {
2301         void *cqc = param->cqc;
2302
2303         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2304
2305         mlx5e_build_common_cq_param(priv, param);
2306         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2307 }
2308
2309 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2310                                      u8 log_wq_size,
2311                                      struct mlx5e_cq_param *param)
2312 {
2313         void *cqc = param->cqc;
2314
2315         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2316
2317         mlx5e_build_common_cq_param(priv, param);
2318
2319         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2320 }
2321
2322 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2323                                     u8 log_wq_size,
2324                                     struct mlx5e_sq_param *param)
2325 {
2326         void *sqc = param->sqc;
2327         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2328
2329         mlx5e_build_sq_param_common(priv, param);
2330
2331         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2332         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2333 }
2334
2335 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2336                                     struct mlx5e_params *params,
2337                                     struct mlx5e_sq_param *param)
2338 {
2339         void *sqc = param->sqc;
2340         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2341
2342         mlx5e_build_sq_param_common(priv, param);
2343         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2344         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2345 }
2346
2347 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2348                                       struct mlx5e_params *params,
2349                                       struct mlx5e_channel_param *cparam)
2350 {
2351         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2352
2353         mlx5e_build_rq_param(priv, params, &cparam->rq);
2354         mlx5e_build_sq_param(priv, params, &cparam->sq);
2355         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2356         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2357         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2358         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2359         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2360 }
2361
2362 int mlx5e_open_channels(struct mlx5e_priv *priv,
2363                         struct mlx5e_channels *chs)
2364 {
2365         struct mlx5e_channel_param *cparam;
2366         int err = -ENOMEM;
2367         int i;
2368
2369         chs->num = chs->params.num_channels;
2370
2371         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2372         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2373         if (!chs->c || !cparam)
2374                 goto err_free;
2375
2376         mlx5e_build_channel_param(priv, &chs->params, cparam);
2377         for (i = 0; i < chs->num; i++) {
2378                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2379                 if (err)
2380                         goto err_close_channels;
2381         }
2382
2383         kvfree(cparam);
2384         return 0;
2385
2386 err_close_channels:
2387         for (i--; i >= 0; i--)
2388                 mlx5e_close_channel(chs->c[i]);
2389
2390 err_free:
2391         kfree(chs->c);
2392         kvfree(cparam);
2393         chs->num = 0;
2394         return err;
2395 }
2396
2397 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2398 {
2399         int i;
2400
2401         for (i = 0; i < chs->num; i++)
2402                 mlx5e_activate_channel(chs->c[i]);
2403 }
2404
2405 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2406 {
2407         int err = 0;
2408         int i;
2409
2410         for (i = 0; i < chs->num; i++)
2411                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2412                                                   err ? 0 : 20000);
2413
2414         return err ? -ETIMEDOUT : 0;
2415 }
2416
2417 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2418 {
2419         int i;
2420
2421         for (i = 0; i < chs->num; i++)
2422                 mlx5e_deactivate_channel(chs->c[i]);
2423 }
2424
2425 void mlx5e_close_channels(struct mlx5e_channels *chs)
2426 {
2427         int i;
2428
2429         for (i = 0; i < chs->num; i++)
2430                 mlx5e_close_channel(chs->c[i]);
2431
2432         kfree(chs->c);
2433         chs->num = 0;
2434 }
2435
2436 static int
2437 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2438 {
2439         struct mlx5_core_dev *mdev = priv->mdev;
2440         void *rqtc;
2441         int inlen;
2442         int err;
2443         u32 *in;
2444         int i;
2445
2446         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2447         in = kvzalloc(inlen, GFP_KERNEL);
2448         if (!in)
2449                 return -ENOMEM;
2450
2451         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2452
2453         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2454         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2455
2456         for (i = 0; i < sz; i++)
2457                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2458
2459         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2460         if (!err)
2461                 rqt->enabled = true;
2462
2463         kvfree(in);
2464         return err;
2465 }
2466
2467 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2468 {
2469         rqt->enabled = false;
2470         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2471 }
2472
2473 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2474 {
2475         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2476         int err;
2477
2478         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2479         if (err)
2480                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2481         return err;
2482 }
2483
2484 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2485 {
2486         struct mlx5e_rqt *rqt;
2487         int err;
2488         int ix;
2489
2490         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2491                 rqt = &priv->direct_tir[ix].rqt;
2492                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2493                 if (err)
2494                         goto err_destroy_rqts;
2495         }
2496
2497         return 0;
2498
2499 err_destroy_rqts:
2500         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2501         for (ix--; ix >= 0; ix--)
2502                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2503
2504         return err;
2505 }
2506
2507 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2508 {
2509         int i;
2510
2511         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++)
2512                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2513 }
2514
2515 static int mlx5e_rx_hash_fn(int hfunc)
2516 {
2517         return (hfunc == ETH_RSS_HASH_TOP) ?
2518                MLX5_RX_HASH_FN_TOEPLITZ :
2519                MLX5_RX_HASH_FN_INVERTED_XOR8;
2520 }
2521
2522 int mlx5e_bits_invert(unsigned long a, int size)
2523 {
2524         int inv = 0;
2525         int i;
2526
2527         for (i = 0; i < size; i++)
2528                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2529
2530         return inv;
2531 }
2532
2533 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2534                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2535 {
2536         int i;
2537
2538         for (i = 0; i < sz; i++) {
2539                 u32 rqn;
2540
2541                 if (rrp.is_rss) {
2542                         int ix = i;
2543
2544                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2545                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2546
2547                         ix = priv->rss_params.indirection_rqt[ix];
2548                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2549                 } else {
2550                         rqn = rrp.rqn;
2551                 }
2552                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2553         }
2554 }
2555
2556 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2557                        struct mlx5e_redirect_rqt_param rrp)
2558 {
2559         struct mlx5_core_dev *mdev = priv->mdev;
2560         void *rqtc;
2561         int inlen;
2562         u32 *in;
2563         int err;
2564
2565         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2566         in = kvzalloc(inlen, GFP_KERNEL);
2567         if (!in)
2568                 return -ENOMEM;
2569
2570         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2571
2572         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2573         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2574         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2575         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2576
2577         kvfree(in);
2578         return err;
2579 }
2580
2581 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2582                                 struct mlx5e_redirect_rqt_param rrp)
2583 {
2584         if (!rrp.is_rss)
2585                 return rrp.rqn;
2586
2587         if (ix >= rrp.rss.channels->num)
2588                 return priv->drop_rq.rqn;
2589
2590         return rrp.rss.channels->c[ix]->rq.rqn;
2591 }
2592
2593 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2594                                 struct mlx5e_redirect_rqt_param rrp)
2595 {
2596         u32 rqtn;
2597         int ix;
2598
2599         if (priv->indir_rqt.enabled) {
2600                 /* RSS RQ table */
2601                 rqtn = priv->indir_rqt.rqtn;
2602                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2603         }
2604
2605         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2606                 struct mlx5e_redirect_rqt_param direct_rrp = {
2607                         .is_rss = false,
2608                         {
2609                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2610                         },
2611                 };
2612
2613                 /* Direct RQ Tables */
2614                 if (!priv->direct_tir[ix].rqt.enabled)
2615                         continue;
2616
2617                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2618                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2619         }
2620 }
2621
2622 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2623                                             struct mlx5e_channels *chs)
2624 {
2625         struct mlx5e_redirect_rqt_param rrp = {
2626                 .is_rss        = true,
2627                 {
2628                         .rss = {
2629                                 .channels  = chs,
2630                                 .hfunc     = priv->rss_params.hfunc,
2631                         }
2632                 },
2633         };
2634
2635         mlx5e_redirect_rqts(priv, rrp);
2636 }
2637
2638 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2639 {
2640         struct mlx5e_redirect_rqt_param drop_rrp = {
2641                 .is_rss = false,
2642                 {
2643                         .rqn = priv->drop_rq.rqn,
2644                 },
2645         };
2646
2647         mlx5e_redirect_rqts(priv, drop_rrp);
2648 }
2649
2650 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2651         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2652                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2653                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2654         },
2655         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2656                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2657                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2658         },
2659         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2660                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2661                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2662         },
2663         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2664                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2665                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2666         },
2667         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2668                                      .l4_prot_type = 0,
2669                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2670         },
2671         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2672                                      .l4_prot_type = 0,
2673                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2674         },
2675         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2676                                       .l4_prot_type = 0,
2677                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2678         },
2679         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2680                                       .l4_prot_type = 0,
2681                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2682         },
2683         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2684                             .l4_prot_type = 0,
2685                             .rx_hash_fields = MLX5_HASH_IP,
2686         },
2687         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2688                             .l4_prot_type = 0,
2689                             .rx_hash_fields = MLX5_HASH_IP,
2690         },
2691 };
2692
2693 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2694 {
2695         return tirc_default_config[tt];
2696 }
2697
2698 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2699 {
2700         if (!params->lro_en)
2701                 return;
2702
2703 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2704
2705         MLX5_SET(tirc, tirc, lro_enable_mask,
2706                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2707                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2708         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2709                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2710         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2711 }
2712
2713 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2714                                     const struct mlx5e_tirc_config *ttconfig,
2715                                     void *tirc, bool inner)
2716 {
2717         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2718                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2719
2720         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2721         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2722                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2723                                              rx_hash_toeplitz_key);
2724                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2725                                                rx_hash_toeplitz_key);
2726
2727                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2728                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2729         }
2730         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2731                  ttconfig->l3_prot_type);
2732         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2733                  ttconfig->l4_prot_type);
2734         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2735                  ttconfig->rx_hash_fields);
2736 }
2737
2738 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2739                                         enum mlx5e_traffic_types tt,
2740                                         u32 rx_hash_fields)
2741 {
2742         *ttconfig                = tirc_default_config[tt];
2743         ttconfig->rx_hash_fields = rx_hash_fields;
2744 }
2745
2746 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2747 {
2748         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2749         struct mlx5e_rss_params *rss = &priv->rss_params;
2750         struct mlx5_core_dev *mdev = priv->mdev;
2751         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2752         struct mlx5e_tirc_config ttconfig;
2753         int tt;
2754
2755         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2756
2757         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2758                 memset(tirc, 0, ctxlen);
2759                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2760                                             rss->rx_hash_fields[tt]);
2761                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2762                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2763         }
2764
2765         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2766                 return;
2767
2768         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2769                 memset(tirc, 0, ctxlen);
2770                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2771                                             rss->rx_hash_fields[tt]);
2772                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2773                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2774                                      inlen);
2775         }
2776 }
2777
2778 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2779 {
2780         struct mlx5_core_dev *mdev = priv->mdev;
2781
2782         void *in;
2783         void *tirc;
2784         int inlen;
2785         int err;
2786         int tt;
2787         int ix;
2788
2789         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2790         in = kvzalloc(inlen, GFP_KERNEL);
2791         if (!in)
2792                 return -ENOMEM;
2793
2794         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2795         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2796
2797         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2798
2799         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2800                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2801                                            inlen);
2802                 if (err)
2803                         goto free_in;
2804         }
2805
2806         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2807                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2808                                            in, inlen);
2809                 if (err)
2810                         goto free_in;
2811         }
2812
2813 free_in:
2814         kvfree(in);
2815
2816         return err;
2817 }
2818
2819 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2820                                             enum mlx5e_traffic_types tt,
2821                                             u32 *tirc)
2822 {
2823         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2824
2825         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2826
2827         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2828         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2829         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2830
2831         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
2832                                        &tirc_default_config[tt], tirc, true);
2833 }
2834
2835 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2836                          struct mlx5e_params *params, u16 mtu)
2837 {
2838         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2839         int err;
2840
2841         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2842         if (err)
2843                 return err;
2844
2845         /* Update vport context MTU */
2846         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2847         return 0;
2848 }
2849
2850 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2851                             struct mlx5e_params *params, u16 *mtu)
2852 {
2853         u16 hw_mtu = 0;
2854         int err;
2855
2856         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2857         if (err || !hw_mtu) /* fallback to port oper mtu */
2858                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2859
2860         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2861 }
2862
2863 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2864 {
2865         struct mlx5e_params *params = &priv->channels.params;
2866         struct net_device *netdev = priv->netdev;
2867         struct mlx5_core_dev *mdev = priv->mdev;
2868         u16 mtu;
2869         int err;
2870
2871         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2872         if (err)
2873                 return err;
2874
2875         mlx5e_query_mtu(mdev, params, &mtu);
2876         if (mtu != params->sw_mtu)
2877                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2878                             __func__, mtu, params->sw_mtu);
2879
2880         params->sw_mtu = mtu;
2881         return 0;
2882 }
2883
2884 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2885 {
2886         struct mlx5e_priv *priv = netdev_priv(netdev);
2887         int nch = priv->channels.params.num_channels;
2888         int ntc = priv->channels.params.num_tc;
2889         int tc;
2890
2891         netdev_reset_tc(netdev);
2892
2893         if (ntc == 1)
2894                 return;
2895
2896         netdev_set_num_tc(netdev, ntc);
2897
2898         /* Map netdev TCs to offset 0
2899          * We have our own UP to TXQ mapping for QoS
2900          */
2901         for (tc = 0; tc < ntc; tc++)
2902                 netdev_set_tc_queue(netdev, tc, nch, 0);
2903 }
2904
2905 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2906 {
2907         int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2908         int i, tc;
2909
2910         for (i = 0; i < max_nch; i++)
2911                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2912                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2913 }
2914
2915 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2916 {
2917         struct mlx5e_channel *c;
2918         struct mlx5e_txqsq *sq;
2919         int i, tc;
2920
2921         for (i = 0; i < priv->channels.num; i++) {
2922                 c = priv->channels.c[i];
2923                 for (tc = 0; tc < c->num_tc; tc++) {
2924                         sq = &c->sq[tc];
2925                         priv->txq2sq[sq->txq_ix] = sq;
2926                 }
2927         }
2928 }
2929
2930 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2931 {
2932         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2933         struct net_device *netdev = priv->netdev;
2934
2935         mlx5e_netdev_set_tcs(netdev);
2936         netif_set_real_num_tx_queues(netdev, num_txqs);
2937         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2938
2939         mlx5e_build_tx2sq_maps(priv);
2940         mlx5e_activate_channels(&priv->channels);
2941         mlx5e_xdp_tx_enable(priv);
2942         netif_tx_start_all_queues(priv->netdev);
2943
2944         if (mlx5e_is_vport_rep(priv))
2945                 mlx5e_add_sqs_fwd_rules(priv);
2946
2947         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2948         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2949 }
2950
2951 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2952 {
2953         mlx5e_redirect_rqts_to_drop(priv);
2954
2955         if (mlx5e_is_vport_rep(priv))
2956                 mlx5e_remove_sqs_fwd_rules(priv);
2957
2958         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2959          * polling for inactive tx queues.
2960          */
2961         netif_tx_stop_all_queues(priv->netdev);
2962         netif_tx_disable(priv->netdev);
2963         mlx5e_xdp_tx_disable(priv);
2964         mlx5e_deactivate_channels(&priv->channels);
2965 }
2966
2967 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2968                                 struct mlx5e_channels *new_chs,
2969                                 mlx5e_fp_hw_modify hw_modify)
2970 {
2971         struct net_device *netdev = priv->netdev;
2972         int new_num_txqs;
2973         int carrier_ok;
2974         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2975
2976         carrier_ok = netif_carrier_ok(netdev);
2977         netif_carrier_off(netdev);
2978
2979         if (new_num_txqs < netdev->real_num_tx_queues)
2980                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2981
2982         mlx5e_deactivate_priv_channels(priv);
2983         mlx5e_close_channels(&priv->channels);
2984
2985         priv->channels = *new_chs;
2986
2987         /* New channels are ready to roll, modify HW settings if needed */
2988         if (hw_modify)
2989                 hw_modify(priv);
2990
2991         mlx5e_refresh_tirs(priv, false);
2992         mlx5e_activate_priv_channels(priv);
2993
2994         /* return carrier back if needed */
2995         if (carrier_ok)
2996                 netif_carrier_on(netdev);
2997 }
2998
2999 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3000 {
3001         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
3002         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3003 }
3004
3005 int mlx5e_open_locked(struct net_device *netdev)
3006 {
3007         struct mlx5e_priv *priv = netdev_priv(netdev);
3008         int err;
3009
3010         set_bit(MLX5E_STATE_OPENED, &priv->state);
3011
3012         err = mlx5e_open_channels(priv, &priv->channels);
3013         if (err)
3014                 goto err_clear_state_opened_flag;
3015
3016         mlx5e_refresh_tirs(priv, false);
3017         mlx5e_activate_priv_channels(priv);
3018         if (priv->profile->update_carrier)
3019                 priv->profile->update_carrier(priv);
3020
3021         mlx5e_queue_update_stats(priv);
3022         return 0;
3023
3024 err_clear_state_opened_flag:
3025         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3026         return err;
3027 }
3028
3029 int mlx5e_open(struct net_device *netdev)
3030 {
3031         struct mlx5e_priv *priv = netdev_priv(netdev);
3032         int err;
3033
3034         mutex_lock(&priv->state_lock);
3035         err = mlx5e_open_locked(netdev);
3036         if (!err)
3037                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3038         mutex_unlock(&priv->state_lock);
3039
3040         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3041                 udp_tunnel_get_rx_info(netdev);
3042
3043         return err;
3044 }
3045
3046 int mlx5e_close_locked(struct net_device *netdev)
3047 {
3048         struct mlx5e_priv *priv = netdev_priv(netdev);
3049
3050         /* May already be CLOSED in case a previous configuration operation
3051          * (e.g RX/TX queue size change) that involves close&open failed.
3052          */
3053         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3054                 return 0;
3055
3056         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3057
3058         netif_carrier_off(priv->netdev);
3059         mlx5e_deactivate_priv_channels(priv);
3060         mlx5e_close_channels(&priv->channels);
3061
3062         return 0;
3063 }
3064
3065 int mlx5e_close(struct net_device *netdev)
3066 {
3067         struct mlx5e_priv *priv = netdev_priv(netdev);
3068         int err;
3069
3070         if (!netif_device_present(netdev))
3071                 return -ENODEV;
3072
3073         mutex_lock(&priv->state_lock);
3074         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3075         err = mlx5e_close_locked(netdev);
3076         mutex_unlock(&priv->state_lock);
3077
3078         return err;
3079 }
3080
3081 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3082                                struct mlx5e_rq *rq,
3083                                struct mlx5e_rq_param *param)
3084 {
3085         void *rqc = param->rqc;
3086         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3087         int err;
3088
3089         param->wq.db_numa_node = param->wq.buf_numa_node;
3090
3091         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3092                                  &rq->wq_ctrl);
3093         if (err)
3094                 return err;
3095
3096         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3097         xdp_rxq_info_unused(&rq->xdp_rxq);
3098
3099         rq->mdev = mdev;
3100
3101         return 0;
3102 }
3103
3104 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3105                                struct mlx5e_cq *cq,
3106                                struct mlx5e_cq_param *param)
3107 {
3108         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3109         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
3110
3111         return mlx5e_alloc_cq_common(mdev, param, cq);
3112 }
3113
3114 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3115                        struct mlx5e_rq *drop_rq)
3116 {
3117         struct mlx5_core_dev *mdev = priv->mdev;
3118         struct mlx5e_cq_param cq_param = {};
3119         struct mlx5e_rq_param rq_param = {};
3120         struct mlx5e_cq *cq = &drop_rq->cq;
3121         int err;
3122
3123         mlx5e_build_drop_rq_param(priv, &rq_param);
3124
3125         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3126         if (err)
3127                 return err;
3128
3129         err = mlx5e_create_cq(cq, &cq_param);
3130         if (err)
3131                 goto err_free_cq;
3132
3133         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3134         if (err)
3135                 goto err_destroy_cq;
3136
3137         err = mlx5e_create_rq(drop_rq, &rq_param);
3138         if (err)
3139                 goto err_free_rq;
3140
3141         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3142         if (err)
3143                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3144
3145         return 0;
3146
3147 err_free_rq:
3148         mlx5e_free_rq(drop_rq);
3149
3150 err_destroy_cq:
3151         mlx5e_destroy_cq(cq);
3152
3153 err_free_cq:
3154         mlx5e_free_cq(cq);
3155
3156         return err;
3157 }
3158
3159 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3160 {
3161         mlx5e_destroy_rq(drop_rq);
3162         mlx5e_free_rq(drop_rq);
3163         mlx5e_destroy_cq(&drop_rq->cq);
3164         mlx5e_free_cq(&drop_rq->cq);
3165 }
3166
3167 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3168                      u32 underlay_qpn, u32 *tisn)
3169 {
3170         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3171         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3172
3173         MLX5_SET(tisc, tisc, prio, tc << 1);
3174         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3175         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3176
3177         if (mlx5_lag_is_lacp_owner(mdev))
3178                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3179
3180         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3181 }
3182
3183 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3184 {
3185         mlx5_core_destroy_tis(mdev, tisn);
3186 }
3187
3188 int mlx5e_create_tises(struct mlx5e_priv *priv)
3189 {
3190         int err;
3191         int tc;
3192
3193         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3194                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3195                 if (err)
3196                         goto err_close_tises;
3197         }
3198
3199         return 0;
3200
3201 err_close_tises:
3202         for (tc--; tc >= 0; tc--)
3203                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3204
3205         return err;
3206 }
3207
3208 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3209 {
3210         int tc;
3211
3212         for (tc = 0; tc < priv->profile->max_tc; tc++)
3213                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3214 }
3215
3216 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3217                                       enum mlx5e_traffic_types tt,
3218                                       u32 *tirc)
3219 {
3220         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3221
3222         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3223
3224         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3225         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3226
3227         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3228                                        &tirc_default_config[tt], tirc, false);
3229 }
3230
3231 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3232 {
3233         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3234
3235         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3236
3237         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3238         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3239         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3240 }
3241
3242 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3243 {
3244         struct mlx5e_tir *tir;
3245         void *tirc;
3246         int inlen;
3247         int i = 0;
3248         int err;
3249         u32 *in;
3250         int tt;
3251
3252         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3253         in = kvzalloc(inlen, GFP_KERNEL);
3254         if (!in)
3255                 return -ENOMEM;
3256
3257         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3258                 memset(in, 0, inlen);
3259                 tir = &priv->indir_tir[tt];
3260                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3261                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3262                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3263                 if (err) {
3264                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3265                         goto err_destroy_inner_tirs;
3266                 }
3267         }
3268
3269         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3270                 goto out;
3271
3272         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3273                 memset(in, 0, inlen);
3274                 tir = &priv->inner_indir_tir[i];
3275                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3276                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3277                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3278                 if (err) {
3279                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3280                         goto err_destroy_inner_tirs;
3281                 }
3282         }
3283
3284 out:
3285         kvfree(in);
3286
3287         return 0;
3288
3289 err_destroy_inner_tirs:
3290         for (i--; i >= 0; i--)
3291                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3292
3293         for (tt--; tt >= 0; tt--)
3294                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3295
3296         kvfree(in);
3297
3298         return err;
3299 }
3300
3301 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3302 {
3303         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3304         struct mlx5e_tir *tir;
3305         void *tirc;
3306         int inlen;
3307         int err;
3308         u32 *in;
3309         int ix;
3310
3311         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3312         in = kvzalloc(inlen, GFP_KERNEL);
3313         if (!in)
3314                 return -ENOMEM;
3315
3316         for (ix = 0; ix < nch; ix++) {
3317                 memset(in, 0, inlen);
3318                 tir = &priv->direct_tir[ix];
3319                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3320                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3321                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3322                 if (err)
3323                         goto err_destroy_ch_tirs;
3324         }
3325
3326         kvfree(in);
3327
3328         return 0;
3329
3330 err_destroy_ch_tirs:
3331         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3332         for (ix--; ix >= 0; ix--)
3333                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3334
3335         kvfree(in);
3336
3337         return err;
3338 }
3339
3340 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3341 {
3342         int i;
3343
3344         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3345                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3346
3347         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3348                 return;
3349
3350         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3351                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3352 }
3353
3354 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3355 {
3356         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3357         int i;
3358
3359         for (i = 0; i < nch; i++)
3360                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3361 }
3362
3363 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3364 {
3365         int err = 0;
3366         int i;
3367
3368         for (i = 0; i < chs->num; i++) {
3369                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3370                 if (err)
3371                         return err;
3372         }
3373
3374         return 0;
3375 }
3376
3377 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3378 {
3379         int err = 0;
3380         int i;
3381
3382         for (i = 0; i < chs->num; i++) {
3383                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3384                 if (err)
3385                         return err;
3386         }
3387
3388         return 0;
3389 }
3390
3391 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3392                                  struct tc_mqprio_qopt *mqprio)
3393 {
3394         struct mlx5e_priv *priv = netdev_priv(netdev);
3395         struct mlx5e_channels new_channels = {};
3396         u8 tc = mqprio->num_tc;
3397         int err = 0;
3398
3399         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3400
3401         if (tc && tc != MLX5E_MAX_NUM_TC)
3402                 return -EINVAL;
3403
3404         mutex_lock(&priv->state_lock);
3405
3406         new_channels.params = priv->channels.params;
3407         new_channels.params.num_tc = tc ? tc : 1;
3408
3409         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3410                 priv->channels.params = new_channels.params;
3411                 goto out;
3412         }
3413
3414         err = mlx5e_open_channels(priv, &new_channels);
3415         if (err)
3416                 goto out;
3417
3418         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3419                                     new_channels.params.num_tc);
3420         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3421 out:
3422         mutex_unlock(&priv->state_lock);
3423         return err;
3424 }
3425
3426 #ifdef CONFIG_MLX5_ESWITCH
3427 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3428                                      struct tc_cls_flower_offload *cls_flower,
3429                                      int flags)
3430 {
3431         switch (cls_flower->command) {
3432         case TC_CLSFLOWER_REPLACE:
3433                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3434                                               flags);
3435         case TC_CLSFLOWER_DESTROY:
3436                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3437                                            flags);
3438         case TC_CLSFLOWER_STATS:
3439                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3440                                           flags);
3441         default:
3442                 return -EOPNOTSUPP;
3443         }
3444 }
3445
3446 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3447                                    void *cb_priv)
3448 {
3449         struct mlx5e_priv *priv = cb_priv;
3450
3451         switch (type) {
3452         case TC_SETUP_CLSFLOWER:
3453                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS |
3454                                                  MLX5E_TC_NIC_OFFLOAD);
3455         default:
3456                 return -EOPNOTSUPP;
3457         }
3458 }
3459
3460 static int mlx5e_setup_tc_block(struct net_device *dev,
3461                                 struct tc_block_offload *f)
3462 {
3463         struct mlx5e_priv *priv = netdev_priv(dev);
3464
3465         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3466                 return -EOPNOTSUPP;
3467
3468         switch (f->command) {
3469         case TC_BLOCK_BIND:
3470                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3471                                              priv, priv, f->extack);
3472         case TC_BLOCK_UNBIND:
3473                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3474                                         priv);
3475                 return 0;
3476         default:
3477                 return -EOPNOTSUPP;
3478         }
3479 }
3480 #endif
3481
3482 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3483                           void *type_data)
3484 {
3485         switch (type) {
3486 #ifdef CONFIG_MLX5_ESWITCH
3487         case TC_SETUP_BLOCK:
3488                 return mlx5e_setup_tc_block(dev, type_data);
3489 #endif
3490         case TC_SETUP_QDISC_MQPRIO:
3491                 return mlx5e_setup_tc_mqprio(dev, type_data);
3492         default:
3493                 return -EOPNOTSUPP;
3494         }
3495 }
3496
3497 void
3498 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3499 {
3500         struct mlx5e_priv *priv = netdev_priv(dev);
3501         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3502         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3503         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3504
3505         if (!mlx5e_monitor_counter_supported(priv)) {
3506                 /* update HW stats in background for next time */
3507                 mlx5e_queue_update_stats(priv);
3508         }
3509
3510         if (mlx5e_is_uplink_rep(priv)) {
3511                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3512                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3513                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3514                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3515         } else {
3516                 mlx5e_grp_sw_update_stats(priv);
3517                 stats->rx_packets = sstats->rx_packets;
3518                 stats->rx_bytes   = sstats->rx_bytes;
3519                 stats->tx_packets = sstats->tx_packets;
3520                 stats->tx_bytes   = sstats->tx_bytes;
3521                 stats->tx_dropped = sstats->tx_queue_dropped;
3522         }
3523
3524         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3525
3526         stats->rx_length_errors =
3527                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3528                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3529                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3530         stats->rx_crc_errors =
3531                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3532         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3533         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3534         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3535                            stats->rx_frame_errors;
3536         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3537
3538         /* vport multicast also counts packets that are dropped due to steering
3539          * or rx out of buffer
3540          */
3541         stats->multicast =
3542                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3543 }
3544
3545 static void mlx5e_set_rx_mode(struct net_device *dev)
3546 {
3547         struct mlx5e_priv *priv = netdev_priv(dev);
3548
3549         queue_work(priv->wq, &priv->set_rx_mode_work);
3550 }
3551
3552 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3553 {
3554         struct mlx5e_priv *priv = netdev_priv(netdev);
3555         struct sockaddr *saddr = addr;
3556
3557         if (!is_valid_ether_addr(saddr->sa_data))
3558                 return -EADDRNOTAVAIL;
3559
3560         netif_addr_lock_bh(netdev);
3561         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3562         netif_addr_unlock_bh(netdev);
3563
3564         queue_work(priv->wq, &priv->set_rx_mode_work);
3565
3566         return 0;
3567 }
3568
3569 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3570         do {                                            \
3571                 if (enable)                             \
3572                         *features |= feature;           \
3573                 else                                    \
3574                         *features &= ~feature;          \
3575         } while (0)
3576
3577 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3578
3579 static int set_feature_lro(struct net_device *netdev, bool enable)
3580 {
3581         struct mlx5e_priv *priv = netdev_priv(netdev);
3582         struct mlx5_core_dev *mdev = priv->mdev;
3583         struct mlx5e_channels new_channels = {};
3584         struct mlx5e_params *old_params;
3585         int err = 0;
3586         bool reset;
3587
3588         mutex_lock(&priv->state_lock);
3589
3590         old_params = &priv->channels.params;
3591         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3592                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3593                 err = -EINVAL;
3594                 goto out;
3595         }
3596
3597         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3598
3599         new_channels.params = *old_params;
3600         new_channels.params.lro_en = enable;
3601
3602         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3603                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3604                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3605                         reset = false;
3606         }
3607
3608         if (!reset) {
3609                 *old_params = new_channels.params;
3610                 err = mlx5e_modify_tirs_lro(priv);
3611                 goto out;
3612         }
3613
3614         err = mlx5e_open_channels(priv, &new_channels);
3615         if (err)
3616                 goto out;
3617
3618         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3619 out:
3620         mutex_unlock(&priv->state_lock);
3621         return err;
3622 }
3623
3624 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3625 {
3626         struct mlx5e_priv *priv = netdev_priv(netdev);
3627
3628         if (enable)
3629                 mlx5e_enable_cvlan_filter(priv);
3630         else
3631                 mlx5e_disable_cvlan_filter(priv);
3632
3633         return 0;
3634 }
3635
3636 #ifdef CONFIG_MLX5_ESWITCH
3637 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3638 {
3639         struct mlx5e_priv *priv = netdev_priv(netdev);
3640
3641         if (!enable && mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD)) {
3642                 netdev_err(netdev,
3643                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3644                 return -EINVAL;
3645         }
3646
3647         return 0;
3648 }
3649 #endif
3650
3651 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3652 {
3653         struct mlx5e_priv *priv = netdev_priv(netdev);
3654         struct mlx5_core_dev *mdev = priv->mdev;
3655
3656         return mlx5_set_port_fcs(mdev, !enable);
3657 }
3658
3659 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3660 {
3661         struct mlx5e_priv *priv = netdev_priv(netdev);
3662         int err;
3663
3664         mutex_lock(&priv->state_lock);
3665
3666         priv->channels.params.scatter_fcs_en = enable;
3667         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3668         if (err)
3669                 priv->channels.params.scatter_fcs_en = !enable;
3670
3671         mutex_unlock(&priv->state_lock);
3672
3673         return err;
3674 }
3675
3676 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3677 {
3678         struct mlx5e_priv *priv = netdev_priv(netdev);
3679         int err = 0;
3680
3681         mutex_lock(&priv->state_lock);
3682
3683         priv->channels.params.vlan_strip_disable = !enable;
3684         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3685                 goto unlock;
3686
3687         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3688         if (err)
3689                 priv->channels.params.vlan_strip_disable = enable;
3690
3691 unlock:
3692         mutex_unlock(&priv->state_lock);
3693
3694         return err;
3695 }
3696
3697 #ifdef CONFIG_MLX5_EN_ARFS
3698 static int set_feature_arfs(struct net_device *netdev, bool enable)
3699 {
3700         struct mlx5e_priv *priv = netdev_priv(netdev);
3701         int err;
3702
3703         if (enable)
3704                 err = mlx5e_arfs_enable(priv);
3705         else
3706                 err = mlx5e_arfs_disable(priv);
3707
3708         return err;
3709 }
3710 #endif
3711
3712 static int mlx5e_handle_feature(struct net_device *netdev,
3713                                 netdev_features_t *features,
3714                                 netdev_features_t wanted_features,
3715                                 netdev_features_t feature,
3716                                 mlx5e_feature_handler feature_handler)
3717 {
3718         netdev_features_t changes = wanted_features ^ netdev->features;
3719         bool enable = !!(wanted_features & feature);
3720         int err;
3721
3722         if (!(changes & feature))
3723                 return 0;
3724
3725         err = feature_handler(netdev, enable);
3726         if (err) {
3727                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3728                            enable ? "Enable" : "Disable", &feature, err);
3729                 return err;
3730         }
3731
3732         MLX5E_SET_FEATURE(features, feature, enable);
3733         return 0;
3734 }
3735
3736 static int mlx5e_set_features(struct net_device *netdev,
3737                               netdev_features_t features)
3738 {
3739         netdev_features_t oper_features = netdev->features;
3740         int err = 0;
3741
3742 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3743         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3744
3745         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3746         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3747                                     set_feature_cvlan_filter);
3748 #ifdef CONFIG_MLX5_ESWITCH
3749         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3750 #endif
3751         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3752         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3753         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3754 #ifdef CONFIG_MLX5_EN_ARFS
3755         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3756 #endif
3757
3758         if (err) {
3759                 netdev->features = oper_features;
3760                 return -EINVAL;
3761         }
3762
3763         return 0;
3764 }
3765
3766 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3767                                             netdev_features_t features)
3768 {
3769         struct mlx5e_priv *priv = netdev_priv(netdev);
3770         struct mlx5e_params *params;
3771
3772         mutex_lock(&priv->state_lock);
3773         params = &priv->channels.params;
3774         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3775                 /* HW strips the outer C-tag header, this is a problem
3776                  * for S-tag traffic.
3777                  */
3778                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3779                 if (!params->vlan_strip_disable)
3780                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3781         }
3782         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3783                 features &= ~NETIF_F_LRO;
3784                 if (params->lro_en)
3785                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3786         }
3787
3788         mutex_unlock(&priv->state_lock);
3789
3790         return features;
3791 }
3792
3793 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3794                      change_hw_mtu_cb set_mtu_cb)
3795 {
3796         struct mlx5e_priv *priv = netdev_priv(netdev);
3797         struct mlx5e_channels new_channels = {};
3798         struct mlx5e_params *params;
3799         int err = 0;
3800         bool reset;
3801
3802         mutex_lock(&priv->state_lock);
3803
3804         params = &priv->channels.params;
3805
3806         reset = !params->lro_en;
3807         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3808
3809         new_channels.params = *params;
3810         new_channels.params.sw_mtu = new_mtu;
3811
3812         if (params->xdp_prog &&
3813             !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3814                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3815                            new_mtu, MLX5E_XDP_MAX_MTU);
3816                 err = -EINVAL;
3817                 goto out;
3818         }
3819
3820         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3821                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, &new_channels.params);
3822                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3823                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3824
3825                 reset = reset && (is_linear || (ppw_old != ppw_new));
3826         }
3827
3828         if (!reset) {
3829                 params->sw_mtu = new_mtu;
3830                 if (set_mtu_cb)
3831                         set_mtu_cb(priv);
3832                 netdev->mtu = params->sw_mtu;
3833                 goto out;
3834         }
3835
3836         err = mlx5e_open_channels(priv, &new_channels);
3837         if (err)
3838                 goto out;
3839
3840         mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
3841         netdev->mtu = new_channels.params.sw_mtu;
3842
3843 out:
3844         mutex_unlock(&priv->state_lock);
3845         return err;
3846 }
3847
3848 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3849 {
3850         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3851 }
3852
3853 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3854 {
3855         struct hwtstamp_config config;
3856         int err;
3857
3858         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3859             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3860                 return -EOPNOTSUPP;
3861
3862         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3863                 return -EFAULT;
3864
3865         /* TX HW timestamp */
3866         switch (config.tx_type) {
3867         case HWTSTAMP_TX_OFF:
3868         case HWTSTAMP_TX_ON:
3869                 break;
3870         default:
3871                 return -ERANGE;
3872         }
3873
3874         mutex_lock(&priv->state_lock);
3875         /* RX HW timestamp */
3876         switch (config.rx_filter) {
3877         case HWTSTAMP_FILTER_NONE:
3878                 /* Reset CQE compression to Admin default */
3879                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3880                 break;
3881         case HWTSTAMP_FILTER_ALL:
3882         case HWTSTAMP_FILTER_SOME:
3883         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3884         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3885         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3886         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3887         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3888         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3889         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3890         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3891         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3892         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3893         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3894         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3895         case HWTSTAMP_FILTER_NTP_ALL:
3896                 /* Disable CQE compression */
3897                 netdev_warn(priv->netdev, "Disabling cqe compression");
3898                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3899                 if (err) {
3900                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3901                         mutex_unlock(&priv->state_lock);
3902                         return err;
3903                 }
3904                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3905                 break;
3906         default:
3907                 mutex_unlock(&priv->state_lock);
3908                 return -ERANGE;
3909         }
3910
3911         memcpy(&priv->tstamp, &config, sizeof(config));
3912         mutex_unlock(&priv->state_lock);
3913
3914         return copy_to_user(ifr->ifr_data, &config,
3915                             sizeof(config)) ? -EFAULT : 0;
3916 }
3917
3918 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3919 {
3920         struct hwtstamp_config *cfg = &priv->tstamp;
3921
3922         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3923                 return -EOPNOTSUPP;
3924
3925         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3926 }
3927
3928 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3929 {
3930         struct mlx5e_priv *priv = netdev_priv(dev);
3931
3932         switch (cmd) {
3933         case SIOCSHWTSTAMP:
3934                 return mlx5e_hwstamp_set(priv, ifr);
3935         case SIOCGHWTSTAMP:
3936                 return mlx5e_hwstamp_get(priv, ifr);
3937         default:
3938                 return -EOPNOTSUPP;
3939         }
3940 }
3941
3942 #ifdef CONFIG_MLX5_ESWITCH
3943 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3944 {
3945         struct mlx5e_priv *priv = netdev_priv(dev);
3946         struct mlx5_core_dev *mdev = priv->mdev;
3947
3948         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3949 }
3950
3951 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3952                              __be16 vlan_proto)
3953 {
3954         struct mlx5e_priv *priv = netdev_priv(dev);
3955         struct mlx5_core_dev *mdev = priv->mdev;
3956
3957         if (vlan_proto != htons(ETH_P_8021Q))
3958                 return -EPROTONOSUPPORT;
3959
3960         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3961                                            vlan, qos);
3962 }
3963
3964 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3965 {
3966         struct mlx5e_priv *priv = netdev_priv(dev);
3967         struct mlx5_core_dev *mdev = priv->mdev;
3968
3969         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3970 }
3971
3972 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3973 {
3974         struct mlx5e_priv *priv = netdev_priv(dev);
3975         struct mlx5_core_dev *mdev = priv->mdev;
3976
3977         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3978 }
3979
3980 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3981                       int max_tx_rate)
3982 {
3983         struct mlx5e_priv *priv = netdev_priv(dev);
3984         struct mlx5_core_dev *mdev = priv->mdev;
3985
3986         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3987                                            max_tx_rate, min_tx_rate);
3988 }
3989
3990 static int mlx5_vport_link2ifla(u8 esw_link)
3991 {
3992         switch (esw_link) {
3993         case MLX5_VPORT_ADMIN_STATE_DOWN:
3994                 return IFLA_VF_LINK_STATE_DISABLE;
3995         case MLX5_VPORT_ADMIN_STATE_UP:
3996                 return IFLA_VF_LINK_STATE_ENABLE;
3997         }
3998         return IFLA_VF_LINK_STATE_AUTO;
3999 }
4000
4001 static int mlx5_ifla_link2vport(u8 ifla_link)
4002 {
4003         switch (ifla_link) {
4004         case IFLA_VF_LINK_STATE_DISABLE:
4005                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4006         case IFLA_VF_LINK_STATE_ENABLE:
4007                 return MLX5_VPORT_ADMIN_STATE_UP;
4008         }
4009         return MLX5_VPORT_ADMIN_STATE_AUTO;
4010 }
4011
4012 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4013                                    int link_state)
4014 {
4015         struct mlx5e_priv *priv = netdev_priv(dev);
4016         struct mlx5_core_dev *mdev = priv->mdev;
4017
4018         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4019                                             mlx5_ifla_link2vport(link_state));
4020 }
4021
4022 int mlx5e_get_vf_config(struct net_device *dev,
4023                         int vf, struct ifla_vf_info *ivi)
4024 {
4025         struct mlx5e_priv *priv = netdev_priv(dev);
4026         struct mlx5_core_dev *mdev = priv->mdev;
4027         int err;
4028
4029         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4030         if (err)
4031                 return err;
4032         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4033         return 0;
4034 }
4035
4036 int mlx5e_get_vf_stats(struct net_device *dev,
4037                        int vf, struct ifla_vf_stats *vf_stats)
4038 {
4039         struct mlx5e_priv *priv = netdev_priv(dev);
4040         struct mlx5_core_dev *mdev = priv->mdev;
4041
4042         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4043                                             vf_stats);
4044 }
4045 #endif
4046
4047 struct mlx5e_vxlan_work {
4048         struct work_struct      work;
4049         struct mlx5e_priv       *priv;
4050         u16                     port;
4051 };
4052
4053 static void mlx5e_vxlan_add_work(struct work_struct *work)
4054 {
4055         struct mlx5e_vxlan_work *vxlan_work =
4056                 container_of(work, struct mlx5e_vxlan_work, work);
4057         struct mlx5e_priv *priv = vxlan_work->priv;
4058         u16 port = vxlan_work->port;
4059
4060         mutex_lock(&priv->state_lock);
4061         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4062         mutex_unlock(&priv->state_lock);
4063
4064         kfree(vxlan_work);
4065 }
4066
4067 static void mlx5e_vxlan_del_work(struct work_struct *work)
4068 {
4069         struct mlx5e_vxlan_work *vxlan_work =
4070                 container_of(work, struct mlx5e_vxlan_work, work);
4071         struct mlx5e_priv *priv         = vxlan_work->priv;
4072         u16 port = vxlan_work->port;
4073
4074         mutex_lock(&priv->state_lock);
4075         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4076         mutex_unlock(&priv->state_lock);
4077         kfree(vxlan_work);
4078 }
4079
4080 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4081 {
4082         struct mlx5e_vxlan_work *vxlan_work;
4083
4084         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4085         if (!vxlan_work)
4086                 return;
4087
4088         if (add)
4089                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4090         else
4091                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4092
4093         vxlan_work->priv = priv;
4094         vxlan_work->port = port;
4095         queue_work(priv->wq, &vxlan_work->work);
4096 }
4097
4098 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4099 {
4100         struct mlx5e_priv *priv = netdev_priv(netdev);
4101
4102         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4103                 return;
4104
4105         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4106                 return;
4107
4108         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4109 }
4110
4111 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4112 {
4113         struct mlx5e_priv *priv = netdev_priv(netdev);
4114
4115         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4116                 return;
4117
4118         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4119                 return;
4120
4121         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4122 }
4123
4124 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4125                                                      struct sk_buff *skb,
4126                                                      netdev_features_t features)
4127 {
4128         unsigned int offset = 0;
4129         struct udphdr *udph;
4130         u8 proto;
4131         u16 port;
4132
4133         switch (vlan_get_protocol(skb)) {
4134         case htons(ETH_P_IP):
4135                 proto = ip_hdr(skb)->protocol;
4136                 break;
4137         case htons(ETH_P_IPV6):
4138                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4139                 break;
4140         default:
4141                 goto out;
4142         }
4143
4144         switch (proto) {
4145         case IPPROTO_GRE:
4146                 return features;
4147         case IPPROTO_UDP:
4148                 udph = udp_hdr(skb);
4149                 port = be16_to_cpu(udph->dest);
4150
4151                 /* Verify if UDP port is being offloaded by HW */
4152                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4153                         return features;
4154         }
4155
4156 out:
4157         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4158         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4159 }
4160
4161 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4162                                        struct net_device *netdev,
4163                                        netdev_features_t features)
4164 {
4165         struct mlx5e_priv *priv = netdev_priv(netdev);
4166
4167         features = vlan_features_check(skb, features);
4168         features = vxlan_features_check(skb, features);
4169
4170 #ifdef CONFIG_MLX5_EN_IPSEC
4171         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4172                 return features;
4173 #endif
4174
4175         /* Validate if the tunneled packet is being offloaded by HW */
4176         if (skb->encapsulation &&
4177             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4178                 return mlx5e_tunnel_features_check(priv, skb, features);
4179
4180         return features;
4181 }
4182
4183 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4184                                         struct mlx5e_txqsq *sq)
4185 {
4186         struct mlx5_eq_comp *eq = sq->cq.mcq.eq;
4187         u32 eqe_count;
4188
4189         netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
4190                    eq->core.eqn, eq->core.cons_index, eq->core.irqn);
4191
4192         eqe_count = mlx5_eq_poll_irq_disabled(eq);
4193         if (!eqe_count)
4194                 return false;
4195
4196         netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->core.eqn);
4197         sq->channel->stats->eq_rearm++;
4198         return true;
4199 }
4200
4201 static void mlx5e_tx_timeout_work(struct work_struct *work)
4202 {
4203         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4204                                                tx_timeout_work);
4205         struct net_device *dev = priv->netdev;
4206         bool reopen_channels = false;
4207         int i, err;
4208
4209         rtnl_lock();
4210         mutex_lock(&priv->state_lock);
4211
4212         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4213                 goto unlock;
4214
4215         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4216                 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
4217                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4218
4219                 if (!netif_xmit_stopped(dev_queue))
4220                         continue;
4221
4222                 netdev_err(dev,
4223                            "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
4224                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4225                            jiffies_to_usecs(jiffies - dev_queue->trans_start));
4226
4227                 /* If we recover a lost interrupt, most likely TX timeout will
4228                  * be resolved, skip reopening channels
4229                  */
4230                 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4231                         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4232                         reopen_channels = true;
4233                 }
4234         }
4235
4236         if (!reopen_channels)
4237                 goto unlock;
4238
4239         mlx5e_close_locked(dev);
4240         err = mlx5e_open_locked(dev);
4241         if (err)
4242                 netdev_err(priv->netdev,
4243                            "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4244                            err);
4245
4246 unlock:
4247         mutex_unlock(&priv->state_lock);
4248         rtnl_unlock();
4249 }
4250
4251 static void mlx5e_tx_timeout(struct net_device *dev)
4252 {
4253         struct mlx5e_priv *priv = netdev_priv(dev);
4254
4255         netdev_err(dev, "TX timeout detected\n");
4256         queue_work(priv->wq, &priv->tx_timeout_work);
4257 }
4258
4259 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4260 {
4261         struct net_device *netdev = priv->netdev;
4262         struct mlx5e_channels new_channels = {};
4263
4264         if (priv->channels.params.lro_en) {
4265                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4266                 return -EINVAL;
4267         }
4268
4269         if (MLX5_IPSEC_DEV(priv->mdev)) {
4270                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4271                 return -EINVAL;
4272         }
4273
4274         new_channels.params = priv->channels.params;
4275         new_channels.params.xdp_prog = prog;
4276
4277         if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4278                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4279                             new_channels.params.sw_mtu, MLX5E_XDP_MAX_MTU);
4280                 return -EINVAL;
4281         }
4282
4283         return 0;
4284 }
4285
4286 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4287 {
4288         struct mlx5e_priv *priv = netdev_priv(netdev);
4289         struct bpf_prog *old_prog;
4290         bool reset, was_opened;
4291         int err = 0;
4292         int i;
4293
4294         mutex_lock(&priv->state_lock);
4295
4296         if (prog) {
4297                 err = mlx5e_xdp_allowed(priv, prog);
4298                 if (err)
4299                         goto unlock;
4300         }
4301
4302         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4303         /* no need for full reset when exchanging programs */
4304         reset = (!priv->channels.params.xdp_prog || !prog);
4305
4306         if (was_opened && reset)
4307                 mlx5e_close_locked(netdev);
4308         if (was_opened && !reset) {
4309                 /* num_channels is invariant here, so we can take the
4310                  * batched reference right upfront.
4311                  */
4312                 prog = bpf_prog_add(prog, priv->channels.num);
4313                 if (IS_ERR(prog)) {
4314                         err = PTR_ERR(prog);
4315                         goto unlock;
4316                 }
4317         }
4318
4319         /* exchange programs, extra prog reference we got from caller
4320          * as long as we don't fail from this point onwards.
4321          */
4322         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4323         if (old_prog)
4324                 bpf_prog_put(old_prog);
4325
4326         if (reset) /* change RQ type according to priv->xdp_prog */
4327                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4328
4329         if (was_opened && reset)
4330                 mlx5e_open_locked(netdev);
4331
4332         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4333                 goto unlock;
4334
4335         /* exchanging programs w/o reset, we update ref counts on behalf
4336          * of the channels RQs here.
4337          */
4338         for (i = 0; i < priv->channels.num; i++) {
4339                 struct mlx5e_channel *c = priv->channels.c[i];
4340
4341                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4342                 napi_synchronize(&c->napi);
4343                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4344
4345                 old_prog = xchg(&c->rq.xdp_prog, prog);
4346
4347                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4348                 /* napi_schedule in case we have missed anything */
4349                 napi_schedule(&c->napi);
4350
4351                 if (old_prog)
4352                         bpf_prog_put(old_prog);
4353         }
4354
4355 unlock:
4356         mutex_unlock(&priv->state_lock);
4357         return err;
4358 }
4359
4360 static u32 mlx5e_xdp_query(struct net_device *dev)
4361 {
4362         struct mlx5e_priv *priv = netdev_priv(dev);
4363         const struct bpf_prog *xdp_prog;
4364         u32 prog_id = 0;
4365
4366         mutex_lock(&priv->state_lock);
4367         xdp_prog = priv->channels.params.xdp_prog;
4368         if (xdp_prog)
4369                 prog_id = xdp_prog->aux->id;
4370         mutex_unlock(&priv->state_lock);
4371
4372         return prog_id;
4373 }
4374
4375 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4376 {
4377         switch (xdp->command) {
4378         case XDP_SETUP_PROG:
4379                 return mlx5e_xdp_set(dev, xdp->prog);
4380         case XDP_QUERY_PROG:
4381                 xdp->prog_id = mlx5e_xdp_query(dev);
4382                 return 0;
4383         default:
4384                 return -EINVAL;
4385         }
4386 }
4387
4388 const struct net_device_ops mlx5e_netdev_ops = {
4389         .ndo_open                = mlx5e_open,
4390         .ndo_stop                = mlx5e_close,
4391         .ndo_start_xmit          = mlx5e_xmit,
4392         .ndo_setup_tc            = mlx5e_setup_tc,
4393         .ndo_select_queue        = mlx5e_select_queue,
4394         .ndo_get_stats64         = mlx5e_get_stats,
4395         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4396         .ndo_set_mac_address     = mlx5e_set_mac,
4397         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4398         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4399         .ndo_set_features        = mlx5e_set_features,
4400         .ndo_fix_features        = mlx5e_fix_features,
4401         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4402         .ndo_do_ioctl            = mlx5e_ioctl,
4403         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4404         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4405         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4406         .ndo_features_check      = mlx5e_features_check,
4407         .ndo_tx_timeout          = mlx5e_tx_timeout,
4408         .ndo_bpf                 = mlx5e_xdp,
4409         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4410 #ifdef CONFIG_MLX5_EN_ARFS
4411         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4412 #endif
4413 #ifdef CONFIG_MLX5_ESWITCH
4414         /* SRIOV E-Switch NDOs */
4415         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4416         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4417         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4418         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4419         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4420         .ndo_get_vf_config       = mlx5e_get_vf_config,
4421         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4422         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4423 #endif
4424 };
4425
4426 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4427 {
4428         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4429                 return -EOPNOTSUPP;
4430         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4431             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4432             !MLX5_CAP_ETH(mdev, csum_cap) ||
4433             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4434             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4435             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4436             MLX5_CAP_FLOWTABLE(mdev,
4437                                flow_table_properties_nic_receive.max_ft_level)
4438                                < 3) {
4439                 mlx5_core_warn(mdev,
4440                                "Not creating net device, some required device capabilities are missing\n");
4441                 return -EOPNOTSUPP;
4442         }
4443         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4444                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4445         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4446                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4447
4448         return 0;
4449 }
4450
4451 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4452                                    int num_channels)
4453 {
4454         int i;
4455
4456         for (i = 0; i < len; i++)
4457                 indirection_rqt[i] = i % num_channels;
4458 }
4459
4460 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4461 {
4462         u32 link_speed = 0;
4463         u32 pci_bw = 0;
4464
4465         mlx5e_port_max_linkspeed(mdev, &link_speed);
4466         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4467         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4468                            link_speed, pci_bw);
4469
4470 #define MLX5E_SLOW_PCI_RATIO (2)
4471
4472         return link_speed && pci_bw &&
4473                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4474 }
4475
4476 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4477 {
4478         struct net_dim_cq_moder moder;
4479
4480         moder.cq_period_mode = cq_period_mode;
4481         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4482         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4483         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4484                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4485
4486         return moder;
4487 }
4488
4489 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4490 {
4491         struct net_dim_cq_moder moder;
4492
4493         moder.cq_period_mode = cq_period_mode;
4494         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4495         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4496         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4497                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4498
4499         return moder;
4500 }
4501
4502 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4503 {
4504         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4505                 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4506                 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4507 }
4508
4509 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4510 {
4511         if (params->tx_dim_enabled) {
4512                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4513
4514                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4515         } else {
4516                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4517         }
4518
4519         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4520                         params->tx_cq_moderation.cq_period_mode ==
4521                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4522 }
4523
4524 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4525 {
4526         if (params->rx_dim_enabled) {
4527                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4528
4529                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4530         } else {
4531                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4532         }
4533
4534         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4535                         params->rx_cq_moderation.cq_period_mode ==
4536                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4537 }
4538
4539 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4540 {
4541         int i;
4542
4543         /* The supported periods are organized in ascending order */
4544         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4545                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4546                         break;
4547
4548         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4549 }
4550
4551 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4552                            struct mlx5e_params *params)
4553 {
4554         /* Prefer Striding RQ, unless any of the following holds:
4555          * - Striding RQ configuration is not possible/supported.
4556          * - Slow PCI heuristic.
4557          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4558          */
4559         if (!slow_pci_heuristic(mdev) &&
4560             mlx5e_striding_rq_possible(mdev, params) &&
4561             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4562              !mlx5e_rx_is_linear_skb(mdev, params)))
4563                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4564         mlx5e_set_rq_type(mdev, params);
4565         mlx5e_init_rq_type_params(mdev, params);
4566 }
4567
4568 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4569                             u16 num_channels)
4570 {
4571         enum mlx5e_traffic_types tt;
4572
4573         rss_params->hfunc = ETH_RSS_HASH_XOR;
4574         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4575                             sizeof(rss_params->toeplitz_hash_key));
4576         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4577                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4578         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4579                 rss_params->rx_hash_fields[tt] =
4580                         tirc_default_config[tt].rx_hash_fields;
4581 }
4582
4583 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4584                             struct mlx5e_rss_params *rss_params,
4585                             struct mlx5e_params *params,
4586                             u16 max_channels, u16 mtu)
4587 {
4588         u8 rx_cq_period_mode;
4589
4590         params->sw_mtu = mtu;
4591         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4592         params->num_channels = max_channels;
4593         params->num_tc       = 1;
4594
4595         /* SQ */
4596         params->log_sq_size = is_kdump_kernel() ?
4597                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4598                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4599
4600         /* XDP SQ */
4601         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4602                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4603
4604         /* set CQE compression */
4605         params->rx_cqe_compress_def = false;
4606         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4607             MLX5_CAP_GEN(mdev, vport_group_manager))
4608                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4609
4610         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4611         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4612
4613         /* RQ */
4614         mlx5e_build_rq_params(mdev, params);
4615
4616         /* HW LRO */
4617
4618         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4619         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4620                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4621                         params->lro_en = !slow_pci_heuristic(mdev);
4622         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4623
4624         /* CQ moderation params */
4625         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4626                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4627                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4628         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4629         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4630         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4631         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4632
4633         /* TX inline */
4634         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4635
4636         /* RSS */
4637         mlx5e_build_rss_params(rss_params, params->num_channels);
4638 }
4639
4640 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4641 {
4642         struct mlx5e_priv *priv = netdev_priv(netdev);
4643
4644         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4645         if (is_zero_ether_addr(netdev->dev_addr) &&
4646             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4647                 eth_hw_addr_random(netdev);
4648                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4649         }
4650 }
4651
4652 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4653 {
4654         struct mlx5e_priv *priv = netdev_priv(netdev);
4655         struct mlx5_core_dev *mdev = priv->mdev;
4656         bool fcs_supported;
4657         bool fcs_enabled;
4658
4659         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4660
4661         netdev->netdev_ops = &mlx5e_netdev_ops;
4662
4663 #ifdef CONFIG_MLX5_CORE_EN_DCB
4664         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4665                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4666 #endif
4667
4668         netdev->watchdog_timeo    = 15 * HZ;
4669
4670         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4671
4672         netdev->vlan_features    |= NETIF_F_SG;
4673         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4674         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4675         netdev->vlan_features    |= NETIF_F_GRO;
4676         netdev->vlan_features    |= NETIF_F_TSO;
4677         netdev->vlan_features    |= NETIF_F_TSO6;
4678         netdev->vlan_features    |= NETIF_F_RXCSUM;
4679         netdev->vlan_features    |= NETIF_F_RXHASH;
4680
4681         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4682         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4683
4684         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4685             mlx5e_check_fragmented_striding_rq_cap(mdev))
4686                 netdev->vlan_features    |= NETIF_F_LRO;
4687
4688         netdev->hw_features       = netdev->vlan_features;
4689         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4690         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4691         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4692         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4693
4694         if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4695                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4696                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4697                 netdev->hw_enc_features |= NETIF_F_TSO;
4698                 netdev->hw_enc_features |= NETIF_F_TSO6;
4699                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4700         }
4701
4702         if (mlx5_vxlan_allowed(mdev->vxlan)) {
4703                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4704                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4705                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4706                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4707                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4708         }
4709
4710         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4711                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4712                                            NETIF_F_GSO_GRE_CSUM;
4713                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4714                                            NETIF_F_GSO_GRE_CSUM;
4715                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4716                                                 NETIF_F_GSO_GRE_CSUM;
4717         }
4718
4719         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4720         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4721         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4722         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4723
4724         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4725
4726         if (fcs_supported)
4727                 netdev->hw_features |= NETIF_F_RXALL;
4728
4729         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4730                 netdev->hw_features |= NETIF_F_RXFCS;
4731
4732         netdev->features          = netdev->hw_features;
4733         if (!priv->channels.params.lro_en)
4734                 netdev->features  &= ~NETIF_F_LRO;
4735
4736         if (fcs_enabled)
4737                 netdev->features  &= ~NETIF_F_RXALL;
4738
4739         if (!priv->channels.params.scatter_fcs_en)
4740                 netdev->features  &= ~NETIF_F_RXFCS;
4741
4742 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4743         if (FT_CAP(flow_modify_en) &&
4744             FT_CAP(modify_root) &&
4745             FT_CAP(identified_miss_table_mode) &&
4746             FT_CAP(flow_table_modify)) {
4747 #ifdef CONFIG_MLX5_ESWITCH
4748                 netdev->hw_features      |= NETIF_F_HW_TC;
4749 #endif
4750 #ifdef CONFIG_MLX5_EN_ARFS
4751                 netdev->hw_features      |= NETIF_F_NTUPLE;
4752 #endif
4753         }
4754
4755         netdev->features         |= NETIF_F_HIGHDMA;
4756         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4757
4758         netdev->priv_flags       |= IFF_UNICAST_FLT;
4759
4760         mlx5e_set_netdev_dev_addr(netdev);
4761         mlx5e_ipsec_build_netdev(priv);
4762         mlx5e_tls_build_netdev(priv);
4763 }
4764
4765 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4766 {
4767         struct mlx5_core_dev *mdev = priv->mdev;
4768         int err;
4769
4770         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4771         if (err) {
4772                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4773                 priv->q_counter = 0;
4774         }
4775
4776         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4777         if (err) {
4778                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4779                 priv->drop_rq_q_counter = 0;
4780         }
4781 }
4782
4783 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4784 {
4785         if (priv->q_counter)
4786                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4787
4788         if (priv->drop_rq_q_counter)
4789                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4790 }
4791
4792 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4793                           struct net_device *netdev,
4794                           const struct mlx5e_profile *profile,
4795                           void *ppriv)
4796 {
4797         struct mlx5e_priv *priv = netdev_priv(netdev);
4798         struct mlx5e_rss_params *rss = &priv->rss_params;
4799         int err;
4800
4801         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4802         if (err)
4803                 return err;
4804
4805         mlx5e_build_nic_params(mdev, rss, &priv->channels.params,
4806                                mlx5e_get_netdev_max_channels(netdev),
4807                                netdev->mtu);
4808
4809         mlx5e_timestamp_init(priv);
4810
4811         err = mlx5e_ipsec_init(priv);
4812         if (err)
4813                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4814         err = mlx5e_tls_init(priv);
4815         if (err)
4816                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4817         mlx5e_build_nic_netdev(netdev);
4818         mlx5e_build_tc2txq_maps(priv);
4819
4820         return 0;
4821 }
4822
4823 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4824 {
4825         mlx5e_tls_cleanup(priv);
4826         mlx5e_ipsec_cleanup(priv);
4827         mlx5e_netdev_cleanup(priv->netdev, priv);
4828 }
4829
4830 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4831 {
4832         struct mlx5_core_dev *mdev = priv->mdev;
4833         int err;
4834
4835         mlx5e_create_q_counters(priv);
4836
4837         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4838         if (err) {
4839                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4840                 goto err_destroy_q_counters;
4841         }
4842
4843         err = mlx5e_create_indirect_rqt(priv);
4844         if (err)
4845                 goto err_close_drop_rq;
4846
4847         err = mlx5e_create_direct_rqts(priv);
4848         if (err)
4849                 goto err_destroy_indirect_rqts;
4850
4851         err = mlx5e_create_indirect_tirs(priv, true);
4852         if (err)
4853                 goto err_destroy_direct_rqts;
4854
4855         err = mlx5e_create_direct_tirs(priv);
4856         if (err)
4857                 goto err_destroy_indirect_tirs;
4858
4859         err = mlx5e_create_flow_steering(priv);
4860         if (err) {
4861                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4862                 goto err_destroy_direct_tirs;
4863         }
4864
4865         err = mlx5e_tc_nic_init(priv);
4866         if (err)
4867                 goto err_destroy_flow_steering;
4868
4869         return 0;
4870
4871 err_destroy_flow_steering:
4872         mlx5e_destroy_flow_steering(priv);
4873 err_destroy_direct_tirs:
4874         mlx5e_destroy_direct_tirs(priv);
4875 err_destroy_indirect_tirs:
4876         mlx5e_destroy_indirect_tirs(priv, true);
4877 err_destroy_direct_rqts:
4878         mlx5e_destroy_direct_rqts(priv);
4879 err_destroy_indirect_rqts:
4880         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4881 err_close_drop_rq:
4882         mlx5e_close_drop_rq(&priv->drop_rq);
4883 err_destroy_q_counters:
4884         mlx5e_destroy_q_counters(priv);
4885         return err;
4886 }
4887
4888 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4889 {
4890         mlx5e_tc_nic_cleanup(priv);
4891         mlx5e_destroy_flow_steering(priv);
4892         mlx5e_destroy_direct_tirs(priv);
4893         mlx5e_destroy_indirect_tirs(priv, true);
4894         mlx5e_destroy_direct_rqts(priv);
4895         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4896         mlx5e_close_drop_rq(&priv->drop_rq);
4897         mlx5e_destroy_q_counters(priv);
4898 }
4899
4900 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4901 {
4902         int err;
4903
4904         err = mlx5e_create_tises(priv);
4905         if (err) {
4906                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4907                 return err;
4908         }
4909
4910 #ifdef CONFIG_MLX5_CORE_EN_DCB
4911         mlx5e_dcbnl_initialize(priv);
4912 #endif
4913         return 0;
4914 }
4915
4916 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4917 {
4918         struct net_device *netdev = priv->netdev;
4919         struct mlx5_core_dev *mdev = priv->mdev;
4920         u16 max_mtu;
4921
4922         mlx5e_init_l2_addr(priv);
4923
4924         /* Marking the link as currently not needed by the Driver */
4925         if (!netif_running(netdev))
4926                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4927
4928         /* MTU range: 68 - hw-specific max */
4929         netdev->min_mtu = ETH_MIN_MTU;
4930         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4931         netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4932         mlx5e_set_dev_port_mtu(priv);
4933
4934         mlx5_lag_add(mdev, netdev);
4935
4936         mlx5e_enable_async_events(priv);
4937         if (mlx5e_monitor_counter_supported(priv))
4938                 mlx5e_monitor_counter_init(priv);
4939
4940         if (netdev->reg_state != NETREG_REGISTERED)
4941                 return;
4942 #ifdef CONFIG_MLX5_CORE_EN_DCB
4943         mlx5e_dcbnl_init_app(priv);
4944 #endif
4945
4946         queue_work(priv->wq, &priv->set_rx_mode_work);
4947
4948         rtnl_lock();
4949         if (netif_running(netdev))
4950                 mlx5e_open(netdev);
4951         netif_device_attach(netdev);
4952         rtnl_unlock();
4953 }
4954
4955 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4956 {
4957         struct mlx5_core_dev *mdev = priv->mdev;
4958
4959 #ifdef CONFIG_MLX5_CORE_EN_DCB
4960         if (priv->netdev->reg_state == NETREG_REGISTERED)
4961                 mlx5e_dcbnl_delete_app(priv);
4962 #endif
4963
4964         rtnl_lock();
4965         if (netif_running(priv->netdev))
4966                 mlx5e_close(priv->netdev);
4967         netif_device_detach(priv->netdev);
4968         rtnl_unlock();
4969
4970         queue_work(priv->wq, &priv->set_rx_mode_work);
4971
4972         if (mlx5e_monitor_counter_supported(priv))
4973                 mlx5e_monitor_counter_cleanup(priv);
4974
4975         mlx5e_disable_async_events(priv);
4976         mlx5_lag_remove(mdev);
4977 }
4978
4979 static const struct mlx5e_profile mlx5e_nic_profile = {
4980         .init              = mlx5e_nic_init,
4981         .cleanup           = mlx5e_nic_cleanup,
4982         .init_rx           = mlx5e_init_nic_rx,
4983         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4984         .init_tx           = mlx5e_init_nic_tx,
4985         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4986         .enable            = mlx5e_nic_enable,
4987         .disable           = mlx5e_nic_disable,
4988         .update_stats      = mlx5e_update_ndo_stats,
4989         .update_carrier    = mlx5e_update_carrier,
4990         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4991         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4992         .max_tc            = MLX5E_MAX_NUM_TC,
4993 };
4994
4995 /* mlx5e generic netdev management API (move to en_common.c) */
4996
4997 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
4998 int mlx5e_netdev_init(struct net_device *netdev,
4999                       struct mlx5e_priv *priv,
5000                       struct mlx5_core_dev *mdev,
5001                       const struct mlx5e_profile *profile,
5002                       void *ppriv)
5003 {
5004         /* priv init */
5005         priv->mdev        = mdev;
5006         priv->netdev      = netdev;
5007         priv->profile     = profile;
5008         priv->ppriv       = ppriv;
5009         priv->msglevel    = MLX5E_MSG_LEVEL;
5010         priv->max_opened_tc = 1;
5011
5012         mutex_init(&priv->state_lock);
5013         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5014         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5015         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5016         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5017
5018         priv->wq = create_singlethread_workqueue("mlx5e");
5019         if (!priv->wq)
5020                 return -ENOMEM;
5021
5022         /* netdev init */
5023         netif_carrier_off(netdev);
5024
5025 #ifdef CONFIG_MLX5_EN_ARFS
5026         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5027 #endif
5028
5029         return 0;
5030 }
5031
5032 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5033 {
5034         destroy_workqueue(priv->wq);
5035 }
5036
5037 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5038                                        const struct mlx5e_profile *profile,
5039                                        int nch,
5040                                        void *ppriv)
5041 {
5042         struct net_device *netdev;
5043         int err;
5044
5045         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5046                                     nch * profile->max_tc,
5047                                     nch);
5048         if (!netdev) {
5049                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5050                 return NULL;
5051         }
5052
5053         err = profile->init(mdev, netdev, profile, ppriv);
5054         if (err) {
5055                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5056                 goto err_free_netdev;
5057         }
5058
5059         return netdev;
5060
5061 err_free_netdev:
5062         free_netdev(netdev);
5063
5064         return NULL;
5065 }
5066
5067 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5068 {
5069         const struct mlx5e_profile *profile;
5070         int max_nch;
5071         int err;
5072
5073         profile = priv->profile;
5074         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5075
5076         /* max number of channels may have changed */
5077         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5078         if (priv->channels.params.num_channels > max_nch) {
5079                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5080                 priv->channels.params.num_channels = max_nch;
5081                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5082                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5083         }
5084
5085         err = profile->init_tx(priv);
5086         if (err)
5087                 goto out;
5088
5089         err = profile->init_rx(priv);
5090         if (err)
5091                 goto err_cleanup_tx;
5092
5093         if (profile->enable)
5094                 profile->enable(priv);
5095
5096         return 0;
5097
5098 err_cleanup_tx:
5099         profile->cleanup_tx(priv);
5100
5101 out:
5102         return err;
5103 }
5104
5105 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5106 {
5107         const struct mlx5e_profile *profile = priv->profile;
5108
5109         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5110
5111         if (profile->disable)
5112                 profile->disable(priv);
5113         flush_workqueue(priv->wq);
5114
5115         profile->cleanup_rx(priv);
5116         profile->cleanup_tx(priv);
5117         cancel_work_sync(&priv->update_stats_work);
5118 }
5119
5120 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5121 {
5122         const struct mlx5e_profile *profile = priv->profile;
5123         struct net_device *netdev = priv->netdev;
5124
5125         if (profile->cleanup)
5126                 profile->cleanup(priv);
5127         free_netdev(netdev);
5128 }
5129
5130 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5131  * hardware contexts and to connect it to the current netdev.
5132  */
5133 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5134 {
5135         struct mlx5e_priv *priv = vpriv;
5136         struct net_device *netdev = priv->netdev;
5137         int err;
5138
5139         if (netif_device_present(netdev))
5140                 return 0;
5141
5142         err = mlx5e_create_mdev_resources(mdev);
5143         if (err)
5144                 return err;
5145
5146         err = mlx5e_attach_netdev(priv);
5147         if (err) {
5148                 mlx5e_destroy_mdev_resources(mdev);
5149                 return err;
5150         }
5151
5152         return 0;
5153 }
5154
5155 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5156 {
5157         struct mlx5e_priv *priv = vpriv;
5158         struct net_device *netdev = priv->netdev;
5159
5160         if (!netif_device_present(netdev))
5161                 return;
5162
5163         mlx5e_detach_netdev(priv);
5164         mlx5e_destroy_mdev_resources(mdev);
5165 }
5166
5167 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5168 {
5169         struct net_device *netdev;
5170         void *priv;
5171         int err;
5172         int nch;
5173
5174         err = mlx5e_check_required_hca_cap(mdev);
5175         if (err)
5176                 return NULL;
5177
5178 #ifdef CONFIG_MLX5_ESWITCH
5179         if (MLX5_ESWITCH_MANAGER(mdev) &&
5180             mlx5_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5181                 mlx5e_rep_register_vport_reps(mdev);
5182                 return mdev;
5183         }
5184 #endif
5185
5186         nch = mlx5e_get_max_num_channels(mdev);
5187         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5188         if (!netdev) {
5189                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5190                 return NULL;
5191         }
5192
5193         priv = netdev_priv(netdev);
5194
5195         err = mlx5e_attach(mdev, priv);
5196         if (err) {
5197                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5198                 goto err_destroy_netdev;
5199         }
5200
5201         err = register_netdev(netdev);
5202         if (err) {
5203                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5204                 goto err_detach;
5205         }
5206
5207 #ifdef CONFIG_MLX5_CORE_EN_DCB
5208         mlx5e_dcbnl_init_app(priv);
5209 #endif
5210         return priv;
5211
5212 err_detach:
5213         mlx5e_detach(mdev, priv);
5214 err_destroy_netdev:
5215         mlx5e_destroy_netdev(priv);
5216         return NULL;
5217 }
5218
5219 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5220 {
5221         struct mlx5e_priv *priv;
5222
5223 #ifdef CONFIG_MLX5_ESWITCH
5224         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5225                 mlx5e_rep_unregister_vport_reps(mdev);
5226                 return;
5227         }
5228 #endif
5229         priv = vpriv;
5230 #ifdef CONFIG_MLX5_CORE_EN_DCB
5231         mlx5e_dcbnl_delete_app(priv);
5232 #endif
5233         unregister_netdev(priv->netdev);
5234         mlx5e_detach(mdev, vpriv);
5235         mlx5e_destroy_netdev(priv);
5236 }
5237
5238 static struct mlx5_interface mlx5e_interface = {
5239         .add       = mlx5e_add,
5240         .remove    = mlx5e_remove,
5241         .attach    = mlx5e_attach,
5242         .detach    = mlx5e_detach,
5243         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5244 };
5245
5246 void mlx5e_init(void)
5247 {
5248         mlx5e_ipsec_build_inverse_table();
5249         mlx5e_build_ptys2ethtool_map();
5250         mlx5_register_interface(&mlx5e_interface);
5251 }
5252
5253 void mlx5e_cleanup(void)
5254 {
5255         mlx5_unregister_interface(&mlx5e_interface);
5256 }