8e380a89ec63abf28998e8d7868f85c8ed52e137
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include "eswitch.h"
39 #include "en.h"
40 #include "en_tc.h"
41 #include "en_rep.h"
42 #include "en_accel/ipsec.h"
43 #include "en_accel/ipsec_rxtx.h"
44 #include "accel/ipsec.h"
45 #include "vxlan.h"
46
47 struct mlx5e_rq_param {
48         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
49         struct mlx5_wq_param    wq;
50 };
51
52 struct mlx5e_sq_param {
53         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
54         struct mlx5_wq_param       wq;
55 };
56
57 struct mlx5e_cq_param {
58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
59         struct mlx5_wq_param       wq;
60         u16                        eq_ix;
61         u8                         cq_period_mode;
62 };
63
64 struct mlx5e_channel_param {
65         struct mlx5e_rq_param      rq;
66         struct mlx5e_sq_param      sq;
67         struct mlx5e_sq_param      xdp_sq;
68         struct mlx5e_sq_param      icosq;
69         struct mlx5e_cq_param      rx_cq;
70         struct mlx5e_cq_param      tx_cq;
71         struct mlx5e_cq_param      icosq_cq;
72 };
73
74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75 {
76         return MLX5_CAP_GEN(mdev, striding_rq) &&
77                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78                 MLX5_CAP_ETH(mdev, reg_umr_sq);
79 }
80
81 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
82                                struct mlx5e_params *params, u8 rq_type)
83 {
84         params->rq_wq_type = rq_type;
85         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
86         switch (params->rq_wq_type) {
87         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
88                 params->log_rq_size = is_kdump_kernel() ?
89                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
90                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
91                 params->mpwqe_log_stride_sz = MLX5E_MPWQE_STRIDE_SZ(mdev,
92                         MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
93                 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
94                         params->mpwqe_log_stride_sz;
95                 break;
96         default: /* MLX5_WQ_TYPE_LINKED_LIST */
97                 params->log_rq_size = is_kdump_kernel() ?
98                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
99                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
100                 params->rq_headroom = params->xdp_prog ?
101                         XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
102                 params->rq_headroom += NET_IP_ALIGN;
103
104                 /* Extra room needed for build_skb */
105                 params->lro_wqe_sz -= params->rq_headroom +
106                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
107         }
108
109         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
110                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
111                        BIT(params->log_rq_size),
112                        BIT(params->mpwqe_log_stride_sz),
113                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
114 }
115
116 static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev,
117                                 struct mlx5e_params *params)
118 {
119         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
120                     !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
121                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
122                     MLX5_WQ_TYPE_LINKED_LIST;
123         mlx5e_init_rq_type_params(mdev, params, rq_type);
124 }
125
126 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
127 {
128         struct mlx5_core_dev *mdev = priv->mdev;
129         u8 port_state;
130
131         port_state = mlx5_query_vport_state(mdev,
132                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
133                                             0);
134
135         if (port_state == VPORT_STATE_UP) {
136                 netdev_info(priv->netdev, "Link up\n");
137                 netif_carrier_on(priv->netdev);
138         } else {
139                 netdev_info(priv->netdev, "Link down\n");
140                 netif_carrier_off(priv->netdev);
141         }
142 }
143
144 static void mlx5e_update_carrier_work(struct work_struct *work)
145 {
146         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
147                                                update_carrier_work);
148
149         mutex_lock(&priv->state_lock);
150         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
151                 if (priv->profile->update_carrier)
152                         priv->profile->update_carrier(priv);
153         mutex_unlock(&priv->state_lock);
154 }
155
156 static void mlx5e_tx_timeout_work(struct work_struct *work)
157 {
158         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
159                                                tx_timeout_work);
160         int err;
161
162         rtnl_lock();
163         mutex_lock(&priv->state_lock);
164         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
165                 goto unlock;
166         mlx5e_close_locked(priv->netdev);
167         err = mlx5e_open_locked(priv->netdev);
168         if (err)
169                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
170                            err);
171 unlock:
172         mutex_unlock(&priv->state_lock);
173         rtnl_unlock();
174 }
175
176 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
177 {
178         struct mlx5e_sw_stats temp, *s = &temp;
179         struct mlx5e_rq_stats *rq_stats;
180         struct mlx5e_sq_stats *sq_stats;
181         int i, j;
182
183         memset(s, 0, sizeof(*s));
184         for (i = 0; i < priv->channels.num; i++) {
185                 struct mlx5e_channel *c = priv->channels.c[i];
186
187                 rq_stats = &c->rq.stats;
188
189                 s->rx_packets   += rq_stats->packets;
190                 s->rx_bytes     += rq_stats->bytes;
191                 s->rx_lro_packets += rq_stats->lro_packets;
192                 s->rx_lro_bytes += rq_stats->lro_bytes;
193                 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
194                 s->rx_csum_none += rq_stats->csum_none;
195                 s->rx_csum_complete += rq_stats->csum_complete;
196                 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
197                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
198                 s->rx_xdp_drop += rq_stats->xdp_drop;
199                 s->rx_xdp_tx += rq_stats->xdp_tx;
200                 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
201                 s->rx_wqe_err   += rq_stats->wqe_err;
202                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
203                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
204                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
205                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
206                 s->rx_page_reuse  += rq_stats->page_reuse;
207                 s->rx_cache_reuse += rq_stats->cache_reuse;
208                 s->rx_cache_full  += rq_stats->cache_full;
209                 s->rx_cache_empty += rq_stats->cache_empty;
210                 s->rx_cache_busy  += rq_stats->cache_busy;
211                 s->rx_cache_waive += rq_stats->cache_waive;
212
213                 for (j = 0; j < priv->channels.params.num_tc; j++) {
214                         sq_stats = &c->sq[j].stats;
215
216                         s->tx_packets           += sq_stats->packets;
217                         s->tx_bytes             += sq_stats->bytes;
218                         s->tx_tso_packets       += sq_stats->tso_packets;
219                         s->tx_tso_bytes         += sq_stats->tso_bytes;
220                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
221                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
222                         s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
223                         s->tx_queue_stopped     += sq_stats->stopped;
224                         s->tx_queue_wake        += sq_stats->wake;
225                         s->tx_queue_dropped     += sq_stats->dropped;
226                         s->tx_xmit_more         += sq_stats->xmit_more;
227                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
228                         s->tx_csum_none         += sq_stats->csum_none;
229                         s->tx_csum_partial      += sq_stats->csum_partial;
230                 }
231         }
232
233         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
234                                 priv->stats.pport.phy_counters,
235                                 counter_set.phys_layer_cntrs.link_down_events);
236         memcpy(&priv->stats.sw, s, sizeof(*s));
237 }
238
239 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
240 {
241         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
242         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
243         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
244         struct mlx5_core_dev *mdev = priv->mdev;
245
246         MLX5_SET(query_vport_counter_in, in, opcode,
247                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
248         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
249         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
250
251         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
252 }
253
254 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
255 {
256         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
257         struct mlx5_core_dev *mdev = priv->mdev;
258         u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
259         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
260         int prio;
261         void *out;
262
263         MLX5_SET(ppcnt_reg, in, local_port, 1);
264
265         out = pstats->IEEE_802_3_counters;
266         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
267         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
268
269         if (!full)
270                 return;
271
272         out = pstats->RFC_2863_counters;
273         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
274         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
275
276         out = pstats->RFC_2819_counters;
277         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
278         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
279
280         out = pstats->phy_counters;
281         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
282         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
283
284         if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
285                 out = pstats->phy_statistical_counters;
286                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
287                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
288         }
289
290         if (MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) {
291                 out = pstats->eth_ext_counters;
292                 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
293                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
294         }
295
296         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
297         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
298                 out = pstats->per_prio_counters[prio];
299                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
300                 mlx5_core_access_reg(mdev, in, sz, out, sz,
301                                      MLX5_REG_PPCNT, 0, 0);
302         }
303 }
304
305 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
306 {
307         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
308         u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
309         int err;
310
311         if (!priv->q_counter)
312                 return;
313
314         err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
315         if (err)
316                 return;
317
318         qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
319 }
320
321 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
322 {
323         struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
324         struct mlx5_core_dev *mdev = priv->mdev;
325         u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
326         int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
327         void *out;
328
329         if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
330                 return;
331
332         out = pcie_stats->pcie_perf_counters;
333         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
334         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
335 }
336
337 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
338 {
339         if (full) {
340                 mlx5e_update_pcie_counters(priv);
341                 mlx5e_ipsec_update_stats(priv);
342         }
343         mlx5e_update_pport_counters(priv, full);
344         mlx5e_update_vport_counters(priv);
345         mlx5e_update_q_counter(priv);
346         mlx5e_update_sw_counters(priv);
347 }
348
349 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
350 {
351         mlx5e_update_stats(priv, false);
352 }
353
354 void mlx5e_update_stats_work(struct work_struct *work)
355 {
356         struct delayed_work *dwork = to_delayed_work(work);
357         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
358                                                update_stats_work);
359         mutex_lock(&priv->state_lock);
360         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
361                 priv->profile->update_stats(priv);
362                 queue_delayed_work(priv->wq, dwork,
363                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
364         }
365         mutex_unlock(&priv->state_lock);
366 }
367
368 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
369                               enum mlx5_dev_event event, unsigned long param)
370 {
371         struct mlx5e_priv *priv = vpriv;
372
373         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
374                 return;
375
376         switch (event) {
377         case MLX5_DEV_EVENT_PORT_UP:
378         case MLX5_DEV_EVENT_PORT_DOWN:
379                 queue_work(priv->wq, &priv->update_carrier_work);
380                 break;
381         default:
382                 break;
383         }
384 }
385
386 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
387 {
388         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
389 }
390
391 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
392 {
393         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
394         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
395 }
396
397 static inline int mlx5e_get_wqe_mtt_sz(void)
398 {
399         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
400          * To avoid copying garbage after the mtt array, we allocate
401          * a little more.
402          */
403         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
404                      MLX5_UMR_MTT_ALIGNMENT);
405 }
406
407 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
408                                        struct mlx5e_icosq *sq,
409                                        struct mlx5e_umr_wqe *wqe,
410                                        u16 ix)
411 {
412         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
413         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
414         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
415         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
416         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
417         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
418
419         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
420                                       ds_cnt);
421         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
422         cseg->imm       = rq->mkey_be;
423
424         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
425         ucseg->xlt_octowords =
426                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
427         ucseg->bsf_octowords =
428                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
429         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
430
431         dseg->lkey = sq->mkey_be;
432         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
433 }
434
435 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
436                                      struct mlx5e_channel *c)
437 {
438         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
439         int mtt_sz = mlx5e_get_wqe_mtt_sz();
440         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
441         int i;
442
443         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
444                                       GFP_KERNEL, cpu_to_node(c->cpu));
445         if (!rq->mpwqe.info)
446                 goto err_out;
447
448         /* We allocate more than mtt_sz as we will align the pointer */
449         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
450                                         cpu_to_node(c->cpu));
451         if (unlikely(!rq->mpwqe.mtt_no_align))
452                 goto err_free_wqe_info;
453
454         for (i = 0; i < wq_sz; i++) {
455                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
456
457                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
458                                         MLX5_UMR_ALIGN);
459                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
460                                                   PCI_DMA_TODEVICE);
461                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
462                         goto err_unmap_mtts;
463
464                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
465         }
466
467         return 0;
468
469 err_unmap_mtts:
470         while (--i >= 0) {
471                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
472
473                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
474                                  PCI_DMA_TODEVICE);
475         }
476         kfree(rq->mpwqe.mtt_no_align);
477 err_free_wqe_info:
478         kfree(rq->mpwqe.info);
479
480 err_out:
481         return -ENOMEM;
482 }
483
484 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
485 {
486         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
487         int mtt_sz = mlx5e_get_wqe_mtt_sz();
488         int i;
489
490         for (i = 0; i < wq_sz; i++) {
491                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
492
493                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
494                                  PCI_DMA_TODEVICE);
495         }
496         kfree(rq->mpwqe.mtt_no_align);
497         kfree(rq->mpwqe.info);
498 }
499
500 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
501                                  u64 npages, u8 page_shift,
502                                  struct mlx5_core_mkey *umr_mkey)
503 {
504         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
505         void *mkc;
506         u32 *in;
507         int err;
508
509         if (!MLX5E_VALID_NUM_MTTS(npages))
510                 return -EINVAL;
511
512         in = kvzalloc(inlen, GFP_KERNEL);
513         if (!in)
514                 return -ENOMEM;
515
516         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
517
518         MLX5_SET(mkc, mkc, free, 1);
519         MLX5_SET(mkc, mkc, umr_en, 1);
520         MLX5_SET(mkc, mkc, lw, 1);
521         MLX5_SET(mkc, mkc, lr, 1);
522         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
523
524         MLX5_SET(mkc, mkc, qpn, 0xffffff);
525         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
526         MLX5_SET64(mkc, mkc, len, npages << page_shift);
527         MLX5_SET(mkc, mkc, translations_octword_size,
528                  MLX5_MTT_OCTW(npages));
529         MLX5_SET(mkc, mkc, log_page_size, page_shift);
530
531         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
532
533         kvfree(in);
534         return err;
535 }
536
537 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
538 {
539         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
540
541         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
542 }
543
544 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
545                           struct mlx5e_params *params,
546                           struct mlx5e_rq_param *rqp,
547                           struct mlx5e_rq *rq)
548 {
549         struct mlx5_core_dev *mdev = c->mdev;
550         void *rqc = rqp->rqc;
551         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
552         u32 byte_count;
553         int npages;
554         int wq_sz;
555         int err;
556         int i;
557
558         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
559
560         err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
561                                 &rq->wq_ctrl);
562         if (err)
563                 return err;
564
565         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
566
567         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
568
569         rq->wq_type = params->rq_wq_type;
570         rq->pdev    = c->pdev;
571         rq->netdev  = c->netdev;
572         rq->tstamp  = c->tstamp;
573         rq->clock   = &mdev->clock;
574         rq->channel = c;
575         rq->ix      = c->ix;
576         rq->mdev    = mdev;
577
578         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
579         if (IS_ERR(rq->xdp_prog)) {
580                 err = PTR_ERR(rq->xdp_prog);
581                 rq->xdp_prog = NULL;
582                 goto err_rq_wq_destroy;
583         }
584
585         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
586         if (err < 0)
587                 goto err_rq_wq_destroy;
588
589         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
590         rq->buff.headroom = params->rq_headroom;
591
592         switch (rq->wq_type) {
593         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
594
595                 rq->post_wqes = mlx5e_post_rx_mpwqes;
596                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
597
598                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
599 #ifdef CONFIG_MLX5_EN_IPSEC
600                 if (MLX5_IPSEC_DEV(mdev)) {
601                         err = -EINVAL;
602                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
603                         goto err_rq_wq_destroy;
604                 }
605 #endif
606                 if (!rq->handle_rx_cqe) {
607                         err = -EINVAL;
608                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
609                         goto err_rq_wq_destroy;
610                 }
611
612                 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
613                 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
614
615                 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
616
617                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
618                 if (err)
619                         goto err_rq_wq_destroy;
620                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
621
622                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
623                 if (err)
624                         goto err_destroy_umr_mkey;
625                 break;
626         default: /* MLX5_WQ_TYPE_LINKED_LIST */
627                 rq->wqe.frag_info =
628                         kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
629                                      GFP_KERNEL, cpu_to_node(c->cpu));
630                 if (!rq->wqe.frag_info) {
631                         err = -ENOMEM;
632                         goto err_rq_wq_destroy;
633                 }
634                 rq->post_wqes = mlx5e_post_rx_wqes;
635                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
636
637 #ifdef CONFIG_MLX5_EN_IPSEC
638                 if (c->priv->ipsec)
639                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
640                 else
641 #endif
642                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
643                 if (!rq->handle_rx_cqe) {
644                         kfree(rq->wqe.frag_info);
645                         err = -EINVAL;
646                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
647                         goto err_rq_wq_destroy;
648                 }
649
650                 byte_count = params->lro_en  ?
651                                 params->lro_wqe_sz :
652                                 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
653 #ifdef CONFIG_MLX5_EN_IPSEC
654                 if (MLX5_IPSEC_DEV(mdev))
655                         byte_count += MLX5E_METADATA_ETHER_LEN;
656 #endif
657                 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
658
659                 /* calc the required page order */
660                 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
661                 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
662                 rq->buff.page_order = order_base_2(npages);
663
664                 byte_count |= MLX5_HW_START_PADDING;
665                 rq->mkey_be = c->mkey_be;
666         }
667
668         for (i = 0; i < wq_sz; i++) {
669                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
670
671                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
672                         u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
673
674                         wqe->data.addr = cpu_to_be64(dma_offset);
675                 }
676
677                 wqe->data.byte_count = cpu_to_be32(byte_count);
678                 wqe->data.lkey = rq->mkey_be;
679         }
680
681         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
682
683         switch (params->rx_cq_moderation.cq_period_mode) {
684         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
685                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
686                 break;
687         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
688         default:
689                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
690         }
691
692         rq->page_cache.head = 0;
693         rq->page_cache.tail = 0;
694
695         return 0;
696
697 err_destroy_umr_mkey:
698         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
699
700 err_rq_wq_destroy:
701         if (rq->xdp_prog)
702                 bpf_prog_put(rq->xdp_prog);
703         xdp_rxq_info_unreg(&rq->xdp_rxq);
704         mlx5_wq_destroy(&rq->wq_ctrl);
705
706         return err;
707 }
708
709 static void mlx5e_free_rq(struct mlx5e_rq *rq)
710 {
711         int i;
712
713         if (rq->xdp_prog)
714                 bpf_prog_put(rq->xdp_prog);
715
716         xdp_rxq_info_unreg(&rq->xdp_rxq);
717
718         switch (rq->wq_type) {
719         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
720                 mlx5e_rq_free_mpwqe_info(rq);
721                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
722                 break;
723         default: /* MLX5_WQ_TYPE_LINKED_LIST */
724                 kfree(rq->wqe.frag_info);
725         }
726
727         for (i = rq->page_cache.head; i != rq->page_cache.tail;
728              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
729                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
730
731                 mlx5e_page_release(rq, dma_info, false);
732         }
733         mlx5_wq_destroy(&rq->wq_ctrl);
734 }
735
736 static int mlx5e_create_rq(struct mlx5e_rq *rq,
737                            struct mlx5e_rq_param *param)
738 {
739         struct mlx5_core_dev *mdev = rq->mdev;
740
741         void *in;
742         void *rqc;
743         void *wq;
744         int inlen;
745         int err;
746
747         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
748                 sizeof(u64) * rq->wq_ctrl.buf.npages;
749         in = kvzalloc(inlen, GFP_KERNEL);
750         if (!in)
751                 return -ENOMEM;
752
753         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
754         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
755
756         memcpy(rqc, param->rqc, sizeof(param->rqc));
757
758         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
759         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
760         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
761                                                 MLX5_ADAPTER_PAGE_SHIFT);
762         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
763
764         mlx5_fill_page_array(&rq->wq_ctrl.buf,
765                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
766
767         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
768
769         kvfree(in);
770
771         return err;
772 }
773
774 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
775                                  int next_state)
776 {
777         struct mlx5e_channel *c = rq->channel;
778         struct mlx5_core_dev *mdev = c->mdev;
779
780         void *in;
781         void *rqc;
782         int inlen;
783         int err;
784
785         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
786         in = kvzalloc(inlen, GFP_KERNEL);
787         if (!in)
788                 return -ENOMEM;
789
790         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
791
792         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
793         MLX5_SET(rqc, rqc, state, next_state);
794
795         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
796
797         kvfree(in);
798
799         return err;
800 }
801
802 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
803 {
804         struct mlx5e_channel *c = rq->channel;
805         struct mlx5e_priv *priv = c->priv;
806         struct mlx5_core_dev *mdev = priv->mdev;
807
808         void *in;
809         void *rqc;
810         int inlen;
811         int err;
812
813         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
814         in = kvzalloc(inlen, GFP_KERNEL);
815         if (!in)
816                 return -ENOMEM;
817
818         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
819
820         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
821         MLX5_SET64(modify_rq_in, in, modify_bitmask,
822                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
823         MLX5_SET(rqc, rqc, scatter_fcs, enable);
824         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
825
826         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
827
828         kvfree(in);
829
830         return err;
831 }
832
833 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
834 {
835         struct mlx5e_channel *c = rq->channel;
836         struct mlx5_core_dev *mdev = c->mdev;
837         void *in;
838         void *rqc;
839         int inlen;
840         int err;
841
842         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
843         in = kvzalloc(inlen, GFP_KERNEL);
844         if (!in)
845                 return -ENOMEM;
846
847         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
848
849         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
850         MLX5_SET64(modify_rq_in, in, modify_bitmask,
851                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
852         MLX5_SET(rqc, rqc, vsd, vsd);
853         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
854
855         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
856
857         kvfree(in);
858
859         return err;
860 }
861
862 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
863 {
864         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
865 }
866
867 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
868 {
869         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
870         struct mlx5e_channel *c = rq->channel;
871
872         struct mlx5_wq_ll *wq = &rq->wq;
873         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
874
875         while (time_before(jiffies, exp_time)) {
876                 if (wq->cur_sz >= min_wqes)
877                         return 0;
878
879                 msleep(20);
880         }
881
882         netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
883                     rq->rqn, wq->cur_sz, min_wqes);
884         return -ETIMEDOUT;
885 }
886
887 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
888 {
889         struct mlx5_wq_ll *wq = &rq->wq;
890         struct mlx5e_rx_wqe *wqe;
891         __be16 wqe_ix_be;
892         u16 wqe_ix;
893
894         /* UMR WQE (if in progress) is always at wq->head */
895         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
896             rq->mpwqe.umr_in_progress)
897                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
898
899         while (!mlx5_wq_ll_is_empty(wq)) {
900                 wqe_ix_be = *wq->tail_next;
901                 wqe_ix    = be16_to_cpu(wqe_ix_be);
902                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
903                 rq->dealloc_wqe(rq, wqe_ix);
904                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
905                                &wqe->next.next_wqe_index);
906         }
907
908         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
909                 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
910                  * but yet to be re-posted.
911                  */
912                 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
913
914                 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
915                         rq->dealloc_wqe(rq, wqe_ix);
916         }
917 }
918
919 static int mlx5e_open_rq(struct mlx5e_channel *c,
920                          struct mlx5e_params *params,
921                          struct mlx5e_rq_param *param,
922                          struct mlx5e_rq *rq)
923 {
924         int err;
925
926         err = mlx5e_alloc_rq(c, params, param, rq);
927         if (err)
928                 return err;
929
930         err = mlx5e_create_rq(rq, param);
931         if (err)
932                 goto err_free_rq;
933
934         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
935         if (err)
936                 goto err_destroy_rq;
937
938         if (params->rx_dim_enabled)
939                 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
940
941         return 0;
942
943 err_destroy_rq:
944         mlx5e_destroy_rq(rq);
945 err_free_rq:
946         mlx5e_free_rq(rq);
947
948         return err;
949 }
950
951 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
952 {
953         struct mlx5e_icosq *sq = &rq->channel->icosq;
954         u16 pi = sq->pc & sq->wq.sz_m1;
955         struct mlx5e_tx_wqe *nopwqe;
956
957         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
958         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
959         nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
960         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
961 }
962
963 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
964 {
965         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
966         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
967 }
968
969 static void mlx5e_close_rq(struct mlx5e_rq *rq)
970 {
971         cancel_work_sync(&rq->dim.work);
972         mlx5e_destroy_rq(rq);
973         mlx5e_free_rx_descs(rq);
974         mlx5e_free_rq(rq);
975 }
976
977 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
978 {
979         kfree(sq->db.di);
980 }
981
982 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
983 {
984         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
985
986         sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
987                                      GFP_KERNEL, numa);
988         if (!sq->db.di) {
989                 mlx5e_free_xdpsq_db(sq);
990                 return -ENOMEM;
991         }
992
993         return 0;
994 }
995
996 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
997                              struct mlx5e_params *params,
998                              struct mlx5e_sq_param *param,
999                              struct mlx5e_xdpsq *sq)
1000 {
1001         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1002         struct mlx5_core_dev *mdev = c->mdev;
1003         int err;
1004
1005         sq->pdev      = c->pdev;
1006         sq->mkey_be   = c->mkey_be;
1007         sq->channel   = c;
1008         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1009         sq->min_inline_mode = params->tx_min_inline_mode;
1010
1011         param->wq.db_numa_node = cpu_to_node(c->cpu);
1012         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1013         if (err)
1014                 return err;
1015         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1016
1017         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1018         if (err)
1019                 goto err_sq_wq_destroy;
1020
1021         return 0;
1022
1023 err_sq_wq_destroy:
1024         mlx5_wq_destroy(&sq->wq_ctrl);
1025
1026         return err;
1027 }
1028
1029 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1030 {
1031         mlx5e_free_xdpsq_db(sq);
1032         mlx5_wq_destroy(&sq->wq_ctrl);
1033 }
1034
1035 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1036 {
1037         kfree(sq->db.ico_wqe);
1038 }
1039
1040 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1041 {
1042         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1043
1044         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1045                                       GFP_KERNEL, numa);
1046         if (!sq->db.ico_wqe)
1047                 return -ENOMEM;
1048
1049         return 0;
1050 }
1051
1052 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1053                              struct mlx5e_sq_param *param,
1054                              struct mlx5e_icosq *sq)
1055 {
1056         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1057         struct mlx5_core_dev *mdev = c->mdev;
1058         int err;
1059
1060         sq->mkey_be   = c->mkey_be;
1061         sq->channel   = c;
1062         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1063
1064         param->wq.db_numa_node = cpu_to_node(c->cpu);
1065         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1066         if (err)
1067                 return err;
1068         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1069
1070         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1071         if (err)
1072                 goto err_sq_wq_destroy;
1073
1074         sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
1075
1076         return 0;
1077
1078 err_sq_wq_destroy:
1079         mlx5_wq_destroy(&sq->wq_ctrl);
1080
1081         return err;
1082 }
1083
1084 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1085 {
1086         mlx5e_free_icosq_db(sq);
1087         mlx5_wq_destroy(&sq->wq_ctrl);
1088 }
1089
1090 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1091 {
1092         kfree(sq->db.wqe_info);
1093         kfree(sq->db.dma_fifo);
1094 }
1095
1096 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1097 {
1098         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1099         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1100
1101         sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1102                                            GFP_KERNEL, numa);
1103         sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1104                                            GFP_KERNEL, numa);
1105         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1106                 mlx5e_free_txqsq_db(sq);
1107                 return -ENOMEM;
1108         }
1109
1110         sq->dma_fifo_mask = df_sz - 1;
1111
1112         return 0;
1113 }
1114
1115 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1116                              int txq_ix,
1117                              struct mlx5e_params *params,
1118                              struct mlx5e_sq_param *param,
1119                              struct mlx5e_txqsq *sq)
1120 {
1121         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1122         struct mlx5_core_dev *mdev = c->mdev;
1123         int err;
1124
1125         sq->pdev      = c->pdev;
1126         sq->tstamp    = c->tstamp;
1127         sq->clock     = &mdev->clock;
1128         sq->mkey_be   = c->mkey_be;
1129         sq->channel   = c;
1130         sq->txq_ix    = txq_ix;
1131         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1132         sq->max_inline      = params->tx_max_inline;
1133         sq->min_inline_mode = params->tx_min_inline_mode;
1134         if (MLX5_IPSEC_DEV(c->priv->mdev))
1135                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1136
1137         param->wq.db_numa_node = cpu_to_node(c->cpu);
1138         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1139         if (err)
1140                 return err;
1141         sq->wq.db    = &sq->wq.db[MLX5_SND_DBR];
1142
1143         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1144         if (err)
1145                 goto err_sq_wq_destroy;
1146
1147         sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1148
1149         return 0;
1150
1151 err_sq_wq_destroy:
1152         mlx5_wq_destroy(&sq->wq_ctrl);
1153
1154         return err;
1155 }
1156
1157 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1158 {
1159         mlx5e_free_txqsq_db(sq);
1160         mlx5_wq_destroy(&sq->wq_ctrl);
1161 }
1162
1163 struct mlx5e_create_sq_param {
1164         struct mlx5_wq_ctrl        *wq_ctrl;
1165         u32                         cqn;
1166         u32                         tisn;
1167         u8                          tis_lst_sz;
1168         u8                          min_inline_mode;
1169 };
1170
1171 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1172                            struct mlx5e_sq_param *param,
1173                            struct mlx5e_create_sq_param *csp,
1174                            u32 *sqn)
1175 {
1176         void *in;
1177         void *sqc;
1178         void *wq;
1179         int inlen;
1180         int err;
1181
1182         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1183                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1184         in = kvzalloc(inlen, GFP_KERNEL);
1185         if (!in)
1186                 return -ENOMEM;
1187
1188         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1189         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1190
1191         memcpy(sqc, param->sqc, sizeof(param->sqc));
1192         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1193         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1194         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1195
1196         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1197                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1198
1199         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1200
1201         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1202         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1203         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1204                                           MLX5_ADAPTER_PAGE_SHIFT);
1205         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1206
1207         mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1208
1209         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1210
1211         kvfree(in);
1212
1213         return err;
1214 }
1215
1216 struct mlx5e_modify_sq_param {
1217         int curr_state;
1218         int next_state;
1219         bool rl_update;
1220         int rl_index;
1221 };
1222
1223 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1224                            struct mlx5e_modify_sq_param *p)
1225 {
1226         void *in;
1227         void *sqc;
1228         int inlen;
1229         int err;
1230
1231         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1232         in = kvzalloc(inlen, GFP_KERNEL);
1233         if (!in)
1234                 return -ENOMEM;
1235
1236         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1237
1238         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1239         MLX5_SET(sqc, sqc, state, p->next_state);
1240         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1241                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1242                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1243         }
1244
1245         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1246
1247         kvfree(in);
1248
1249         return err;
1250 }
1251
1252 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1253 {
1254         mlx5_core_destroy_sq(mdev, sqn);
1255 }
1256
1257 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1258                                struct mlx5e_sq_param *param,
1259                                struct mlx5e_create_sq_param *csp,
1260                                u32 *sqn)
1261 {
1262         struct mlx5e_modify_sq_param msp = {0};
1263         int err;
1264
1265         err = mlx5e_create_sq(mdev, param, csp, sqn);
1266         if (err)
1267                 return err;
1268
1269         msp.curr_state = MLX5_SQC_STATE_RST;
1270         msp.next_state = MLX5_SQC_STATE_RDY;
1271         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1272         if (err)
1273                 mlx5e_destroy_sq(mdev, *sqn);
1274
1275         return err;
1276 }
1277
1278 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1279                                 struct mlx5e_txqsq *sq, u32 rate);
1280
1281 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1282                             u32 tisn,
1283                             int txq_ix,
1284                             struct mlx5e_params *params,
1285                             struct mlx5e_sq_param *param,
1286                             struct mlx5e_txqsq *sq)
1287 {
1288         struct mlx5e_create_sq_param csp = {};
1289         u32 tx_rate;
1290         int err;
1291
1292         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1293         if (err)
1294                 return err;
1295
1296         csp.tisn            = tisn;
1297         csp.tis_lst_sz      = 1;
1298         csp.cqn             = sq->cq.mcq.cqn;
1299         csp.wq_ctrl         = &sq->wq_ctrl;
1300         csp.min_inline_mode = sq->min_inline_mode;
1301         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1302         if (err)
1303                 goto err_free_txqsq;
1304
1305         tx_rate = c->priv->tx_rates[sq->txq_ix];
1306         if (tx_rate)
1307                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1308
1309         return 0;
1310
1311 err_free_txqsq:
1312         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1313         mlx5e_free_txqsq(sq);
1314
1315         return err;
1316 }
1317
1318 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1319 {
1320         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1321         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1322         netdev_tx_reset_queue(sq->txq);
1323         netif_tx_start_queue(sq->txq);
1324 }
1325
1326 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1327 {
1328         __netif_tx_lock_bh(txq);
1329         netif_tx_stop_queue(txq);
1330         __netif_tx_unlock_bh(txq);
1331 }
1332
1333 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1334 {
1335         struct mlx5e_channel *c = sq->channel;
1336
1337         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1338         /* prevent netif_tx_wake_queue */
1339         napi_synchronize(&c->napi);
1340
1341         netif_tx_disable_queue(sq->txq);
1342
1343         /* last doorbell out, godspeed .. */
1344         if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1345                 struct mlx5e_tx_wqe *nop;
1346
1347                 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1348                 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1349                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1350         }
1351 }
1352
1353 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1354 {
1355         struct mlx5e_channel *c = sq->channel;
1356         struct mlx5_core_dev *mdev = c->mdev;
1357
1358         mlx5e_destroy_sq(mdev, sq->sqn);
1359         if (sq->rate_limit)
1360                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1361         mlx5e_free_txqsq_descs(sq);
1362         mlx5e_free_txqsq(sq);
1363 }
1364
1365 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1366                             struct mlx5e_params *params,
1367                             struct mlx5e_sq_param *param,
1368                             struct mlx5e_icosq *sq)
1369 {
1370         struct mlx5e_create_sq_param csp = {};
1371         int err;
1372
1373         err = mlx5e_alloc_icosq(c, param, sq);
1374         if (err)
1375                 return err;
1376
1377         csp.cqn             = sq->cq.mcq.cqn;
1378         csp.wq_ctrl         = &sq->wq_ctrl;
1379         csp.min_inline_mode = params->tx_min_inline_mode;
1380         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1381         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1382         if (err)
1383                 goto err_free_icosq;
1384
1385         return 0;
1386
1387 err_free_icosq:
1388         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1389         mlx5e_free_icosq(sq);
1390
1391         return err;
1392 }
1393
1394 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1395 {
1396         struct mlx5e_channel *c = sq->channel;
1397
1398         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1399         napi_synchronize(&c->napi);
1400
1401         mlx5e_destroy_sq(c->mdev, sq->sqn);
1402         mlx5e_free_icosq(sq);
1403 }
1404
1405 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1406                             struct mlx5e_params *params,
1407                             struct mlx5e_sq_param *param,
1408                             struct mlx5e_xdpsq *sq)
1409 {
1410         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1411         struct mlx5e_create_sq_param csp = {};
1412         unsigned int inline_hdr_sz = 0;
1413         int err;
1414         int i;
1415
1416         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1417         if (err)
1418                 return err;
1419
1420         csp.tis_lst_sz      = 1;
1421         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1422         csp.cqn             = sq->cq.mcq.cqn;
1423         csp.wq_ctrl         = &sq->wq_ctrl;
1424         csp.min_inline_mode = sq->min_inline_mode;
1425         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1426         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1427         if (err)
1428                 goto err_free_xdpsq;
1429
1430         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1431                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1432                 ds_cnt++;
1433         }
1434
1435         /* Pre initialize fixed WQE fields */
1436         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1437                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1438                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1439                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1440                 struct mlx5_wqe_data_seg *dseg;
1441
1442                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1443                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1444
1445                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1446                 dseg->lkey = sq->mkey_be;
1447         }
1448
1449         return 0;
1450
1451 err_free_xdpsq:
1452         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1453         mlx5e_free_xdpsq(sq);
1454
1455         return err;
1456 }
1457
1458 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1459 {
1460         struct mlx5e_channel *c = sq->channel;
1461
1462         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1463         napi_synchronize(&c->napi);
1464
1465         mlx5e_destroy_sq(c->mdev, sq->sqn);
1466         mlx5e_free_xdpsq_descs(sq);
1467         mlx5e_free_xdpsq(sq);
1468 }
1469
1470 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1471                                  struct mlx5e_cq_param *param,
1472                                  struct mlx5e_cq *cq)
1473 {
1474         struct mlx5_core_cq *mcq = &cq->mcq;
1475         int eqn_not_used;
1476         unsigned int irqn;
1477         int err;
1478         u32 i;
1479
1480         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1481                                &cq->wq_ctrl);
1482         if (err)
1483                 return err;
1484
1485         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1486
1487         mcq->cqe_sz     = 64;
1488         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1489         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1490         *mcq->set_ci_db = 0;
1491         *mcq->arm_db    = 0;
1492         mcq->vector     = param->eq_ix;
1493         mcq->comp       = mlx5e_completion_event;
1494         mcq->event      = mlx5e_cq_error_event;
1495         mcq->irqn       = irqn;
1496
1497         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1498                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1499
1500                 cqe->op_own = 0xf1;
1501         }
1502
1503         cq->mdev = mdev;
1504
1505         return 0;
1506 }
1507
1508 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1509                           struct mlx5e_cq_param *param,
1510                           struct mlx5e_cq *cq)
1511 {
1512         struct mlx5_core_dev *mdev = c->priv->mdev;
1513         int err;
1514
1515         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1516         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1517         param->eq_ix   = c->ix;
1518
1519         err = mlx5e_alloc_cq_common(mdev, param, cq);
1520
1521         cq->napi    = &c->napi;
1522         cq->channel = c;
1523
1524         return err;
1525 }
1526
1527 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1528 {
1529         mlx5_cqwq_destroy(&cq->wq_ctrl);
1530 }
1531
1532 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1533 {
1534         struct mlx5_core_dev *mdev = cq->mdev;
1535         struct mlx5_core_cq *mcq = &cq->mcq;
1536
1537         void *in;
1538         void *cqc;
1539         int inlen;
1540         unsigned int irqn_not_used;
1541         int eqn;
1542         int err;
1543
1544         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1545                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1546         in = kvzalloc(inlen, GFP_KERNEL);
1547         if (!in)
1548                 return -ENOMEM;
1549
1550         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1551
1552         memcpy(cqc, param->cqc, sizeof(param->cqc));
1553
1554         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1555                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1556
1557         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1558
1559         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1560         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1561         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1562         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1563                                             MLX5_ADAPTER_PAGE_SHIFT);
1564         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1565
1566         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1567
1568         kvfree(in);
1569
1570         if (err)
1571                 return err;
1572
1573         mlx5e_cq_arm(cq);
1574
1575         return 0;
1576 }
1577
1578 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1579 {
1580         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1581 }
1582
1583 static int mlx5e_open_cq(struct mlx5e_channel *c,
1584                          struct net_dim_cq_moder moder,
1585                          struct mlx5e_cq_param *param,
1586                          struct mlx5e_cq *cq)
1587 {
1588         struct mlx5_core_dev *mdev = c->mdev;
1589         int err;
1590
1591         err = mlx5e_alloc_cq(c, param, cq);
1592         if (err)
1593                 return err;
1594
1595         err = mlx5e_create_cq(cq, param);
1596         if (err)
1597                 goto err_free_cq;
1598
1599         if (MLX5_CAP_GEN(mdev, cq_moderation))
1600                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1601         return 0;
1602
1603 err_free_cq:
1604         mlx5e_free_cq(cq);
1605
1606         return err;
1607 }
1608
1609 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1610 {
1611         mlx5e_destroy_cq(cq);
1612         mlx5e_free_cq(cq);
1613 }
1614
1615 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1616 {
1617         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1618 }
1619
1620 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1621                              struct mlx5e_params *params,
1622                              struct mlx5e_channel_param *cparam)
1623 {
1624         int err;
1625         int tc;
1626
1627         for (tc = 0; tc < c->num_tc; tc++) {
1628                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1629                                     &cparam->tx_cq, &c->sq[tc].cq);
1630                 if (err)
1631                         goto err_close_tx_cqs;
1632         }
1633
1634         return 0;
1635
1636 err_close_tx_cqs:
1637         for (tc--; tc >= 0; tc--)
1638                 mlx5e_close_cq(&c->sq[tc].cq);
1639
1640         return err;
1641 }
1642
1643 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1644 {
1645         int tc;
1646
1647         for (tc = 0; tc < c->num_tc; tc++)
1648                 mlx5e_close_cq(&c->sq[tc].cq);
1649 }
1650
1651 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1652                           struct mlx5e_params *params,
1653                           struct mlx5e_channel_param *cparam)
1654 {
1655         int err;
1656         int tc;
1657
1658         for (tc = 0; tc < params->num_tc; tc++) {
1659                 int txq_ix = c->ix + tc * params->num_channels;
1660
1661                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1662                                        params, &cparam->sq, &c->sq[tc]);
1663                 if (err)
1664                         goto err_close_sqs;
1665         }
1666
1667         return 0;
1668
1669 err_close_sqs:
1670         for (tc--; tc >= 0; tc--)
1671                 mlx5e_close_txqsq(&c->sq[tc]);
1672
1673         return err;
1674 }
1675
1676 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1677 {
1678         int tc;
1679
1680         for (tc = 0; tc < c->num_tc; tc++)
1681                 mlx5e_close_txqsq(&c->sq[tc]);
1682 }
1683
1684 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1685                                 struct mlx5e_txqsq *sq, u32 rate)
1686 {
1687         struct mlx5e_priv *priv = netdev_priv(dev);
1688         struct mlx5_core_dev *mdev = priv->mdev;
1689         struct mlx5e_modify_sq_param msp = {0};
1690         u16 rl_index = 0;
1691         int err;
1692
1693         if (rate == sq->rate_limit)
1694                 /* nothing to do */
1695                 return 0;
1696
1697         if (sq->rate_limit)
1698                 /* remove current rl index to free space to next ones */
1699                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1700
1701         sq->rate_limit = 0;
1702
1703         if (rate) {
1704                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1705                 if (err) {
1706                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1707                                    rate, err);
1708                         return err;
1709                 }
1710         }
1711
1712         msp.curr_state = MLX5_SQC_STATE_RDY;
1713         msp.next_state = MLX5_SQC_STATE_RDY;
1714         msp.rl_index   = rl_index;
1715         msp.rl_update  = true;
1716         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1717         if (err) {
1718                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1719                            rate, err);
1720                 /* remove the rate from the table */
1721                 if (rate)
1722                         mlx5_rl_remove_rate(mdev, rate);
1723                 return err;
1724         }
1725
1726         sq->rate_limit = rate;
1727         return 0;
1728 }
1729
1730 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1731 {
1732         struct mlx5e_priv *priv = netdev_priv(dev);
1733         struct mlx5_core_dev *mdev = priv->mdev;
1734         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1735         int err = 0;
1736
1737         if (!mlx5_rl_is_supported(mdev)) {
1738                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1739                 return -EINVAL;
1740         }
1741
1742         /* rate is given in Mb/sec, HW config is in Kb/sec */
1743         rate = rate << 10;
1744
1745         /* Check whether rate in valid range, 0 is always valid */
1746         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1747                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1748                 return -ERANGE;
1749         }
1750
1751         mutex_lock(&priv->state_lock);
1752         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1753                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1754         if (!err)
1755                 priv->tx_rates[index] = rate;
1756         mutex_unlock(&priv->state_lock);
1757
1758         return err;
1759 }
1760
1761 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1762                               struct mlx5e_params *params,
1763                               struct mlx5e_channel_param *cparam,
1764                               struct mlx5e_channel **cp)
1765 {
1766         struct net_dim_cq_moder icocq_moder = {0, 0};
1767         struct net_device *netdev = priv->netdev;
1768         int cpu = mlx5e_get_cpu(priv, ix);
1769         struct mlx5e_channel *c;
1770         unsigned int irq;
1771         int err;
1772         int eqn;
1773
1774         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1775         if (!c)
1776                 return -ENOMEM;
1777
1778         c->priv     = priv;
1779         c->mdev     = priv->mdev;
1780         c->tstamp   = &priv->tstamp;
1781         c->ix       = ix;
1782         c->cpu      = cpu;
1783         c->pdev     = &priv->mdev->pdev->dev;
1784         c->netdev   = priv->netdev;
1785         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1786         c->num_tc   = params->num_tc;
1787         c->xdp      = !!params->xdp_prog;
1788
1789         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1790         c->irq_desc = irq_to_desc(irq);
1791
1792         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1793
1794         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1795         if (err)
1796                 goto err_napi_del;
1797
1798         err = mlx5e_open_tx_cqs(c, params, cparam);
1799         if (err)
1800                 goto err_close_icosq_cq;
1801
1802         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1803         if (err)
1804                 goto err_close_tx_cqs;
1805
1806         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1807         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1808                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1809         if (err)
1810                 goto err_close_rx_cq;
1811
1812         napi_enable(&c->napi);
1813
1814         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1815         if (err)
1816                 goto err_disable_napi;
1817
1818         err = mlx5e_open_sqs(c, params, cparam);
1819         if (err)
1820                 goto err_close_icosq;
1821
1822         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1823         if (err)
1824                 goto err_close_sqs;
1825
1826         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1827         if (err)
1828                 goto err_close_xdp_sq;
1829
1830         *cp = c;
1831
1832         return 0;
1833 err_close_xdp_sq:
1834         if (c->xdp)
1835                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1836
1837 err_close_sqs:
1838         mlx5e_close_sqs(c);
1839
1840 err_close_icosq:
1841         mlx5e_close_icosq(&c->icosq);
1842
1843 err_disable_napi:
1844         napi_disable(&c->napi);
1845         if (c->xdp)
1846                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1847
1848 err_close_rx_cq:
1849         mlx5e_close_cq(&c->rq.cq);
1850
1851 err_close_tx_cqs:
1852         mlx5e_close_tx_cqs(c);
1853
1854 err_close_icosq_cq:
1855         mlx5e_close_cq(&c->icosq.cq);
1856
1857 err_napi_del:
1858         netif_napi_del(&c->napi);
1859         kfree(c);
1860
1861         return err;
1862 }
1863
1864 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1865 {
1866         int tc;
1867
1868         for (tc = 0; tc < c->num_tc; tc++)
1869                 mlx5e_activate_txqsq(&c->sq[tc]);
1870         mlx5e_activate_rq(&c->rq);
1871         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1872 }
1873
1874 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1875 {
1876         int tc;
1877
1878         mlx5e_deactivate_rq(&c->rq);
1879         for (tc = 0; tc < c->num_tc; tc++)
1880                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1881 }
1882
1883 static void mlx5e_close_channel(struct mlx5e_channel *c)
1884 {
1885         mlx5e_close_rq(&c->rq);
1886         if (c->xdp)
1887                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1888         mlx5e_close_sqs(c);
1889         mlx5e_close_icosq(&c->icosq);
1890         napi_disable(&c->napi);
1891         if (c->xdp)
1892                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1893         mlx5e_close_cq(&c->rq.cq);
1894         mlx5e_close_tx_cqs(c);
1895         mlx5e_close_cq(&c->icosq.cq);
1896         netif_napi_del(&c->napi);
1897
1898         kfree(c);
1899 }
1900
1901 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1902                                  struct mlx5e_params *params,
1903                                  struct mlx5e_rq_param *param)
1904 {
1905         void *rqc = param->rqc;
1906         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1907
1908         switch (params->rq_wq_type) {
1909         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1910                 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1911                 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
1912                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1913                 break;
1914         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1915                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1916         }
1917
1918         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1919         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1920         MLX5_SET(wq, wq, log_wq_sz,        params->log_rq_size);
1921         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1922         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1923         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
1924         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
1925
1926         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1927         param->wq.linear = 1;
1928 }
1929
1930 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1931 {
1932         void *rqc = param->rqc;
1933         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1934
1935         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1936         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1937 }
1938
1939 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1940                                         struct mlx5e_sq_param *param)
1941 {
1942         void *sqc = param->sqc;
1943         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1944
1945         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1946         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1947
1948         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1949 }
1950
1951 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1952                                  struct mlx5e_params *params,
1953                                  struct mlx5e_sq_param *param)
1954 {
1955         void *sqc = param->sqc;
1956         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1957
1958         mlx5e_build_sq_param_common(priv, param);
1959         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1960         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1961 }
1962
1963 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1964                                         struct mlx5e_cq_param *param)
1965 {
1966         void *cqc = param->cqc;
1967
1968         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1969 }
1970
1971 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1972                                     struct mlx5e_params *params,
1973                                     struct mlx5e_cq_param *param)
1974 {
1975         void *cqc = param->cqc;
1976         u8 log_cq_size;
1977
1978         switch (params->rq_wq_type) {
1979         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1980                 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
1981                 break;
1982         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1983                 log_cq_size = params->log_rq_size;
1984         }
1985
1986         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1987         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1988                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1989                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1990         }
1991
1992         mlx5e_build_common_cq_param(priv, param);
1993         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
1994 }
1995
1996 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1997                                     struct mlx5e_params *params,
1998                                     struct mlx5e_cq_param *param)
1999 {
2000         void *cqc = param->cqc;
2001
2002         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2003
2004         mlx5e_build_common_cq_param(priv, param);
2005         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2006 }
2007
2008 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2009                                      u8 log_wq_size,
2010                                      struct mlx5e_cq_param *param)
2011 {
2012         void *cqc = param->cqc;
2013
2014         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2015
2016         mlx5e_build_common_cq_param(priv, param);
2017
2018         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2019 }
2020
2021 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2022                                     u8 log_wq_size,
2023                                     struct mlx5e_sq_param *param)
2024 {
2025         void *sqc = param->sqc;
2026         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2027
2028         mlx5e_build_sq_param_common(priv, param);
2029
2030         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2031         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2032 }
2033
2034 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2035                                     struct mlx5e_params *params,
2036                                     struct mlx5e_sq_param *param)
2037 {
2038         void *sqc = param->sqc;
2039         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2040
2041         mlx5e_build_sq_param_common(priv, param);
2042         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2043 }
2044
2045 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2046                                       struct mlx5e_params *params,
2047                                       struct mlx5e_channel_param *cparam)
2048 {
2049         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2050
2051         mlx5e_build_rq_param(priv, params, &cparam->rq);
2052         mlx5e_build_sq_param(priv, params, &cparam->sq);
2053         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2054         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2055         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2056         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2057         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2058 }
2059
2060 int mlx5e_open_channels(struct mlx5e_priv *priv,
2061                         struct mlx5e_channels *chs)
2062 {
2063         struct mlx5e_channel_param *cparam;
2064         int err = -ENOMEM;
2065         int i;
2066
2067         chs->num = chs->params.num_channels;
2068
2069         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2070         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2071         if (!chs->c || !cparam)
2072                 goto err_free;
2073
2074         mlx5e_build_channel_param(priv, &chs->params, cparam);
2075         for (i = 0; i < chs->num; i++) {
2076                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2077                 if (err)
2078                         goto err_close_channels;
2079         }
2080
2081         kfree(cparam);
2082         return 0;
2083
2084 err_close_channels:
2085         for (i--; i >= 0; i--)
2086                 mlx5e_close_channel(chs->c[i]);
2087
2088 err_free:
2089         kfree(chs->c);
2090         kfree(cparam);
2091         chs->num = 0;
2092         return err;
2093 }
2094
2095 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2096 {
2097         int i;
2098
2099         for (i = 0; i < chs->num; i++)
2100                 mlx5e_activate_channel(chs->c[i]);
2101 }
2102
2103 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2104 {
2105         int err = 0;
2106         int i;
2107
2108         for (i = 0; i < chs->num; i++) {
2109                 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2110                 if (err)
2111                         break;
2112         }
2113
2114         return err;
2115 }
2116
2117 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2118 {
2119         int i;
2120
2121         for (i = 0; i < chs->num; i++)
2122                 mlx5e_deactivate_channel(chs->c[i]);
2123 }
2124
2125 void mlx5e_close_channels(struct mlx5e_channels *chs)
2126 {
2127         int i;
2128
2129         for (i = 0; i < chs->num; i++)
2130                 mlx5e_close_channel(chs->c[i]);
2131
2132         kfree(chs->c);
2133         chs->num = 0;
2134 }
2135
2136 static int
2137 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2138 {
2139         struct mlx5_core_dev *mdev = priv->mdev;
2140         void *rqtc;
2141         int inlen;
2142         int err;
2143         u32 *in;
2144         int i;
2145
2146         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2147         in = kvzalloc(inlen, GFP_KERNEL);
2148         if (!in)
2149                 return -ENOMEM;
2150
2151         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2152
2153         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2154         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2155
2156         for (i = 0; i < sz; i++)
2157                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2158
2159         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2160         if (!err)
2161                 rqt->enabled = true;
2162
2163         kvfree(in);
2164         return err;
2165 }
2166
2167 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2168 {
2169         rqt->enabled = false;
2170         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2171 }
2172
2173 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2174 {
2175         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2176         int err;
2177
2178         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2179         if (err)
2180                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2181         return err;
2182 }
2183
2184 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2185 {
2186         struct mlx5e_rqt *rqt;
2187         int err;
2188         int ix;
2189
2190         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2191                 rqt = &priv->direct_tir[ix].rqt;
2192                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2193                 if (err)
2194                         goto err_destroy_rqts;
2195         }
2196
2197         return 0;
2198
2199 err_destroy_rqts:
2200         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2201         for (ix--; ix >= 0; ix--)
2202                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2203
2204         return err;
2205 }
2206
2207 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2208 {
2209         int i;
2210
2211         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2212                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2213 }
2214
2215 static int mlx5e_rx_hash_fn(int hfunc)
2216 {
2217         return (hfunc == ETH_RSS_HASH_TOP) ?
2218                MLX5_RX_HASH_FN_TOEPLITZ :
2219                MLX5_RX_HASH_FN_INVERTED_XOR8;
2220 }
2221
2222 int mlx5e_bits_invert(unsigned long a, int size)
2223 {
2224         int inv = 0;
2225         int i;
2226
2227         for (i = 0; i < size; i++)
2228                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2229
2230         return inv;
2231 }
2232
2233 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2234                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2235 {
2236         int i;
2237
2238         for (i = 0; i < sz; i++) {
2239                 u32 rqn;
2240
2241                 if (rrp.is_rss) {
2242                         int ix = i;
2243
2244                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2245                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2246
2247                         ix = priv->channels.params.indirection_rqt[ix];
2248                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2249                 } else {
2250                         rqn = rrp.rqn;
2251                 }
2252                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2253         }
2254 }
2255
2256 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2257                        struct mlx5e_redirect_rqt_param rrp)
2258 {
2259         struct mlx5_core_dev *mdev = priv->mdev;
2260         void *rqtc;
2261         int inlen;
2262         u32 *in;
2263         int err;
2264
2265         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2266         in = kvzalloc(inlen, GFP_KERNEL);
2267         if (!in)
2268                 return -ENOMEM;
2269
2270         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2271
2272         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2273         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2274         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2275         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2276
2277         kvfree(in);
2278         return err;
2279 }
2280
2281 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2282                                 struct mlx5e_redirect_rqt_param rrp)
2283 {
2284         if (!rrp.is_rss)
2285                 return rrp.rqn;
2286
2287         if (ix >= rrp.rss.channels->num)
2288                 return priv->drop_rq.rqn;
2289
2290         return rrp.rss.channels->c[ix]->rq.rqn;
2291 }
2292
2293 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2294                                 struct mlx5e_redirect_rqt_param rrp)
2295 {
2296         u32 rqtn;
2297         int ix;
2298
2299         if (priv->indir_rqt.enabled) {
2300                 /* RSS RQ table */
2301                 rqtn = priv->indir_rqt.rqtn;
2302                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2303         }
2304
2305         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2306                 struct mlx5e_redirect_rqt_param direct_rrp = {
2307                         .is_rss = false,
2308                         {
2309                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2310                         },
2311                 };
2312
2313                 /* Direct RQ Tables */
2314                 if (!priv->direct_tir[ix].rqt.enabled)
2315                         continue;
2316
2317                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2318                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2319         }
2320 }
2321
2322 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2323                                             struct mlx5e_channels *chs)
2324 {
2325         struct mlx5e_redirect_rqt_param rrp = {
2326                 .is_rss        = true,
2327                 {
2328                         .rss = {
2329                                 .channels  = chs,
2330                                 .hfunc     = chs->params.rss_hfunc,
2331                         }
2332                 },
2333         };
2334
2335         mlx5e_redirect_rqts(priv, rrp);
2336 }
2337
2338 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2339 {
2340         struct mlx5e_redirect_rqt_param drop_rrp = {
2341                 .is_rss = false,
2342                 {
2343                         .rqn = priv->drop_rq.rqn,
2344                 },
2345         };
2346
2347         mlx5e_redirect_rqts(priv, drop_rrp);
2348 }
2349
2350 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2351 {
2352         if (!params->lro_en)
2353                 return;
2354
2355 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2356
2357         MLX5_SET(tirc, tirc, lro_enable_mask,
2358                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2359                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2360         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2361                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2362         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2363 }
2364
2365 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2366                                     enum mlx5e_traffic_types tt,
2367                                     void *tirc, bool inner)
2368 {
2369         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2370                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2371
2372 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2373                                  MLX5_HASH_FIELD_SEL_DST_IP)
2374
2375 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2376                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2377                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2378                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2379
2380 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2381                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2382                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2383
2384         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2385         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2386                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2387                                              rx_hash_toeplitz_key);
2388                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2389                                                rx_hash_toeplitz_key);
2390
2391                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2392                 memcpy(rss_key, params->toeplitz_hash_key, len);
2393         }
2394
2395         switch (tt) {
2396         case MLX5E_TT_IPV4_TCP:
2397                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2398                          MLX5_L3_PROT_TYPE_IPV4);
2399                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2400                          MLX5_L4_PROT_TYPE_TCP);
2401                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2402                          MLX5_HASH_IP_L4PORTS);
2403                 break;
2404
2405         case MLX5E_TT_IPV6_TCP:
2406                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2407                          MLX5_L3_PROT_TYPE_IPV6);
2408                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2409                          MLX5_L4_PROT_TYPE_TCP);
2410                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2411                          MLX5_HASH_IP_L4PORTS);
2412                 break;
2413
2414         case MLX5E_TT_IPV4_UDP:
2415                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2416                          MLX5_L3_PROT_TYPE_IPV4);
2417                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2418                          MLX5_L4_PROT_TYPE_UDP);
2419                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2420                          MLX5_HASH_IP_L4PORTS);
2421                 break;
2422
2423         case MLX5E_TT_IPV6_UDP:
2424                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2425                          MLX5_L3_PROT_TYPE_IPV6);
2426                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2427                          MLX5_L4_PROT_TYPE_UDP);
2428                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2429                          MLX5_HASH_IP_L4PORTS);
2430                 break;
2431
2432         case MLX5E_TT_IPV4_IPSEC_AH:
2433                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2434                          MLX5_L3_PROT_TYPE_IPV4);
2435                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2436                          MLX5_HASH_IP_IPSEC_SPI);
2437                 break;
2438
2439         case MLX5E_TT_IPV6_IPSEC_AH:
2440                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2441                          MLX5_L3_PROT_TYPE_IPV6);
2442                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2443                          MLX5_HASH_IP_IPSEC_SPI);
2444                 break;
2445
2446         case MLX5E_TT_IPV4_IPSEC_ESP:
2447                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2448                          MLX5_L3_PROT_TYPE_IPV4);
2449                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2450                          MLX5_HASH_IP_IPSEC_SPI);
2451                 break;
2452
2453         case MLX5E_TT_IPV6_IPSEC_ESP:
2454                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2455                          MLX5_L3_PROT_TYPE_IPV6);
2456                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2457                          MLX5_HASH_IP_IPSEC_SPI);
2458                 break;
2459
2460         case MLX5E_TT_IPV4:
2461                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2462                          MLX5_L3_PROT_TYPE_IPV4);
2463                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2464                          MLX5_HASH_IP);
2465                 break;
2466
2467         case MLX5E_TT_IPV6:
2468                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2469                          MLX5_L3_PROT_TYPE_IPV6);
2470                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2471                          MLX5_HASH_IP);
2472                 break;
2473         default:
2474                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2475         }
2476 }
2477
2478 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2479 {
2480         struct mlx5_core_dev *mdev = priv->mdev;
2481
2482         void *in;
2483         void *tirc;
2484         int inlen;
2485         int err;
2486         int tt;
2487         int ix;
2488
2489         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2490         in = kvzalloc(inlen, GFP_KERNEL);
2491         if (!in)
2492                 return -ENOMEM;
2493
2494         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2495         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2496
2497         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2498
2499         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2500                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2501                                            inlen);
2502                 if (err)
2503                         goto free_in;
2504         }
2505
2506         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2507                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2508                                            in, inlen);
2509                 if (err)
2510                         goto free_in;
2511         }
2512
2513 free_in:
2514         kvfree(in);
2515
2516         return err;
2517 }
2518
2519 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2520                                             enum mlx5e_traffic_types tt,
2521                                             u32 *tirc)
2522 {
2523         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2524
2525         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2526
2527         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2528         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2529         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2530
2531         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2532 }
2533
2534 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2535 {
2536         struct mlx5_core_dev *mdev = priv->mdev;
2537         u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
2538         int err;
2539
2540         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2541         if (err)
2542                 return err;
2543
2544         /* Update vport context MTU */
2545         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2546         return 0;
2547 }
2548
2549 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2550 {
2551         struct mlx5_core_dev *mdev = priv->mdev;
2552         u16 hw_mtu = 0;
2553         int err;
2554
2555         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2556         if (err || !hw_mtu) /* fallback to port oper mtu */
2557                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2558
2559         *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
2560 }
2561
2562 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2563 {
2564         struct net_device *netdev = priv->netdev;
2565         u16 mtu;
2566         int err;
2567
2568         err = mlx5e_set_mtu(priv, netdev->mtu);
2569         if (err)
2570                 return err;
2571
2572         mlx5e_query_mtu(priv, &mtu);
2573         if (mtu != netdev->mtu)
2574                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2575                             __func__, mtu, netdev->mtu);
2576
2577         netdev->mtu = mtu;
2578         return 0;
2579 }
2580
2581 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2582 {
2583         struct mlx5e_priv *priv = netdev_priv(netdev);
2584         int nch = priv->channels.params.num_channels;
2585         int ntc = priv->channels.params.num_tc;
2586         int tc;
2587
2588         netdev_reset_tc(netdev);
2589
2590         if (ntc == 1)
2591                 return;
2592
2593         netdev_set_num_tc(netdev, ntc);
2594
2595         /* Map netdev TCs to offset 0
2596          * We have our own UP to TXQ mapping for QoS
2597          */
2598         for (tc = 0; tc < ntc; tc++)
2599                 netdev_set_tc_queue(netdev, tc, nch, 0);
2600 }
2601
2602 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2603 {
2604         struct mlx5e_channel *c;
2605         struct mlx5e_txqsq *sq;
2606         int i, tc;
2607
2608         for (i = 0; i < priv->channels.num; i++)
2609                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2610                         priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2611
2612         for (i = 0; i < priv->channels.num; i++) {
2613                 c = priv->channels.c[i];
2614                 for (tc = 0; tc < c->num_tc; tc++) {
2615                         sq = &c->sq[tc];
2616                         priv->txq2sq[sq->txq_ix] = sq;
2617                 }
2618         }
2619 }
2620
2621 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2622 {
2623         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2624         struct net_device *netdev = priv->netdev;
2625
2626         mlx5e_netdev_set_tcs(netdev);
2627         netif_set_real_num_tx_queues(netdev, num_txqs);
2628         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2629
2630         mlx5e_build_channels_tx_maps(priv);
2631         mlx5e_activate_channels(&priv->channels);
2632         netif_tx_start_all_queues(priv->netdev);
2633
2634         if (MLX5_VPORT_MANAGER(priv->mdev))
2635                 mlx5e_add_sqs_fwd_rules(priv);
2636
2637         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2638         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2639 }
2640
2641 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2642 {
2643         mlx5e_redirect_rqts_to_drop(priv);
2644
2645         if (MLX5_VPORT_MANAGER(priv->mdev))
2646                 mlx5e_remove_sqs_fwd_rules(priv);
2647
2648         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2649          * polling for inactive tx queues.
2650          */
2651         netif_tx_stop_all_queues(priv->netdev);
2652         netif_tx_disable(priv->netdev);
2653         mlx5e_deactivate_channels(&priv->channels);
2654 }
2655
2656 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2657                                 struct mlx5e_channels *new_chs,
2658                                 mlx5e_fp_hw_modify hw_modify)
2659 {
2660         struct net_device *netdev = priv->netdev;
2661         int new_num_txqs;
2662         int carrier_ok;
2663         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2664
2665         carrier_ok = netif_carrier_ok(netdev);
2666         netif_carrier_off(netdev);
2667
2668         if (new_num_txqs < netdev->real_num_tx_queues)
2669                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2670
2671         mlx5e_deactivate_priv_channels(priv);
2672         mlx5e_close_channels(&priv->channels);
2673
2674         priv->channels = *new_chs;
2675
2676         /* New channels are ready to roll, modify HW settings if needed */
2677         if (hw_modify)
2678                 hw_modify(priv);
2679
2680         mlx5e_refresh_tirs(priv, false);
2681         mlx5e_activate_priv_channels(priv);
2682
2683         /* return carrier back if needed */
2684         if (carrier_ok)
2685                 netif_carrier_on(netdev);
2686 }
2687
2688 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2689 {
2690         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2691         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2692 }
2693
2694 int mlx5e_open_locked(struct net_device *netdev)
2695 {
2696         struct mlx5e_priv *priv = netdev_priv(netdev);
2697         int err;
2698
2699         set_bit(MLX5E_STATE_OPENED, &priv->state);
2700
2701         err = mlx5e_open_channels(priv, &priv->channels);
2702         if (err)
2703                 goto err_clear_state_opened_flag;
2704
2705         mlx5e_refresh_tirs(priv, false);
2706         mlx5e_activate_priv_channels(priv);
2707         if (priv->profile->update_carrier)
2708                 priv->profile->update_carrier(priv);
2709
2710         if (priv->profile->update_stats)
2711                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2712
2713         return 0;
2714
2715 err_clear_state_opened_flag:
2716         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2717         return err;
2718 }
2719
2720 int mlx5e_open(struct net_device *netdev)
2721 {
2722         struct mlx5e_priv *priv = netdev_priv(netdev);
2723         int err;
2724
2725         mutex_lock(&priv->state_lock);
2726         err = mlx5e_open_locked(netdev);
2727         if (!err)
2728                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2729         mutex_unlock(&priv->state_lock);
2730
2731         return err;
2732 }
2733
2734 int mlx5e_close_locked(struct net_device *netdev)
2735 {
2736         struct mlx5e_priv *priv = netdev_priv(netdev);
2737
2738         /* May already be CLOSED in case a previous configuration operation
2739          * (e.g RX/TX queue size change) that involves close&open failed.
2740          */
2741         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2742                 return 0;
2743
2744         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2745
2746         netif_carrier_off(priv->netdev);
2747         mlx5e_deactivate_priv_channels(priv);
2748         mlx5e_close_channels(&priv->channels);
2749
2750         return 0;
2751 }
2752
2753 int mlx5e_close(struct net_device *netdev)
2754 {
2755         struct mlx5e_priv *priv = netdev_priv(netdev);
2756         int err;
2757
2758         if (!netif_device_present(netdev))
2759                 return -ENODEV;
2760
2761         mutex_lock(&priv->state_lock);
2762         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2763         err = mlx5e_close_locked(netdev);
2764         mutex_unlock(&priv->state_lock);
2765
2766         return err;
2767 }
2768
2769 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2770                                struct mlx5e_rq *rq,
2771                                struct mlx5e_rq_param *param)
2772 {
2773         void *rqc = param->rqc;
2774         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2775         int err;
2776
2777         param->wq.db_numa_node = param->wq.buf_numa_node;
2778
2779         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2780                                 &rq->wq_ctrl);
2781         if (err)
2782                 return err;
2783
2784         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2785         xdp_rxq_info_unused(&rq->xdp_rxq);
2786
2787         rq->mdev = mdev;
2788
2789         return 0;
2790 }
2791
2792 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2793                                struct mlx5e_cq *cq,
2794                                struct mlx5e_cq_param *param)
2795 {
2796         return mlx5e_alloc_cq_common(mdev, param, cq);
2797 }
2798
2799 static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2800                               struct mlx5e_rq *drop_rq)
2801 {
2802         struct mlx5e_cq_param cq_param = {};
2803         struct mlx5e_rq_param rq_param = {};
2804         struct mlx5e_cq *cq = &drop_rq->cq;
2805         int err;
2806
2807         mlx5e_build_drop_rq_param(&rq_param);
2808
2809         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2810         if (err)
2811                 return err;
2812
2813         err = mlx5e_create_cq(cq, &cq_param);
2814         if (err)
2815                 goto err_free_cq;
2816
2817         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2818         if (err)
2819                 goto err_destroy_cq;
2820
2821         err = mlx5e_create_rq(drop_rq, &rq_param);
2822         if (err)
2823                 goto err_free_rq;
2824
2825         return 0;
2826
2827 err_free_rq:
2828         mlx5e_free_rq(drop_rq);
2829
2830 err_destroy_cq:
2831         mlx5e_destroy_cq(cq);
2832
2833 err_free_cq:
2834         mlx5e_free_cq(cq);
2835
2836         return err;
2837 }
2838
2839 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2840 {
2841         mlx5e_destroy_rq(drop_rq);
2842         mlx5e_free_rq(drop_rq);
2843         mlx5e_destroy_cq(&drop_rq->cq);
2844         mlx5e_free_cq(&drop_rq->cq);
2845 }
2846
2847 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2848                      u32 underlay_qpn, u32 *tisn)
2849 {
2850         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2851         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2852
2853         MLX5_SET(tisc, tisc, prio, tc << 1);
2854         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2855         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2856
2857         if (mlx5_lag_is_lacp_owner(mdev))
2858                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2859
2860         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2861 }
2862
2863 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2864 {
2865         mlx5_core_destroy_tis(mdev, tisn);
2866 }
2867
2868 int mlx5e_create_tises(struct mlx5e_priv *priv)
2869 {
2870         int err;
2871         int tc;
2872
2873         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2874                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2875                 if (err)
2876                         goto err_close_tises;
2877         }
2878
2879         return 0;
2880
2881 err_close_tises:
2882         for (tc--; tc >= 0; tc--)
2883                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2884
2885         return err;
2886 }
2887
2888 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2889 {
2890         int tc;
2891
2892         for (tc = 0; tc < priv->profile->max_tc; tc++)
2893                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2894 }
2895
2896 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2897                                       enum mlx5e_traffic_types tt,
2898                                       u32 *tirc)
2899 {
2900         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2901
2902         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2903
2904         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2905         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2906         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2907 }
2908
2909 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2910 {
2911         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2912
2913         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2914
2915         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2916         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2917         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2918 }
2919
2920 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2921 {
2922         struct mlx5e_tir *tir;
2923         void *tirc;
2924         int inlen;
2925         int i = 0;
2926         int err;
2927         u32 *in;
2928         int tt;
2929
2930         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2931         in = kvzalloc(inlen, GFP_KERNEL);
2932         if (!in)
2933                 return -ENOMEM;
2934
2935         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2936                 memset(in, 0, inlen);
2937                 tir = &priv->indir_tir[tt];
2938                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2939                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2940                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2941                 if (err) {
2942                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2943                         goto err_destroy_inner_tirs;
2944                 }
2945         }
2946
2947         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2948                 goto out;
2949
2950         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2951                 memset(in, 0, inlen);
2952                 tir = &priv->inner_indir_tir[i];
2953                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2954                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2955                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2956                 if (err) {
2957                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2958                         goto err_destroy_inner_tirs;
2959                 }
2960         }
2961
2962 out:
2963         kvfree(in);
2964
2965         return 0;
2966
2967 err_destroy_inner_tirs:
2968         for (i--; i >= 0; i--)
2969                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2970
2971         for (tt--; tt >= 0; tt--)
2972                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2973
2974         kvfree(in);
2975
2976         return err;
2977 }
2978
2979 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2980 {
2981         int nch = priv->profile->max_nch(priv->mdev);
2982         struct mlx5e_tir *tir;
2983         void *tirc;
2984         int inlen;
2985         int err;
2986         u32 *in;
2987         int ix;
2988
2989         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2990         in = kvzalloc(inlen, GFP_KERNEL);
2991         if (!in)
2992                 return -ENOMEM;
2993
2994         for (ix = 0; ix < nch; ix++) {
2995                 memset(in, 0, inlen);
2996                 tir = &priv->direct_tir[ix];
2997                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2998                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2999                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3000                 if (err)
3001                         goto err_destroy_ch_tirs;
3002         }
3003
3004         kvfree(in);
3005
3006         return 0;
3007
3008 err_destroy_ch_tirs:
3009         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3010         for (ix--; ix >= 0; ix--)
3011                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3012
3013         kvfree(in);
3014
3015         return err;
3016 }
3017
3018 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3019 {
3020         int i;
3021
3022         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3023                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3024
3025         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3026                 return;
3027
3028         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3029                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3030 }
3031
3032 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3033 {
3034         int nch = priv->profile->max_nch(priv->mdev);
3035         int i;
3036
3037         for (i = 0; i < nch; i++)
3038                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3039 }
3040
3041 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3042 {
3043         int err = 0;
3044         int i;
3045
3046         for (i = 0; i < chs->num; i++) {
3047                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3048                 if (err)
3049                         return err;
3050         }
3051
3052         return 0;
3053 }
3054
3055 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3056 {
3057         int err = 0;
3058         int i;
3059
3060         for (i = 0; i < chs->num; i++) {
3061                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3062                 if (err)
3063                         return err;
3064         }
3065
3066         return 0;
3067 }
3068
3069 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3070                                  struct tc_mqprio_qopt *mqprio)
3071 {
3072         struct mlx5e_priv *priv = netdev_priv(netdev);
3073         struct mlx5e_channels new_channels = {};
3074         u8 tc = mqprio->num_tc;
3075         int err = 0;
3076
3077         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3078
3079         if (tc && tc != MLX5E_MAX_NUM_TC)
3080                 return -EINVAL;
3081
3082         mutex_lock(&priv->state_lock);
3083
3084         new_channels.params = priv->channels.params;
3085         new_channels.params.num_tc = tc ? tc : 1;
3086
3087         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3088                 priv->channels.params = new_channels.params;
3089                 goto out;
3090         }
3091
3092         err = mlx5e_open_channels(priv, &new_channels);
3093         if (err)
3094                 goto out;
3095
3096         mlx5e_switch_priv_channels(priv, &new_channels, NULL);