drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include <net/page_pool.h>
  39 #include "eswitch.h"
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "en_rep.h"
  43 #include "en_accel/ipsec.h"
  44 #include "en_accel/ipsec_rxtx.h"
  45 #include "en_accel/tls.h"
  46 #include "accel/ipsec.h"
  47 #include "accel/tls.h"
  48 #include "vxlan.h"
  49 #include "en/port.h"
  50 #include "en/xdp.h"
  51
  52 struct mlx5e_rq_param {
  53         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  54         struct mlx5_wq_param    wq;
  55         struct mlx5e_rq_frags_info frags_info;
  56 };
  57
  58 struct mlx5e_sq_param {
  59         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  60         struct mlx5_wq_param       wq;
  61 };
  62
  63 struct mlx5e_cq_param {
  64         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  65         struct mlx5_wq_param       wq;
  66         u16                        eq_ix;
  67         u8                         cq_period_mode;
  68 };
  69
  70 struct mlx5e_channel_param {
  71         struct mlx5e_rq_param      rq;
  72         struct mlx5e_sq_param      sq;
  73         struct mlx5e_sq_param      xdp_sq;
  74         struct mlx5e_sq_param      icosq;
  75         struct mlx5e_cq_param      rx_cq;
  76         struct mlx5e_cq_param      tx_cq;
  77         struct mlx5e_cq_param      icosq_cq;
  78 };
  79
  80 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  81 {
  82         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  83                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  84                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  85         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  86         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  87
  88         if (!striding_rq_umr)
  89                 return false;
  90         if (!inline_umr) {
  91                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  92                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  93                 return false;
  94         }
  95         return true;
  96 }
  97
  98 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
  99 {
 100         u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 101         u16 linear_rq_headroom = params->xdp_prog ?
 102                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 103         u32 frag_sz;
 104
 105         linear_rq_headroom += NET_IP_ALIGN;
 106
 107         frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
 108
 109         if (params->xdp_prog && frag_sz < PAGE_SIZE)
 110                 frag_sz = PAGE_SIZE;
 111
 112         return frag_sz;
 113 }
 114
 115 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 116 {
 117         u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 118
 119         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 120 }
 121
 122 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
 123                                    struct mlx5e_params *params)
 124 {
 125         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 126
 127         return !params->lro_en && frag_sz <= PAGE_SIZE;
 128 }
 129
 130 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 131                                          struct mlx5e_params *params)
 132 {
 133         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 134         s8 signed_log_num_strides_param;
 135         u8 log_num_strides;
 136
 137         if (!mlx5e_rx_is_linear_skb(mdev, params))
 138                 return false;
 139
 140         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 141                 return true;
 142
 143         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 144         signed_log_num_strides_param =
 145                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 146
 147         return signed_log_num_strides_param >= 0;
 148 }
 149
 150 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 151 {
 152         if (params->log_rq_mtu_frames <
 153             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 154                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 155
 156         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 157 }
 158
 159 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 160                                           struct mlx5e_params *params)
 161 {
 162         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 163                 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
 164
 165         return MLX5E_MPWQE_STRIDE_SZ(mdev,
 166                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 167 }
 168
 169 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 170                                           struct mlx5e_params *params)
 171 {
 172         return MLX5_MPWRQ_LOG_WQE_SZ -
 173                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 174 }
 175
 176 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 177                                  struct mlx5e_params *params)
 178 {
 179         u16 linear_rq_headroom = params->xdp_prog ?
 180                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 181         bool is_linear_skb;
 182
 183         linear_rq_headroom += NET_IP_ALIGN;
 184
 185         is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
 186                 mlx5e_rx_is_linear_skb(mdev, params) :
 187                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
 188
 189         return is_linear_skb ? linear_rq_headroom : 0;
 190 }
 191
 192 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 193                                struct mlx5e_params *params)
 194 {
 195         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 196         params->log_rq_mtu_frames = is_kdump_kernel() ?
 197                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 198                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 199
 200         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 201                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 202                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 203                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 204                        BIT(params->log_rq_mtu_frames),
 205                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 206                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 207 }
 208
 209 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 210                                 struct mlx5e_params *params)
 211 {
 212         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 213                 !MLX5_IPSEC_DEV(mdev) &&
 214                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 215 }
 216
 217 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 218 {
 219         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 220                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 221                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 222                 MLX5_WQ_TYPE_CYCLIC;
 223 }
 224
 225 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 226 {
 227         struct mlx5_core_dev *mdev = priv->mdev;
 228         u8 port_state;
 229
 230         port_state = mlx5_query_vport_state(mdev,
 231                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
 232                                             0);
 233
 234         if (port_state == VPORT_STATE_UP) {
 235                 netdev_info(priv->netdev, "Link up\n");
 236                 netif_carrier_on(priv->netdev);
 237         } else {
 238                 netdev_info(priv->netdev, "Link down\n");
 239                 netif_carrier_off(priv->netdev);
 240         }
 241 }
 242
 243 static void mlx5e_update_carrier_work(struct work_struct *work)
 244 {
 245         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 246                                                update_carrier_work);
 247
 248         mutex_lock(&priv->state_lock);
 249         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 250                 if (priv->profile->update_carrier)
 251                         priv->profile->update_carrier(priv);
 252         mutex_unlock(&priv->state_lock);
 253 }
 254
 255 void mlx5e_update_stats(struct mlx5e_priv *priv)
 256 {
 257         int i;
 258
 259         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 260                 if (mlx5e_stats_grps[i].update_stats)
 261                         mlx5e_stats_grps[i].update_stats(priv);
 262 }
 263
 264 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 265 {
 266         int i;
 267
 268         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 269                 if (mlx5e_stats_grps[i].update_stats_mask &
 270                     MLX5E_NDO_UPDATE_STATS)
 271                         mlx5e_stats_grps[i].update_stats(priv);
 272 }
 273
 274 void mlx5e_update_stats_work(struct work_struct *work)
 275 {
 276         struct delayed_work *dwork = to_delayed_work(work);
 277         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 278                                                update_stats_work);
 279
 280         mutex_lock(&priv->state_lock);
 281         priv->profile->update_stats(priv);
 282         mutex_unlock(&priv->state_lock);
 283 }
 284
 285 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 286                               enum mlx5_dev_event event, unsigned long param)
 287 {
 288         struct mlx5e_priv *priv = vpriv;
 289
 290         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 291                 return;
 292
 293         switch (event) {
 294         case MLX5_DEV_EVENT_PORT_UP:
 295         case MLX5_DEV_EVENT_PORT_DOWN:
 296                 queue_work(priv->wq, &priv->update_carrier_work);
 297                 break;
 298         default:
 299                 break;
 300         }
 301 }
 302
 303 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 304 {
 305         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 306 }
 307
 308 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 309 {
 310         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 311         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 312 }
 313
 314 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 315                                        struct mlx5e_icosq *sq,
 316                                        struct mlx5e_umr_wqe *wqe)
 317 {
 318         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 319         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 320         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 321
 322         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 323                                       ds_cnt);
 324         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 325         cseg->imm       = rq->mkey_be;
 326
 327         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 328         ucseg->xlt_octowords =
 329                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 330         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 331 }
 332
 333 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 334 {
 335         switch (rq->wq_type) {
 336         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 337                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 338         default:
 339                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 340         }
 341 }
 342
 343 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 344 {
 345         switch (rq->wq_type) {
 346         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 347                 return rq->mpwqe.wq.cur_sz;
 348         default:
 349                 return rq->wqe.wq.cur_sz;
 350         }
 351 }
 352
 353 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 354                                      struct mlx5e_channel *c)
 355 {
 356         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 357
 358         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 359                                                   sizeof(*rq->mpwqe.info)),
 360                                        GFP_KERNEL, cpu_to_node(c->cpu));
 361         if (!rq->mpwqe.info)
 362                 return -ENOMEM;
 363
 364         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 365
 366         return 0;
 367 }
 368
 369 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 370                                  u64 npages, u8 page_shift,
 371                                  struct mlx5_core_mkey *umr_mkey)
 372 {
 373         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 374         void *mkc;
 375         u32 *in;
 376         int err;
 377
 378         in = kvzalloc(inlen, GFP_KERNEL);
 379         if (!in)
 380                 return -ENOMEM;
 381
 382         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 383
 384         MLX5_SET(mkc, mkc, free, 1);
 385         MLX5_SET(mkc, mkc, umr_en, 1);
 386         MLX5_SET(mkc, mkc, lw, 1);
 387         MLX5_SET(mkc, mkc, lr, 1);
 388         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 389
 390         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 391         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 392         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 393         MLX5_SET(mkc, mkc, translations_octword_size,
 394                  MLX5_MTT_OCTW(npages));
 395         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 396
 397         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 398
 399         kvfree(in);
 400         return err;
 401 }
 402
 403 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 404 {
 405         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 406
 407         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 408 }
 409
 410 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 411 {
 412         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 413 }
 414
 415 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 416 {
 417         struct mlx5e_wqe_frag_info next_frag, *prev;
 418         int i;
 419
 420         next_frag.di = &rq->wqe.di[0];
 421         next_frag.offset = 0;
 422         prev = NULL;
 423
 424         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 425                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 426                 struct mlx5e_wqe_frag_info *frag =
 427                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 428                 int f;
 429
 430                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 431                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 432                                 next_frag.di++;
 433                                 next_frag.offset = 0;
 434                                 if (prev)
 435                                         prev->last_in_page = true;
 436                         }
 437                         *frag = next_frag;
 438
 439                         /* prepare next */
 440                         next_frag.offset += frag_info[f].frag_stride;
 441                         prev = frag;
 442                 }
 443         }
 444
 445         if (prev)
 446                 prev->last_in_page = true;
 447 }
 448
 449 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 450                               struct mlx5e_params *params,
 451                               int wq_sz, int cpu)
 452 {
 453         int len = wq_sz << rq->wqe.info.log_num_frags;
 454
 455         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 456                                    GFP_KERNEL, cpu_to_node(cpu));
 457         if (!rq->wqe.di)
 458                 return -ENOMEM;
 459
 460         mlx5e_init_frags_partition(rq);
 461
 462         return 0;
 463 }
 464
 465 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 466 {
 467         kvfree(rq->wqe.di);
 468 }
 469
 470 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 471                           struct mlx5e_params *params,
 472                           struct mlx5e_rq_param *rqp,
 473                           struct mlx5e_rq *rq)
 474 {
 475         struct page_pool_params pp_params = { 0 };
 476         struct mlx5_core_dev *mdev = c->mdev;
 477         void *rqc = rqp->rqc;
 478         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 479         u32 pool_size;
 480         int wq_sz;
 481         int err;
 482         int i;
 483
 484         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 485
 486         rq->wq_type = params->rq_wq_type;
 487         rq->pdev    = c->pdev;
 488         rq->netdev  = c->netdev;
 489         rq->tstamp  = c->tstamp;
 490         rq->clock   = &mdev->clock;
 491         rq->channel = c;
 492         rq->ix      = c->ix;
 493         rq->mdev    = mdev;
 494         rq->stats   = &c->priv->channel_stats[c->ix].rq;
 495
 496         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 497         if (IS_ERR(rq->xdp_prog)) {
 498                 err = PTR_ERR(rq->xdp_prog);
 499                 rq->xdp_prog = NULL;
 500                 goto err_rq_wq_destroy;
 501         }
 502
 503         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 504         if (err < 0)
 505                 goto err_rq_wq_destroy;
 506
 507         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 508         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 509         pool_size = 1 << params->log_rq_mtu_frames;
 510
 511         switch (rq->wq_type) {
 512         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 513                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 514                                         &rq->wq_ctrl);
 515                 if (err)
 516                         return err;
 517
 518                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 519
 520                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 521
 522                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 523
 524                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 525                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 526
 527                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 528 #ifdef CONFIG_MLX5_EN_IPSEC
 529                 if (MLX5_IPSEC_DEV(mdev)) {
 530                         err = -EINVAL;
 531                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 532                         goto err_rq_wq_destroy;
 533                 }
 534 #endif
 535                 if (!rq->handle_rx_cqe) {
 536                         err = -EINVAL;
 537                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 538                         goto err_rq_wq_destroy;
 539                 }
 540
 541                 rq->mpwqe.skb_from_cqe_mpwrq =
 542                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 543                         mlx5e_skb_from_cqe_mpwrq_linear :
 544                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 545                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 546                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 547
 548                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 549                 if (err)
 550                         goto err_rq_wq_destroy;
 551                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 552
 553                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 554                 if (err)
 555                         goto err_free;
 556                 break;
 557         default: /* MLX5_WQ_TYPE_CYCLIC */
 558                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 559                                          &rq->wq_ctrl);
 560                 if (err)
 561                         return err;
 562
 563                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 564
 565                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 566
 567                 rq->wqe.info = rqp->frags_info;
 568                 rq->wqe.frags =
 569                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 570                                         (wq_sz << rq->wqe.info.log_num_frags)),
 571                                       GFP_KERNEL, cpu_to_node(c->cpu));
 572                 if (!rq->wqe.frags) {
 573                         err = -ENOMEM;
 574                         goto err_free;
 575                 }
 576
 577                 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
 578                 if (err)
 579                         goto err_free;
 580                 rq->post_wqes = mlx5e_post_rx_wqes;
 581                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 582
 583 #ifdef CONFIG_MLX5_EN_IPSEC
 584                 if (c->priv->ipsec)
 585                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 586                 else
 587 #endif
 588                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 589                 if (!rq->handle_rx_cqe) {
 590                         err = -EINVAL;
 591                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 592                         goto err_free;
 593                 }
 594
 595                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
 596                         mlx5e_skb_from_cqe_linear :
 597                         mlx5e_skb_from_cqe_nonlinear;
 598                 rq->mkey_be = c->mkey_be;
 599         }
 600
 601         /* Create a page_pool and register it with rxq */
 602         pp_params.order     = 0;
 603         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 604         pp_params.pool_size = pool_size;
 605         pp_params.nid       = cpu_to_node(c->cpu);
 606         pp_params.dev       = c->pdev;
 607         pp_params.dma_dir   = rq->buff.map_dir;
 608
 609         /* page_pool can be used even when there is no rq->xdp_prog,
 610          * given page_pool does not handle DMA mapping there is no
 611          * required state to clear. And page_pool gracefully handle
 612          * elevated refcnt.
 613          */
 614         rq->page_pool = page_pool_create(&pp_params);
 615         if (IS_ERR(rq->page_pool)) {
 616                 err = PTR_ERR(rq->page_pool);
 617                 rq->page_pool = NULL;
 618                 goto err_free;
 619         }
 620         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 621                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 622         if (err)
 623                 goto err_free;
 624
 625         for (i = 0; i < wq_sz; i++) {
 626                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 627                         struct mlx5e_rx_wqe_ll *wqe =
 628                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 629                         u32 byte_count =
 630                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 631                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 632
 633                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 634                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 635                         wqe->data[0].lkey = rq->mkey_be;
 636                 } else {
 637                         struct mlx5e_rx_wqe_cyc *wqe =
 638                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 639                         int f;
 640
 641                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 642                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 643                                         MLX5_HW_START_PADDING;
 644
 645                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 646                                 wqe->data[f].lkey = rq->mkey_be;
 647                         }
 648                         /* check if num_frags is not a pow of two */
 649                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 650                                 wqe->data[f].byte_count = 0;
 651                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 652                                 wqe->data[f].addr = 0;
 653                         }
 654                 }
 655         }
 656
 657         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 658
 659         switch (params->rx_cq_moderation.cq_period_mode) {
 660         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 661                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 662                 break;
 663         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 664         default:
 665                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 666         }
 667
 668         rq->page_cache.head = 0;
 669         rq->page_cache.tail = 0;
 670
 671         return 0;
 672
 673 err_free:
 674         switch (rq->wq_type) {
 675         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 676                 kvfree(rq->mpwqe.info);
 677                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 678                 break;
 679         default: /* MLX5_WQ_TYPE_CYCLIC */
 680                 kvfree(rq->wqe.frags);
 681                 mlx5e_free_di_list(rq);
 682         }
 683
 684 err_rq_wq_destroy:
 685         if (rq->xdp_prog)
 686                 bpf_prog_put(rq->xdp_prog);
 687         xdp_rxq_info_unreg(&rq->xdp_rxq);
 688         if (rq->page_pool)
 689                 page_pool_destroy(rq->page_pool);
 690         mlx5_wq_destroy(&rq->wq_ctrl);
 691
 692         return err;
 693 }
 694
 695 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 696 {
 697         int i;
 698
 699         if (rq->xdp_prog)
 700                 bpf_prog_put(rq->xdp_prog);
 701
 702         xdp_rxq_info_unreg(&rq->xdp_rxq);
 703         if (rq->page_pool)
 704                 page_pool_destroy(rq->page_pool);
 705
 706         switch (rq->wq_type) {
 707         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 708                 kvfree(rq->mpwqe.info);
 709                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 710                 break;
 711         default: /* MLX5_WQ_TYPE_CYCLIC */
 712                 kvfree(rq->wqe.frags);
 713                 mlx5e_free_di_list(rq);
 714         }
 715
 716         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 717              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 718                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 719
 720                 mlx5e_page_release(rq, dma_info, false);
 721         }
 722         mlx5_wq_destroy(&rq->wq_ctrl);
 723 }
 724
 725 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 726                            struct mlx5e_rq_param *param)
 727 {
 728         struct mlx5_core_dev *mdev = rq->mdev;
 729
 730         void *in;
 731         void *rqc;
 732         void *wq;
 733         int inlen;
 734         int err;
 735
 736         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 737                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 738         in = kvzalloc(inlen, GFP_KERNEL);
 739         if (!in)
 740                 return -ENOMEM;
 741
 742         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 743         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 744
 745         memcpy(rqc, param->rqc, sizeof(param->rqc));
 746
 747         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 748         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 749         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 750                                                 MLX5_ADAPTER_PAGE_SHIFT);
 751         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 752
 753         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 754                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 755
 756         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 757
 758         kvfree(in);
 759
 760         return err;
 761 }
 762
 763 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 764                                  int next_state)
 765 {
 766         struct mlx5_core_dev *mdev = rq->mdev;
 767
 768         void *in;
 769         void *rqc;
 770         int inlen;
 771         int err;
 772
 773         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 774         in = kvzalloc(inlen, GFP_KERNEL);
 775         if (!in)
 776                 return -ENOMEM;
 777
 778         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 779
 780         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 781         MLX5_SET(rqc, rqc, state, next_state);
 782
 783         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 784
 785         kvfree(in);
 786
 787         return err;
 788 }
 789
 790 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 791 {
 792         struct mlx5e_channel *c = rq->channel;
 793         struct mlx5e_priv *priv = c->priv;
 794         struct mlx5_core_dev *mdev = priv->mdev;
 795
 796         void *in;
 797         void *rqc;
 798         int inlen;
 799         int err;
 800
 801         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 802         in = kvzalloc(inlen, GFP_KERNEL);
 803         if (!in)
 804                 return -ENOMEM;
 805
 806         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 807
 808         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 809         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 810                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 811         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 812         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 813
 814         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 815
 816         kvfree(in);
 817
 818         return err;
 819 }
 820
 821 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 822 {
 823         struct mlx5e_channel *c = rq->channel;
 824         struct mlx5_core_dev *mdev = c->mdev;
 825         void *in;
 826         void *rqc;
 827         int inlen;
 828         int err;
 829
 830         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 831         in = kvzalloc(inlen, GFP_KERNEL);
 832         if (!in)
 833                 return -ENOMEM;
 834
 835         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 836
 837         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 838         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 839                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 840         MLX5_SET(rqc, rqc, vsd, vsd);
 841         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 842
 843         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 844
 845         kvfree(in);
 846
 847         return err;
 848 }
 849
 850 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 851 {
 852         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 853 }
 854
 855 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 856 {
 857         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 858         struct mlx5e_channel *c = rq->channel;
 859
 860         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 861
 862         do {
 863                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 864                         return 0;
 865
 866                 msleep(20);
 867         } while (time_before(jiffies, exp_time));
 868
 869         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 870                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 871
 872         return -ETIMEDOUT;
 873 }
 874
 875 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 876 {
 877         __be16 wqe_ix_be;
 878         u16 wqe_ix;
 879
 880         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 881                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 882
 883                 /* UMR WQE (if in progress) is always at wq->head */
 884                 if (rq->mpwqe.umr_in_progress)
 885                         rq->dealloc_wqe(rq, wq->head);
 886
 887                 while (!mlx5_wq_ll_is_empty(wq)) {
 888                         struct mlx5e_rx_wqe_ll *wqe;
 889
 890                         wqe_ix_be = *wq->tail_next;
 891                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 892                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 893                         rq->dealloc_wqe(rq, wqe_ix);
 894                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 895                                        &wqe->next.next_wqe_index);
 896                 }
 897         } else {
 898                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 899
 900                 while (!mlx5_wq_cyc_is_empty(wq)) {
 901                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 902                         rq->dealloc_wqe(rq, wqe_ix);
 903                         mlx5_wq_cyc_pop(wq);
 904                 }
 905         }
 906
 907 }
 908
 909 static int mlx5e_open_rq(struct mlx5e_channel *c,
 910                          struct mlx5e_params *params,
 911                          struct mlx5e_rq_param *param,
 912                          struct mlx5e_rq *rq)
 913 {
 914         int err;
 915
 916         err = mlx5e_alloc_rq(c, params, param, rq);
 917         if (err)
 918                 return err;
 919
 920         err = mlx5e_create_rq(rq, param);
 921         if (err)
 922                 goto err_free_rq;
 923
 924         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 925         if (err)
 926                 goto err_destroy_rq;
 927
 928         if (params->rx_dim_enabled)
 929                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 930
 931         return 0;
 932
 933 err_destroy_rq:
 934         mlx5e_destroy_rq(rq);
 935 err_free_rq:
 936         mlx5e_free_rq(rq);
 937
 938         return err;
 939 }
 940
 941 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 942 {
 943         struct mlx5e_icosq *sq = &rq->channel->icosq;
 944         struct mlx5_wq_cyc *wq = &sq->wq;
 945         struct mlx5e_tx_wqe *nopwqe;
 946
 947         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 948
 949         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 950         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 951         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 952         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 953 }
 954
 955 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 956 {
 957         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 958         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 959 }
 960
 961 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 962 {
 963         cancel_work_sync(&rq->dim.work);
 964         mlx5e_destroy_rq(rq);
 965         mlx5e_free_rx_descs(rq);
 966         mlx5e_free_rq(rq);
 967 }
 968
 969 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 970 {
 971         kvfree(sq->db.xdpi);
 972 }
 973
 974 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 975 {
 976         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 977
 978         sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)),
 979                                     GFP_KERNEL, numa);
 980         if (!sq->db.xdpi) {
 981                 mlx5e_free_xdpsq_db(sq);
 982                 return -ENOMEM;
 983         }
 984
 985         return 0;
 986 }
 987
 988 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 989                              struct mlx5e_params *params,
 990                              struct mlx5e_sq_param *param,
 991                              struct mlx5e_xdpsq *sq)
 992 {
 993         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 994         struct mlx5_core_dev *mdev = c->mdev;
 995         struct mlx5_wq_cyc *wq = &sq->wq;
 996         int err;
 997
 998         sq->pdev      = c->pdev;
 999         sq->mkey_be   = c->mkey_be;
1000         sq->channel   = c;
1001         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1002         sq->min_inline_mode = params->tx_min_inline_mode;
1003         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1004
1005         param->wq.db_numa_node = cpu_to_node(c->cpu);
1006         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1007         if (err)
1008                 return err;
1009         wq->db = &wq->db[MLX5_SND_DBR];
1010
1011         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1012         if (err)
1013                 goto err_sq_wq_destroy;
1014
1015         return 0;
1016
1017 err_sq_wq_destroy:
1018         mlx5_wq_destroy(&sq->wq_ctrl);
1019
1020         return err;
1021 }
1022
1023 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1024 {
1025         mlx5e_free_xdpsq_db(sq);
1026         mlx5_wq_destroy(&sq->wq_ctrl);
1027 }
1028
1029 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1030 {
1031         kvfree(sq->db.ico_wqe);
1032 }
1033
1034 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1035 {
1036         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1037
1038         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1039                                                   sizeof(*sq->db.ico_wqe)),
1040                                        GFP_KERNEL, numa);
1041         if (!sq->db.ico_wqe)
1042                 return -ENOMEM;
1043
1044         return 0;
1045 }
1046
1047 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1048                              struct mlx5e_sq_param *param,
1049                              struct mlx5e_icosq *sq)
1050 {
1051         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1052         struct mlx5_core_dev *mdev = c->mdev;
1053         struct mlx5_wq_cyc *wq = &sq->wq;
1054         int err;
1055
1056         sq->channel   = c;
1057         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1058
1059         param->wq.db_numa_node = cpu_to_node(c->cpu);
1060         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1061         if (err)
1062                 return err;
1063         wq->db = &wq->db[MLX5_SND_DBR];
1064
1065         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1066         if (err)
1067                 goto err_sq_wq_destroy;
1068
1069         return 0;
1070
1071 err_sq_wq_destroy:
1072         mlx5_wq_destroy(&sq->wq_ctrl);
1073
1074         return err;
1075 }
1076
1077 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1078 {
1079         mlx5e_free_icosq_db(sq);
1080         mlx5_wq_destroy(&sq->wq_ctrl);
1081 }
1082
1083 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1084 {
1085         kvfree(sq->db.wqe_info);
1086         kvfree(sq->db.dma_fifo);
1087 }
1088
1089 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1090 {
1091         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1092         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1093
1094         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1095                                                    sizeof(*sq->db.dma_fifo)),
1096                                         GFP_KERNEL, numa);
1097         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1098                                                    sizeof(*sq->db.wqe_info)),
1099                                         GFP_KERNEL, numa);
1100         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1101                 mlx5e_free_txqsq_db(sq);
1102                 return -ENOMEM;
1103         }
1104
1105         sq->dma_fifo_mask = df_sz - 1;
1106
1107         return 0;
1108 }
1109
1110 static void mlx5e_sq_recover(struct work_struct *work);
1111 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1112                              int txq_ix,
1113                              struct mlx5e_params *params,
1114                              struct mlx5e_sq_param *param,
1115                              struct mlx5e_txqsq *sq,
1116                              int tc)
1117 {
1118         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1119         struct mlx5_core_dev *mdev = c->mdev;
1120         struct mlx5_wq_cyc *wq = &sq->wq;
1121         int err;
1122
1123         sq->pdev      = c->pdev;
1124         sq->tstamp    = c->tstamp;
1125         sq->clock     = &mdev->clock;
1126         sq->mkey_be   = c->mkey_be;
1127         sq->channel   = c;
1128         sq->txq_ix    = txq_ix;
1129         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1130         sq->min_inline_mode = params->tx_min_inline_mode;
1131         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1132         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1133         if (MLX5_IPSEC_DEV(c->priv->mdev))
1134                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1135         if (mlx5_accel_is_tls_device(c->priv->mdev))
1136                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1137
1138         param->wq.db_numa_node = cpu_to_node(c->cpu);
1139         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1140         if (err)
1141                 return err;
1142         wq->db    = &wq->db[MLX5_SND_DBR];
1143
1144         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1145         if (err)
1146                 goto err_sq_wq_destroy;
1147
1148         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1149         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1150
1151         return 0;
1152
1153 err_sq_wq_destroy:
1154         mlx5_wq_destroy(&sq->wq_ctrl);
1155
1156         return err;
1157 }
1158
1159 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1160 {
1161         mlx5e_free_txqsq_db(sq);
1162         mlx5_wq_destroy(&sq->wq_ctrl);
1163 }
1164
1165 struct mlx5e_create_sq_param {
1166         struct mlx5_wq_ctrl        *wq_ctrl;
1167         u32                         cqn;
1168         u32                         tisn;
1169         u8                          tis_lst_sz;
1170         u8                          min_inline_mode;
1171 };
1172
1173 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1174                            struct mlx5e_sq_param *param,
1175                            struct mlx5e_create_sq_param *csp,
1176                            u32 *sqn)
1177 {
1178         void *in;
1179         void *sqc;
1180         void *wq;
1181         int inlen;
1182         int err;
1183
1184         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1185                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1186         in = kvzalloc(inlen, GFP_KERNEL);
1187         if (!in)
1188                 return -ENOMEM;
1189
1190         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1191         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1192
1193         memcpy(sqc, param->sqc, sizeof(param->sqc));
1194         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1195         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1196         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1197
1198         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1199                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1200
1201         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1202         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1203
1204         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1205         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1206         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1207                                           MLX5_ADAPTER_PAGE_SHIFT);
1208         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1209
1210         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1211                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1212
1213         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1214
1215         kvfree(in);
1216
1217         return err;
1218 }
1219
1220 struct mlx5e_modify_sq_param {
1221         int curr_state;
1222         int next_state;
1223         bool rl_update;
1224         int rl_index;
1225 };
1226
1227 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1228                            struct mlx5e_modify_sq_param *p)
1229 {
1230         void *in;
1231         void *sqc;
1232         int inlen;
1233         int err;
1234
1235         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1236         in = kvzalloc(inlen, GFP_KERNEL);
1237         if (!in)
1238                 return -ENOMEM;
1239
1240         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1241
1242         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1243         MLX5_SET(sqc, sqc, state, p->next_state);
1244         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1245                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1246                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1247         }
1248
1249         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1250
1251         kvfree(in);
1252
1253         return err;
1254 }
1255
1256 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1257 {
1258         mlx5_core_destroy_sq(mdev, sqn);
1259 }
1260
1261 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1262                                struct mlx5e_sq_param *param,
1263                                struct mlx5e_create_sq_param *csp,
1264                                u32 *sqn)
1265 {
1266         struct mlx5e_modify_sq_param msp = {0};
1267         int err;
1268
1269         err = mlx5e_create_sq(mdev, param, csp, sqn);
1270         if (err)
1271                 return err;
1272
1273         msp.curr_state = MLX5_SQC_STATE_RST;
1274         msp.next_state = MLX5_SQC_STATE_RDY;
1275         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1276         if (err)
1277                 mlx5e_destroy_sq(mdev, *sqn);
1278
1279         return err;
1280 }
1281
1282 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1283                                 struct mlx5e_txqsq *sq, u32 rate);
1284
1285 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1286                             u32 tisn,
1287                             int txq_ix,
1288                             struct mlx5e_params *params,
1289                             struct mlx5e_sq_param *param,
1290                             struct mlx5e_txqsq *sq,
1291                             int tc)
1292 {
1293         struct mlx5e_create_sq_param csp = {};
1294         u32 tx_rate;
1295         int err;
1296
1297         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1298         if (err)
1299                 return err;
1300
1301         csp.tisn            = tisn;
1302         csp.tis_lst_sz      = 1;
1303         csp.cqn             = sq->cq.mcq.cqn;
1304         csp.wq_ctrl         = &sq->wq_ctrl;
1305         csp.min_inline_mode = sq->min_inline_mode;
1306         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1307         if (err)
1308                 goto err_free_txqsq;
1309
1310         tx_rate = c->priv->tx_rates[sq->txq_ix];
1311         if (tx_rate)
1312                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1313
1314         if (params->tx_dim_enabled)
1315                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1316
1317         return 0;
1318
1319 err_free_txqsq:
1320         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1321         mlx5e_free_txqsq(sq);
1322
1323         return err;
1324 }
1325
1326 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1327 {
1328         WARN_ONCE(sq->cc != sq->pc,
1329                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1330                   sq->sqn, sq->cc, sq->pc);
1331         sq->cc = 0;
1332         sq->dma_fifo_cc = 0;
1333         sq->pc = 0;
1334 }
1335
1336 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1337 {
1338         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1339         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1340         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1341         netdev_tx_reset_queue(sq->txq);
1342         netif_tx_start_queue(sq->txq);
1343 }
1344
1345 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1346 {
1347         __netif_tx_lock_bh(txq);
1348         netif_tx_stop_queue(txq);
1349         __netif_tx_unlock_bh(txq);
1350 }
1351
1352 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1353 {
1354         struct mlx5e_channel *c = sq->channel;
1355         struct mlx5_wq_cyc *wq = &sq->wq;
1356
1357         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1358         /* prevent netif_tx_wake_queue */
1359         napi_synchronize(&c->napi);
1360
1361         netif_tx_disable_queue(sq->txq);
1362
1363         /* last doorbell out, godspeed .. */
1364         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1365                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1366                 struct mlx5e_tx_wqe *nop;
1367
1368                 sq->db.wqe_info[pi].skb = NULL;
1369                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1370                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1371         }
1372 }
1373
1374 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1375 {
1376         struct mlx5e_channel *c = sq->channel;
1377         struct mlx5_core_dev *mdev = c->mdev;
1378         struct mlx5_rate_limit rl = {0};
1379
1380         mlx5e_destroy_sq(mdev, sq->sqn);
1381         if (sq->rate_limit) {
1382                 rl.rate = sq->rate_limit;
1383                 mlx5_rl_remove_rate(mdev, &rl);
1384         }
1385         mlx5e_free_txqsq_descs(sq);
1386         mlx5e_free_txqsq(sq);
1387 }
1388
1389 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1390 {
1391         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1392
1393         while (time_before(jiffies, exp_time)) {
1394                 if (sq->cc == sq->pc)
1395                         return 0;
1396
1397                 msleep(20);
1398         }
1399
1400         netdev_err(sq->channel->netdev,
1401                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1402                    sq->sqn, sq->cc, sq->pc);
1403
1404         return -ETIMEDOUT;
1405 }
1406
1407 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1408 {
1409         struct mlx5_core_dev *mdev = sq->channel->mdev;
1410         struct net_device *dev = sq->channel->netdev;
1411         struct mlx5e_modify_sq_param msp = {0};
1412         int err;
1413
1414         msp.curr_state = curr_state;
1415         msp.next_state = MLX5_SQC_STATE_RST;
1416
1417         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1418         if (err) {
1419                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1420                 return err;
1421         }
1422
1423         memset(&msp, 0, sizeof(msp));
1424         msp.curr_state = MLX5_SQC_STATE_RST;
1425         msp.next_state = MLX5_SQC_STATE_RDY;
1426
1427         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1428         if (err) {
1429                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1430                 return err;
1431         }
1432
1433         return 0;
1434 }
1435
1436 static void mlx5e_sq_recover(struct work_struct *work)
1437 {
1438         struct mlx5e_txqsq_recover *recover =
1439                 container_of(work, struct mlx5e_txqsq_recover,
1440                              recover_work);
1441         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1442                                               recover);
1443         struct mlx5_core_dev *mdev = sq->channel->mdev;
1444         struct net_device *dev = sq->channel->netdev;
1445         u8 state;
1446         int err;
1447
1448         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1449         if (err) {
1450                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1451                            sq->sqn, err);
1452                 return;
1453         }
1454
1455         if (state != MLX5_RQC_STATE_ERR) {
1456                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1457                 return;
1458         }
1459
1460         netif_tx_disable_queue(sq->txq);
1461
1462         if (mlx5e_wait_for_sq_flush(sq))
1463                 return;
1464
1465         /* If the interval between two consecutive recovers per SQ is too
1466          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1467          * If we reached this state, there is probably a bug that needs to be
1468          * fixed. let's keep the queue close and let tx timeout cleanup.
1469          */
1470         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1471             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1472                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1473                            sq->sqn);
1474                 return;
1475         }
1476
1477         /* At this point, no new packets will arrive from the stack as TXQ is
1478          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1479          * pending WQEs.  SQ can safely reset the SQ.
1480          */
1481         if (mlx5e_sq_to_ready(sq, state))
1482                 return;
1483
1484         mlx5e_reset_txqsq_cc_pc(sq);
1485         sq->stats->recover++;
1486         recover->last_recover = jiffies;
1487         mlx5e_activate_txqsq(sq);
1488 }
1489
1490 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1491                             struct mlx5e_params *params,
1492                             struct mlx5e_sq_param *param,
1493                             struct mlx5e_icosq *sq)
1494 {
1495         struct mlx5e_create_sq_param csp = {};
1496         int err;
1497
1498         err = mlx5e_alloc_icosq(c, param, sq);
1499         if (err)
1500                 return err;
1501
1502         csp.cqn             = sq->cq.mcq.cqn;
1503         csp.wq_ctrl         = &sq->wq_ctrl;
1504         csp.min_inline_mode = params->tx_min_inline_mode;
1505         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1506         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1507         if (err)
1508                 goto err_free_icosq;
1509
1510         return 0;
1511
1512 err_free_icosq:
1513         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1514         mlx5e_free_icosq(sq);
1515
1516         return err;
1517 }
1518
1519 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1520 {
1521         struct mlx5e_channel *c = sq->channel;
1522
1523         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1524         napi_synchronize(&c->napi);
1525
1526         mlx5e_destroy_sq(c->mdev, sq->sqn);
1527         mlx5e_free_icosq(sq);
1528 }
1529
1530 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1531                             struct mlx5e_params *params,
1532                             struct mlx5e_sq_param *param,
1533                             struct mlx5e_xdpsq *sq)
1534 {
1535         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1536         struct mlx5e_create_sq_param csp = {};
1537         unsigned int inline_hdr_sz = 0;
1538         int err;
1539         int i;
1540
1541         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1542         if (err)
1543                 return err;
1544
1545         csp.tis_lst_sz      = 1;
1546         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1547         csp.cqn             = sq->cq.mcq.cqn;
1548         csp.wq_ctrl         = &sq->wq_ctrl;
1549         csp.min_inline_mode = sq->min_inline_mode;
1550         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1551         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1552         if (err)
1553                 goto err_free_xdpsq;
1554
1555         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1556                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1557                 ds_cnt++;
1558         }
1559
1560         /* Pre initialize fixed WQE fields */
1561         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1562                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1563                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1564                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1565                 struct mlx5_wqe_data_seg *dseg;
1566
1567                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1568                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1569
1570                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1571                 dseg->lkey = sq->mkey_be;
1572         }
1573
1574         return 0;
1575
1576 err_free_xdpsq:
1577         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1578         mlx5e_free_xdpsq(sq);
1579
1580         return err;
1581 }
1582
1583 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1584 {
1585         struct mlx5e_channel *c = sq->channel;
1586
1587         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1588         napi_synchronize(&c->napi);
1589
1590         mlx5e_destroy_sq(c->mdev, sq->sqn);
1591         mlx5e_free_xdpsq_descs(sq);
1592         mlx5e_free_xdpsq(sq);
1593 }
1594
1595 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1596                                  struct mlx5e_cq_param *param,
1597                                  struct mlx5e_cq *cq)
1598 {
1599         struct mlx5_core_cq *mcq = &cq->mcq;
1600         int eqn_not_used;
1601         unsigned int irqn;
1602         int err;
1603         u32 i;
1604
1605         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1606                                &cq->wq_ctrl);
1607         if (err)
1608                 return err;
1609
1610         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1611
1612         mcq->cqe_sz     = 64;
1613         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1614         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1615         *mcq->set_ci_db = 0;
1616         *mcq->arm_db    = 0;
1617         mcq->vector     = param->eq_ix;
1618         mcq->comp       = mlx5e_completion_event;
1619         mcq->event      = mlx5e_cq_error_event;
1620         mcq->irqn       = irqn;
1621
1622         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1623                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1624
1625                 cqe->op_own = 0xf1;
1626         }
1627
1628         cq->mdev = mdev;
1629
1630         return 0;
1631 }
1632
1633 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1634                           struct mlx5e_cq_param *param,
1635                           struct mlx5e_cq *cq)
1636 {
1637         struct mlx5_core_dev *mdev = c->priv->mdev;
1638         int err;
1639
1640         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1641         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1642         param->eq_ix   = c->ix;
1643
1644         err = mlx5e_alloc_cq_common(mdev, param, cq);
1645
1646         cq->napi    = &c->napi;
1647         cq->channel = c;
1648
1649         return err;
1650 }
1651
1652 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1653 {
1654         mlx5_wq_destroy(&cq->wq_ctrl);
1655 }
1656
1657 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1658 {
1659         struct mlx5_core_dev *mdev = cq->mdev;
1660         struct mlx5_core_cq *mcq = &cq->mcq;
1661
1662         void *in;
1663         void *cqc;
1664         int inlen;
1665         unsigned int irqn_not_used;
1666         int eqn;
1667         int err;
1668
1669         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1670                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1671         in = kvzalloc(inlen, GFP_KERNEL);
1672         if (!in)
1673                 return -ENOMEM;
1674
1675         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1676
1677         memcpy(cqc, param->cqc, sizeof(param->cqc));
1678
1679         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1680                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1681
1682         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1683
1684         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1685         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1686         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1687         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1688                                             MLX5_ADAPTER_PAGE_SHIFT);
1689         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1690
1691         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1692
1693         kvfree(in);
1694
1695         if (err)
1696                 return err;
1697
1698         mlx5e_cq_arm(cq);
1699
1700         return 0;
1701 }
1702
1703 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1704 {
1705         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1706 }
1707
1708 static int mlx5e_open_cq(struct mlx5e_channel *c,
1709                          struct net_dim_cq_moder moder,
1710                          struct mlx5e_cq_param *param,
1711                          struct mlx5e_cq *cq)
1712 {
1713         struct mlx5_core_dev *mdev = c->mdev;
1714         int err;
1715
1716         err = mlx5e_alloc_cq(c, param, cq);
1717         if (err)
1718                 return err;
1719
1720         err = mlx5e_create_cq(cq, param);
1721         if (err)
1722                 goto err_free_cq;
1723
1724         if (MLX5_CAP_GEN(mdev, cq_moderation))
1725                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1726         return 0;
1727
1728 err_free_cq:
1729         mlx5e_free_cq(cq);
1730
1731         return err;
1732 }
1733
1734 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1735 {
1736         mlx5e_destroy_cq(cq);
1737         mlx5e_free_cq(cq);
1738 }
1739
1740 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1741 {
1742         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1743 }
1744
1745 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1746                              struct mlx5e_params *params,
1747                              struct mlx5e_channel_param *cparam)
1748 {
1749         int err;
1750         int tc;
1751
1752         for (tc = 0; tc < c->num_tc; tc++) {
1753                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1754                                     &cparam->tx_cq, &c->sq[tc].cq);
1755                 if (err)
1756                         goto err_close_tx_cqs;
1757         }
1758
1759         return 0;
1760
1761 err_close_tx_cqs:
1762         for (tc--; tc >= 0; tc--)
1763                 mlx5e_close_cq(&c->sq[tc].cq);
1764
1765         return err;
1766 }
1767
1768 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1769 {
1770         int tc;
1771
1772         for (tc = 0; tc < c->num_tc; tc++)
1773                 mlx5e_close_cq(&c->sq[tc].cq);
1774 }
1775
1776 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1777                           struct mlx5e_params *params,
1778                           struct mlx5e_channel_param *cparam)
1779 {
1780         struct mlx5e_priv *priv = c->priv;
1781         int err, tc, max_nch = priv->profile->max_nch(priv->mdev);
1782
1783         for (tc = 0; tc < params->num_tc; tc++) {
1784                 int txq_ix = c->ix + tc * max_nch;
1785
1786                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1787                                        params, &cparam->sq, &c->sq[tc], tc);
1788                 if (err)
1789                         goto err_close_sqs;
1790         }
1791
1792         return 0;
1793
1794 err_close_sqs:
1795         for (tc--; tc >= 0; tc--)
1796                 mlx5e_close_txqsq(&c->sq[tc]);
1797
1798         return err;
1799 }
1800
1801 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1802 {
1803         int tc;
1804
1805         for (tc = 0; tc < c->num_tc; tc++)
1806                 mlx5e_close_txqsq(&c->sq[tc]);
1807 }
1808
1809 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1810                                 struct mlx5e_txqsq *sq, u32 rate)
1811 {
1812         struct mlx5e_priv *priv = netdev_priv(dev);
1813         struct mlx5_core_dev *mdev = priv->mdev;
1814         struct mlx5e_modify_sq_param msp = {0};
1815         struct mlx5_rate_limit rl = {0};
1816         u16 rl_index = 0;
1817         int err;
1818
1819         if (rate == sq->rate_limit)
1820                 /* nothing to do */
1821                 return 0;
1822
1823         if (sq->rate_limit) {
1824                 rl.rate = sq->rate_limit;
1825                 /* remove current rl index to free space to next ones */
1826                 mlx5_rl_remove_rate(mdev, &rl);
1827         }
1828
1829         sq->rate_limit = 0;
1830
1831         if (rate) {
1832                 rl.rate = rate;
1833                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1834                 if (err) {
1835                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1836                                    rate, err);
1837                         return err;
1838                 }
1839         }
1840
1841         msp.curr_state = MLX5_SQC_STATE_RDY;
1842         msp.next_state = MLX5_SQC_STATE_RDY;
1843         msp.rl_index   = rl_index;
1844         msp.rl_update  = true;
1845         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1846         if (err) {
1847                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1848                            rate, err);
1849                 /* remove the rate from the table */
1850                 if (rate)
1851                         mlx5_rl_remove_rate(mdev, &rl);
1852                 return err;
1853         }
1854
1855         sq->rate_limit = rate;
1856         return 0;
1857 }
1858
1859 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1860 {
1861         struct mlx5e_priv *priv = netdev_priv(dev);
1862         struct mlx5_core_dev *mdev = priv->mdev;
1863         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1864         int err = 0;
1865
1866         if (!mlx5_rl_is_supported(mdev)) {
1867                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1868                 return -EINVAL;
1869         }
1870
1871         /* rate is given in Mb/sec, HW config is in Kb/sec */
1872         rate = rate << 10;
1873
1874         /* Check whether rate in valid range, 0 is always valid */
1875         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1876                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1877                 return -ERANGE;
1878         }
1879
1880         mutex_lock(&priv->state_lock);
1881         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1882                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1883         if (!err)
1884                 priv->tx_rates[index] = rate;
1885         mutex_unlock(&priv->state_lock);
1886
1887         return err;
1888 }
1889
1890 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1891                               struct mlx5e_params *params,
1892                               struct mlx5e_channel_param *cparam,
1893                               struct mlx5e_channel **cp)
1894 {
1895         struct net_dim_cq_moder icocq_moder = {0, 0};
1896         struct net_device *netdev = priv->netdev;
1897         int cpu = mlx5e_get_cpu(priv, ix);
1898         struct mlx5e_channel *c;
1899         unsigned int irq;
1900         int err;
1901         int eqn;
1902
1903         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1904         if (!c)
1905                 return -ENOMEM;
1906
1907         c->priv     = priv;
1908         c->mdev     = priv->mdev;
1909         c->tstamp   = &priv->tstamp;
1910         c->ix       = ix;
1911         c->cpu      = cpu;
1912         c->pdev     = &priv->mdev->pdev->dev;
1913         c->netdev   = priv->netdev;
1914         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1915         c->num_tc   = params->num_tc;
1916         c->xdp      = !!params->xdp_prog;
1917         c->stats    = &priv->channel_stats[ix].ch;
1918
1919         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1920         c->irq_desc = irq_to_desc(irq);
1921
1922         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1923
1924         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1925         if (err)
1926                 goto err_napi_del;
1927
1928         err = mlx5e_open_tx_cqs(c, params, cparam);
1929         if (err)
1930                 goto err_close_icosq_cq;
1931
1932         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1933         if (err)
1934                 goto err_close_tx_cqs;
1935
1936         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1937         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1938                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1939         if (err)
1940                 goto err_close_rx_cq;
1941
1942         napi_enable(&c->napi);
1943
1944         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1945         if (err)
1946                 goto err_disable_napi;
1947
1948         err = mlx5e_open_sqs(c, params, cparam);
1949         if (err)
1950                 goto err_close_icosq;
1951
1952         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1953         if (err)
1954                 goto err_close_sqs;
1955
1956         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1957         if (err)
1958                 goto err_close_xdp_sq;
1959
1960         *cp = c;
1961
1962         return 0;
1963 err_close_xdp_sq:
1964         if (c->xdp)
1965                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1966
1967 err_close_sqs:
1968         mlx5e_close_sqs(c);
1969
1970 err_close_icosq:
1971         mlx5e_close_icosq(&c->icosq);
1972
1973 err_disable_napi:
1974         napi_disable(&c->napi);
1975         if (c->xdp)
1976                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1977
1978 err_close_rx_cq:
1979         mlx5e_close_cq(&c->rq.cq);
1980
1981 err_close_tx_cqs:
1982         mlx5e_close_tx_cqs(c);
1983
1984 err_close_icosq_cq:
1985         mlx5e_close_cq(&c->icosq.cq);
1986
1987 err_napi_del:
1988         netif_napi_del(&c->napi);
1989         kvfree(c);
1990
1991         return err;
1992 }
1993
1994 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1995 {
1996         int tc;
1997
1998         for (tc = 0; tc < c->num_tc; tc++)
1999                 mlx5e_activate_txqsq(&c->sq[tc]);
2000         mlx5e_activate_rq(&c->rq);
2001         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
2002 }
2003
2004 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2005 {
2006         int tc;
2007
2008         mlx5e_deactivate_rq(&c->rq);
2009         for (tc = 0; tc < c->num_tc; tc++)
2010                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2011 }
2012
2013 static void mlx5e_close_channel(struct mlx5e_channel *c)
2014 {
2015         mlx5e_close_rq(&c->rq);
2016         if (c->xdp)
2017                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2018         mlx5e_close_sqs(c);
2019         mlx5e_close_icosq(&c->icosq);
2020         napi_disable(&c->napi);
2021         if (c->xdp)
2022                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2023         mlx5e_close_cq(&c->rq.cq);
2024         mlx5e_close_tx_cqs(c);
2025         mlx5e_close_cq(&c->icosq.cq);
2026         netif_napi_del(&c->napi);
2027
2028         kvfree(c);
2029 }
2030
2031 #define DEFAULT_FRAG_SIZE (2048)
2032
2033 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2034                                       struct mlx5e_params *params,
2035                                       struct mlx5e_rq_frags_info *info)
2036 {
2037         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2038         int frag_size_max = DEFAULT_FRAG_SIZE;
2039         u32 buf_size = 0;
2040         int i;
2041
2042 #ifdef CONFIG_MLX5_EN_IPSEC
2043         if (MLX5_IPSEC_DEV(mdev))
2044                 byte_count += MLX5E_METADATA_ETHER_LEN;
2045 #endif
2046
2047         if (mlx5e_rx_is_linear_skb(mdev, params)) {
2048                 int frag_stride;
2049
2050                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2051                 frag_stride = roundup_pow_of_two(frag_stride);
2052
2053                 info->arr[0].frag_size = byte_count;
2054                 info->arr[0].frag_stride = frag_stride;
2055                 info->num_frags = 1;
2056                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2057                 goto out;
2058         }
2059
2060         if (byte_count > PAGE_SIZE +
2061             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2062                 frag_size_max = PAGE_SIZE;
2063
2064         i = 0;
2065         while (buf_size < byte_count) {
2066                 int frag_size = byte_count - buf_size;
2067
2068                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2069                         frag_size = min(frag_size, frag_size_max);
2070
2071                 info->arr[i].frag_size = frag_size;
2072                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2073
2074                 buf_size += frag_size;
2075                 i++;
2076         }
2077         info->num_frags = i;
2078         /* number of different wqes sharing a page */
2079         info->wqe_bulk = 1 + (info->num_frags % 2);
2080
2081 out:
2082         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2083         info->log_num_frags = order_base_2(info->num_frags);
2084 }
2085
2086 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2087 {
2088         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2089
2090         switch (wq_type) {
2091         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2092                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2093                 break;
2094         default: /* MLX5_WQ_TYPE_CYCLIC */
2095                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2096         }
2097
2098         return order_base_2(sz);
2099 }
2100
2101 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2102                                  struct mlx5e_params *params,
2103                                  struct mlx5e_rq_param *param)
2104 {
2105         struct mlx5_core_dev *mdev = priv->mdev;
2106         void *rqc = param->rqc;
2107         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2108         int ndsegs = 1;
2109
2110         switch (params->rq_wq_type) {
2111         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2112                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2113                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2114                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2115                 MLX5_SET(wq, wq, log_wqe_stride_size,
2116                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2117                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2118                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2119                 break;
2120         default: /* MLX5_WQ_TYPE_CYCLIC */
2121                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2122                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2123                 ndsegs = param->frags_info.num_frags;
2124         }
2125
2126         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2127         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2128         MLX5_SET(wq, wq, log_wq_stride,
2129                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2130         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2131         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2132         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2133         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2134
2135         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2136 }
2137
2138 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2139                                       struct mlx5e_rq_param *param)
2140 {
2141         struct mlx5_core_dev *mdev = priv->mdev;
2142         void *rqc = param->rqc;
2143         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2144
2145         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2146         MLX5_SET(wq, wq, log_wq_stride,
2147                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2148         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2149
2150         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2151 }
2152
2153 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2154                                         struct mlx5e_sq_param *param)
2155 {
2156         void *sqc = param->sqc;
2157         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2158
2159         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2160         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2161
2162         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2163 }
2164
2165 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2166                                  struct mlx5e_params *params,
2167                                  struct mlx5e_sq_param *param)
2168 {
2169         void *sqc = param->sqc;
2170         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2171
2172         mlx5e_build_sq_param_common(priv, param);
2173         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2174         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2175 }
2176
2177 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2178                                         struct mlx5e_cq_param *param)
2179 {
2180         void *cqc = param->cqc;
2181
2182         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2183 }
2184
2185 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2186                                     struct mlx5e_params *params,
2187                                     struct mlx5e_cq_param *param)
2188 {
2189         struct mlx5_core_dev *mdev = priv->mdev;
2190         void *cqc = param->cqc;
2191         u8 log_cq_size;
2192
2193         switch (params->rq_wq_type) {
2194         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2195                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2196                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2197                 break;
2198         default: /* MLX5_WQ_TYPE_CYCLIC */
2199                 log_cq_size = params->log_rq_mtu_frames;
2200         }
2201
2202         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2203         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2204                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2205                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2206         }
2207
2208         mlx5e_build_common_cq_param(priv, param);
2209         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2210 }
2211
2212 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2213                                     struct mlx5e_params *params,
2214                                     struct mlx5e_cq_param *param)
2215 {
2216         void *cqc = param->cqc;
2217
2218         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2219
2220         mlx5e_build_common_cq_param(priv, param);
2221         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2222 }
2223
2224 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2225                                      u8 log_wq_size,
2226                                      struct mlx5e_cq_param *param)
2227 {
2228         void *cqc = param->cqc;
2229
2230         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2231
2232         mlx5e_build_common_cq_param(priv, param);
2233
2234         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2235 }
2236
2237 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2238                                     u8 log_wq_size,
2239                                     struct mlx5e_sq_param *param)
2240 {
2241         void *sqc = param->sqc;
2242         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2243
2244         mlx5e_build_sq_param_common(priv, param);
2245
2246         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2247         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2248 }
2249
2250 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2251                                     struct mlx5e_params *params,
2252                                     struct mlx5e_sq_param *param)
2253 {
2254         void *sqc = param->sqc;
2255         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2256
2257         mlx5e_build_sq_param_common(priv, param);
2258         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2259 }
2260
2261 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2262                                       struct mlx5e_params *params,
2263                                       struct mlx5e_channel_param *cparam)
2264 {
2265         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2266
2267         mlx5e_build_rq_param(priv, params, &cparam->rq);
2268         mlx5e_build_sq_param(priv, params, &cparam->sq);
2269         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2270         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2271         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2272         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2273         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2274 }
2275
2276 int mlx5e_open_channels(struct mlx5e_priv *priv,
2277                         struct mlx5e_channels *chs)
2278 {
2279         struct mlx5e_channel_param *cparam;
2280         int err = -ENOMEM;
2281         int i;
2282
2283         chs->num = chs->params.num_channels;
2284
2285         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2286         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2287         if (!chs->c || !cparam)
2288                 goto err_free;
2289
2290         mlx5e_build_channel_param(priv, &chs->params, cparam);
2291         for (i = 0; i < chs->num; i++) {
2292                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2293                 if (err)
2294                         goto err_close_channels;
2295         }
2296
2297         kvfree(cparam);
2298         return 0;
2299
2300 err_close_channels:
2301         for (i--; i >= 0; i--)
2302                 mlx5e_close_channel(chs->c[i]);
2303
2304 err_free:
2305         kfree(chs->c);
2306         kvfree(cparam);
2307         chs->num = 0;
2308         return err;
2309 }
2310
2311 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2312 {
2313         int i;
2314
2315         for (i = 0; i < chs->num; i++)
2316                 mlx5e_activate_channel(chs->c[i]);
2317 }
2318
2319 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2320 {
2321         int err = 0;
2322         int i;
2323
2324         for (i = 0; i < chs->num; i++)
2325                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2326                                                   err ? 0 : 20000);
2327
2328         return err ? -ETIMEDOUT : 0;
2329 }
2330
2331 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2332 {
2333         int i;
2334
2335         for (i = 0; i < chs->num; i++)
2336                 mlx5e_deactivate_channel(chs->c[i]);
2337 }
2338
2339 void mlx5e_close_channels(struct mlx5e_channels *chs)
2340 {
2341         int i;
2342
2343         for (i = 0; i < chs->num; i++)
2344                 mlx5e_close_channel(chs->c[i]);
2345
2346         kfree(chs->c);
2347         chs->num = 0;
2348 }
2349
2350 static int
2351 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2352 {
2353         struct mlx5_core_dev *mdev = priv->mdev;
2354         void *rqtc;
2355         int inlen;
2356         int err;
2357         u32 *in;
2358         int i;
2359
2360         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2361         in = kvzalloc(inlen, GFP_KERNEL);
2362         if (!in)
2363                 return -ENOMEM;
2364
2365         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2366
2367         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2368         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2369
2370         for (i = 0; i < sz; i++)
2371                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2372
2373         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2374         if (!err)
2375                 rqt->enabled = true;
2376
2377         kvfree(in);
2378         return err;
2379 }
2380
2381 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2382 {
2383         rqt->enabled = false;
2384         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2385 }
2386
2387 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2388 {
2389         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2390         int err;
2391
2392         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2393         if (err)
2394                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2395         return err;
2396 }
2397
2398 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2399 {
2400         struct mlx5e_rqt *rqt;
2401         int err;
2402         int ix;
2403
2404         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2405                 rqt = &priv->direct_tir[ix].rqt;
2406                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2407                 if (err)
2408                         goto err_destroy_rqts;
2409         }
2410
2411         return 0;
2412
2413 err_destroy_rqts:
2414         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2415         for (ix--; ix >= 0; ix--)
2416                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2417
2418         return err;
2419 }
2420
2421 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2422 {
2423         int i;
2424
2425         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2426                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2427 }
2428
2429 static int mlx5e_rx_hash_fn(int hfunc)
2430 {
2431         return (hfunc == ETH_RSS_HASH_TOP) ?
2432                MLX5_RX_HASH_FN_TOEPLITZ :
2433                MLX5_RX_HASH_FN_INVERTED_XOR8;
2434 }
2435
2436 int mlx5e_bits_invert(unsigned long a, int size)
2437 {
2438         int inv = 0;
2439         int i;
2440
2441         for (i = 0; i < size; i++)
2442                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2443
2444         return inv;
2445 }
2446
2447 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2448                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2449 {
2450         int i;
2451
2452         for (i = 0; i < sz; i++) {
2453                 u32 rqn;
2454
2455                 if (rrp.is_rss) {
2456                         int ix = i;
2457
2458                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2459                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2460
2461                         ix = priv->channels.params.indirection_rqt[ix];
2462                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2463                 } else {
2464                         rqn = rrp.rqn;
2465                 }
2466                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2467         }
2468 }
2469
2470 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2471                        struct mlx5e_redirect_rqt_param rrp)
2472 {
2473         struct mlx5_core_dev *mdev = priv->mdev;
2474         void *rqtc;
2475         int inlen;
2476         u32 *in;
2477         int err;
2478
2479         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2480         in = kvzalloc(inlen, GFP_KERNEL);
2481         if (!in)
2482                 return -ENOMEM;
2483
2484         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2485
2486         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2487         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2488         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2489         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2490
2491         kvfree(in);
2492         return err;
2493 }
2494
2495 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2496                                 struct mlx5e_redirect_rqt_param rrp)
2497 {
2498         if (!rrp.is_rss)
2499                 return rrp.rqn;
2500
2501         if (ix >= rrp.rss.channels->num)
2502                 return priv->drop_rq.rqn;
2503
2504         return rrp.rss.channels->c[ix]->rq.rqn;
2505 }
2506
2507 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2508                                 struct mlx5e_redirect_rqt_param rrp)
2509 {
2510         u32 rqtn;
2511         int ix;
2512
2513         if (priv->indir_rqt.enabled) {
2514                 /* RSS RQ table */
2515                 rqtn = priv->indir_rqt.rqtn;
2516                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2517         }
2518
2519         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2520                 struct mlx5e_redirect_rqt_param direct_rrp = {
2521                         .is_rss = false,
2522                         {
2523                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2524                         },
2525                 };
2526
2527                 /* Direct RQ Tables */
2528                 if (!priv->direct_tir[ix].rqt.enabled)
2529                         continue;
2530
2531                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2532                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2533         }
2534 }
2535
2536 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2537                                             struct mlx5e_channels *chs)
2538 {
2539         struct mlx5e_redirect_rqt_param rrp = {
2540                 .is_rss        = true,
2541                 {
2542                         .rss = {
2543                                 .channels  = chs,
2544                                 .hfunc     = chs->params.rss_hfunc,
2545                         }
2546                 },
2547         };
2548
2549         mlx5e_redirect_rqts(priv, rrp);
2550 }
2551
2552 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2553 {
2554         struct mlx5e_redirect_rqt_param drop_rrp = {
2555                 .is_rss = false,
2556                 {
2557                         .rqn = priv->drop_rq.rqn,
2558                 },
2559         };
2560
2561         mlx5e_redirect_rqts(priv, drop_rrp);
2562 }
2563
2564 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2565 {
2566         if (!params->lro_en)
2567                 return;
2568
2569 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2570
2571         MLX5_SET(tirc, tirc, lro_enable_mask,
2572                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2573                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2574         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2575                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2576         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2577 }
2578
2579 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2580                                     enum mlx5e_traffic_types tt,
2581                                     void *tirc, bool inner)
2582 {
2583         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2584                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2585
2586 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2587                                  MLX5_HASH_FIELD_SEL_DST_IP)
2588
2589 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2590                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2591                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2592                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2593
2594 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2595                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2596                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2597
2598         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2599         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2600                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2601                                              rx_hash_toeplitz_key);
2602                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2603                                                rx_hash_toeplitz_key);
2604
2605                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2606                 memcpy(rss_key, params->toeplitz_hash_key, len);
2607         }
2608
2609         switch (tt) {
2610         case MLX5E_TT_IPV4_TCP:
2611                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2612                          MLX5_L3_PROT_TYPE_IPV4);
2613                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2614                          MLX5_L4_PROT_TYPE_TCP);
2615                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2616                          MLX5_HASH_IP_L4PORTS);
2617                 break;
2618
2619         case MLX5E_TT_IPV6_TCP:
2620                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2621                          MLX5_L3_PROT_TYPE_IPV6);
2622                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2623                          MLX5_L4_PROT_TYPE_TCP);
2624                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2625                          MLX5_HASH_IP_L4PORTS);
2626                 break;
2627
2628         case MLX5E_TT_IPV4_UDP:
2629                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2630                          MLX5_L3_PROT_TYPE_IPV4);
2631                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2632                          MLX5_L4_PROT_TYPE_UDP);
2633                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2634                          MLX5_HASH_IP_L4PORTS);
2635                 break;
2636
2637         case MLX5E_TT_IPV6_UDP:
2638                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2639                          MLX5_L3_PROT_TYPE_IPV6);
2640                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2641                          MLX5_L4_PROT_TYPE_UDP);
2642                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2643                          MLX5_HASH_IP_L4PORTS);
2644                 break;
2645
2646         case MLX5E_TT_IPV4_IPSEC_AH:
2647                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2648                          MLX5_L3_PROT_TYPE_IPV4);
2649                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2650                          MLX5_HASH_IP_IPSEC_SPI);
2651                 break;
2652
2653         case MLX5E_TT_IPV6_IPSEC_AH:
2654                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2655                          MLX5_L3_PROT_TYPE_IPV6);
2656                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2657                          MLX5_HASH_IP_IPSEC_SPI);
2658                 break;
2659
2660         case MLX5E_TT_IPV4_IPSEC_ESP:
2661                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2662                          MLX5_L3_PROT_TYPE_IPV4);
2663                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2664                          MLX5_HASH_IP_IPSEC_SPI);
2665                 break;
2666
2667         case MLX5E_TT_IPV6_IPSEC_ESP:
2668                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2669                          MLX5_L3_PROT_TYPE_IPV6);
2670                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2671                          MLX5_HASH_IP_IPSEC_SPI);
2672                 break;
2673
2674         case MLX5E_TT_IPV4:
2675                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2676                          MLX5_L3_PROT_TYPE_IPV4);
2677                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2678                          MLX5_HASH_IP);
2679                 break;
2680
2681         case MLX5E_TT_IPV6:
2682                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2683                          MLX5_L3_PROT_TYPE_IPV6);
2684                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2685                          MLX5_HASH_IP);
2686                 break;
2687         default:
2688                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2689         }
2690 }
2691
2692 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2693 {
2694         struct mlx5_core_dev *mdev = priv->mdev;
2695
2696         void *in;
2697         void *tirc;
2698         int inlen;
2699         int err;
2700         int tt;
2701         int ix;
2702
2703         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2704         in = kvzalloc(inlen, GFP_KERNEL);
2705         if (!in)
2706                 return -ENOMEM;
2707
2708         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2709         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2710
2711         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2712
2713         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2714                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2715                                            inlen);
2716                 if (err)
2717                         goto free_in;
2718         }
2719
2720         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2721                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2722                                            in, inlen);
2723                 if (err)
2724                         goto free_in;
2725         }
2726
2727 free_in:
2728         kvfree(in);
2729
2730         return err;
2731 }
2732
2733 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2734                                             enum mlx5e_traffic_types tt,
2735                                             u32 *tirc)
2736 {
2737         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2738
2739         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2740
2741         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2742         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2743         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2744
2745         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2746 }
2747
2748 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2749                          struct mlx5e_params *params, u16 mtu)
2750 {
2751         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2752         int err;
2753
2754         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2755         if (err)
2756                 return err;
2757
2758         /* Update vport context MTU */
2759         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2760         return 0;
2761 }
2762
2763 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2764                             struct mlx5e_params *params, u16 *mtu)
2765 {
2766         u16 hw_mtu = 0;
2767         int err;
2768
2769         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2770         if (err || !hw_mtu) /* fallback to port oper mtu */
2771                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2772
2773         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2774 }
2775
2776 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2777 {
2778         struct mlx5e_params *params = &priv->channels.params;
2779         struct net_device *netdev = priv->netdev;
2780         struct mlx5_core_dev *mdev = priv->mdev;
2781         u16 mtu;
2782         int err;
2783
2784         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2785         if (err)
2786                 return err;
2787
2788         mlx5e_query_mtu(mdev, params, &mtu);
2789         if (mtu != params->sw_mtu)
2790                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2791                             __func__, mtu, params->sw_mtu);
2792
2793         params->sw_mtu = mtu;
2794         return 0;
2795 }
2796
2797 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2798 {
2799         struct mlx5e_priv *priv = netdev_priv(netdev);
2800         int nch = priv->channels.params.num_channels;
2801         int ntc = priv->channels.params.num_tc;
2802         int tc;
2803
2804         netdev_reset_tc(netdev);
2805
2806         if (ntc == 1)
2807                 return;
2808
2809         netdev_set_num_tc(netdev, ntc);
2810
2811         /* Map netdev TCs to offset 0
2812          * We have our own UP to TXQ mapping for QoS
2813          */
2814         for (tc = 0; tc < ntc; tc++)
2815                 netdev_set_tc_queue(netdev, tc, nch, 0);
2816 }
2817
2818 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2819 {
2820         int max_nch = priv->profile->max_nch(priv->mdev);
2821         int i, tc;
2822
2823         for (i = 0; i < max_nch; i++)
2824                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2825                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2826 }
2827
2828 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2829 {
2830         struct mlx5e_channel *c;
2831         struct mlx5e_txqsq *sq;
2832         int i, tc;
2833
2834         for (i = 0; i < priv->channels.num; i++) {
2835                 c = priv->channels.c[i];
2836                 for (tc = 0; tc < c->num_tc; tc++) {
2837                         sq = &c->sq[tc];
2838                         priv->txq2sq[sq->txq_ix] = sq;
2839                 }
2840         }
2841 }
2842
2843 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2844 {
2845         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2846         struct net_device *netdev = priv->netdev;
2847
2848         mlx5e_netdev_set_tcs(netdev);
2849         netif_set_real_num_tx_queues(netdev, num_txqs);
2850         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2851
2852         mlx5e_build_tx2sq_maps(priv);
2853         mlx5e_activate_channels(&priv->channels);
2854         netif_tx_start_all_queues(priv->netdev);
2855
2856         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2857                 mlx5e_add_sqs_fwd_rules(priv);
2858
2859         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2860         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2861 }
2862
2863 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2864 {
2865         mlx5e_redirect_rqts_to_drop(priv);
2866
2867         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2868                 mlx5e_remove_sqs_fwd_rules(priv);
2869
2870         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2871          * polling for inactive tx queues.
2872          */
2873         netif_tx_stop_all_queues(priv->netdev);
2874         netif_tx_disable(priv->netdev);
2875         mlx5e_deactivate_channels(&priv->channels);
2876 }
2877
2878 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2879                                 struct mlx5e_channels *new_chs,
2880                                 mlx5e_fp_hw_modify hw_modify)
2881 {
2882         struct net_device *netdev = priv->netdev;
2883         int new_num_txqs;
2884         int carrier_ok;
2885         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2886
2887         carrier_ok = netif_carrier_ok(netdev);
2888         netif_carrier_off(netdev);
2889
2890         if (new_num_txqs < netdev->real_num_tx_queues)
2891                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2892
2893         mlx5e_deactivate_priv_channels(priv);
2894         mlx5e_close_channels(&priv->channels);
2895
2896         priv->channels = *new_chs;
2897
2898         /* New channels are ready to roll, modify HW settings if needed */
2899         if (hw_modify)
2900                 hw_modify(priv);
2901
2902         mlx5e_refresh_tirs(priv, false);
2903         mlx5e_activate_priv_channels(priv);
2904
2905         /* return carrier back if needed */
2906         if (carrier_ok)
2907                 netif_carrier_on(netdev);
2908 }
2909
2910 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2911 {
2912         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2913         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2914 }
2915
2916 int mlx5e_open_locked(struct net_device *netdev)
2917 {
2918         struct mlx5e_priv *priv = netdev_priv(netdev);
2919         int err;
2920
2921         set_bit(MLX5E_STATE_OPENED, &priv->state);
2922
2923         err = mlx5e_open_channels(priv, &priv->channels);
2924         if (err)
2925                 goto err_clear_state_opened_flag;
2926
2927         mlx5e_refresh_tirs(priv, false);
2928         mlx5e_activate_priv_channels(priv);
2929         if (priv->profile->update_carrier)
2930                 priv->profile->update_carrier(priv);
2931
2932         if (priv->profile->update_stats)
2933                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2934
2935         return 0;
2936
2937 err_clear_state_opened_flag:
2938         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2939         return err;
2940 }
2941
2942 int mlx5e_open(struct net_device *netdev)
2943 {
2944         struct mlx5e_priv *priv = netdev_priv(netdev);
2945         int err;
2946
2947         mutex_lock(&priv->state_lock);
2948         err = mlx5e_open_locked(netdev);
2949         if (!err)
2950                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2951         mutex_unlock(&priv->state_lock);
2952
2953         if (mlx5e_vxlan_allowed(priv->mdev))
2954                 udp_tunnel_get_rx_info(netdev);
2955
2956         return err;
2957 }
2958
2959 int mlx5e_close_locked(struct net_device *netdev)
2960 {
2961         struct mlx5e_priv *priv = netdev_priv(netdev);
2962
2963         /* May already be CLOSED in case a previous configuration operation
2964          * (e.g RX/TX queue size change) that involves close&open failed.
2965          */
2966         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2967                 return 0;
2968
2969         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2970
2971         netif_carrier_off(priv->netdev);
2972         mlx5e_deactivate_priv_channels(priv);
2973         mlx5e_close_channels(&priv->channels);
2974
2975         return 0;
2976 }
2977
2978 int mlx5e_close(struct net_device *netdev)
2979 {
2980         struct mlx5e_priv *priv = netdev_priv(netdev);
2981         int err;
2982
2983         if (!netif_device_present(netdev))
2984                 return -ENODEV;
2985
2986         mutex_lock(&priv->state_lock);
2987         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2988         err = mlx5e_close_locked(netdev);
2989         mutex_unlock(&priv->state_lock);
2990
2991         return err;
2992 }
2993
2994 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2995                                struct mlx5e_rq *rq,
2996                                struct mlx5e_rq_param *param)
2997 {
2998         void *rqc = param->rqc;
2999         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3000         int err;
3001
3002         param->wq.db_numa_node = param->wq.buf_numa_node;
3003
3004         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3005                                  &rq->wq_ctrl);
3006         if (err)
3007                 return err;
3008
3009         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3010         xdp_rxq_info_unused(&rq->xdp_rxq);
3011
3012         rq->mdev = mdev;
3013
3014         return 0;
3015 }
3016
3017 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3018                                struct mlx5e_cq *cq,
3019                                struct mlx5e_cq_param *param)
3020 {
3021         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3022         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
3023
3024         return mlx5e_alloc_cq_common(mdev, param, cq);
3025 }
3026
3027 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3028                               struct mlx5e_rq *drop_rq)
3029 {
3030         struct mlx5_core_dev *mdev = priv->mdev;
3031         struct mlx5e_cq_param cq_param = {};
3032         struct mlx5e_rq_param rq_param = {};
3033         struct mlx5e_cq *cq = &drop_rq->cq;
3034         int err;
3035
3036         mlx5e_build_drop_rq_param(priv, &rq_param);
3037
3038         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3039         if (err)
3040                 return err;
3041
3042         err = mlx5e_create_cq(cq, &cq_param);
3043         if (err)
3044                 goto err_free_cq;
3045
3046         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3047         if (err)
3048                 goto err_destroy_cq;
3049
3050         err = mlx5e_create_rq(drop_rq, &rq_param);
3051         if (err)
3052                 goto err_free_rq;
3053
3054         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3055         if (err)
3056                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3057
3058         return 0;
3059
3060 err_free_rq:
3061         mlx5e_free_rq(drop_rq);
3062
3063 err_destroy_cq:
3064         mlx5e_destroy_cq(cq);
3065
3066 err_free_cq:
3067         mlx5e_free_cq(cq);
3068
3069         return err;
3070 }
3071
3072 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3073 {
3074         mlx5e_destroy_rq(drop_rq);
3075         mlx5e_free_rq(drop_rq);
3076         mlx5e_destroy_cq(&drop_rq->cq);
3077         mlx5e_free_cq(&drop_rq->cq);
3078 }
3079
3080 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3081                      u32 underlay_qpn, u32 *tisn)
3082 {
3083         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3084         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3085
3086         MLX5_SET(tisc, tisc, prio, tc << 1);
3087         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3088         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3089
3090         if (mlx5_lag_is_lacp_owner(mdev))
3091                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3092
3093         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3094 }
3095
3096 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3097 {
3098         mlx5_core_destroy_tis(mdev, tisn);
3099 }
3100
3101 int mlx5e_create_tises(struct mlx5e_priv *priv)
3102 {
3103         int err;
3104         int tc;
3105
3106         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3107                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3108                 if (err)
3109                         goto err_close_tises;
3110         }
3111
3112         return 0;
3113
3114 err_close_tises:
3115         for (tc--; tc >= 0; tc--)
3116                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3117
3118         return err;
3119 }
3120
3121 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3122 {
3123         int tc;
3124
3125         for (tc = 0; tc < priv->profile->max_tc; tc++)
3126                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3127 }
3128
3129 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3130                                       enum mlx5e_traffic_types tt,
3131                                       u32 *tirc)
3132 {
3133         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3134
3135         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3136
3137         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3138         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3139         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
3140 }
3141
3142 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3143 {
3144         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3145
3146         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3147
3148         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3149         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3150         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3151 }
3152
3153 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
3154 {
3155         struct mlx5e_tir *tir;
3156         void *tirc;
3157         int inlen;
3158         int i = 0;
3159         int err;
3160         u32 *in;
3161         int tt;
3162
3163         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3164         in = kvzalloc(inlen, GFP_KERNEL);
3165         if (!in)
3166                 return -ENOMEM;
3167
3168         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3169                 memset(in, 0, inlen);
3170                 tir = &priv->indir_tir[tt];
3171                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3172                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3173                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3174                 if (err) {
3175                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3176                         goto err_destroy_inner_tirs;
3177                 }
3178         }
3179
3180         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3181                 goto out;
3182
3183         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3184                 memset(in, 0, inlen);
3185                 tir = &priv->inner_indir_tir[i];
3186                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3187                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3188                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3189                 if (err) {
3190                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3191                         goto err_destroy_inner_tirs;
3192                 }
3193         }
3194
3195 out:
3196         kvfree(in);
3197
3198         return 0;
3199
3200 err_destroy_inner_tirs:
3201         for (i--; i >= 0; i--)
3202                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3203
3204         for (tt--; tt >= 0; tt--)
3205                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3206
3207         kvfree(in);
3208
3209         return err;
3210 }
3211
3212 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3213 {
3214         int nch = priv->profile->max_nch(priv->mdev);
3215         struct mlx5e_tir *tir;
3216         void *tirc;
3217         int inlen;
3218         int err;
3219         u32 *in;
3220         int ix;
3221
3222         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3223         in = kvzalloc(inlen, GFP_KERNEL);
3224         if (!in)
3225                 return -ENOMEM;
3226
3227         for (ix = 0; ix < nch; ix++) {
3228                 memset(in, 0, inlen);
3229                 tir = &priv->direct_tir[ix];
3230                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3231                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3232                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3233                 if (err)
3234                         goto err_destroy_ch_tirs;
3235         }
3236
3237         kvfree(in);
3238
3239         return 0;
3240
3241 err_destroy_ch_tirs:
3242         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3243         for (ix--; ix >= 0; ix--)
3244                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3245
3246         kvfree(in);
3247
3248         return err;
3249 }
3250
3251 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3252 {
3253         int i;
3254
3255         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3256                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3257
3258         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3259                 return;
3260
3261         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3262                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3263 }
3264
3265 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3266 {
3267         int nch = priv->profile->max_nch(priv->mdev);
3268         int i;
3269
3270         for (i = 0; i < nch; i++)
3271                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3272 }
3273
3274 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3275 {
3276         int err = 0;
3277         int i;
3278
3279         for (i = 0; i < chs->num; i++) {
3280                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3281                 if (err)
3282                         return err;
3283         }
3284
3285         return 0;
3286 }
3287
3288 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3289 {
3290         int err = 0;
3291         int i;
3292
3293         for (i = 0; i < chs->num; i++) {
3294                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3295                 if (err)
3296                         return err;
3297         }
3298
3299         return 0;
3300 }
3301
3302 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3303                                  struct tc_mqprio_qopt *mqprio)
3304 {
3305         struct mlx5e_priv *priv = netdev_priv(netdev);
3306         struct mlx5e_channels new_channels = {};
3307         u8 tc = mqprio->num_tc;
3308         int err = 0;
3309
3310         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3311
3312         if (tc && tc != MLX5E_MAX_NUM_TC)
3313                 return -EINVAL;
3314
3315         mutex_lock(&priv->state_lock);
3316
3317         new_channels.params = priv->channels.params;
3318         new_channels.params.num_tc = tc ? tc : 1;
3319
3320         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3321                 priv->channels.params = new_channels.params;
3322                 goto out;
3323         }
3324
3325         err = mlx5e_open_channels(priv, &new_channels);
3326         if (err)
3327                 goto out;
3328
3329         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3330                                     new_channels.params.num_tc);
3331         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3332 out:
3333         mutex_unlock(&priv->state_lock);
3334         return err;
3335 }
3336
3337 #ifdef CONFIG_MLX5_ESWITCH
3338 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3339                                      struct tc_cls_flower_offload *cls_flower,
3340                                      int flags)
3341 {
3342         switch (cls_flower->command) {
3343         case TC_CLSFLOWER_REPLACE:
3344                 return mlx5e_configure_flower(priv, cls_flower, flags);
3345         case TC_CLSFLOWER_DESTROY:
3346                 return mlx5e_delete_flower(priv, cls_flower, flags);
3347         case TC_CLSFLOWER_STATS:
3348                 return mlx5e_stats_flower(priv, cls_flower, flags);
3349         default:
3350                 return -EOPNOTSUPP;
3351         }
3352 }
3353
3354 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3355                                    void *cb_priv)
3356 {
3357         struct mlx5e_priv *priv = cb_priv;
3358
3359         if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3360                 return -EOPNOTSUPP;
3361
3362         switch (type) {
3363         case TC_SETUP_CLSFLOWER:
3364                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS);
3365         default:
3366                 return -EOPNOTSUPP;
3367         }
3368 }
3369
3370 static int mlx5e_setup_tc_block(struct net_device *dev,
3371                                 struct tc_block_offload *f)
3372 {
3373         struct mlx5e_priv *priv = netdev_priv(dev);
3374
3375         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3376                 return -EOPNOTSUPP;
3377
3378         switch (f->command) {
3379         case TC_BLOCK_BIND:
3380                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3381                                              priv, priv, f->extack);
3382         case TC_BLOCK_UNBIND:
3383                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3384                                         priv);
3385                 return 0;
3386         default:
3387                 return -EOPNOTSUPP;
3388         }
3389 }
3390 #endif
3391
3392 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3393                           void *type_data)
3394 {
3395         switch (type) {
3396 #ifdef CONFIG_MLX5_ESWITCH
3397         case TC_SETUP_BLOCK:
3398                 return mlx5e_setup_tc_block(dev, type_data);
3399 #endif
3400         case TC_SETUP_QDISC_MQPRIO:
3401                 return mlx5e_setup_tc_mqprio(dev, type_data);
3402         default:
3403                 return -EOPNOTSUPP;
3404         }
3405 }
3406
3407 static void
3408 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3409 {
3410         struct mlx5e_priv *priv = netdev_priv(dev);
3411         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3412         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3413         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3414
3415         /* update HW stats in background for next time */
3416         queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
3417
3418         if (mlx5e_is_uplink_rep(priv)) {
3419                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3420                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3421                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3422                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3423         } else {
3424                 mlx5e_grp_sw_update_stats(priv);
3425                 stats->rx_packets = sstats->rx_packets;
3426                 stats->rx_bytes   = sstats->rx_bytes;
3427                 stats->tx_packets = sstats->tx_packets;
3428                 stats->tx_bytes   = sstats->tx_bytes;
3429                 stats->tx_dropped = sstats->tx_queue_dropped;
3430         }
3431
3432         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3433
3434         stats->rx_length_errors =
3435                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3436                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3437                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3438         stats->rx_crc_errors =
3439                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3440         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3441         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3442         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3443                            stats->rx_frame_errors;
3444         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3445
3446         /* vport multicast also counts packets that are dropped due to steering
3447          * or rx out of buffer
3448          */
3449         stats->multicast =
3450                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3451 }
3452
3453 static void mlx5e_set_rx_mode(struct net_device *dev)
3454 {
3455         struct mlx5e_priv *priv = netdev_priv(dev);
3456
3457         queue_work(priv->wq, &priv->set_rx_mode_work);
3458 }
3459
3460 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3461 {
3462         struct mlx5e_priv *priv = netdev_priv(netdev);
3463         struct sockaddr *saddr = addr;
3464
3465         if (!is_valid_ether_addr(saddr->sa_data))
3466                 return -EADDRNOTAVAIL;
3467
3468         netif_addr_lock_bh(netdev);
3469         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3470         netif_addr_unlock_bh(netdev);
3471
3472         queue_work(priv->wq, &priv->set_rx_mode_work);
3473
3474         return 0;
3475 }
3476
3477 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3478         do {                                            \
3479                 if (enable)                             \
3480                         *features |= feature;           \
3481                 else                                    \
3482                         *features &= ~feature;          \
3483         } while (0)
3484
3485 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3486
3487 static int set_feature_lro(struct net_device *netdev, bool enable)
3488 {
3489         struct mlx5e_priv *priv = netdev_priv(netdev);
3490         struct mlx5_core_dev *mdev = priv->mdev;
3491         struct mlx5e_channels new_channels = {};
3492         struct mlx5e_params *old_params;
3493         int err = 0;
3494         bool reset;
3495
3496         mutex_lock(&priv->state_lock);
3497
3498         old_params = &priv->channels.params;
3499         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3500                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3501                 err = -EINVAL;
3502                 goto out;
3503         }
3504
3505         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3506
3507         new_channels.params = *old_params;
3508         new_channels.params.lro_en = enable;
3509
3510         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3511                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3512                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3513                         reset = false;
3514         }
3515
3516         if (!reset) {
3517                 *old_params = new_channels.params;
3518                 err = mlx5e_modify_tirs_lro(priv);
3519                 goto out;
3520         }
3521
3522         err = mlx5e_open_channels(priv, &new_channels);
3523         if (err)
3524                 goto out;
3525
3526         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3527 out:
3528         mutex_unlock(&priv->state_lock);
3529         return err;
3530 }
3531
3532 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3533 {
3534         struct mlx5e_priv *priv = netdev_priv(netdev);
3535
3536         if (enable)
3537                 mlx5e_enable_cvlan_filter(priv);
3538         else
3539                 mlx5e_disable_cvlan_filter(priv);
3540
3541         return 0;
3542 }
3543
3544 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3545 {
3546         struct mlx5e_priv *priv = netdev_priv(netdev);
3547
3548         if (!enable && mlx5e_tc_num_filters(priv)) {
3549                 netdev_err(netdev,
3550                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3551                 return -EINVAL;
3552         }
3553
3554         return 0;
3555 }
3556
3557 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3558 {
3559         struct mlx5e_priv *priv = netdev_priv(netdev);
3560         struct mlx5_core_dev *mdev = priv->mdev;
3561
3562         return mlx5_set_port_fcs(mdev, !enable);
3563 }
3564
3565 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3566 {
3567         struct mlx5e_priv *priv = netdev_priv(netdev);
3568         int err;
3569
3570         mutex_lock(&priv->state_lock);
3571
3572         priv->channels.params.scatter_fcs_en = enable;
3573         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3574         if (err)
3575                 priv->channels.params.scatter_fcs_en = !enable;
3576
3577         mutex_unlock(&priv->state_lock);
3578
3579         return err;
3580 }
3581
3582 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3583 {
3584         struct mlx5e_priv *priv = netdev_priv(netdev);
3585         int err = 0;
3586
3587         mutex_lock(&priv->state_lock);
3588
3589         priv->channels.params.vlan_strip_disable = !enable;
3590         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3591                 goto unlock;
3592
3593         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3594         if (err)
3595                 priv->channels.params.vlan_strip_disable = enable;
3596
3597 unlock:
3598         mutex_unlock(&priv->state_lock);
3599
3600         return err;
3601 }
3602
3603 #ifdef CONFIG_RFS_ACCEL
3604 static int set_feature_arfs(struct net_device *netdev, bool enable)
3605 {
3606         struct mlx5e_priv *priv = netdev_priv(netdev);
3607         int err;
3608
3609         if (enable)
3610                 err = mlx5e_arfs_enable(priv);
3611         else
3612                 err = mlx5e_arfs_disable(priv);
3613
3614         return err;
3615 }
3616 #endif
3617
3618 static int mlx5e_handle_feature(struct net_device *netdev,
3619                                 netdev_features_t *features,
3620                                 netdev_features_t wanted_features,
3621                                 netdev_features_t feature,
3622                                 mlx5e_feature_handler feature_handler)
3623 {
3624         netdev_features_t changes = wanted_features ^ netdev->features;
3625         bool enable = !!(wanted_features & feature);
3626         int err;
3627
3628         if (!(changes & feature))
3629                 return 0;
3630
3631         err = feature_handler(netdev, enable);
3632         if (err) {
3633                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3634                            enable ? "Enable" : "Disable", &feature, err);
3635                 return err;
3636         }
3637
3638         MLX5E_SET_FEATURE(features, feature, enable);
3639         return 0;
3640 }
3641
3642 static int mlx5e_set_features(struct net_device *netdev,
3643                               netdev_features_t features)
3644 {
3645         netdev_features_t oper_features = netdev->features;
3646         int err = 0;
3647
3648 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3649         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3650
3651         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3652         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3653                                     set_feature_cvlan_filter);
3654         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3655         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3656         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3657         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3658 #ifdef CONFIG_RFS_ACCEL
3659         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3660 #endif
3661
3662         if (err) {
3663                 netdev->features = oper_features;
3664                 return -EINVAL;
3665         }
3666
3667         return 0;
3668 }
3669
3670 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3671                                             netdev_features_t features)
3672 {
3673         struct mlx5e_priv *priv = netdev_priv(netdev);
3674         struct mlx5e_params *params;
3675
3676         mutex_lock(&priv->state_lock);
3677         params = &priv->channels.params;
3678         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3679                 /* HW strips the outer C-tag header, this is a problem
3680                  * for S-tag traffic.
3681                  */
3682                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3683                 if (!params->vlan_strip_disable)
3684                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3685         }
3686         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3687                 features &= ~NETIF_F_LRO;
3688                 if (params->lro_en)
3689                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3690         }
3691
3692         mutex_unlock(&priv->state_lock);
3693
3694         return features;
3695 }
3696
3697 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3698                      change_hw_mtu_cb set_mtu_cb)
3699 {
3700         struct mlx5e_priv *priv = netdev_priv(netdev);
3701         struct mlx5e_channels new_channels = {};
3702         struct mlx5e_params *params;
3703         int err = 0;
3704         bool reset;
3705
3706         mutex_lock(&priv->state_lock);
3707
3708         params = &priv->channels.params;
3709
3710         reset = !params->lro_en;
3711         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3712
3713         new_channels.params = *params;
3714         new_channels.params.sw_mtu = new_mtu;
3715
3716         if (params->xdp_prog &&
3717             !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3718                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3719                            new_mtu, MLX5E_XDP_MAX_MTU);
3720                 err = -EINVAL;
3721                 goto out;
3722         }
3723
3724         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3725                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3726                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3727
3728                 reset = reset && (ppw_old != ppw_new);
3729         }
3730
3731         if (!reset) {
3732                 params->sw_mtu = new_mtu;
3733                 set_mtu_cb(priv);
3734                 netdev->mtu = params->sw_mtu;
3735                 goto out;
3736         }
3737
3738         err = mlx5e_open_channels(priv, &new_channels);
3739         if (err)
3740                 goto out;
3741
3742         mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
3743         netdev->mtu = new_channels.params.sw_mtu;
3744
3745 out:
3746         mutex_unlock(&priv->state_lock);
3747         return err;
3748 }
3749
3750 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3751 {
3752         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3753 }
3754
3755 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3756 {
3757         struct hwtstamp_config config;
3758         int err;
3759
3760         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3761                 return -EOPNOTSUPP;
3762
3763         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3764                 return -EFAULT;
3765
3766         /* TX HW timestamp */
3767         switch (config.tx_type) {
3768         case HWTSTAMP_TX_OFF:
3769         case HWTSTAMP_TX_ON:
3770                 break;
3771         default:
3772                 return -ERANGE;
3773         }
3774
3775         mutex_lock(&priv->state_lock);
3776         /* RX HW timestamp */
3777         switch (config.rx_filter) {
3778         case HWTSTAMP_FILTER_NONE:
3779                 /* Reset CQE compression to Admin default */
3780                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3781                 break;
3782         case HWTSTAMP_FILTER_ALL:
3783         case HWTSTAMP_FILTER_SOME:
3784         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3785         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3786         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3787         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3788         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3789         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3790         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3791         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3792         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3793         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3794         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3795         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3796         case HWTSTAMP_FILTER_NTP_ALL:
3797                 /* Disable CQE compression */
3798                 netdev_warn(priv->netdev, "Disabling cqe compression");
3799                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3800                 if (err) {
3801                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3802                         mutex_unlock(&priv->state_lock);
3803                         return err;
3804                 }
3805                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3806                 break;
3807         default:
3808                 mutex_unlock(&priv->state_lock);
3809                 return -ERANGE;
3810         }
3811
3812         memcpy(&priv->tstamp, &config, sizeof(config));
3813         mutex_unlock(&priv->state_lock);
3814
3815         return copy_to_user(ifr->ifr_data, &config,
3816                             sizeof(config)) ? -EFAULT : 0;
3817 }
3818
3819 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3820 {
3821         struct hwtstamp_config *cfg = &priv->tstamp;
3822
3823         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3824                 return -EOPNOTSUPP;
3825
3826         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3827 }
3828
3829 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3830 {
3831         struct mlx5e_priv *priv = netdev_priv(dev);
3832
3833         switch (cmd) {
3834         case SIOCSHWTSTAMP:
3835                 return mlx5e_hwstamp_set(priv, ifr);
3836         case SIOCGHWTSTAMP:
3837                 return mlx5e_hwstamp_get(priv, ifr);
3838         default:
3839                 return -EOPNOTSUPP;
3840         }
3841 }
3842
3843 #ifdef CONFIG_MLX5_ESWITCH
3844 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3845 {
3846         struct mlx5e_priv *priv = netdev_priv(dev);
3847         struct mlx5_core_dev *mdev = priv->mdev;
3848
3849         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3850 }
3851
3852 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3853                              __be16 vlan_proto)
3854 {
3855         struct mlx5e_priv *priv = netdev_priv(dev);
3856         struct mlx5_core_dev *mdev = priv->mdev;
3857
3858         if (vlan_proto != htons(ETH_P_8021Q))
3859                 return -EPROTONOSUPPORT;
3860
3861         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3862                                            vlan, qos);
3863 }
3864
3865 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3866 {
3867         struct mlx5e_priv *priv = netdev_priv(dev);
3868         struct mlx5_core_dev *mdev = priv->mdev;
3869
3870         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3871 }
3872
3873 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3874 {
3875         struct mlx5e_priv *priv = netdev_priv(dev);
3876         struct mlx5_core_dev *mdev = priv->mdev;
3877
3878         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3879 }
3880
3881 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3882                              int max_tx_rate)
3883 {
3884         struct mlx5e_priv *priv = netdev_priv(dev);
3885         struct mlx5_core_dev *mdev = priv->mdev;
3886
3887         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3888                                            max_tx_rate, min_tx_rate);
3889 }
3890
3891 static int mlx5_vport_link2ifla(u8 esw_link)
3892 {
3893         switch (esw_link) {
3894         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3895                 return IFLA_VF_LINK_STATE_DISABLE;
3896         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3897                 return IFLA_VF_LINK_STATE_ENABLE;
3898         }
3899         return IFLA_VF_LINK_STATE_AUTO;
3900 }
3901
3902 static int mlx5_ifla_link2vport(u8 ifla_link)
3903 {
3904         switch (ifla_link) {
3905         case IFLA_VF_LINK_STATE_DISABLE:
3906                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3907         case IFLA_VF_LINK_STATE_ENABLE:
3908                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3909         }
3910         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3911 }
3912
3913 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3914                                    int link_state)
3915 {
3916         struct mlx5e_priv *priv = netdev_priv(dev);
3917         struct mlx5_core_dev *mdev = priv->mdev;
3918
3919         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3920                                             mlx5_ifla_link2vport(link_state));
3921 }
3922
3923 static int mlx5e_get_vf_config(struct net_device *dev,
3924                                int vf, struct ifla_vf_info *ivi)
3925 {
3926         struct mlx5e_priv *priv = netdev_priv(dev);
3927         struct mlx5_core_dev *mdev = priv->mdev;
3928         int err;
3929
3930         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3931         if (err)
3932                 return err;
3933         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3934         return 0;
3935 }
3936
3937 static int mlx5e_get_vf_stats(struct net_device *dev,
3938                               int vf, struct ifla_vf_stats *vf_stats)
3939 {
3940         struct mlx5e_priv *priv = netdev_priv(dev);
3941         struct mlx5_core_dev *mdev = priv->mdev;
3942
3943         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3944                                             vf_stats);
3945 }
3946 #endif
3947
3948 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3949                                  struct udp_tunnel_info *ti)
3950 {
3951         struct mlx5e_priv *priv = netdev_priv(netdev);
3952
3953         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3954                 return;
3955
3956         if (!mlx5e_vxlan_allowed(priv->mdev))
3957                 return;
3958
3959         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3960 }
3961
3962 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3963                                  struct udp_tunnel_info *ti)
3964 {
3965         struct mlx5e_priv *priv = netdev_priv(netdev);
3966
3967         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3968                 return;
3969
3970         if (!mlx5e_vxlan_allowed(priv->mdev))
3971                 return;
3972
3973         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3974 }
3975
3976 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3977                                                      struct sk_buff *skb,
3978                                                      netdev_features_t features)
3979 {
3980         unsigned int offset = 0;
3981         struct udphdr *udph;
3982         u8 proto;
3983         u16 port;
3984
3985         switch (vlan_get_protocol(skb)) {
3986         case htons(ETH_P_IP):
3987                 proto = ip_hdr(skb)->protocol;
3988                 break;
3989         case htons(ETH_P_IPV6):
3990                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3991                 break;
3992         default:
3993                 goto out;
3994         }
3995
3996         switch (proto) {
3997         case IPPROTO_GRE:
3998                 return features;
3999         case IPPROTO_UDP:
4000                 udph = udp_hdr(skb);
4001                 port = be16_to_cpu(udph->dest);
4002
4003                 /* Verify if UDP port is being offloaded by HW */
4004                 if (mlx5e_vxlan_lookup_port(priv, port))
4005                         return features;
4006         }
4007
4008 out:
4009         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4010         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4011 }
4012
4013 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4014                                               struct net_device *netdev,
4015                                               netdev_features_t features)
4016 {
4017         struct mlx5e_priv *priv = netdev_priv(netdev);
4018
4019         features = vlan_features_check(skb, features);
4020         features = vxlan_features_check(skb, features);
4021
4022 #ifdef CONFIG_MLX5_EN_IPSEC
4023         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4024                 return features;
4025 #endif
4026
4027         /* Validate if the tunneled packet is being offloaded by HW */
4028         if (skb->encapsulation &&
4029             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4030                 return mlx5e_tunnel_features_check(priv, skb, features);
4031
4032         return features;
4033 }
4034
4035 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4036                                         struct mlx5e_txqsq *sq)
4037 {
4038         struct mlx5_eq *eq = sq->cq.mcq.eq;
4039         u32 eqe_count;
4040
4041         netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
4042                    eq->eqn, eq->cons_index, eq->irqn);
4043
4044         eqe_count = mlx5_eq_poll_irq_disabled(eq);
4045         if (!eqe_count)
4046                 return false;
4047
4048         netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
4049         sq->channel->stats->eq_rearm++;
4050         return true;
4051 }
4052
4053 static void mlx5e_tx_timeout_work(struct work_struct *work)
4054 {
4055         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4056                                                tx_timeout_work);
4057         struct net_device *dev = priv->netdev;
4058         bool reopen_channels = false;
4059         int i, err;
4060
4061         rtnl_lock();
4062         mutex_lock(&priv->state_lock);
4063
4064         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4065                 goto unlock;
4066
4067         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4068                 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
4069                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4070
4071                 if (!netif_xmit_stopped(dev_queue))
4072                         continue;
4073
4074                 netdev_err(dev,
4075                            "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
4076                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4077                            jiffies_to_usecs(jiffies - dev_queue->trans_start));
4078
4079                 /* If we recover a lost interrupt, most likely TX timeout will
4080                  * be resolved, skip reopening channels
4081                  */
4082                 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4083                         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4084                         reopen_channels = true;
4085                 }
4086         }
4087
4088         if (!reopen_channels)
4089                 goto unlock;
4090
4091         mlx5e_close_locked(dev);
4092         err = mlx5e_open_locked(dev);
4093         if (err)
4094                 netdev_err(priv->netdev,
4095                            "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4096                            err);
4097
4098 unlock:
4099         mutex_unlock(&priv->state_lock);
4100         rtnl_unlock();
4101 }
4102
4103 static void mlx5e_tx_timeout(struct net_device *dev)
4104 {
4105         struct mlx5e_priv *priv = netdev_priv(dev);
4106
4107         netdev_err(dev, "TX timeout detected\n");
4108         queue_work(priv->wq, &priv->tx_timeout_work);
4109 }
4110
4111 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4112 {
4113         struct net_device *netdev = priv->netdev;
4114         struct mlx5e_channels new_channels = {};
4115
4116         if (priv->channels.params.lro_en) {
4117                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4118                 return -EINVAL;
4119         }
4120
4121         if (MLX5_IPSEC_DEV(priv->mdev)) {
4122                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4123                 return -EINVAL;
4124         }
4125
4126         new_channels.params = priv->channels.params;
4127         new_channels.params.xdp_prog = prog;
4128
4129         if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4130                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4131                             new_channels.params.sw_mtu, MLX5E_XDP_MAX_MTU);
4132                 return -EINVAL;
4133         }
4134
4135         return 0;
4136 }
4137
4138 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4139 {
4140         struct mlx5e_priv *priv = netdev_priv(netdev);
4141         struct bpf_prog *old_prog;
4142         bool reset, was_opened;
4143         int err;
4144         int i;
4145
4146         mutex_lock(&priv->state_lock);
4147
4148         if (prog) {
4149                 err = mlx5e_xdp_allowed(priv, prog);
4150                 if (err)
4151                         goto unlock;
4152         }
4153
4154         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4155         /* no need for full reset when exchanging programs */
4156         reset = (!priv->channels.params.xdp_prog || !prog);
4157
4158         if (was_opened && reset)
4159                 mlx5e_close_locked(netdev);
4160         if (was_opened && !reset) {
4161                 /* num_channels is invariant here, so we can take the
4162                  * batched reference right upfront.
4163                  */
4164                 prog = bpf_prog_add(prog, priv->channels.num);
4165                 if (IS_ERR(prog)) {
4166                         err = PTR_ERR(prog);
4167                         goto unlock;
4168                 }
4169         }
4170
4171         /* exchange programs, extra prog reference we got from caller
4172          * as long as we don't fail from this point onwards.
4173          */
4174         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4175         if (old_prog)
4176                 bpf_prog_put(old_prog);
4177
4178         if (reset) /* change RQ type according to priv->xdp_prog */
4179                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4180
4181         if (was_opened && reset)
4182                 mlx5e_open_locked(netdev);
4183
4184         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4185                 goto unlock;
4186
4187         /* exchanging programs w/o reset, we update ref counts on behalf
4188          * of the channels RQs here.
4189          */
4190         for (i = 0; i < priv->channels.num; i++) {
4191                 struct mlx5e_channel *c = priv->channels.c[i];
4192
4193                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4194                 napi_synchronize(&c->napi);
4195                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4196
4197                 old_prog = xchg(&c->rq.xdp_prog, prog);
4198
4199                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4200                 /* napi_schedule in case we have missed anything */
4201                 napi_schedule(&c->napi);
4202
4203                 if (old_prog)
4204                         bpf_prog_put(old_prog);
4205         }
4206
4207 unlock:
4208         mutex_unlock(&priv->state_lock);
4209         return err;
4210 }
4211
4212 static u32 mlx5e_xdp_query(struct net_device *dev)
4213 {
4214         struct mlx5e_priv *priv = netdev_priv(dev);
4215         const struct bpf_prog *xdp_prog;
4216         u32 prog_id = 0;
4217
4218         mutex_lock(&priv->state_lock);
4219         xdp_prog = priv->channels.params.xdp_prog;
4220         if (xdp_prog)
4221                 prog_id = xdp_prog->aux->id;
4222         mutex_unlock(&priv->state_lock);
4223
4224         return prog_id;
4225 }
4226
4227 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4228 {
4229         switch (xdp->command) {
4230         case XDP_SETUP_PROG:
4231                 return mlx5e_xdp_set(dev, xdp->prog);
4232         case XDP_QUERY_PROG:
4233                 xdp->prog_id = mlx5e_xdp_query(dev);
4234                 return 0;
4235         default:
4236                 return -EINVAL;
4237         }
4238 }
4239
4240 #ifdef CONFIG_NET_POLL_CONTROLLER
4241 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
4242  * reenabling interrupts.
4243  */
4244 static void mlx5e_netpoll(struct net_device *dev)
4245 {
4246         struct mlx5e_priv *priv = netdev_priv(dev);
4247         struct mlx5e_channels *chs = &priv->channels;
4248
4249         int i;
4250
4251         for (i = 0; i < chs->num; i++)
4252                 napi_schedule(&chs->c[i]->napi);
4253 }
4254 #endif
4255
4256 static const struct net_device_ops mlx5e_netdev_ops = {
4257         .ndo_open                = mlx5e_open,
4258         .ndo_stop                = mlx5e_close,
4259         .ndo_start_xmit          = mlx5e_xmit,
4260         .ndo_setup_tc            = mlx5e_setup_tc,
4261         .ndo_select_queue        = mlx5e_select_queue,
4262         .ndo_get_stats64         = mlx5e_get_stats,
4263         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4264         .ndo_set_mac_address     = mlx5e_set_mac,
4265         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4266         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4267         .ndo_set_features        = mlx5e_set_features,
4268         .ndo_fix_features        = mlx5e_fix_features,
4269         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4270         .ndo_do_ioctl            = mlx5e_ioctl,
4271         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4272         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4273         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4274         .ndo_features_check      = mlx5e_features_check,
4275 #ifdef CONFIG_RFS_ACCEL
4276         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4277 #endif
4278         .ndo_tx_timeout          = mlx5e_tx_timeout,
4279         .ndo_bpf                 = mlx5e_xdp,
4280 #ifdef CONFIG_NET_POLL_CONTROLLER
4281         .ndo_poll_controller     = mlx5e_netpoll,
4282 #endif
4283 #ifdef CONFIG_MLX5_ESWITCH
4284         /* SRIOV E-Switch NDOs */
4285         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4286         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4287         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4288         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4289         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4290         .ndo_get_vf_config       = mlx5e_get_vf_config,
4291         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4292         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4293         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4294         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4295 #endif
4296 };
4297
4298 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4299 {
4300         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4301                 return -EOPNOTSUPP;
4302         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4303             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4304             !MLX5_CAP_ETH(mdev, csum_cap) ||
4305             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4306             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4307             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4308             MLX5_CAP_FLOWTABLE(mdev,
4309                                flow_table_properties_nic_receive.max_ft_level)
4310                                < 3) {
4311                 mlx5_core_warn(mdev,
4312                                "Not creating net device, some required device capabilities are missing\n");
4313                 return -EOPNOTSUPP;
4314         }
4315         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4316                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4317         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4318                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4319
4320         return 0;
4321 }
4322
4323 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4324                                    int num_channels)
4325 {
4326         int i;
4327
4328         for (i = 0; i < len; i++)
4329                 indirection_rqt[i] = i % num_channels;
4330 }
4331
4332 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4333 {
4334         u32 link_speed = 0;
4335         u32 pci_bw = 0;
4336
4337         mlx5e_port_max_linkspeed(mdev, &link_speed);
4338         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4339         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4340                            link_speed, pci_bw);
4341
4342 #define MLX5E_SLOW_PCI_RATIO (2)
4343
4344         return link_speed && pci_bw &&
4345                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4346 }
4347
4348 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4349 {
4350         struct net_dim_cq_moder moder;
4351
4352         moder.cq_period_mode = cq_period_mode;
4353         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4354         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4355         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4356                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4357
4358         return moder;
4359 }
4360
4361 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4362 {
4363         struct net_dim_cq_moder moder;
4364
4365         moder.cq_period_mode = cq_period_mode;
4366         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4367         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4368         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4369                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4370
4371         return moder;
4372 }
4373
4374 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4375 {
4376         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4377                 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4378                 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4379 }
4380
4381 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4382 {
4383         if (params->tx_dim_enabled) {
4384                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4385
4386                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4387         } else {
4388                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4389         }
4390
4391         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4392                         params->tx_cq_moderation.cq_period_mode ==
4393                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4394 }
4395
4396 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4397 {
4398         if (params->rx_dim_enabled) {
4399                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4400
4401                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4402         } else {
4403                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4404         }
4405
4406         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4407                         params->rx_cq_moderation.cq_period_mode ==
4408                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4409 }
4410
4411 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4412 {
4413         int i;
4414
4415         /* The supported periods are organized in ascending order */
4416         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4417                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4418                         break;
4419
4420         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4421 }
4422
4423 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4424                             struct mlx5e_params *params,
4425                             u16 max_channels, u16 mtu)
4426 {
4427         u8 rx_cq_period_mode;
4428
4429         params->sw_mtu = mtu;
4430         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4431         params->num_channels = max_channels;
4432         params->num_tc       = 1;
4433
4434         /* SQ */
4435         params->log_sq_size = is_kdump_kernel() ?
4436                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4437                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4438
4439         /* set CQE compression */
4440         params->rx_cqe_compress_def = false;
4441         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4442             MLX5_CAP_GEN(mdev, vport_group_manager))
4443                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4444
4445         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4446
4447         /* RQ */
4448         /* Prefer Striding RQ, unless any of the following holds:
4449          * - Striding RQ configuration is not possible/supported.
4450          * - Slow PCI heuristic.
4451          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4452          */
4453         if (!slow_pci_heuristic(mdev) &&
4454             mlx5e_striding_rq_possible(mdev, params) &&
4455             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4456              !mlx5e_rx_is_linear_skb(mdev, params)))
4457                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4458         mlx5e_set_rq_type(mdev, params);
4459         mlx5e_init_rq_type_params(mdev, params);
4460
4461         /* HW LRO */
4462
4463         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4464         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4465                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4466                         params->lro_en = !slow_pci_heuristic(mdev);
4467         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4468
4469         /* CQ moderation params */
4470         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4471                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4472                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4473         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4474         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4475         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4476         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4477
4478         /* TX inline */
4479         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4480
4481         /* RSS */
4482         params->rss_hfunc = ETH_RSS_HASH_XOR;
4483         netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4484         mlx5e_build_default_indir_rqt(params->indirection_rqt,
4485                                       MLX5E_INDIR_RQT_SIZE, max_channels);
4486 }
4487
4488 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4489                                         struct net_device *netdev,
4490                                         const struct mlx5e_profile *profile,
4491                                         void *ppriv)
4492 {
4493         struct mlx5e_priv *priv = netdev_priv(netdev);
4494
4495         priv->mdev        = mdev;
4496         priv->netdev      = netdev;
4497         priv->profile     = profile;
4498         priv->ppriv       = ppriv;
4499         priv->msglevel    = MLX5E_MSG_LEVEL;
4500         priv->max_opened_tc = 1;
4501
4502         mlx5e_build_nic_params(mdev, &priv->channels.params,
4503                                profile->max_nch(mdev), netdev->mtu);
4504
4505         mutex_init(&priv->state_lock);
4506
4507         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4508         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4509         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4510         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4511
4512         mlx5e_timestamp_init(priv);
4513 }
4514
4515 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4516 {
4517         struct mlx5e_priv *priv = netdev_priv(netdev);
4518
4519         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4520         if (is_zero_ether_addr(netdev->dev_addr) &&
4521             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4522                 eth_hw_addr_random(netdev);
4523                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4524         }
4525 }
4526
4527 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4528 static const struct switchdev_ops mlx5e_switchdev_ops = {
4529         .switchdev_port_attr_get        = mlx5e_attr_get,
4530 };
4531 #endif
4532
4533 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4534 {
4535         struct mlx5e_priv *priv = netdev_priv(netdev);
4536         struct mlx5_core_dev *mdev = priv->mdev;
4537         bool fcs_supported;
4538         bool fcs_enabled;
4539
4540         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4541
4542         netdev->netdev_ops = &mlx5e_netdev_ops;
4543
4544 #ifdef CONFIG_MLX5_CORE_EN_DCB
4545         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4546                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4547 #endif
4548
4549         netdev->watchdog_timeo    = 15 * HZ;
4550
4551         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4552
4553         netdev->vlan_features    |= NETIF_F_SG;
4554         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4555         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4556         netdev->vlan_features    |= NETIF_F_GRO;
4557         netdev->vlan_features    |= NETIF_F_TSO;
4558         netdev->vlan_features    |= NETIF_F_TSO6;
4559         netdev->vlan_features    |= NETIF_F_RXCSUM;
4560         netdev->vlan_features    |= NETIF_F_RXHASH;
4561
4562         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4563         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4564
4565         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4566             mlx5e_check_fragmented_striding_rq_cap(mdev))
4567                 netdev->vlan_features    |= NETIF_F_LRO;
4568
4569         netdev->hw_features       = netdev->vlan_features;
4570         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4571         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4572         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4573         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4574
4575         if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4576                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4577                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4578                 netdev->hw_enc_features |= NETIF_F_TSO;
4579                 netdev->hw_enc_features |= NETIF_F_TSO6;
4580                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4581         }
4582
4583         if (mlx5e_vxlan_allowed(mdev)) {
4584                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4585                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4586                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4587                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4588                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4589         }
4590
4591         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4592                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4593                                            NETIF_F_GSO_GRE_CSUM;
4594                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4595                                            NETIF_F_GSO_GRE_CSUM;
4596                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4597                                                 NETIF_F_GSO_GRE_CSUM;
4598         }
4599
4600         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4601         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4602         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4603         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4604
4605         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4606
4607         if (fcs_supported)
4608                 netdev->hw_features |= NETIF_F_RXALL;
4609
4610         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4611                 netdev->hw_features |= NETIF_F_RXFCS;
4612
4613         netdev->features          = netdev->hw_features;
4614         if (!priv->channels.params.lro_en)
4615                 netdev->features  &= ~NETIF_F_LRO;
4616
4617         if (fcs_enabled)
4618                 netdev->features  &= ~NETIF_F_RXALL;
4619
4620         if (!priv->channels.params.scatter_fcs_en)
4621                 netdev->features  &= ~NETIF_F_RXFCS;
4622
4623 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4624         if (FT_CAP(flow_modify_en) &&
4625             FT_CAP(modify_root) &&
4626             FT_CAP(identified_miss_table_mode) &&
4627             FT_CAP(flow_table_modify)) {
4628                 netdev->hw_features      |= NETIF_F_HW_TC;
4629 #ifdef CONFIG_RFS_ACCEL
4630                 netdev->hw_features      |= NETIF_F_NTUPLE;
4631 #endif
4632         }
4633
4634         netdev->features         |= NETIF_F_HIGHDMA;
4635         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4636
4637         netdev->priv_flags       |= IFF_UNICAST_FLT;
4638
4639         mlx5e_set_netdev_dev_addr(netdev);
4640
4641 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4642         if (MLX5_ESWITCH_MANAGER(mdev))
4643                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4644 #endif
4645
4646         mlx5e_ipsec_build_netdev(priv);
4647         mlx5e_tls_build_netdev(priv);
4648 }
4649
4650 static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4651 {
4652         struct mlx5_core_dev *mdev = priv->mdev;
4653         int err;
4654
4655         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4656         if (err) {
4657                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4658                 priv->q_counter = 0;
4659         }
4660
4661         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4662         if (err) {
4663                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4664                 priv->drop_rq_q_counter = 0;
4665         }
4666 }
4667
4668 static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4669 {
4670         if (priv->q_counter)
4671                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4672
4673         if (priv->drop_rq_q_counter)
4674                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4675 }
4676
4677 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4678                            struct net_device *netdev,
4679                            const struct mlx5e_profile *profile,
4680                            void *ppriv)
4681 {
4682         struct mlx5e_priv *priv = netdev_priv(netdev);
4683         int err;
4684
4685         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4686         err = mlx5e_ipsec_init(priv);
4687         if (err)
4688                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4689         err = mlx5e_tls_init(priv);
4690         if (err)
4691                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4692         mlx5e_build_nic_netdev(netdev);
4693         mlx5e_build_tc2txq_maps(priv);
4694         mlx5e_vxlan_init(priv);
4695 }
4696
4697 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4698 {
4699         mlx5e_tls_cleanup(priv);
4700         mlx5e_ipsec_cleanup(priv);
4701         mlx5e_vxlan_cleanup(priv);
4702 }
4703
4704 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4705 {
4706         struct mlx5_core_dev *mdev = priv->mdev;
4707         int err;
4708
4709         err = mlx5e_create_indirect_rqt(priv);
4710         if (err)
4711                 return err;
4712
4713         err = mlx5e_create_direct_rqts(priv);
4714         if (err)
4715                 goto err_destroy_indirect_rqts;
4716
4717         err = mlx5e_create_indirect_tirs(priv);
4718         if (err)
4719                 goto err_destroy_direct_rqts;
4720
4721         err = mlx5e_create_direct_tirs(priv);
4722         if (err)
4723                 goto err_destroy_indirect_tirs;
4724
4725         err = mlx5e_create_flow_steering(priv);
4726         if (err) {
4727                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4728                 goto err_destroy_direct_tirs;
4729         }
4730
4731         err = mlx5e_tc_nic_init(priv);
4732         if (err)
4733                 goto err_destroy_flow_steering;
4734
4735         return 0;
4736
4737 err_destroy_flow_steering:
4738         mlx5e_destroy_flow_steering(priv);
4739 err_destroy_direct_tirs:
4740         mlx5e_destroy_direct_tirs(priv);
4741 err_destroy_indirect_tirs:
4742         mlx5e_destroy_indirect_tirs(priv);
4743 err_destroy_direct_rqts:
4744         mlx5e_destroy_direct_rqts(priv);
4745 err_destroy_indirect_rqts:
4746         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4747         return err;
4748 }
4749
4750 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4751 {
4752         mlx5e_tc_nic_cleanup(priv);
4753         mlx5e_destroy_flow_steering(priv);
4754         mlx5e_destroy_direct_tirs(priv);
4755         mlx5e_destroy_indirect_tirs(priv);
4756         mlx5e_destroy_direct_rqts(priv);
4757         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4758 }
4759
4760 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4761 {
4762         int err;
4763
4764         err = mlx5e_create_tises(priv);
4765         if (err) {
4766                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4767                 return err;
4768         }
4769
4770 #ifdef CONFIG_MLX5_CORE_EN_DCB
4771         mlx5e_dcbnl_initialize(priv);
4772 #endif
4773         return 0;
4774 }
4775
4776 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4777 {
4778         struct net_device *netdev = priv->netdev;
4779         struct mlx5_core_dev *mdev = priv->mdev;
4780         u16 max_mtu;
4781
4782         mlx5e_init_l2_addr(priv);
4783
4784         /* Marking the link as currently not needed by the Driver */
4785         if (!netif_running(netdev))
4786                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4787
4788         /* MTU range: 68 - hw-specific max */
4789         netdev->min_mtu = ETH_MIN_MTU;
4790         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4791         netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4792         mlx5e_set_dev_port_mtu(priv);
4793
4794         mlx5_lag_add(mdev, netdev);
4795
4796         mlx5e_enable_async_events(priv);
4797
4798         if (MLX5_ESWITCH_MANAGER(priv->mdev))
4799                 mlx5e_register_vport_reps(priv);
4800
4801         if (netdev->reg_state != NETREG_REGISTERED)
4802                 return;
4803 #ifdef CONFIG_MLX5_CORE_EN_DCB
4804         mlx5e_dcbnl_init_app(priv);
4805 #endif
4806
4807         queue_work(priv->wq, &priv->set_rx_mode_work);
4808
4809         rtnl_lock();
4810         if (netif_running(netdev))
4811                 mlx5e_open(netdev);
4812         netif_device_attach(netdev);
4813         rtnl_unlock();
4814 }
4815
4816 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4817 {
4818         struct mlx5_core_dev *mdev = priv->mdev;
4819
4820 #ifdef CONFIG_MLX5_CORE_EN_DCB
4821         if (priv->netdev->reg_state == NETREG_REGISTERED)
4822                 mlx5e_dcbnl_delete_app(priv);
4823 #endif
4824
4825         rtnl_lock();
4826         if (netif_running(priv->netdev))
4827                 mlx5e_close(priv->netdev);
4828         netif_device_detach(priv->netdev);
4829         rtnl_unlock();
4830
4831         queue_work(priv->wq, &priv->set_rx_mode_work);
4832
4833         if (MLX5_ESWITCH_MANAGER(priv->mdev))
4834                 mlx5e_unregister_vport_reps(priv);
4835
4836         mlx5e_disable_async_events(priv);
4837         mlx5_lag_remove(mdev);
4838 }
4839
4840 static const struct mlx5e_profile mlx5e_nic_profile = {
4841         .init              = mlx5e_nic_init,
4842         .cleanup           = mlx5e_nic_cleanup,
4843         .init_rx           = mlx5e_init_nic_rx,
4844         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4845         .init_tx           = mlx5e_init_nic_tx,
4846         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4847         .enable            = mlx5e_nic_enable,
4848         .disable           = mlx5e_nic_disable,
4849         .update_stats      = mlx5e_update_ndo_stats,
4850         .max_nch           = mlx5e_get_max_num_channels,
4851         .update_carrier    = mlx5e_update_carrier,
4852         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4853         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4854         .max_tc            = MLX5E_MAX_NUM_TC,
4855 };
4856
4857 /* mlx5e generic netdev management API (move to en_common.c) */
4858
4859 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4860                                        const struct mlx5e_profile *profile,
4861                                        void *ppriv)
4862 {
4863         int nch = profile->max_nch(mdev);
4864         struct net_device *netdev;
4865         struct mlx5e_priv *priv;
4866
4867         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4868                                     nch * profile->max_tc,
4869                                     nch);
4870         if (!netdev) {
4871                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4872                 return NULL;
4873         }
4874
4875 #ifdef CONFIG_RFS_ACCEL
4876         netdev->rx_cpu_rmap = mdev->rmap;
4877 #endif
4878
4879         profile->init(mdev, netdev, profile, ppriv);
4880
4881         netif_carrier_off(netdev);
4882
4883         priv = netdev_priv(netdev);
4884
4885         priv->wq = create_singlethread_workqueue("mlx5e");
4886         if (!priv->wq)
4887                 goto err_cleanup_nic;
4888
4889         return netdev;
4890
4891 err_cleanup_nic:
4892         if (profile->cleanup)
4893                 profile->cleanup(priv);
4894         free_netdev(netdev);
4895
4896         return NULL;
4897 }
4898
4899 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4900 {
4901         struct mlx5_core_dev *mdev = priv->mdev;
4902         const struct mlx5e_profile *profile;
4903         int err;
4904
4905         profile = priv->profile;
4906         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4907
4908         err = profile->init_tx(priv);
4909         if (err)
4910                 goto out;
4911
4912         mlx5e_create_q_counters(priv);
4913
4914         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4915         if (err) {
4916                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4917                 goto err_destroy_q_counters;
4918         }
4919
4920         err = profile->init_rx(priv);
4921         if (err)
4922                 goto err_close_drop_rq;
4923
4924         if (profile->enable)
4925                 profile->enable(priv);
4926
4927         return 0;
4928
4929 err_close_drop_rq:
4930         mlx5e_close_drop_rq(&priv->drop_rq);
4931
4932 err_destroy_q_counters:
4933         mlx5e_destroy_q_counters(priv);
4934         profile->cleanup_tx(priv);
4935
4936 out:
4937         return err;
4938 }
4939
4940 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4941 {
4942         const struct mlx5e_profile *profile = priv->profile;
4943
4944         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4945
4946         if (profile->disable)
4947                 profile->disable(priv);
4948         flush_workqueue(priv->wq);
4949
4950         profile->cleanup_rx(priv);
4951         mlx5e_close_drop_rq(&priv->drop_rq);
4952         mlx5e_destroy_q_counters(priv);
4953         profile->cleanup_tx(priv);
4954         cancel_delayed_work_sync(&priv->update_stats_work);
4955 }
4956
4957 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4958 {
4959         const struct mlx5e_profile *profile = priv->profile;
4960         struct net_device *netdev = priv->netdev;
4961
4962         destroy_workqueue(priv->wq);
4963         if (profile->cleanup)
4964                 profile->cleanup(priv);
4965         free_netdev(netdev);
4966 }
4967
4968 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4969  * hardware contexts and to connect it to the current netdev.
4970  */
4971 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4972 {
4973         struct mlx5e_priv *priv = vpriv;
4974         struct net_device *netdev = priv->netdev;
4975         int err;
4976
4977         if (netif_device_present(netdev))
4978                 return 0;
4979
4980         err = mlx5e_create_mdev_resources(mdev);
4981         if (err)
4982                 return err;
4983
4984         err = mlx5e_attach_netdev(priv);
4985         if (err) {
4986                 mlx5e_destroy_mdev_resources(mdev);
4987                 return err;
4988         }
4989
4990         return 0;
4991 }
4992
4993 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4994 {
4995         struct mlx5e_priv *priv = vpriv;
4996         struct net_device *netdev = priv->netdev;
4997
4998         if (!netif_device_present(netdev))
4999                 return;
5000
5001         mlx5e_detach_netdev(priv);
5002         mlx5e_destroy_mdev_resources(mdev);
5003 }
5004
5005 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5006 {
5007         struct net_device *netdev;
5008         void *rpriv = NULL;
5009         void *priv;
5010         int err;
5011
5012         err = mlx5e_check_required_hca_cap(mdev);
5013         if (err)
5014                 return NULL;
5015
5016 #ifdef CONFIG_MLX5_ESWITCH
5017         if (MLX5_ESWITCH_MANAGER(mdev)) {
5018                 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
5019                 if (!rpriv) {
5020                         mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
5021                         return NULL;
5022                 }
5023         }
5024 #endif
5025
5026         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
5027         if (!netdev) {
5028                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5029                 goto err_free_rpriv;
5030         }
5031
5032         priv = netdev_priv(netdev);
5033
5034         err = mlx5e_attach(mdev, priv);
5035         if (err) {
5036                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5037                 goto err_destroy_netdev;
5038         }
5039
5040         err = register_netdev(netdev);
5041         if (err) {
5042                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5043                 goto err_detach;
5044         }
5045
5046 #ifdef CONFIG_MLX5_CORE_EN_DCB
5047         mlx5e_dcbnl_init_app(priv);
5048 #endif
5049         return priv;
5050
5051 err_detach:
5052         mlx5e_detach(mdev, priv);
5053 err_destroy_netdev:
5054         mlx5e_destroy_netdev(priv);
5055 err_free_rpriv:
5056         kfree(rpriv);
5057         return NULL;
5058 }
5059
5060 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5061 {
5062         struct mlx5e_priv *priv = vpriv;
5063         void *ppriv = priv->ppriv;
5064
5065 #ifdef CONFIG_MLX5_CORE_EN_DCB
5066         mlx5e_dcbnl_delete_app(priv);
5067 #endif
5068         unregister_netdev(priv->netdev);
5069         mlx5e_detach(mdev, vpriv);
5070         mlx5e_destroy_netdev(priv);
5071         kfree(ppriv);
5072 }
5073
5074 static void *mlx5e_get_netdev(void *vpriv)
5075 {
5076         struct mlx5e_priv *priv = vpriv;
5077
5078         return priv->netdev;
5079 }
5080
5081 static struct mlx5_interface mlx5e_interface = {
5082         .add       = mlx5e_add,
5083         .remove    = mlx5e_remove,
5084         .attach    = mlx5e_attach,
5085         .detach    = mlx5e_detach,
5086         .event     = mlx5e_async_event,
5087         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5088         .get_dev   = mlx5e_get_netdev,
5089 };
5090
5091 void mlx5e_init(void)
5092 {
5093         mlx5e_ipsec_build_inverse_table();
5094         mlx5e_build_ptys2ethtool_map();
5095         mlx5_register_interface(&mlx5e_interface);
5096 }
5097
5098 void mlx5e_cleanup(void)
5099 {
5100         mlx5_unregister_interface(&mlx5e_interface);
5101 }