net/mlx5e: Expose physical layer statistical counters to ethtool
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include "en.h"
39 #include "en_tc.h"
40 #include "eswitch.h"
41 #include "vxlan.h"
42
43 struct mlx5e_rq_param {
44         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
45         struct mlx5_wq_param    wq;
46         bool                    am_enabled;
47 };
48
49 struct mlx5e_sq_param {
50         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
51         struct mlx5_wq_param       wq;
52         u16                        max_inline;
53         u8                         min_inline_mode;
54         enum mlx5e_sq_type         type;
55 };
56
57 struct mlx5e_cq_param {
58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
59         struct mlx5_wq_param       wq;
60         u16                        eq_ix;
61         u8                         cq_period_mode;
62 };
63
64 struct mlx5e_channel_param {
65         struct mlx5e_rq_param      rq;
66         struct mlx5e_sq_param      sq;
67         struct mlx5e_sq_param      xdp_sq;
68         struct mlx5e_sq_param      icosq;
69         struct mlx5e_cq_param      rx_cq;
70         struct mlx5e_cq_param      tx_cq;
71         struct mlx5e_cq_param      icosq_cq;
72 };
73
74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75 {
76         return MLX5_CAP_GEN(mdev, striding_rq) &&
77                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78                 MLX5_CAP_ETH(mdev, reg_umr_sq);
79 }
80
81 static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
82 {
83         priv->params.rq_wq_type = rq_type;
84         switch (priv->params.rq_wq_type) {
85         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
86                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
87                 priv->params.mpwqe_log_stride_sz =
88                         MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
89                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
90                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
91                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
92                         priv->params.mpwqe_log_stride_sz;
93                 break;
94         default: /* MLX5_WQ_TYPE_LINKED_LIST */
95                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
96         }
97         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
98                                                BIT(priv->params.log_rq_size));
99
100         mlx5_core_info(priv->mdev,
101                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
102                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
103                        BIT(priv->params.log_rq_size),
104                        BIT(priv->params.mpwqe_log_stride_sz),
105                        MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS));
106 }
107
108 static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
109 {
110         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
111                     !priv->xdp_prog ?
112                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
113                     MLX5_WQ_TYPE_LINKED_LIST;
114         mlx5e_set_rq_type_params(priv, rq_type);
115 }
116
117 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
118 {
119         struct mlx5_core_dev *mdev = priv->mdev;
120         u8 port_state;
121
122         port_state = mlx5_query_vport_state(mdev,
123                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
124
125         if (port_state == VPORT_STATE_UP) {
126                 netdev_info(priv->netdev, "Link up\n");
127                 netif_carrier_on(priv->netdev);
128         } else {
129                 netdev_info(priv->netdev, "Link down\n");
130                 netif_carrier_off(priv->netdev);
131         }
132 }
133
134 static void mlx5e_update_carrier_work(struct work_struct *work)
135 {
136         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
137                                                update_carrier_work);
138
139         mutex_lock(&priv->state_lock);
140         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
141                 mlx5e_update_carrier(priv);
142         mutex_unlock(&priv->state_lock);
143 }
144
145 static void mlx5e_tx_timeout_work(struct work_struct *work)
146 {
147         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
148                                                tx_timeout_work);
149         int err;
150
151         rtnl_lock();
152         mutex_lock(&priv->state_lock);
153         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
154                 goto unlock;
155         mlx5e_close_locked(priv->netdev);
156         err = mlx5e_open_locked(priv->netdev);
157         if (err)
158                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
159                            err);
160 unlock:
161         mutex_unlock(&priv->state_lock);
162         rtnl_unlock();
163 }
164
165 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
166 {
167         struct mlx5e_sw_stats *s = &priv->stats.sw;
168         struct mlx5e_rq_stats *rq_stats;
169         struct mlx5e_sq_stats *sq_stats;
170         u64 tx_offload_none = 0;
171         int i, j;
172
173         memset(s, 0, sizeof(*s));
174         for (i = 0; i < priv->params.num_channels; i++) {
175                 rq_stats = &priv->channel[i]->rq.stats;
176
177                 s->rx_packets   += rq_stats->packets;
178                 s->rx_bytes     += rq_stats->bytes;
179                 s->rx_lro_packets += rq_stats->lro_packets;
180                 s->rx_lro_bytes += rq_stats->lro_bytes;
181                 s->rx_csum_none += rq_stats->csum_none;
182                 s->rx_csum_complete += rq_stats->csum_complete;
183                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
184                 s->rx_xdp_drop += rq_stats->xdp_drop;
185                 s->rx_xdp_tx += rq_stats->xdp_tx;
186                 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
187                 s->rx_wqe_err   += rq_stats->wqe_err;
188                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
189                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
190                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
191                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
192                 s->rx_cache_reuse += rq_stats->cache_reuse;
193                 s->rx_cache_full  += rq_stats->cache_full;
194                 s->rx_cache_empty += rq_stats->cache_empty;
195                 s->rx_cache_busy  += rq_stats->cache_busy;
196
197                 for (j = 0; j < priv->params.num_tc; j++) {
198                         sq_stats = &priv->channel[i]->sq[j].stats;
199
200                         s->tx_packets           += sq_stats->packets;
201                         s->tx_bytes             += sq_stats->bytes;
202                         s->tx_tso_packets       += sq_stats->tso_packets;
203                         s->tx_tso_bytes         += sq_stats->tso_bytes;
204                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
205                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
206                         s->tx_queue_stopped     += sq_stats->stopped;
207                         s->tx_queue_wake        += sq_stats->wake;
208                         s->tx_queue_dropped     += sq_stats->dropped;
209                         s->tx_xmit_more         += sq_stats->xmit_more;
210                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
211                         tx_offload_none         += sq_stats->csum_none;
212                 }
213         }
214
215         /* Update calculated offload counters */
216         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
217         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
218
219         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
220                                 priv->stats.pport.phy_counters,
221                                 counter_set.phys_layer_cntrs.link_down_events);
222 }
223
224 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
225 {
226         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
227         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
228         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
229         struct mlx5_core_dev *mdev = priv->mdev;
230
231         MLX5_SET(query_vport_counter_in, in, opcode,
232                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
233         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
234         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
235
236         memset(out, 0, outlen);
237         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
238 }
239
240 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
241 {
242         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
243         struct mlx5_core_dev *mdev = priv->mdev;
244         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
245         int prio;
246         void *out;
247         u32 *in;
248
249         in = mlx5_vzalloc(sz);
250         if (!in)
251                 goto free_out;
252
253         MLX5_SET(ppcnt_reg, in, local_port, 1);
254
255         out = pstats->IEEE_802_3_counters;
256         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
257         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
258
259         out = pstats->RFC_2863_counters;
260         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
261         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
262
263         out = pstats->RFC_2819_counters;
264         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
265         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
266
267         out = pstats->phy_counters;
268         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
269         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
270
271         if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
272                 out = pstats->phy_statistical_counters;
273                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
274                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
275         }
276
277         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
278         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
279                 out = pstats->per_prio_counters[prio];
280                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
281                 mlx5_core_access_reg(mdev, in, sz, out, sz,
282                                      MLX5_REG_PPCNT, 0, 0);
283         }
284
285 free_out:
286         kvfree(in);
287 }
288
289 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
290 {
291         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
292
293         if (!priv->q_counter)
294                 return;
295
296         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
297                                       &qcnt->rx_out_of_buffer);
298 }
299
300 void mlx5e_update_stats(struct mlx5e_priv *priv)
301 {
302         mlx5e_update_q_counter(priv);
303         mlx5e_update_vport_counters(priv);
304         mlx5e_update_pport_counters(priv);
305         mlx5e_update_sw_counters(priv);
306 }
307
308 void mlx5e_update_stats_work(struct work_struct *work)
309 {
310         struct delayed_work *dwork = to_delayed_work(work);
311         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
312                                                update_stats_work);
313         mutex_lock(&priv->state_lock);
314         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
315                 priv->profile->update_stats(priv);
316                 queue_delayed_work(priv->wq, dwork,
317                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
318         }
319         mutex_unlock(&priv->state_lock);
320 }
321
322 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
323                               enum mlx5_dev_event event, unsigned long param)
324 {
325         struct mlx5e_priv *priv = vpriv;
326         struct ptp_clock_event ptp_event;
327         struct mlx5_eqe *eqe = NULL;
328
329         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
330                 return;
331
332         switch (event) {
333         case MLX5_DEV_EVENT_PORT_UP:
334         case MLX5_DEV_EVENT_PORT_DOWN:
335                 queue_work(priv->wq, &priv->update_carrier_work);
336                 break;
337         case MLX5_DEV_EVENT_PPS:
338                 eqe = (struct mlx5_eqe *)param;
339                 ptp_event.type = PTP_CLOCK_EXTTS;
340                 ptp_event.index = eqe->data.pps.pin;
341                 ptp_event.timestamp =
342                         timecounter_cyc2time(&priv->tstamp.clock,
343                                              be64_to_cpu(eqe->data.pps.time_stamp));
344                 mlx5e_pps_event_handler(vpriv, &ptp_event);
345                 break;
346         default:
347                 break;
348         }
349 }
350
351 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
352 {
353         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
354 }
355
356 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
357 {
358         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
359         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
360 }
361
362 static inline int mlx5e_get_wqe_mtt_sz(void)
363 {
364         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
365          * To avoid copying garbage after the mtt array, we allocate
366          * a little more.
367          */
368         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
369                      MLX5_UMR_MTT_ALIGNMENT);
370 }
371
372 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
373                                        struct mlx5e_umr_wqe *wqe, u16 ix)
374 {
375         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
376         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
377         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
378         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
379         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
380         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
381
382         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
383                                       ds_cnt);
384         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
385         cseg->imm       = rq->mkey_be;
386
387         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
388         ucseg->xlt_octowords =
389                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
390         ucseg->bsf_octowords =
391                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
392         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
393
394         dseg->lkey = sq->mkey_be;
395         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
396 }
397
398 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
399                                      struct mlx5e_channel *c)
400 {
401         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
402         int mtt_sz = mlx5e_get_wqe_mtt_sz();
403         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
404         int i;
405
406         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
407                                       GFP_KERNEL, cpu_to_node(c->cpu));
408         if (!rq->mpwqe.info)
409                 goto err_out;
410
411         /* We allocate more than mtt_sz as we will align the pointer */
412         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
413                                         cpu_to_node(c->cpu));
414         if (unlikely(!rq->mpwqe.mtt_no_align))
415                 goto err_free_wqe_info;
416
417         for (i = 0; i < wq_sz; i++) {
418                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
419
420                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
421                                         MLX5_UMR_ALIGN);
422                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
423                                                   PCI_DMA_TODEVICE);
424                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
425                         goto err_unmap_mtts;
426
427                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
428         }
429
430         return 0;
431
432 err_unmap_mtts:
433         while (--i >= 0) {
434                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
435
436                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
437                                  PCI_DMA_TODEVICE);
438         }
439         kfree(rq->mpwqe.mtt_no_align);
440 err_free_wqe_info:
441         kfree(rq->mpwqe.info);
442
443 err_out:
444         return -ENOMEM;
445 }
446
447 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
448 {
449         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
450         int mtt_sz = mlx5e_get_wqe_mtt_sz();
451         int i;
452
453         for (i = 0; i < wq_sz; i++) {
454                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
455
456                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
457                                  PCI_DMA_TODEVICE);
458         }
459         kfree(rq->mpwqe.mtt_no_align);
460         kfree(rq->mpwqe.info);
461 }
462
463 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv,
464                                  u64 npages, u8 page_shift,
465                                  struct mlx5_core_mkey *umr_mkey)
466 {
467         struct mlx5_core_dev *mdev = priv->mdev;
468         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
469         void *mkc;
470         u32 *in;
471         int err;
472
473         if (!MLX5E_VALID_NUM_MTTS(npages))
474                 return -EINVAL;
475
476         in = mlx5_vzalloc(inlen);
477         if (!in)
478                 return -ENOMEM;
479
480         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
481
482         MLX5_SET(mkc, mkc, free, 1);
483         MLX5_SET(mkc, mkc, umr_en, 1);
484         MLX5_SET(mkc, mkc, lw, 1);
485         MLX5_SET(mkc, mkc, lr, 1);
486         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
487
488         MLX5_SET(mkc, mkc, qpn, 0xffffff);
489         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
490         MLX5_SET64(mkc, mkc, len, npages << page_shift);
491         MLX5_SET(mkc, mkc, translations_octword_size,
492                  MLX5_MTT_OCTW(npages));
493         MLX5_SET(mkc, mkc, log_page_size, page_shift);
494
495         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
496
497         kvfree(in);
498         return err;
499 }
500
501 static int mlx5e_create_rq_umr_mkey(struct mlx5e_rq *rq)
502 {
503         struct mlx5e_priv *priv = rq->priv;
504         u64 num_mtts = MLX5E_REQUIRED_MTTS(BIT(priv->params.log_rq_size));
505
506         return mlx5e_create_umr_mkey(priv, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
507 }
508
509 static int mlx5e_create_rq(struct mlx5e_channel *c,
510                            struct mlx5e_rq_param *param,
511                            struct mlx5e_rq *rq)
512 {
513         struct mlx5e_priv *priv = c->priv;
514         struct mlx5_core_dev *mdev = priv->mdev;
515         void *rqc = param->rqc;
516         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
517         u32 byte_count;
518         u32 frag_sz;
519         int npages;
520         int wq_sz;
521         int err;
522         int i;
523
524         param->wq.db_numa_node = cpu_to_node(c->cpu);
525
526         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
527                                 &rq->wq_ctrl);
528         if (err)
529                 return err;
530
531         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
532
533         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
534
535         rq->wq_type = priv->params.rq_wq_type;
536         rq->pdev    = c->pdev;
537         rq->netdev  = c->netdev;
538         rq->tstamp  = &priv->tstamp;
539         rq->channel = c;
540         rq->ix      = c->ix;
541         rq->priv    = c->priv;
542
543         rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
544         if (IS_ERR(rq->xdp_prog)) {
545                 err = PTR_ERR(rq->xdp_prog);
546                 rq->xdp_prog = NULL;
547                 goto err_rq_wq_destroy;
548         }
549
550         if (rq->xdp_prog) {
551                 rq->buff.map_dir = DMA_BIDIRECTIONAL;
552                 rq->rx_headroom = XDP_PACKET_HEADROOM;
553         } else {
554                 rq->buff.map_dir = DMA_FROM_DEVICE;
555                 rq->rx_headroom = MLX5_RX_HEADROOM;
556         }
557
558         switch (priv->params.rq_wq_type) {
559         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
560                 if (mlx5e_is_vf_vport_rep(priv)) {
561                         err = -EINVAL;
562                         goto err_rq_wq_destroy;
563                 }
564
565                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
566                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
567                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
568
569                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
570                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
571
572                 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
573                 byte_count = rq->buff.wqe_sz;
574
575                 err = mlx5e_create_rq_umr_mkey(rq);
576                 if (err)
577                         goto err_rq_wq_destroy;
578                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
579
580                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
581                 if (err)
582                         goto err_destroy_umr_mkey;
583                 break;
584         default: /* MLX5_WQ_TYPE_LINKED_LIST */
585                 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
586                                             GFP_KERNEL, cpu_to_node(c->cpu));
587                 if (!rq->dma_info) {
588                         err = -ENOMEM;
589                         goto err_rq_wq_destroy;
590                 }
591
592                 if (mlx5e_is_vf_vport_rep(priv))
593                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
594                 else
595                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
596
597                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
598                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
599
600                 rq->buff.wqe_sz = (priv->params.lro_en) ?
601                                 priv->params.lro_wqe_sz :
602                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
603                 byte_count = rq->buff.wqe_sz;
604
605                 /* calc the required page order */
606                 frag_sz = rq->rx_headroom +
607                           byte_count /* packet data */ +
608                           SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
609                 frag_sz = SKB_DATA_ALIGN(frag_sz);
610
611                 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
612                 rq->buff.page_order = order_base_2(npages);
613
614                 byte_count |= MLX5_HW_START_PADDING;
615                 rq->mkey_be = c->mkey_be;
616         }
617
618         for (i = 0; i < wq_sz; i++) {
619                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
620
621                 wqe->data.byte_count = cpu_to_be32(byte_count);
622                 wqe->data.lkey = rq->mkey_be;
623         }
624
625         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
626         rq->am.mode = priv->params.rx_cq_period_mode;
627
628         rq->page_cache.head = 0;
629         rq->page_cache.tail = 0;
630
631         return 0;
632
633 err_destroy_umr_mkey:
634         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
635
636 err_rq_wq_destroy:
637         if (rq->xdp_prog)
638                 bpf_prog_put(rq->xdp_prog);
639         mlx5_wq_destroy(&rq->wq_ctrl);
640
641         return err;
642 }
643
644 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
645 {
646         int i;
647
648         if (rq->xdp_prog)
649                 bpf_prog_put(rq->xdp_prog);
650
651         switch (rq->wq_type) {
652         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
653                 mlx5e_rq_free_mpwqe_info(rq);
654                 mlx5_core_destroy_mkey(rq->priv->mdev, &rq->umr_mkey);
655                 break;
656         default: /* MLX5_WQ_TYPE_LINKED_LIST */
657                 kfree(rq->dma_info);
658         }
659
660         for (i = rq->page_cache.head; i != rq->page_cache.tail;
661              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
662                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
663
664                 mlx5e_page_release(rq, dma_info, false);
665         }
666         mlx5_wq_destroy(&rq->wq_ctrl);
667 }
668
669 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
670 {
671         struct mlx5e_priv *priv = rq->priv;
672         struct mlx5_core_dev *mdev = priv->mdev;
673
674         void *in;
675         void *rqc;
676         void *wq;
677         int inlen;
678         int err;
679
680         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
681                 sizeof(u64) * rq->wq_ctrl.buf.npages;
682         in = mlx5_vzalloc(inlen);
683         if (!in)
684                 return -ENOMEM;
685
686         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
687         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
688
689         memcpy(rqc, param->rqc, sizeof(param->rqc));
690
691         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
692         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
693         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
694         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
695                                                 MLX5_ADAPTER_PAGE_SHIFT);
696         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
697
698         mlx5_fill_page_array(&rq->wq_ctrl.buf,
699                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
700
701         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
702
703         kvfree(in);
704
705         return err;
706 }
707
708 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
709                                  int next_state)
710 {
711         struct mlx5e_channel *c = rq->channel;
712         struct mlx5e_priv *priv = c->priv;
713         struct mlx5_core_dev *mdev = priv->mdev;
714
715         void *in;
716         void *rqc;
717         int inlen;
718         int err;
719
720         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
721         in = mlx5_vzalloc(inlen);
722         if (!in)
723                 return -ENOMEM;
724
725         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
726
727         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
728         MLX5_SET(rqc, rqc, state, next_state);
729
730         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
731
732         kvfree(in);
733
734         return err;
735 }
736
737 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
738 {
739         struct mlx5e_channel *c = rq->channel;
740         struct mlx5e_priv *priv = c->priv;
741         struct mlx5_core_dev *mdev = priv->mdev;
742
743         void *in;
744         void *rqc;
745         int inlen;
746         int err;
747
748         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
749         in = mlx5_vzalloc(inlen);
750         if (!in)
751                 return -ENOMEM;
752
753         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
754
755         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
756         MLX5_SET64(modify_rq_in, in, modify_bitmask,
757                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
758         MLX5_SET(rqc, rqc, vsd, vsd);
759         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
760
761         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
762
763         kvfree(in);
764
765         return err;
766 }
767
768 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
769 {
770         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
771 }
772
773 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
774 {
775         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
776         struct mlx5e_channel *c = rq->channel;
777         struct mlx5e_priv *priv = c->priv;
778         struct mlx5_wq_ll *wq = &rq->wq;
779
780         while (time_before(jiffies, exp_time)) {
781                 if (wq->cur_sz >= priv->params.min_rx_wqes)
782                         return 0;
783
784                 msleep(20);
785         }
786
787         return -ETIMEDOUT;
788 }
789
790 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
791 {
792         struct mlx5_wq_ll *wq = &rq->wq;
793         struct mlx5e_rx_wqe *wqe;
794         __be16 wqe_ix_be;
795         u16 wqe_ix;
796
797         /* UMR WQE (if in progress) is always at wq->head */
798         if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
799                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
800
801         while (!mlx5_wq_ll_is_empty(wq)) {
802                 wqe_ix_be = *wq->tail_next;
803                 wqe_ix    = be16_to_cpu(wqe_ix_be);
804                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
805                 rq->dealloc_wqe(rq, wqe_ix);
806                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
807                                &wqe->next.next_wqe_index);
808         }
809 }
810
811 static int mlx5e_open_rq(struct mlx5e_channel *c,
812                          struct mlx5e_rq_param *param,
813                          struct mlx5e_rq *rq)
814 {
815         struct mlx5e_sq *sq = &c->icosq;
816         u16 pi = sq->pc & sq->wq.sz_m1;
817         int err;
818
819         err = mlx5e_create_rq(c, param, rq);
820         if (err)
821                 return err;
822
823         err = mlx5e_enable_rq(rq, param);
824         if (err)
825                 goto err_destroy_rq;
826
827         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
828         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
829         if (err)
830                 goto err_disable_rq;
831
832         if (param->am_enabled)
833                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
834
835         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
836         sq->db.ico_wqe[pi].num_wqebbs = 1;
837         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
838
839         return 0;
840
841 err_disable_rq:
842         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
843         mlx5e_disable_rq(rq);
844 err_destroy_rq:
845         mlx5e_destroy_rq(rq);
846
847         return err;
848 }
849
850 static void mlx5e_close_rq(struct mlx5e_rq *rq)
851 {
852         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
853         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
854         cancel_work_sync(&rq->am.work);
855
856         mlx5e_disable_rq(rq);
857         mlx5e_free_rx_descs(rq);
858         mlx5e_destroy_rq(rq);
859 }
860
861 static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
862 {
863         kfree(sq->db.xdp.di);
864         kfree(sq->db.xdp.wqe_info);
865 }
866
867 static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
868 {
869         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
870
871         sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
872                                      GFP_KERNEL, numa);
873         sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
874                                            GFP_KERNEL, numa);
875         if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
876                 mlx5e_free_sq_xdp_db(sq);
877                 return -ENOMEM;
878         }
879
880         return 0;
881 }
882
883 static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
884 {
885         kfree(sq->db.ico_wqe);
886 }
887
888 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
889 {
890         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
891
892         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
893                                       GFP_KERNEL, numa);
894         if (!sq->db.ico_wqe)
895                 return -ENOMEM;
896
897         return 0;
898 }
899
900 static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
901 {
902         kfree(sq->db.txq.wqe_info);
903         kfree(sq->db.txq.dma_fifo);
904         kfree(sq->db.txq.skb);
905 }
906
907 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
908 {
909         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
910         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
911
912         sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
913                                       GFP_KERNEL, numa);
914         sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
915                                            GFP_KERNEL, numa);
916         sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
917                                            GFP_KERNEL, numa);
918         if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
919                 mlx5e_free_sq_txq_db(sq);
920                 return -ENOMEM;
921         }
922
923         sq->dma_fifo_mask = df_sz - 1;
924
925         return 0;
926 }
927
928 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
929 {
930         switch (sq->type) {
931         case MLX5E_SQ_TXQ:
932                 mlx5e_free_sq_txq_db(sq);
933                 break;
934         case MLX5E_SQ_ICO:
935                 mlx5e_free_sq_ico_db(sq);
936                 break;
937         case MLX5E_SQ_XDP:
938                 mlx5e_free_sq_xdp_db(sq);
939                 break;
940         }
941 }
942
943 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
944 {
945         switch (sq->type) {
946         case MLX5E_SQ_TXQ:
947                 return mlx5e_alloc_sq_txq_db(sq, numa);
948         case MLX5E_SQ_ICO:
949                 return mlx5e_alloc_sq_ico_db(sq, numa);
950         case MLX5E_SQ_XDP:
951                 return mlx5e_alloc_sq_xdp_db(sq, numa);
952         }
953
954         return 0;
955 }
956
957 static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
958 {
959         switch (sq_type) {
960         case MLX5E_SQ_ICO:
961                 return MLX5E_ICOSQ_MAX_WQEBBS;
962         case MLX5E_SQ_XDP:
963                 return MLX5E_XDP_TX_WQEBBS;
964         }
965         return MLX5_SEND_WQE_MAX_WQEBBS;
966 }
967
968 static int mlx5e_create_sq(struct mlx5e_channel *c,
969                            int tc,
970                            struct mlx5e_sq_param *param,
971                            struct mlx5e_sq *sq)
972 {
973         struct mlx5e_priv *priv = c->priv;
974         struct mlx5_core_dev *mdev = priv->mdev;
975
976         void *sqc = param->sqc;
977         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
978         int err;
979
980         sq->type      = param->type;
981         sq->pdev      = c->pdev;
982         sq->tstamp    = &priv->tstamp;
983         sq->mkey_be   = c->mkey_be;
984         sq->channel   = c;
985         sq->tc        = tc;
986
987         err = mlx5_alloc_bfreg(mdev, &sq->bfreg, MLX5_CAP_GEN(mdev, bf), false);
988         if (err)
989                 return err;
990
991         param->wq.db_numa_node = cpu_to_node(c->cpu);
992
993         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
994                                  &sq->wq_ctrl);
995         if (err)
996                 goto err_unmap_free_uar;
997
998         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
999         if (sq->bfreg.wc)
1000                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
1001
1002         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1003         sq->max_inline  = param->max_inline;
1004         sq->min_inline_mode =
1005                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT ?
1006                 param->min_inline_mode : 0;
1007
1008         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
1009         if (err)
1010                 goto err_sq_wq_destroy;
1011
1012         if (sq->type == MLX5E_SQ_TXQ) {
1013                 int txq_ix;
1014
1015                 txq_ix = c->ix + tc * priv->params.num_channels;
1016                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
1017                 priv->txq_to_sq_map[txq_ix] = sq;
1018         }
1019
1020         sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
1021         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
1022
1023         return 0;
1024
1025 err_sq_wq_destroy:
1026         mlx5_wq_destroy(&sq->wq_ctrl);
1027
1028 err_unmap_free_uar:
1029         mlx5_free_bfreg(mdev, &sq->bfreg);
1030
1031         return err;
1032 }
1033
1034 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
1035 {
1036         struct mlx5e_channel *c = sq->channel;
1037         struct mlx5e_priv *priv = c->priv;
1038
1039         mlx5e_free_sq_db(sq);
1040         mlx5_wq_destroy(&sq->wq_ctrl);
1041         mlx5_free_bfreg(priv->mdev, &sq->bfreg);
1042 }
1043
1044 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1045 {
1046         struct mlx5e_channel *c = sq->channel;
1047         struct mlx5e_priv *priv = c->priv;
1048         struct mlx5_core_dev *mdev = priv->mdev;
1049
1050         void *in;
1051         void *sqc;
1052         void *wq;
1053         int inlen;
1054         int err;
1055
1056         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1057                 sizeof(u64) * sq->wq_ctrl.buf.npages;
1058         in = mlx5_vzalloc(inlen);
1059         if (!in)
1060                 return -ENOMEM;
1061
1062         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1063         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1064
1065         memcpy(sqc, param->sqc, sizeof(param->sqc));
1066
1067         MLX5_SET(sqc,  sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1068                                        0 : priv->tisn[sq->tc]);
1069         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
1070         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
1071         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
1072         MLX5_SET(sqc,  sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
1073
1074         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1075         MLX5_SET(wq,   wq, uar_page,      sq->bfreg.index);
1076         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
1077                                           MLX5_ADAPTER_PAGE_SHIFT);
1078         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
1079
1080         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1081                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1082
1083         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1084
1085         kvfree(in);
1086
1087         return err;
1088 }
1089
1090 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1091                            int next_state, bool update_rl, int rl_index)
1092 {
1093         struct mlx5e_channel *c = sq->channel;
1094         struct mlx5e_priv *priv = c->priv;
1095         struct mlx5_core_dev *mdev = priv->mdev;
1096
1097         void *in;
1098         void *sqc;
1099         int inlen;
1100         int err;
1101
1102         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1103         in = mlx5_vzalloc(inlen);
1104         if (!in)
1105                 return -ENOMEM;
1106
1107         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1108
1109         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1110         MLX5_SET(sqc, sqc, state, next_state);
1111         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1112                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1113                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
1114         }
1115
1116         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
1117
1118         kvfree(in);
1119
1120         return err;
1121 }
1122
1123 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1124 {
1125         struct mlx5e_channel *c = sq->channel;
1126         struct mlx5e_priv *priv = c->priv;
1127         struct mlx5_core_dev *mdev = priv->mdev;
1128
1129         mlx5_core_destroy_sq(mdev, sq->sqn);
1130         if (sq->rate_limit)
1131                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1132 }
1133
1134 static int mlx5e_open_sq(struct mlx5e_channel *c,
1135                          int tc,
1136                          struct mlx5e_sq_param *param,
1137                          struct mlx5e_sq *sq)
1138 {
1139         int err;
1140
1141         err = mlx5e_create_sq(c, tc, param, sq);
1142         if (err)
1143                 return err;
1144
1145         err = mlx5e_enable_sq(sq, param);
1146         if (err)
1147                 goto err_destroy_sq;
1148
1149         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1150         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1151                               false, 0);
1152         if (err)
1153                 goto err_disable_sq;
1154
1155         if (sq->txq) {
1156                 netdev_tx_reset_queue(sq->txq);
1157                 netif_tx_start_queue(sq->txq);
1158         }
1159
1160         return 0;
1161
1162 err_disable_sq:
1163         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1164         mlx5e_disable_sq(sq);
1165 err_destroy_sq:
1166         mlx5e_destroy_sq(sq);
1167
1168         return err;
1169 }
1170
1171 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1172 {
1173         __netif_tx_lock_bh(txq);
1174         netif_tx_stop_queue(txq);
1175         __netif_tx_unlock_bh(txq);
1176 }
1177
1178 static void mlx5e_close_sq(struct mlx5e_sq *sq)
1179 {
1180         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1181         /* prevent netif_tx_wake_queue */
1182         napi_synchronize(&sq->channel->napi);
1183
1184         if (sq->txq) {
1185                 netif_tx_disable_queue(sq->txq);
1186
1187                 /* last doorbell out, godspeed .. */
1188                 if (mlx5e_sq_has_room_for(sq, 1)) {
1189                         sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1190                         mlx5e_send_nop(sq, true);
1191                 }
1192         }
1193
1194         mlx5e_disable_sq(sq);
1195         mlx5e_free_sq_descs(sq);
1196         mlx5e_destroy_sq(sq);
1197 }
1198
1199 static int mlx5e_create_cq(struct mlx5e_channel *c,
1200                            struct mlx5e_cq_param *param,
1201                            struct mlx5e_cq *cq)
1202 {
1203         struct mlx5e_priv *priv = c->priv;
1204         struct mlx5_core_dev *mdev = priv->mdev;
1205         struct mlx5_core_cq *mcq = &cq->mcq;
1206         int eqn_not_used;
1207         unsigned int irqn;
1208         int err;
1209         u32 i;
1210
1211         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1212         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1213         param->eq_ix   = c->ix;
1214
1215         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1216                                &cq->wq_ctrl);
1217         if (err)
1218                 return err;
1219
1220         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1221
1222         cq->napi        = &c->napi;
1223
1224         mcq->cqe_sz     = 64;
1225         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1226         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1227         *mcq->set_ci_db = 0;
1228         *mcq->arm_db    = 0;
1229         mcq->vector     = param->eq_ix;
1230         mcq->comp       = mlx5e_completion_event;
1231         mcq->event      = mlx5e_cq_error_event;
1232         mcq->irqn       = irqn;
1233
1234         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1235                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1236
1237                 cqe->op_own = 0xf1;
1238         }
1239
1240         cq->channel = c;
1241         cq->priv = priv;
1242
1243         return 0;
1244 }
1245
1246 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1247 {
1248         mlx5_cqwq_destroy(&cq->wq_ctrl);
1249 }
1250
1251 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1252 {
1253         struct mlx5e_priv *priv = cq->priv;
1254         struct mlx5_core_dev *mdev = priv->mdev;
1255         struct mlx5_core_cq *mcq = &cq->mcq;
1256
1257         void *in;
1258         void *cqc;
1259         int inlen;
1260         unsigned int irqn_not_used;
1261         int eqn;
1262         int err;
1263
1264         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1265                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1266         in = mlx5_vzalloc(inlen);
1267         if (!in)
1268                 return -ENOMEM;
1269
1270         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1271
1272         memcpy(cqc, param->cqc, sizeof(param->cqc));
1273
1274         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1275                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1276
1277         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1278
1279         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1280         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1281         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1282         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1283                                             MLX5_ADAPTER_PAGE_SHIFT);
1284         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1285
1286         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1287
1288         kvfree(in);
1289
1290         if (err)
1291                 return err;
1292
1293         mlx5e_cq_arm(cq);
1294
1295         return 0;
1296 }
1297
1298 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1299 {
1300         struct mlx5e_priv *priv = cq->priv;
1301         struct mlx5_core_dev *mdev = priv->mdev;
1302
1303         mlx5_core_destroy_cq(mdev, &cq->mcq);
1304 }
1305
1306 static int mlx5e_open_cq(struct mlx5e_channel *c,
1307                          struct mlx5e_cq_param *param,
1308                          struct mlx5e_cq *cq,
1309                          struct mlx5e_cq_moder moderation)
1310 {
1311         int err;
1312         struct mlx5e_priv *priv = c->priv;
1313         struct mlx5_core_dev *mdev = priv->mdev;
1314
1315         err = mlx5e_create_cq(c, param, cq);
1316         if (err)
1317                 return err;
1318
1319         err = mlx5e_enable_cq(cq, param);
1320         if (err)
1321                 goto err_destroy_cq;
1322
1323         if (MLX5_CAP_GEN(mdev, cq_moderation))
1324                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1325                                                moderation.usec,
1326                                                moderation.pkts);
1327         return 0;
1328
1329 err_destroy_cq:
1330         mlx5e_destroy_cq(cq);
1331
1332         return err;
1333 }
1334
1335 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1336 {
1337         mlx5e_disable_cq(cq);
1338         mlx5e_destroy_cq(cq);
1339 }
1340
1341 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1342 {
1343         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1344 }
1345
1346 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1347                              struct mlx5e_channel_param *cparam)
1348 {
1349         struct mlx5e_priv *priv = c->priv;
1350         int err;
1351         int tc;
1352
1353         for (tc = 0; tc < c->num_tc; tc++) {
1354                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1355                                     priv->params.tx_cq_moderation);
1356                 if (err)
1357                         goto err_close_tx_cqs;
1358         }
1359
1360         return 0;
1361
1362 err_close_tx_cqs:
1363         for (tc--; tc >= 0; tc--)
1364                 mlx5e_close_cq(&c->sq[tc].cq);
1365
1366         return err;
1367 }
1368
1369 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1370 {
1371         int tc;
1372
1373         for (tc = 0; tc < c->num_tc; tc++)
1374                 mlx5e_close_cq(&c->sq[tc].cq);
1375 }
1376
1377 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1378                           struct mlx5e_channel_param *cparam)
1379 {
1380         int err;
1381         int tc;
1382
1383         for (tc = 0; tc < c->num_tc; tc++) {
1384                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1385                 if (err)
1386                         goto err_close_sqs;
1387         }
1388
1389         return 0;
1390
1391 err_close_sqs:
1392         for (tc--; tc >= 0; tc--)
1393                 mlx5e_close_sq(&c->sq[tc]);
1394
1395         return err;
1396 }
1397
1398 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1399 {
1400         int tc;
1401
1402         for (tc = 0; tc < c->num_tc; tc++)
1403                 mlx5e_close_sq(&c->sq[tc]);
1404 }
1405
1406 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1407 {
1408         int i;
1409
1410         for (i = 0; i < priv->profile->max_tc; i++)
1411                 priv->channeltc_to_txq_map[ix][i] =
1412                         ix + i * priv->params.num_channels;
1413 }
1414
1415 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1416                                 struct mlx5e_sq *sq, u32 rate)
1417 {
1418         struct mlx5e_priv *priv = netdev_priv(dev);
1419         struct mlx5_core_dev *mdev = priv->mdev;
1420         u16 rl_index = 0;
1421         int err;
1422
1423         if (rate == sq->rate_limit)
1424                 /* nothing to do */
1425                 return 0;
1426
1427         if (sq->rate_limit)
1428                 /* remove current rl index to free space to next ones */
1429                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1430
1431         sq->rate_limit = 0;
1432
1433         if (rate) {
1434                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1435                 if (err) {
1436                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1437                                    rate, err);
1438                         return err;
1439                 }
1440         }
1441
1442         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1443                               MLX5_SQC_STATE_RDY, true, rl_index);
1444         if (err) {
1445                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1446                            rate, err);
1447                 /* remove the rate from the table */
1448                 if (rate)
1449                         mlx5_rl_remove_rate(mdev, rate);
1450                 return err;
1451         }
1452
1453         sq->rate_limit = rate;
1454         return 0;
1455 }
1456
1457 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1458 {
1459         struct mlx5e_priv *priv = netdev_priv(dev);
1460         struct mlx5_core_dev *mdev = priv->mdev;
1461         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1462         int err = 0;
1463
1464         if (!mlx5_rl_is_supported(mdev)) {
1465                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1466                 return -EINVAL;
1467         }
1468
1469         /* rate is given in Mb/sec, HW config is in Kb/sec */
1470         rate = rate << 10;
1471
1472         /* Check whether rate in valid range, 0 is always valid */
1473         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1474                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1475                 return -ERANGE;
1476         }
1477
1478         mutex_lock(&priv->state_lock);
1479         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1480                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1481         if (!err)
1482                 priv->tx_rates[index] = rate;
1483         mutex_unlock(&priv->state_lock);
1484
1485         return err;
1486 }
1487
1488 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1489                               struct mlx5e_channel_param *cparam,
1490                               struct mlx5e_channel **cp)
1491 {
1492         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1493         struct net_device *netdev = priv->netdev;
1494         struct mlx5e_cq_moder rx_cq_profile;
1495         int cpu = mlx5e_get_cpu(priv, ix);
1496         struct mlx5e_channel *c;
1497         struct mlx5e_sq *sq;
1498         int err;
1499         int i;
1500
1501         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1502         if (!c)
1503                 return -ENOMEM;
1504
1505         c->priv     = priv;
1506         c->ix       = ix;
1507         c->cpu      = cpu;
1508         c->pdev     = &priv->mdev->pdev->dev;
1509         c->netdev   = priv->netdev;
1510         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1511         c->num_tc   = priv->params.num_tc;
1512         c->xdp      = !!priv->xdp_prog;
1513
1514         if (priv->params.rx_am_enabled)
1515                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1516         else
1517                 rx_cq_profile = priv->params.rx_cq_moderation;
1518
1519         mlx5e_build_channeltc_to_txq_map(priv, ix);
1520
1521         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1522
1523         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1524         if (err)
1525                 goto err_napi_del;
1526
1527         err = mlx5e_open_tx_cqs(c, cparam);
1528         if (err)
1529                 goto err_close_icosq_cq;
1530
1531         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1532                             rx_cq_profile);
1533         if (err)
1534                 goto err_close_tx_cqs;
1535
1536         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1537         err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1538                                      priv->params.tx_cq_moderation) : 0;
1539         if (err)
1540                 goto err_close_rx_cq;
1541
1542         napi_enable(&c->napi);
1543
1544         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1545         if (err)
1546                 goto err_disable_napi;
1547
1548         err = mlx5e_open_sqs(c, cparam);
1549         if (err)
1550                 goto err_close_icosq;
1551
1552         for (i = 0; i < priv->params.num_tc; i++) {
1553                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1554
1555                 if (priv->tx_rates[txq_ix]) {
1556                         sq = priv->txq_to_sq_map[txq_ix];
1557                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1558                                              priv->tx_rates[txq_ix]);
1559                 }
1560         }
1561
1562         err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1563         if (err)
1564                 goto err_close_sqs;
1565
1566         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1567         if (err)
1568                 goto err_close_xdp_sq;
1569
1570         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1571         *cp = c;
1572
1573         return 0;
1574 err_close_xdp_sq:
1575         if (c->xdp)
1576                 mlx5e_close_sq(&c->xdp_sq);
1577
1578 err_close_sqs:
1579         mlx5e_close_sqs(c);
1580
1581 err_close_icosq:
1582         mlx5e_close_sq(&c->icosq);
1583
1584 err_disable_napi:
1585         napi_disable(&c->napi);
1586         if (c->xdp)
1587                 mlx5e_close_cq(&c->xdp_sq.cq);
1588
1589 err_close_rx_cq:
1590         mlx5e_close_cq(&c->rq.cq);
1591
1592 err_close_tx_cqs:
1593         mlx5e_close_tx_cqs(c);
1594
1595 err_close_icosq_cq:
1596         mlx5e_close_cq(&c->icosq.cq);
1597
1598 err_napi_del:
1599         netif_napi_del(&c->napi);
1600         kfree(c);
1601
1602         return err;
1603 }
1604
1605 static void mlx5e_close_channel(struct mlx5e_channel *c)
1606 {
1607         mlx5e_close_rq(&c->rq);
1608         if (c->xdp)
1609                 mlx5e_close_sq(&c->xdp_sq);
1610         mlx5e_close_sqs(c);
1611         mlx5e_close_sq(&c->icosq);
1612         napi_disable(&c->napi);
1613         if (c->xdp)
1614                 mlx5e_close_cq(&c->xdp_sq.cq);
1615         mlx5e_close_cq(&c->rq.cq);
1616         mlx5e_close_tx_cqs(c);
1617         mlx5e_close_cq(&c->icosq.cq);
1618         netif_napi_del(&c->napi);
1619
1620         kfree(c);
1621 }
1622
1623 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1624                                  struct mlx5e_rq_param *param)
1625 {
1626         void *rqc = param->rqc;
1627         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1628
1629         switch (priv->params.rq_wq_type) {
1630         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1631                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1632                          priv->params.mpwqe_log_num_strides - 9);
1633                 MLX5_SET(wq, wq, log_wqe_stride_size,
1634                          priv->params.mpwqe_log_stride_sz - 6);
1635                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1636                 break;
1637         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1638                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1639         }
1640
1641         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1642         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1643         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1644         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1645         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1646
1647         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1648         param->wq.linear = 1;
1649
1650         param->am_enabled = priv->params.rx_am_enabled;
1651 }
1652
1653 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1654 {
1655         void *rqc = param->rqc;
1656         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1657
1658         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1659         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1660 }
1661
1662 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1663                                         struct mlx5e_sq_param *param)
1664 {
1665         void *sqc = param->sqc;
1666         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1667
1668         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1669         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1670
1671         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1672 }
1673
1674 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1675                                  struct mlx5e_sq_param *param)
1676 {
1677         void *sqc = param->sqc;
1678         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1679
1680         mlx5e_build_sq_param_common(priv, param);
1681         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1682
1683         param->max_inline = priv->params.tx_max_inline;
1684         param->min_inline_mode = priv->params.tx_min_inline_mode;
1685         param->type = MLX5E_SQ_TXQ;
1686 }
1687
1688 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1689                                         struct mlx5e_cq_param *param)
1690 {
1691         void *cqc = param->cqc;
1692
1693         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1694 }
1695
1696 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1697                                     struct mlx5e_cq_param *param)
1698 {
1699         void *cqc = param->cqc;
1700         u8 log_cq_size;
1701
1702         switch (priv->params.rq_wq_type) {
1703         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1704                 log_cq_size = priv->params.log_rq_size +
1705                         priv->params.mpwqe_log_num_strides;
1706                 break;
1707         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1708                 log_cq_size = priv->params.log_rq_size;
1709         }
1710
1711         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1712         if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1713                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1714                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1715         }
1716
1717         mlx5e_build_common_cq_param(priv, param);
1718
1719         param->cq_period_mode = priv->params.rx_cq_period_mode;
1720 }
1721
1722 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1723                                     struct mlx5e_cq_param *param)
1724 {
1725         void *cqc = param->cqc;
1726
1727         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1728
1729         mlx5e_build_common_cq_param(priv, param);
1730
1731         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1732 }
1733
1734 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1735                                      struct mlx5e_cq_param *param,
1736                                      u8 log_wq_size)
1737 {
1738         void *cqc = param->cqc;
1739
1740         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1741
1742         mlx5e_build_common_cq_param(priv, param);
1743
1744         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1745 }
1746
1747 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1748                                     struct mlx5e_sq_param *param,
1749                                     u8 log_wq_size)
1750 {
1751         void *sqc = param->sqc;
1752         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1753
1754         mlx5e_build_sq_param_common(priv, param);
1755
1756         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1757         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1758
1759         param->type = MLX5E_SQ_ICO;
1760 }
1761
1762 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1763                                     struct mlx5e_sq_param *param)
1764 {
1765         void *sqc = param->sqc;
1766         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1767
1768         mlx5e_build_sq_param_common(priv, param);
1769         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1770
1771         param->max_inline = priv->params.tx_max_inline;
1772         /* FOR XDP SQs will support only L2 inline mode */
1773         param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1774         param->type = MLX5E_SQ_XDP;
1775 }
1776
1777 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1778 {
1779         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1780
1781         mlx5e_build_rq_param(priv, &cparam->rq);
1782         mlx5e_build_sq_param(priv, &cparam->sq);
1783         mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
1784         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1785         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1786         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1787         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1788 }
1789
1790 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1791 {
1792         struct mlx5e_channel_param *cparam;
1793         int nch = priv->params.num_channels;
1794         int err = -ENOMEM;
1795         int i;
1796         int j;
1797
1798         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1799                                 GFP_KERNEL);
1800
1801         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1802                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1803
1804         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1805
1806         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1807                 goto err_free_txq_to_sq_map;
1808
1809         mlx5e_build_channel_param(priv, cparam);
1810
1811         for (i = 0; i < nch; i++) {
1812                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1813                 if (err)
1814                         goto err_close_channels;
1815         }
1816
1817         for (j = 0; j < nch; j++) {
1818                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1819                 if (err)
1820                         goto err_close_channels;
1821         }
1822
1823         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1824          * polling for inactive tx queues.
1825          */
1826         netif_tx_start_all_queues(priv->netdev);
1827
1828         kfree(cparam);
1829         return 0;
1830
1831 err_close_channels:
1832         for (i--; i >= 0; i--)
1833                 mlx5e_close_channel(priv->channel[i]);
1834
1835 err_free_txq_to_sq_map:
1836         kfree(priv->txq_to_sq_map);
1837         kfree(priv->channel);
1838         kfree(cparam);
1839
1840         return err;
1841 }
1842
1843 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1844 {
1845         int i;
1846
1847         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1848          * polling for inactive tx queues.
1849          */
1850         netif_tx_stop_all_queues(priv->netdev);
1851         netif_tx_disable(priv->netdev);
1852
1853         for (i = 0; i < priv->params.num_channels; i++)
1854                 mlx5e_close_channel(priv->channel[i]);
1855
1856         kfree(priv->txq_to_sq_map);
1857         kfree(priv->channel);
1858 }
1859
1860 static int mlx5e_rx_hash_fn(int hfunc)
1861 {
1862         return (hfunc == ETH_RSS_HASH_TOP) ?
1863                MLX5_RX_HASH_FN_TOEPLITZ :
1864                MLX5_RX_HASH_FN_INVERTED_XOR8;
1865 }
1866
1867 static int mlx5e_bits_invert(unsigned long a, int size)
1868 {
1869         int inv = 0;
1870         int i;
1871
1872         for (i = 0; i < size; i++)
1873                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1874
1875         return inv;
1876 }
1877
1878 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1879 {
1880         int i;
1881
1882         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1883                 int ix = i;
1884                 u32 rqn;
1885
1886                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1887                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1888
1889                 ix = priv->params.indirection_rqt[ix];
1890                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1891                                 priv->channel[ix]->rq.rqn :
1892                                 priv->drop_rq.rqn;
1893                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1894         }
1895 }
1896
1897 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1898                                       int ix)
1899 {
1900         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1901                         priv->channel[ix]->rq.rqn :
1902                         priv->drop_rq.rqn;
1903
1904         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1905 }
1906
1907 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1908                             int ix, struct mlx5e_rqt *rqt)
1909 {
1910         struct mlx5_core_dev *mdev = priv->mdev;
1911         void *rqtc;
1912         int inlen;
1913         int err;
1914         u32 *in;
1915
1916         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1917         in = mlx5_vzalloc(inlen);
1918         if (!in)
1919                 return -ENOMEM;
1920
1921         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1922
1923         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1924         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1925
1926         if (sz > 1) /* RSS */
1927                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1928         else
1929                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1930
1931         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1932         if (!err)
1933                 rqt->enabled = true;
1934
1935         kvfree(in);
1936         return err;
1937 }
1938
1939 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1940 {
1941         rqt->enabled = false;
1942         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1943 }
1944
1945 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1946 {
1947         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1948
1949         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1950 }
1951
1952 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1953 {
1954         struct mlx5e_rqt *rqt;
1955         int err;
1956         int ix;
1957
1958         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1959                 rqt = &priv->direct_tir[ix].rqt;
1960                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1961                 if (err)
1962                         goto err_destroy_rqts;
1963         }
1964
1965         return 0;
1966
1967 err_destroy_rqts:
1968         for (ix--; ix >= 0; ix--)
1969                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1970
1971         return err;
1972 }
1973
1974 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1975 {
1976         struct mlx5_core_dev *mdev = priv->mdev;
1977         void *rqtc;
1978         int inlen;
1979         u32 *in;
1980         int err;
1981
1982         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1983         in = mlx5_vzalloc(inlen);
1984         if (!in)
1985                 return -ENOMEM;
1986
1987         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1988
1989         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1990         if (sz > 1) /* RSS */
1991                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1992         else
1993                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1994
1995         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1996
1997         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1998
1999         kvfree(in);
2000
2001         return err;
2002 }
2003
2004 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
2005 {
2006         u32 rqtn;
2007         int ix;
2008
2009         if (priv->indir_rqt.enabled) {
2010                 rqtn = priv->indir_rqt.rqtn;
2011                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
2012         }
2013
2014         for (ix = 0; ix < priv->params.num_channels; ix++) {
2015                 if (!priv->direct_tir[ix].rqt.enabled)
2016                         continue;
2017                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2018                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
2019         }
2020 }
2021
2022 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
2023 {
2024         if (!priv->params.lro_en)
2025                 return;
2026
2027 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2028
2029         MLX5_SET(tirc, tirc, lro_enable_mask,
2030                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2031                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2032         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2033                  (priv->params.lro_wqe_sz -
2034                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2035         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
2036 }
2037
2038 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
2039 {
2040         MLX5_SET(tirc, tirc, rx_hash_fn,
2041                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
2042         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
2043                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2044                                              rx_hash_toeplitz_key);
2045                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2046                                                rx_hash_toeplitz_key);
2047
2048                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2049                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2050         }
2051 }
2052
2053 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2054 {
2055         struct mlx5_core_dev *mdev = priv->mdev;
2056
2057         void *in;
2058         void *tirc;
2059         int inlen;
2060         int err;
2061         int tt;
2062         int ix;
2063
2064         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2065         in = mlx5_vzalloc(inlen);
2066         if (!in)
2067                 return -ENOMEM;
2068
2069         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2070         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2071
2072         mlx5e_build_tir_ctx_lro(tirc, priv);
2073
2074         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2075                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2076                                            inlen);
2077                 if (err)
2078                         goto free_in;
2079         }
2080
2081         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2082                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2083                                            in, inlen);
2084                 if (err)
2085                         goto free_in;
2086         }
2087
2088 free_in:
2089         kvfree(in);
2090
2091         return err;
2092 }
2093
2094 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2095 {
2096         struct mlx5_core_dev *mdev = priv->mdev;
2097         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2098         int err;
2099
2100         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2101         if (err)
2102                 return err;
2103
2104         /* Update vport context MTU */
2105         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2106         return 0;
2107 }
2108
2109 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2110 {
2111         struct mlx5_core_dev *mdev = priv->mdev;
2112         u16 hw_mtu = 0;
2113         int err;
2114
2115         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2116         if (err || !hw_mtu) /* fallback to port oper mtu */
2117                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2118
2119         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2120 }
2121
2122 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2123 {
2124         struct mlx5e_priv *priv = netdev_priv(netdev);
2125         u16 mtu;
2126         int err;
2127
2128         err = mlx5e_set_mtu(priv, netdev->mtu);
2129         if (err)
2130                 return err;
2131
2132         mlx5e_query_mtu(priv, &mtu);
2133         if (mtu != netdev->mtu)
2134                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2135                             __func__, mtu, netdev->mtu);
2136
2137         netdev->mtu = mtu;
2138         return 0;
2139 }
2140
2141 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2142 {
2143         struct mlx5e_priv *priv = netdev_priv(netdev);
2144         int nch = priv->params.num_channels;
2145         int ntc = priv->params.num_tc;
2146         int tc;
2147
2148         netdev_reset_tc(netdev);
2149
2150         if (ntc == 1)
2151                 return;
2152
2153         netdev_set_num_tc(netdev, ntc);
2154
2155         /* Map netdev TCs to offset 0
2156          * We have our own UP to TXQ mapping for QoS
2157          */
2158         for (tc = 0; tc < ntc; tc++)
2159                 netdev_set_tc_queue(netdev, tc, nch, 0);
2160 }
2161
2162 int mlx5e_open_locked(struct net_device *netdev)
2163 {
2164         struct mlx5e_priv *priv = netdev_priv(netdev);
2165         struct mlx5_core_dev *mdev = priv->mdev;
2166         int num_txqs;
2167         int err;
2168
2169         set_bit(MLX5E_STATE_OPENED, &priv->state);
2170
2171         mlx5e_netdev_set_tcs(netdev);
2172
2173         num_txqs = priv->params.num_channels * priv->params.num_tc;
2174         netif_set_real_num_tx_queues(netdev, num_txqs);
2175         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2176
2177         err = mlx5e_open_channels(priv);
2178         if (err) {
2179                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2180                            __func__, err);
2181                 goto err_clear_state_opened_flag;
2182         }
2183
2184         err = mlx5e_refresh_tirs_self_loopback(priv->mdev, false);
2185         if (err) {
2186                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2187                            __func__, err);
2188                 goto err_close_channels;
2189         }
2190
2191         mlx5e_redirect_rqts(priv);
2192         mlx5e_update_carrier(priv);
2193         mlx5e_timestamp_init(priv);
2194 #ifdef CONFIG_RFS_ACCEL
2195         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2196 #endif
2197         if (priv->profile->update_stats)
2198                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2199
2200         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2201                 err = mlx5e_add_sqs_fwd_rules(priv);
2202                 if (err)
2203                         goto err_close_channels;
2204         }
2205         return 0;
2206
2207 err_close_channels:
2208         mlx5e_close_channels(priv);
2209 err_clear_state_opened_flag:
2210         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2211         return err;
2212 }
2213
2214 int mlx5e_open(struct net_device *netdev)
2215 {
2216         struct mlx5e_priv *priv = netdev_priv(netdev);
2217         int err;
2218
2219         mutex_lock(&priv->state_lock);
2220         err = mlx5e_open_locked(netdev);
2221         mutex_unlock(&priv->state_lock);
2222
2223         return err;
2224 }
2225
2226 int mlx5e_close_locked(struct net_device *netdev)
2227 {
2228         struct mlx5e_priv *priv = netdev_priv(netdev);
2229         struct mlx5_core_dev *mdev = priv->mdev;
2230
2231         /* May already be CLOSED in case a previous configuration operation
2232          * (e.g RX/TX queue size change) that involves close&open failed.
2233          */
2234         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2235                 return 0;
2236
2237         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2238
2239         if (MLX5_CAP_GEN(mdev, vport_group_manager))
2240                 mlx5e_remove_sqs_fwd_rules(priv);
2241
2242         mlx5e_timestamp_cleanup(priv);
2243         netif_carrier_off(priv->netdev);
2244         mlx5e_redirect_rqts(priv);
2245         mlx5e_close_channels(priv);
2246
2247         return 0;
2248 }
2249
2250 int mlx5e_close(struct net_device *netdev)
2251 {
2252         struct mlx5e_priv *priv = netdev_priv(netdev);
2253         int err;
2254
2255         if (!netif_device_present(netdev))
2256                 return -ENODEV;
2257
2258         mutex_lock(&priv->state_lock);
2259         err = mlx5e_close_locked(netdev);
2260         mutex_unlock(&priv->state_lock);
2261
2262         return err;
2263 }
2264
2265 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2266                                 struct mlx5e_rq *rq,
2267                                 struct mlx5e_rq_param *param)
2268 {
2269         struct mlx5_core_dev *mdev = priv->mdev;
2270         void *rqc = param->rqc;
2271         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2272         int err;
2273
2274         param->wq.db_numa_node = param->wq.buf_numa_node;
2275
2276         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2277                                 &rq->wq_ctrl);
2278         if (err)
2279                 return err;
2280
2281         rq->priv = priv;
2282
2283         return 0;
2284 }
2285
2286 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2287                                 struct mlx5e_cq *cq,
2288                                 struct mlx5e_cq_param *param)
2289 {
2290         struct mlx5_core_dev *mdev = priv->mdev;
2291         struct mlx5_core_cq *mcq = &cq->mcq;
2292         int eqn_not_used;
2293         unsigned int irqn;
2294         int err;
2295
2296         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2297                                &cq->wq_ctrl);
2298         if (err)
2299                 return err;
2300
2301         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2302
2303         mcq->cqe_sz     = 64;
2304         mcq->set_ci_db  = cq->wq_ctrl.db.db;
2305         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
2306         *mcq->set_ci_db = 0;
2307         *mcq->arm_db    = 0;
2308         mcq->vector     = param->eq_ix;
2309         mcq->comp       = mlx5e_completion_event;
2310         mcq->event      = mlx5e_cq_error_event;
2311         mcq->irqn       = irqn;
2312
2313         cq->priv = priv;
2314
2315         return 0;
2316 }
2317
2318 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2319 {
2320         struct mlx5e_cq_param cq_param;
2321         struct mlx5e_rq_param rq_param;
2322         struct mlx5e_rq *rq = &priv->drop_rq;
2323         struct mlx5e_cq *cq = &priv->drop_rq.cq;
2324         int err;
2325
2326         memset(&cq_param, 0, sizeof(cq_param));
2327         memset(&rq_param, 0, sizeof(rq_param));
2328         mlx5e_build_drop_rq_param(&rq_param);
2329
2330         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2331         if (err)
2332                 return err;
2333
2334         err = mlx5e_enable_cq(cq, &cq_param);
2335         if (err)
2336                 goto err_destroy_cq;
2337
2338         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2339         if (err)
2340                 goto err_disable_cq;
2341
2342         err = mlx5e_enable_rq(rq, &rq_param);
2343         if (err)
2344                 goto err_destroy_rq;
2345
2346         return 0;
2347
2348 err_destroy_rq:
2349         mlx5e_destroy_rq(&priv->drop_rq);
2350
2351 err_disable_cq:
2352         mlx5e_disable_cq(&priv->drop_rq.cq);
2353
2354 err_destroy_cq:
2355         mlx5e_destroy_cq(&priv->drop_rq.cq);
2356
2357         return err;
2358 }
2359
2360 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2361 {
2362         mlx5e_disable_rq(&priv->drop_rq);
2363         mlx5e_destroy_rq(&priv->drop_rq);
2364         mlx5e_disable_cq(&priv->drop_rq.cq);
2365         mlx5e_destroy_cq(&priv->drop_rq.cq);
2366 }
2367
2368 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2369 {
2370         struct mlx5_core_dev *mdev = priv->mdev;
2371         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2372         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2373
2374         MLX5_SET(tisc, tisc, prio, tc << 1);
2375         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2376
2377         if (mlx5_lag_is_lacp_owner(mdev))
2378                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2379
2380         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2381 }
2382
2383 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2384 {
2385         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2386 }
2387
2388 int mlx5e_create_tises(struct mlx5e_priv *priv)
2389 {
2390         int err;
2391         int tc;
2392
2393         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2394                 err = mlx5e_create_tis(priv, tc);
2395                 if (err)
2396                         goto err_close_tises;
2397         }
2398
2399         return 0;
2400
2401 err_close_tises:
2402         for (tc--; tc >= 0; tc--)
2403                 mlx5e_destroy_tis(priv, tc);
2404
2405         return err;
2406 }
2407
2408 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2409 {
2410         int tc;
2411
2412         for (tc = 0; tc < priv->profile->max_tc; tc++)
2413                 mlx5e_destroy_tis(priv, tc);
2414 }
2415
2416 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2417                                       enum mlx5e_traffic_types tt)
2418 {
2419         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2420
2421         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2422
2423 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2424                                  MLX5_HASH_FIELD_SEL_DST_IP)
2425
2426 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2427                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2428                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2429                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2430
2431 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2432                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2433                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2434
2435         mlx5e_build_tir_ctx_lro(tirc, priv);
2436
2437         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2438         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2439         mlx5e_build_tir_ctx_hash(tirc, priv);
2440
2441         switch (tt) {
2442         case MLX5E_TT_IPV4_TCP:
2443                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2444                          MLX5_L3_PROT_TYPE_IPV4);
2445                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2446                          MLX5_L4_PROT_TYPE_TCP);
2447                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2448                          MLX5_HASH_IP_L4PORTS);
2449                 break;
2450
2451         case MLX5E_TT_IPV6_TCP:
2452                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2453                          MLX5_L3_PROT_TYPE_IPV6);
2454                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2455                          MLX5_L4_PROT_TYPE_TCP);
2456                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2457                          MLX5_HASH_IP_L4PORTS);
2458                 break;
2459
2460         case MLX5E_TT_IPV4_UDP:
2461                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2462                          MLX5_L3_PROT_TYPE_IPV4);
2463                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2464                          MLX5_L4_PROT_TYPE_UDP);
2465                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2466                          MLX5_HASH_IP_L4PORTS);
2467                 break;
2468
2469         case MLX5E_TT_IPV6_UDP:
2470                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2471                          MLX5_L3_PROT_TYPE_IPV6);
2472                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2473                          MLX5_L4_PROT_TYPE_UDP);
2474                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2475                          MLX5_HASH_IP_L4PORTS);
2476                 break;
2477
2478         case MLX5E_TT_IPV4_IPSEC_AH:
2479                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2480                          MLX5_L3_PROT_TYPE_IPV4);
2481                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2482                          MLX5_HASH_IP_IPSEC_SPI);
2483                 break;
2484
2485         case MLX5E_TT_IPV6_IPSEC_AH:
2486                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2487                          MLX5_L3_PROT_TYPE_IPV6);
2488                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2489                          MLX5_HASH_IP_IPSEC_SPI);
2490                 break;
2491
2492         case MLX5E_TT_IPV4_IPSEC_ESP:
2493                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2494                          MLX5_L3_PROT_TYPE_IPV4);
2495                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2496                          MLX5_HASH_IP_IPSEC_SPI);
2497                 break;
2498
2499         case MLX5E_TT_IPV6_IPSEC_ESP:
2500                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2501                          MLX5_L3_PROT_TYPE_IPV6);
2502                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2503                          MLX5_HASH_IP_IPSEC_SPI);
2504                 break;
2505
2506         case MLX5E_TT_IPV4:
2507                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2508                          MLX5_L3_PROT_TYPE_IPV4);
2509                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2510                          MLX5_HASH_IP);
2511                 break;
2512
2513         case MLX5E_TT_IPV6:
2514                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2515                          MLX5_L3_PROT_TYPE_IPV6);
2516                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2517                          MLX5_HASH_IP);
2518                 break;
2519         default:
2520                 WARN_ONCE(true,
2521                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2522         }
2523 }
2524
2525 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2526                                        u32 rqtn)
2527 {
2528         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2529
2530         mlx5e_build_tir_ctx_lro(tirc, priv);
2531
2532         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2533         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2534         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2535 }
2536
2537 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2538 {
2539         struct mlx5e_tir *tir;
2540         void *tirc;
2541         int inlen;
2542         int err;
2543         u32 *in;
2544         int tt;
2545
2546         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2547         in = mlx5_vzalloc(inlen);
2548         if (!in)
2549                 return -ENOMEM;
2550
2551         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2552                 memset(in, 0, inlen);
2553                 tir = &priv->indir_tir[tt];
2554                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2555                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2556                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2557                 if (err)
2558                         goto err_destroy_tirs;
2559         }
2560
2561         kvfree(in);
2562
2563         return 0;
2564
2565 err_destroy_tirs:
2566         for (tt--; tt >= 0; tt--)
2567                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2568
2569         kvfree(in);
2570
2571         return err;
2572 }
2573
2574 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2575 {
2576         int nch = priv->profile->max_nch(priv->mdev);
2577         struct mlx5e_tir *tir;
2578         void *tirc;
2579         int inlen;
2580         int err;
2581         u32 *in;
2582         int ix;
2583
2584         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2585         in = mlx5_vzalloc(inlen);
2586         if (!in)
2587                 return -ENOMEM;
2588
2589         for (ix = 0; ix < nch; ix++) {
2590                 memset(in, 0, inlen);
2591                 tir = &priv->direct_tir[ix];
2592                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2593                 mlx5e_build_direct_tir_ctx(priv, tirc,
2594                                            priv->direct_tir[ix].rqt.rqtn);
2595                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2596                 if (err)
2597                         goto err_destroy_ch_tirs;
2598         }
2599
2600         kvfree(in);
2601
2602         return 0;
2603
2604 err_destroy_ch_tirs:
2605         for (ix--; ix >= 0; ix--)
2606                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2607
2608         kvfree(in);
2609
2610         return err;
2611 }
2612
2613 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2614 {
2615         int i;
2616
2617         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2618                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2619 }
2620
2621 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2622 {
2623         int nch = priv->profile->max_nch(priv->mdev);
2624         int i;
2625
2626         for (i = 0; i < nch; i++)
2627                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2628 }
2629
2630 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2631 {
2632         int err = 0;
2633         int i;
2634
2635         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2636                 return 0;
2637
2638         for (i = 0; i < priv->params.num_channels; i++) {
2639                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2640                 if (err)
2641                         return err;
2642         }
2643
2644         return 0;
2645 }
2646
2647 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2648 {
2649         struct mlx5e_priv *priv = netdev_priv(netdev);
2650         bool was_opened;
2651         int err = 0;
2652
2653         if (tc && tc != MLX5E_MAX_NUM_TC)
2654                 return -EINVAL;
2655
2656         mutex_lock(&priv->state_lock);
2657
2658         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2659         if (was_opened)
2660                 mlx5e_close_locked(priv->netdev);
2661
2662         priv->params.num_tc = tc ? tc : 1;
2663
2664         if (was_opened)
2665                 err = mlx5e_open_locked(priv->netdev);
2666
2667         mutex_unlock(&priv->state_lock);
2668
2669         return err;
2670 }
2671
2672 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2673                               __be16 proto, struct tc_to_netdev *tc)
2674 {
2675         struct mlx5e_priv *priv = netdev_priv(dev);
2676
2677         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2678                 goto mqprio;
2679
2680         switch (tc->type) {
2681         case TC_SETUP_CLSFLOWER:
2682                 switch (tc->cls_flower->command) {
2683                 case TC_CLSFLOWER_REPLACE:
2684                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2685                 case TC_CLSFLOWER_DESTROY:
2686                         return mlx5e_delete_flower(priv, tc->cls_flower);
2687                 case TC_CLSFLOWER_STATS:
2688                         return mlx5e_stats_flower(priv, tc->cls_flower);
2689                 }
2690         default:
2691                 return -EOPNOTSUPP;
2692         }
2693
2694 mqprio:
2695         if (tc->type != TC_SETUP_MQPRIO)
2696                 return -EINVAL;
2697
2698         return mlx5e_setup_tc(dev, tc->tc);
2699 }
2700
2701 static void
2702 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2703 {
2704         struct mlx5e_priv *priv = netdev_priv(dev);
2705         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2706         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2707         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2708
2709         if (mlx5e_is_uplink_rep(priv)) {
2710                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2711                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
2712                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2713                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2714         } else {
2715                 stats->rx_packets = sstats->rx_packets;
2716                 stats->rx_bytes   = sstats->rx_bytes;
2717                 stats->tx_packets = sstats->tx_packets;
2718                 stats->tx_bytes   = sstats->tx_bytes;
2719                 stats->tx_dropped = sstats->tx_queue_dropped;
2720         }
2721
2722         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2723
2724         stats->rx_length_errors =
2725                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2726                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2727                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2728         stats->rx_crc_errors =
2729                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2730         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2731         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2732         stats->tx_carrier_errors =
2733                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2734         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2735                            stats->rx_frame_errors;
2736         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2737
2738         /* vport multicast also counts packets that are dropped due to steering
2739          * or rx out of buffer
2740          */
2741         stats->multicast =
2742                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2743
2744 }
2745
2746 static void mlx5e_set_rx_mode(struct net_device *dev)
2747 {
2748         struct mlx5e_priv *priv = netdev_priv(dev);
2749
2750         queue_work(priv->wq, &priv->set_rx_mode_work);
2751 }
2752
2753 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2754 {
2755         struct mlx5e_priv *priv = netdev_priv(netdev);
2756         struct sockaddr *saddr = addr;
2757
2758         if (!is_valid_ether_addr(saddr->sa_data))
2759                 return -EADDRNOTAVAIL;
2760
2761         netif_addr_lock_bh(netdev);
2762         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2763         netif_addr_unlock_bh(netdev);
2764
2765         queue_work(priv->wq, &priv->set_rx_mode_work);
2766
2767         return 0;
2768 }
2769
2770 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2771         do {                                            \
2772                 if (enable)                             \
2773                         netdev->features |= feature;    \
2774                 else                                    \
2775                         netdev->features &= ~feature;   \
2776         } while (0)
2777
2778 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2779
2780 static int set_feature_lro(struct net_device *netdev, bool enable)
2781 {
2782         struct mlx5e_priv *priv = netdev_priv(netdev);
2783         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2784         int err;
2785
2786         mutex_lock(&priv->state_lock);
2787
2788         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2789                 mlx5e_close_locked(priv->netdev);
2790
2791         priv->params.lro_en = enable;
2792         err = mlx5e_modify_tirs_lro(priv);
2793         if (err) {
2794                 netdev_err(netdev, "lro modify failed, %d\n", err);
2795                 priv->params.lro_en = !enable;
2796         }
2797
2798         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2799                 mlx5e_open_locked(priv->netdev);
2800
2801         mutex_unlock(&priv->state_lock);
2802
2803         return err;
2804 }
2805
2806 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2807 {
2808         struct mlx5e_priv *priv = netdev_priv(netdev);
2809
2810         if (enable)
2811                 mlx5e_enable_vlan_filter(priv);
2812         else
2813                 mlx5e_disable_vlan_filter(priv);
2814
2815         return 0;
2816 }
2817
2818 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2819 {
2820         struct mlx5e_priv *priv = netdev_priv(netdev);
2821
2822         if (!enable && mlx5e_tc_num_filters(priv)) {
2823                 netdev_err(netdev,
2824                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2825                 return -EINVAL;
2826         }
2827
2828         return 0;
2829 }
2830
2831 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2832 {
2833         struct mlx5e_priv *priv = netdev_priv(netdev);
2834         struct mlx5_core_dev *mdev = priv->mdev;
2835
2836         return mlx5_set_port_fcs(mdev, !enable);
2837 }
2838
2839 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2840 {
2841         struct mlx5e_priv *priv = netdev_priv(netdev);
2842         int err;
2843
2844         mutex_lock(&priv->state_lock);
2845
2846         priv->params.vlan_strip_disable = !enable;
2847         err = mlx5e_modify_rqs_vsd(priv, !enable);
2848         if (err)
2849                 priv->params.vlan_strip_disable = enable;
2850
2851         mutex_unlock(&priv->state_lock);
2852
2853         return err;
2854 }
2855
2856 #ifdef CONFIG_RFS_ACCEL
2857 static int set_feature_arfs(struct net_device *netdev, bool enable)
2858 {
2859         struct mlx5e_priv *priv = netdev_priv(netdev);
2860         int err;
2861
2862         if (enable)
2863                 err = mlx5e_arfs_enable(priv);
2864         else
2865                 err = mlx5e_arfs_disable(priv);
2866
2867         return err;
2868 }
2869 #endif
2870
2871 static int mlx5e_handle_feature(struct net_device *netdev,
2872                                 netdev_features_t wanted_features,
2873                                 netdev_features_t feature,
2874                                 mlx5e_feature_handler feature_handler)
2875 {
2876         netdev_features_t changes = wanted_features ^ netdev->features;
2877         bool enable = !!(wanted_features & feature);
2878         int err;
2879
2880         if (!(changes & feature))
2881                 return 0;
2882
2883         err = feature_handler(netdev, enable);
2884         if (err) {
2885                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2886                            enable ? "Enable" : "Disable", feature, err);
2887                 return err;
2888         }
2889
2890         MLX5E_SET_FEATURE(netdev, feature, enable);
2891         return 0;
2892 }
2893
2894 static int mlx5e_set_features(struct net_device *netdev,
2895                               netdev_features_t features)
2896 {
2897         int err;
2898
2899         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2900                                     set_feature_lro);
2901         err |= mlx5e_handle_feature(netdev, features,
2902                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2903                                     set_feature_vlan_filter);
2904         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2905                                     set_feature_tc_num_filters);
2906         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2907                                     set_feature_rx_all);
2908         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2909                                     set_feature_rx_vlan);
2910 #ifdef CONFIG_RFS_ACCEL
2911         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2912                                     set_feature_arfs);
2913 #endif
2914
2915         return err ? -EINVAL : 0;
2916 }
2917
2918 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2919 {
2920         struct mlx5e_priv *priv = netdev_priv(netdev);
2921         bool was_opened;
2922         int err = 0;
2923         bool reset;
2924
2925         mutex_lock(&priv->state_lock);
2926
2927         reset = !priv->params.lro_en &&
2928                 (priv->params.rq_wq_type !=
2929                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2930
2931         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2932         if (was_opened && reset)
2933                 mlx5e_close_locked(netdev);
2934
2935         netdev->mtu = new_mtu;
2936         mlx5e_set_dev_port_mtu(netdev);
2937
2938         if (was_opened && reset)
2939                 err = mlx5e_open_locked(netdev);
2940
2941         mutex_unlock(&priv->state_lock);
2942
2943         return err;
2944 }
2945
2946 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2947 {
2948         switch (cmd) {
2949         case SIOCSHWTSTAMP:
2950                 return mlx5e_hwstamp_set(dev, ifr);
2951         case SIOCGHWTSTAMP:
2952                 return mlx5e_hwstamp_get(dev, ifr);
2953         default:
2954                 return -EOPNOTSUPP;
2955         }
2956 }
2957
2958 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2959 {
2960         struct mlx5e_priv *priv = netdev_priv(dev);
2961         struct mlx5_core_dev *mdev = priv->mdev;
2962
2963         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2964 }
2965
2966 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2967                              __be16 vlan_proto)
2968 {
2969         struct mlx5e_priv *priv = netdev_priv(dev);
2970         struct mlx5_core_dev *mdev = priv->mdev;
2971
2972         if (vlan_proto != htons(ETH_P_8021Q))
2973                 return -EPROTONOSUPPORT;
2974
2975         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2976                                            vlan, qos);
2977 }
2978
2979 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2980 {
2981         struct mlx5e_priv *priv = netdev_priv(dev);
2982         struct mlx5_core_dev *mdev = priv->mdev;
2983
2984         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2985 }
2986
2987 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2988 {
2989         struct mlx5e_priv *priv = netdev_priv(dev);
2990         struct mlx5_core_dev *mdev = priv->mdev;
2991
2992         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2993 }
2994
2995 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2996                              int max_tx_rate)
2997 {
2998         struct mlx5e_priv *priv = netdev_priv(dev);
2999         struct mlx5_core_dev *mdev = priv->mdev;
3000
3001         if (min_tx_rate)
3002                 return -EOPNOTSUPP;
3003
3004         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3005                                            max_tx_rate);
3006 }
3007
3008 static int mlx5_vport_link2ifla(u8 esw_link)
3009 {
3010         switch (esw_link) {
3011         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3012                 return IFLA_VF_LINK_STATE_DISABLE;
3013         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3014                 return IFLA_VF_LINK_STATE_ENABLE;
3015         }
3016         return IFLA_VF_LINK_STATE_AUTO;
3017 }
3018
3019 static int mlx5_ifla_link2vport(u8 ifla_link)
3020 {
3021         switch (ifla_link) {
3022         case IFLA_VF_LINK_STATE_DISABLE:
3023                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3024         case IFLA_VF_LINK_STATE_ENABLE:
3025                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3026         }
3027         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3028 }
3029
3030 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3031                                    int link_state)
3032 {
3033         struct mlx5e_priv *priv = netdev_priv(dev);
3034         struct mlx5_core_dev *mdev = priv->mdev;
3035
3036         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3037                                             mlx5_ifla_link2vport(link_state));
3038 }
3039
3040 static int mlx5e_get_vf_config(struct net_device *dev,
3041                                int vf, struct ifla_vf_info *ivi)
3042 {
3043         struct mlx5e_priv *priv = netdev_priv(dev);
3044         struct mlx5_core_dev *mdev = priv->mdev;
3045         int err;
3046
3047         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3048         if (err)
3049                 return err;
3050         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3051         return 0;
3052 }
3053
3054 static int mlx5e_get_vf_stats(struct net_device *dev,
3055                               int vf, struct ifla_vf_stats *vf_stats)
3056 {
3057         struct mlx5e_priv *priv = netdev_priv(dev);
3058         struct mlx5_core_dev *mdev = priv->mdev;
3059
3060         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3061                                             vf_stats);
3062 }
3063
3064 void mlx5e_add_vxlan_port(struct net_device *netdev,
3065                           struct udp_tunnel_info *ti)
3066 {
3067         struct mlx5e_priv *priv = netdev_priv(netdev);
3068
3069         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3070                 return;
3071
3072         if (!mlx5e_vxlan_allowed(priv->mdev))
3073                 return;
3074
3075         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3076 }
3077
3078 void mlx5e_del_vxlan_port(struct net_device *netdev,
3079                           struct udp_tunnel_info *ti)
3080 {
3081         struct mlx5e_priv *priv = netdev_priv(netdev);
3082
3083         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3084                 return;
3085
3086         if (!mlx5e_vxlan_allowed(priv->mdev))
3087                 return;
3088
3089         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3090 }
3091
3092 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3093                                                     struct sk_buff *skb,
3094                                                     netdev_features_t features)
3095 {
3096         struct udphdr *udph;
3097         u16 proto;
3098         u16 port = 0;
3099
3100         switch (vlan_get_protocol(skb)) {