2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include <net/page_pool.h>
43 #include "en_accel/ipsec.h"
44 #include "en_accel/ipsec_rxtx.h"
45 #include "en_accel/tls.h"
46 #include "accel/ipsec.h"
47 #include "accel/tls.h"
48 #include "lib/vxlan.h"
52 struct mlx5e_rq_param {
53 u32 rqc[MLX5_ST_SZ_DW(rqc)];
54 struct mlx5_wq_param wq;
55 struct mlx5e_rq_frags_info frags_info;
58 struct mlx5e_sq_param {
59 u32 sqc[MLX5_ST_SZ_DW(sqc)];
60 struct mlx5_wq_param wq;
63 struct mlx5e_cq_param {
64 u32 cqc[MLX5_ST_SZ_DW(cqc)];
65 struct mlx5_wq_param wq;
70 struct mlx5e_channel_param {
71 struct mlx5e_rq_param rq;
72 struct mlx5e_sq_param sq;
73 struct mlx5e_sq_param xdp_sq;
74 struct mlx5e_sq_param icosq;
75 struct mlx5e_cq_param rx_cq;
76 struct mlx5e_cq_param tx_cq;
77 struct mlx5e_cq_param icosq_cq;
80 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
82 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
83 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
84 MLX5_CAP_ETH(mdev, reg_umr_sq);
85 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
86 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
91 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
92 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
98 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
100 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
101 u16 linear_rq_headroom = params->xdp_prog ?
102 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
105 linear_rq_headroom += NET_IP_ALIGN;
107 frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
109 if (params->xdp_prog && frag_sz < PAGE_SIZE)
115 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
117 u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
119 return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
122 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
123 struct mlx5e_params *params)
125 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
127 return !params->lro_en && frag_sz <= PAGE_SIZE;
130 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
131 struct mlx5e_params *params)
133 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
134 s8 signed_log_num_strides_param;
137 if (!mlx5e_rx_is_linear_skb(mdev, params))
140 if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
143 log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
144 signed_log_num_strides_param =
145 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
147 return signed_log_num_strides_param >= 0;
150 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
152 if (params->log_rq_mtu_frames <
153 mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
154 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
156 return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
159 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
160 struct mlx5e_params *params)
162 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
163 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
165 return MLX5E_MPWQE_STRIDE_SZ(mdev,
166 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
169 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
170 struct mlx5e_params *params)
172 return MLX5_MPWRQ_LOG_WQE_SZ -
173 mlx5e_mpwqe_get_log_stride_size(mdev, params);
176 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
177 struct mlx5e_params *params)
179 u16 linear_rq_headroom = params->xdp_prog ?
180 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
183 linear_rq_headroom += NET_IP_ALIGN;
185 is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
186 mlx5e_rx_is_linear_skb(mdev, params) :
187 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
189 return is_linear_skb ? linear_rq_headroom : 0;
192 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
193 struct mlx5e_params *params)
195 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
196 params->log_rq_mtu_frames = is_kdump_kernel() ?
197 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
198 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
200 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
201 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
202 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
203 BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
204 BIT(params->log_rq_mtu_frames),
205 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
206 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
209 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
210 struct mlx5e_params *params)
212 return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
213 !MLX5_IPSEC_DEV(mdev) &&
214 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
217 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
219 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
220 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
221 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
225 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
227 struct mlx5_core_dev *mdev = priv->mdev;
230 port_state = mlx5_query_vport_state(mdev,
231 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
234 if (port_state == VPORT_STATE_UP) {
235 netdev_info(priv->netdev, "Link up\n");
236 netif_carrier_on(priv->netdev);
238 netdev_info(priv->netdev, "Link down\n");
239 netif_carrier_off(priv->netdev);
243 static void mlx5e_update_carrier_work(struct work_struct *work)
245 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
246 update_carrier_work);
248 mutex_lock(&priv->state_lock);
249 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
250 if (priv->profile->update_carrier)
251 priv->profile->update_carrier(priv);
252 mutex_unlock(&priv->state_lock);
255 void mlx5e_update_stats(struct mlx5e_priv *priv)
259 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
260 if (mlx5e_stats_grps[i].update_stats)
261 mlx5e_stats_grps[i].update_stats(priv);
264 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
268 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
269 if (mlx5e_stats_grps[i].update_stats_mask &
270 MLX5E_NDO_UPDATE_STATS)
271 mlx5e_stats_grps[i].update_stats(priv);
274 void mlx5e_update_stats_work(struct work_struct *work)
276 struct delayed_work *dwork = to_delayed_work(work);
277 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
280 mutex_lock(&priv->state_lock);
281 priv->profile->update_stats(priv);
282 mutex_unlock(&priv->state_lock);
285 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
286 enum mlx5_dev_event event, unsigned long param)
288 struct mlx5e_priv *priv = vpriv;
290 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
294 case MLX5_DEV_EVENT_PORT_UP:
295 case MLX5_DEV_EVENT_PORT_DOWN:
296 queue_work(priv->wq, &priv->update_carrier_work);
303 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
305 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
308 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
310 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
311 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
314 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
315 struct mlx5e_icosq *sq,
316 struct mlx5e_umr_wqe *wqe)
318 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
319 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
320 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
322 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
324 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
325 cseg->imm = rq->mkey_be;
327 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
328 ucseg->xlt_octowords =
329 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
330 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
333 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
335 switch (rq->wq_type) {
336 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
337 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
339 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
343 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
345 switch (rq->wq_type) {
346 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
347 return rq->mpwqe.wq.cur_sz;
349 return rq->wqe.wq.cur_sz;
353 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
354 struct mlx5e_channel *c)
356 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
358 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
359 sizeof(*rq->mpwqe.info)),
360 GFP_KERNEL, cpu_to_node(c->cpu));
364 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
369 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
370 u64 npages, u8 page_shift,
371 struct mlx5_core_mkey *umr_mkey)
373 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
378 in = kvzalloc(inlen, GFP_KERNEL);
382 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
384 MLX5_SET(mkc, mkc, free, 1);
385 MLX5_SET(mkc, mkc, umr_en, 1);
386 MLX5_SET(mkc, mkc, lw, 1);
387 MLX5_SET(mkc, mkc, lr, 1);
388 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
390 MLX5_SET(mkc, mkc, qpn, 0xffffff);
391 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
392 MLX5_SET64(mkc, mkc, len, npages << page_shift);
393 MLX5_SET(mkc, mkc, translations_octword_size,
394 MLX5_MTT_OCTW(npages));
395 MLX5_SET(mkc, mkc, log_page_size, page_shift);
397 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
403 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
405 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
407 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
410 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
412 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
415 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
417 struct mlx5e_wqe_frag_info next_frag, *prev;
420 next_frag.di = &rq->wqe.di[0];
421 next_frag.offset = 0;
424 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
425 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
426 struct mlx5e_wqe_frag_info *frag =
427 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
430 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
431 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
433 next_frag.offset = 0;
435 prev->last_in_page = true;
440 next_frag.offset += frag_info[f].frag_stride;
446 prev->last_in_page = true;
449 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
450 struct mlx5e_params *params,
453 int len = wq_sz << rq->wqe.info.log_num_frags;
455 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
456 GFP_KERNEL, cpu_to_node(cpu));
460 mlx5e_init_frags_partition(rq);
465 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
470 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
471 struct mlx5e_params *params,
472 struct mlx5e_rq_param *rqp,
475 struct page_pool_params pp_params = { 0 };
476 struct mlx5_core_dev *mdev = c->mdev;
477 void *rqc = rqp->rqc;
478 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
484 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
486 rq->wq_type = params->rq_wq_type;
488 rq->netdev = c->netdev;
489 rq->tstamp = c->tstamp;
490 rq->clock = &mdev->clock;
494 rq->stats = &c->priv->channel_stats[c->ix].rq;
496 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
497 if (IS_ERR(rq->xdp_prog)) {
498 err = PTR_ERR(rq->xdp_prog);
500 goto err_rq_wq_destroy;
503 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
505 goto err_rq_wq_destroy;
507 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
508 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
509 pool_size = 1 << params->log_rq_mtu_frames;
511 switch (rq->wq_type) {
512 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
513 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
518 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
520 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
522 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
524 rq->post_wqes = mlx5e_post_rx_mpwqes;
525 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
527 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
528 #ifdef CONFIG_MLX5_EN_IPSEC
529 if (MLX5_IPSEC_DEV(mdev)) {
531 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
532 goto err_rq_wq_destroy;
535 if (!rq->handle_rx_cqe) {
537 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
538 goto err_rq_wq_destroy;
541 rq->mpwqe.skb_from_cqe_mpwrq =
542 mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
543 mlx5e_skb_from_cqe_mpwrq_linear :
544 mlx5e_skb_from_cqe_mpwrq_nonlinear;
545 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
546 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
548 err = mlx5e_create_rq_umr_mkey(mdev, rq);
550 goto err_rq_wq_destroy;
551 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
553 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
557 default: /* MLX5_WQ_TYPE_CYCLIC */
558 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
563 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
565 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
567 rq->wqe.info = rqp->frags_info;
569 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
570 (wq_sz << rq->wqe.info.log_num_frags)),
571 GFP_KERNEL, cpu_to_node(c->cpu));
572 if (!rq->wqe.frags) {
577 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
580 rq->post_wqes = mlx5e_post_rx_wqes;
581 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
583 #ifdef CONFIG_MLX5_EN_IPSEC
585 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
588 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
589 if (!rq->handle_rx_cqe) {
591 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
595 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
596 mlx5e_skb_from_cqe_linear :
597 mlx5e_skb_from_cqe_nonlinear;
598 rq->mkey_be = c->mkey_be;
601 /* Create a page_pool and register it with rxq */
603 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
604 pp_params.pool_size = pool_size;
605 pp_params.nid = cpu_to_node(c->cpu);
606 pp_params.dev = c->pdev;
607 pp_params.dma_dir = rq->buff.map_dir;
609 /* page_pool can be used even when there is no rq->xdp_prog,
610 * given page_pool does not handle DMA mapping there is no
611 * required state to clear. And page_pool gracefully handle
614 rq->page_pool = page_pool_create(&pp_params);
615 if (IS_ERR(rq->page_pool)) {
616 err = PTR_ERR(rq->page_pool);
617 rq->page_pool = NULL;
620 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
621 MEM_TYPE_PAGE_POOL, rq->page_pool);
625 for (i = 0; i < wq_sz; i++) {
626 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
627 struct mlx5e_rx_wqe_ll *wqe =
628 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
630 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
631 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
633 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
634 wqe->data[0].byte_count = cpu_to_be32(byte_count);
635 wqe->data[0].lkey = rq->mkey_be;
637 struct mlx5e_rx_wqe_cyc *wqe =
638 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
641 for (f = 0; f < rq->wqe.info.num_frags; f++) {
642 u32 frag_size = rq->wqe.info.arr[f].frag_size |
643 MLX5_HW_START_PADDING;
645 wqe->data[f].byte_count = cpu_to_be32(frag_size);
646 wqe->data[f].lkey = rq->mkey_be;
648 /* check if num_frags is not a pow of two */
649 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
650 wqe->data[f].byte_count = 0;
651 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
652 wqe->data[f].addr = 0;
657 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
659 switch (params->rx_cq_moderation.cq_period_mode) {
660 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
661 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
663 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
665 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
668 rq->page_cache.head = 0;
669 rq->page_cache.tail = 0;
674 switch (rq->wq_type) {
675 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
676 kvfree(rq->mpwqe.info);
677 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
679 default: /* MLX5_WQ_TYPE_CYCLIC */
680 kvfree(rq->wqe.frags);
681 mlx5e_free_di_list(rq);
686 bpf_prog_put(rq->xdp_prog);
687 xdp_rxq_info_unreg(&rq->xdp_rxq);
689 page_pool_destroy(rq->page_pool);
690 mlx5_wq_destroy(&rq->wq_ctrl);
695 static void mlx5e_free_rq(struct mlx5e_rq *rq)
700 bpf_prog_put(rq->xdp_prog);
702 xdp_rxq_info_unreg(&rq->xdp_rxq);
704 page_pool_destroy(rq->page_pool);
706 switch (rq->wq_type) {
707 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
708 kvfree(rq->mpwqe.info);
709 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
711 default: /* MLX5_WQ_TYPE_CYCLIC */
712 kvfree(rq->wqe.frags);
713 mlx5e_free_di_list(rq);
716 for (i = rq->page_cache.head; i != rq->page_cache.tail;
717 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
718 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
720 mlx5e_page_release(rq, dma_info, false);
722 mlx5_wq_destroy(&rq->wq_ctrl);
725 static int mlx5e_create_rq(struct mlx5e_rq *rq,
726 struct mlx5e_rq_param *param)
728 struct mlx5_core_dev *mdev = rq->mdev;
736 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
737 sizeof(u64) * rq->wq_ctrl.buf.npages;
738 in = kvzalloc(inlen, GFP_KERNEL);
742 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
743 wq = MLX5_ADDR_OF(rqc, rqc, wq);
745 memcpy(rqc, param->rqc, sizeof(param->rqc));
747 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
748 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
749 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
750 MLX5_ADAPTER_PAGE_SHIFT);
751 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
753 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
754 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
756 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
763 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
766 struct mlx5_core_dev *mdev = rq->mdev;
773 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
774 in = kvzalloc(inlen, GFP_KERNEL);
778 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
780 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
781 MLX5_SET(rqc, rqc, state, next_state);
783 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
790 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
792 struct mlx5e_channel *c = rq->channel;
793 struct mlx5e_priv *priv = c->priv;
794 struct mlx5_core_dev *mdev = priv->mdev;
801 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
802 in = kvzalloc(inlen, GFP_KERNEL);
806 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
808 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
809 MLX5_SET64(modify_rq_in, in, modify_bitmask,
810 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
811 MLX5_SET(rqc, rqc, scatter_fcs, enable);
812 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
814 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
821 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
823 struct mlx5e_channel *c = rq->channel;
824 struct mlx5_core_dev *mdev = c->mdev;
830 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
831 in = kvzalloc(inlen, GFP_KERNEL);
835 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
837 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
838 MLX5_SET64(modify_rq_in, in, modify_bitmask,
839 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
840 MLX5_SET(rqc, rqc, vsd, vsd);
841 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
843 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
850 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
852 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
855 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
857 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
858 struct mlx5e_channel *c = rq->channel;
860 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
863 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
867 } while (time_before(jiffies, exp_time));
869 netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
870 c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
875 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
880 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
881 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
883 /* UMR WQE (if in progress) is always at wq->head */
884 if (rq->mpwqe.umr_in_progress)
885 rq->dealloc_wqe(rq, wq->head);
887 while (!mlx5_wq_ll_is_empty(wq)) {
888 struct mlx5e_rx_wqe_ll *wqe;
890 wqe_ix_be = *wq->tail_next;
891 wqe_ix = be16_to_cpu(wqe_ix_be);
892 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
893 rq->dealloc_wqe(rq, wqe_ix);
894 mlx5_wq_ll_pop(wq, wqe_ix_be,
895 &wqe->next.next_wqe_index);
898 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
900 while (!mlx5_wq_cyc_is_empty(wq)) {
901 wqe_ix = mlx5_wq_cyc_get_tail(wq);
902 rq->dealloc_wqe(rq, wqe_ix);
909 static int mlx5e_open_rq(struct mlx5e_channel *c,
910 struct mlx5e_params *params,
911 struct mlx5e_rq_param *param,
916 err = mlx5e_alloc_rq(c, params, param, rq);
920 err = mlx5e_create_rq(rq, param);
924 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
928 if (params->rx_dim_enabled)
929 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
934 mlx5e_destroy_rq(rq);
941 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
943 struct mlx5e_icosq *sq = &rq->channel->icosq;
944 struct mlx5_wq_cyc *wq = &sq->wq;
945 struct mlx5e_tx_wqe *nopwqe;
947 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
949 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
950 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
951 nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
952 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
955 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
957 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
958 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
961 static void mlx5e_close_rq(struct mlx5e_rq *rq)
963 cancel_work_sync(&rq->dim.work);
964 mlx5e_destroy_rq(rq);
965 mlx5e_free_rx_descs(rq);
969 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
974 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
976 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
978 sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)),
981 mlx5e_free_xdpsq_db(sq);
988 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
989 struct mlx5e_params *params,
990 struct mlx5e_sq_param *param,
991 struct mlx5e_xdpsq *sq,
994 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
995 struct mlx5_core_dev *mdev = c->mdev;
996 struct mlx5_wq_cyc *wq = &sq->wq;
1000 sq->mkey_be = c->mkey_be;
1002 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1003 sq->min_inline_mode = params->tx_min_inline_mode;
1004 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1005 sq->stats = is_redirect ?
1006 &c->priv->channel_stats[c->ix].xdpsq :
1007 &c->priv->channel_stats[c->ix].rq_xdpsq;
1009 param->wq.db_numa_node = cpu_to_node(c->cpu);
1010 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1013 wq->db = &wq->db[MLX5_SND_DBR];
1015 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1017 goto err_sq_wq_destroy;
1022 mlx5_wq_destroy(&sq->wq_ctrl);
1027 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1029 mlx5e_free_xdpsq_db(sq);
1030 mlx5_wq_destroy(&sq->wq_ctrl);
1033 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1035 kvfree(sq->db.ico_wqe);
1038 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1040 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1042 sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1043 sizeof(*sq->db.ico_wqe)),
1045 if (!sq->db.ico_wqe)
1051 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1052 struct mlx5e_sq_param *param,
1053 struct mlx5e_icosq *sq)
1055 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1056 struct mlx5_core_dev *mdev = c->mdev;
1057 struct mlx5_wq_cyc *wq = &sq->wq;
1061 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1063 param->wq.db_numa_node = cpu_to_node(c->cpu);
1064 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1067 wq->db = &wq->db[MLX5_SND_DBR];
1069 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1071 goto err_sq_wq_destroy;
1076 mlx5_wq_destroy(&sq->wq_ctrl);
1081 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1083 mlx5e_free_icosq_db(sq);
1084 mlx5_wq_destroy(&sq->wq_ctrl);
1087 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1089 kvfree(sq->db.wqe_info);
1090 kvfree(sq->db.dma_fifo);
1093 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1095 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1096 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1098 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1099 sizeof(*sq->db.dma_fifo)),
1101 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1102 sizeof(*sq->db.wqe_info)),
1104 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1105 mlx5e_free_txqsq_db(sq);
1109 sq->dma_fifo_mask = df_sz - 1;
1114 static void mlx5e_sq_recover(struct work_struct *work);
1115 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1117 struct mlx5e_params *params,
1118 struct mlx5e_sq_param *param,
1119 struct mlx5e_txqsq *sq,
1122 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1123 struct mlx5_core_dev *mdev = c->mdev;
1124 struct mlx5_wq_cyc *wq = &sq->wq;
1128 sq->tstamp = c->tstamp;
1129 sq->clock = &mdev->clock;
1130 sq->mkey_be = c->mkey_be;
1132 sq->txq_ix = txq_ix;
1133 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1134 sq->min_inline_mode = params->tx_min_inline_mode;
1135 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1136 INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1137 if (MLX5_IPSEC_DEV(c->priv->mdev))
1138 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1139 if (mlx5_accel_is_tls_device(c->priv->mdev))
1140 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1142 param->wq.db_numa_node = cpu_to_node(c->cpu);
1143 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1146 wq->db = &wq->db[MLX5_SND_DBR];
1148 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1150 goto err_sq_wq_destroy;
1152 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1153 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1158 mlx5_wq_destroy(&sq->wq_ctrl);
1163 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1165 mlx5e_free_txqsq_db(sq);
1166 mlx5_wq_destroy(&sq->wq_ctrl);
1169 struct mlx5e_create_sq_param {
1170 struct mlx5_wq_ctrl *wq_ctrl;
1177 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1178 struct mlx5e_sq_param *param,
1179 struct mlx5e_create_sq_param *csp,
1188 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1189 sizeof(u64) * csp->wq_ctrl->buf.npages;
1190 in = kvzalloc(inlen, GFP_KERNEL);
1194 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1195 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1197 memcpy(sqc, param->sqc, sizeof(param->sqc));
1198 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1199 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1200 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1202 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1203 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1205 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1206 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1208 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1209 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1210 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1211 MLX5_ADAPTER_PAGE_SHIFT);
1212 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1214 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1215 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1217 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1224 struct mlx5e_modify_sq_param {
1231 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1232 struct mlx5e_modify_sq_param *p)
1239 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1240 in = kvzalloc(inlen, GFP_KERNEL);
1244 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1246 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1247 MLX5_SET(sqc, sqc, state, p->next_state);
1248 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1249 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1250 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1253 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1260 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1262 mlx5_core_destroy_sq(mdev, sqn);
1265 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1266 struct mlx5e_sq_param *param,
1267 struct mlx5e_create_sq_param *csp,
1270 struct mlx5e_modify_sq_param msp = {0};
1273 err = mlx5e_create_sq(mdev, param, csp, sqn);
1277 msp.curr_state = MLX5_SQC_STATE_RST;
1278 msp.next_state = MLX5_SQC_STATE_RDY;
1279 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1281 mlx5e_destroy_sq(mdev, *sqn);
1286 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1287 struct mlx5e_txqsq *sq, u32 rate);
1289 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1292 struct mlx5e_params *params,
1293 struct mlx5e_sq_param *param,
1294 struct mlx5e_txqsq *sq,
1297 struct mlx5e_create_sq_param csp = {};
1301 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1307 csp.cqn = sq->cq.mcq.cqn;
1308 csp.wq_ctrl = &sq->wq_ctrl;
1309 csp.min_inline_mode = sq->min_inline_mode;
1310 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1312 goto err_free_txqsq;
1314 tx_rate = c->priv->tx_rates[sq->txq_ix];
1316 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1318 if (params->tx_dim_enabled)
1319 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1324 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1325 mlx5e_free_txqsq(sq);
1330 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1332 WARN_ONCE(sq->cc != sq->pc,
1333 "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1334 sq->sqn, sq->cc, sq->pc);
1336 sq->dma_fifo_cc = 0;
1340 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1342 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1343 clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1344 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1345 netdev_tx_reset_queue(sq->txq);
1346 netif_tx_start_queue(sq->txq);
1349 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1351 __netif_tx_lock_bh(txq);
1352 netif_tx_stop_queue(txq);
1353 __netif_tx_unlock_bh(txq);
1356 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1358 struct mlx5e_channel *c = sq->channel;
1359 struct mlx5_wq_cyc *wq = &sq->wq;
1361 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1362 /* prevent netif_tx_wake_queue */
1363 napi_synchronize(&c->napi);
1365 netif_tx_disable_queue(sq->txq);
1367 /* last doorbell out, godspeed .. */
1368 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1369 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1370 struct mlx5e_tx_wqe *nop;
1372 sq->db.wqe_info[pi].skb = NULL;
1373 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1374 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1378 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1380 struct mlx5e_channel *c = sq->channel;
1381 struct mlx5_core_dev *mdev = c->mdev;
1382 struct mlx5_rate_limit rl = {0};
1384 mlx5e_destroy_sq(mdev, sq->sqn);
1385 if (sq->rate_limit) {
1386 rl.rate = sq->rate_limit;
1387 mlx5_rl_remove_rate(mdev, &rl);
1389 mlx5e_free_txqsq_descs(sq);
1390 mlx5e_free_txqsq(sq);
1393 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1395 unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1397 while (time_before(jiffies, exp_time)) {
1398 if (sq->cc == sq->pc)
1404 netdev_err(sq->channel->netdev,
1405 "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1406 sq->sqn, sq->cc, sq->pc);
1411 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1413 struct mlx5_core_dev *mdev = sq->channel->mdev;
1414 struct net_device *dev = sq->channel->netdev;
1415 struct mlx5e_modify_sq_param msp = {0};
1418 msp.curr_state = curr_state;
1419 msp.next_state = MLX5_SQC_STATE_RST;
1421 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1423 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1427 memset(&msp, 0, sizeof(msp));
1428 msp.curr_state = MLX5_SQC_STATE_RST;
1429 msp.next_state = MLX5_SQC_STATE_RDY;
1431 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1433 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1440 static void mlx5e_sq_recover(struct work_struct *work)
1442 struct mlx5e_txqsq_recover *recover =
1443 container_of(work, struct mlx5e_txqsq_recover,
1445 struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1447 struct mlx5_core_dev *mdev = sq->channel->mdev;
1448 struct net_device *dev = sq->channel->netdev;
1452 err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1454 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1459 if (state != MLX5_RQC_STATE_ERR) {
1460 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1464 netif_tx_disable_queue(sq->txq);
1466 if (mlx5e_wait_for_sq_flush(sq))
1469 /* If the interval between two consecutive recovers per SQ is too
1470 * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1471 * If we reached this state, there is probably a bug that needs to be
1472 * fixed. let's keep the queue close and let tx timeout cleanup.
1474 if (jiffies_to_msecs(jiffies - recover->last_recover) <
1475 MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1476 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1481 /* At this point, no new packets will arrive from the stack as TXQ is
1482 * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1483 * pending WQEs. SQ can safely reset the SQ.
1485 if (mlx5e_sq_to_ready(sq, state))
1488 mlx5e_reset_txqsq_cc_pc(sq);
1489 sq->stats->recover++;
1490 recover->last_recover = jiffies;
1491 mlx5e_activate_txqsq(sq);
1494 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1495 struct mlx5e_params *params,
1496 struct mlx5e_sq_param *param,
1497 struct mlx5e_icosq *sq)
1499 struct mlx5e_create_sq_param csp = {};
1502 err = mlx5e_alloc_icosq(c, param, sq);
1506 csp.cqn = sq->cq.mcq.cqn;
1507 csp.wq_ctrl = &sq->wq_ctrl;
1508 csp.min_inline_mode = params->tx_min_inline_mode;
1509 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1510 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1512 goto err_free_icosq;
1517 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1518 mlx5e_free_icosq(sq);
1523 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1525 struct mlx5e_channel *c = sq->channel;
1527 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1528 napi_synchronize(&c->napi);
1530 mlx5e_destroy_sq(c->mdev, sq->sqn);
1531 mlx5e_free_icosq(sq);
1534 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1535 struct mlx5e_params *params,
1536 struct mlx5e_sq_param *param,
1537 struct mlx5e_xdpsq *sq,
1540 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1541 struct mlx5e_create_sq_param csp = {};
1542 unsigned int inline_hdr_sz = 0;
1546 err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1551 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1552 csp.cqn = sq->cq.mcq.cqn;
1553 csp.wq_ctrl = &sq->wq_ctrl;
1554 csp.min_inline_mode = sq->min_inline_mode;
1556 set_bit(MLX5E_SQ_STATE_REDIRECT, &sq->state);
1557 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1558 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1560 goto err_free_xdpsq;
1562 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1563 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1567 /* Pre initialize fixed WQE fields */
1568 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1569 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1570 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1571 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1572 struct mlx5_wqe_data_seg *dseg;
1574 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1575 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1577 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1578 dseg->lkey = sq->mkey_be;
1584 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1585 mlx5e_free_xdpsq(sq);
1590 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1592 struct mlx5e_channel *c = sq->channel;
1594 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1595 napi_synchronize(&c->napi);
1597 mlx5e_destroy_sq(c->mdev, sq->sqn);
1598 mlx5e_free_xdpsq_descs(sq);
1599 mlx5e_free_xdpsq(sq);
1602 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1603 struct mlx5e_cq_param *param,
1604 struct mlx5e_cq *cq)
1606 struct mlx5_core_cq *mcq = &cq->mcq;
1612 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1617 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1620 mcq->set_ci_db = cq->wq_ctrl.db.db;
1621 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1622 *mcq->set_ci_db = 0;
1624 mcq->vector = param->eq_ix;
1625 mcq->comp = mlx5e_completion_event;
1626 mcq->event = mlx5e_cq_error_event;
1629 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1630 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1640 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1641 struct mlx5e_cq_param *param,
1642 struct mlx5e_cq *cq)
1644 struct mlx5_core_dev *mdev = c->priv->mdev;
1647 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1648 param->wq.db_numa_node = cpu_to_node(c->cpu);
1649 param->eq_ix = c->ix;
1651 err = mlx5e_alloc_cq_common(mdev, param, cq);
1653 cq->napi = &c->napi;
1659 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1661 mlx5_wq_destroy(&cq->wq_ctrl);
1664 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1666 struct mlx5_core_dev *mdev = cq->mdev;
1667 struct mlx5_core_cq *mcq = &cq->mcq;
1672 unsigned int irqn_not_used;
1676 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1677 sizeof(u64) * cq->wq_ctrl.buf.npages;
1678 in = kvzalloc(inlen, GFP_KERNEL);
1682 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1684 memcpy(cqc, param->cqc, sizeof(param->cqc));
1686 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1687 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1689 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1691 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1692 MLX5_SET(cqc, cqc, c_eqn, eqn);
1693 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1694 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1695 MLX5_ADAPTER_PAGE_SHIFT);
1696 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1698 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1710 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1712 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1715 static int mlx5e_open_cq(struct mlx5e_channel *c,
1716 struct net_dim_cq_moder moder,
1717 struct mlx5e_cq_param *param,
1718 struct mlx5e_cq *cq)
1720 struct mlx5_core_dev *mdev = c->mdev;
1723 err = mlx5e_alloc_cq(c, param, cq);
1727 err = mlx5e_create_cq(cq, param);
1731 if (MLX5_CAP_GEN(mdev, cq_moderation))
1732 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1741 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1743 mlx5e_destroy_cq(cq);
1747 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1749 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1752 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1753 struct mlx5e_params *params,
1754 struct mlx5e_channel_param *cparam)
1759 for (tc = 0; tc < c->num_tc; tc++) {
1760 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1761 &cparam->tx_cq, &c->sq[tc].cq);
1763 goto err_close_tx_cqs;
1769 for (tc--; tc >= 0; tc--)
1770 mlx5e_close_cq(&c->sq[tc].cq);
1775 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1779 for (tc = 0; tc < c->num_tc; tc++)
1780 mlx5e_close_cq(&c->sq[tc].cq);
1783 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1784 struct mlx5e_params *params,
1785 struct mlx5e_channel_param *cparam)
1787 struct mlx5e_priv *priv = c->priv;
1788 int err, tc, max_nch = priv->profile->max_nch(priv->mdev);
1790 for (tc = 0; tc < params->num_tc; tc++) {
1791 int txq_ix = c->ix + tc * max_nch;
1793 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1794 params, &cparam->sq, &c->sq[tc], tc);
1802 for (tc--; tc >= 0; tc--)
1803 mlx5e_close_txqsq(&c->sq[tc]);
1808 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1812 for (tc = 0; tc < c->num_tc; tc++)
1813 mlx5e_close_txqsq(&c->sq[tc]);
1816 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1817 struct mlx5e_txqsq *sq, u32 rate)
1819 struct mlx5e_priv *priv = netdev_priv(dev);
1820 struct mlx5_core_dev *mdev = priv->mdev;
1821 struct mlx5e_modify_sq_param msp = {0};
1822 struct mlx5_rate_limit rl = {0};
1826 if (rate == sq->rate_limit)
1830 if (sq->rate_limit) {
1831 rl.rate = sq->rate_limit;
1832 /* remove current rl index to free space to next ones */
1833 mlx5_rl_remove_rate(mdev, &rl);
1840 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1842 netdev_err(dev, "Failed configuring rate %u: %d\n",
1848 msp.curr_state = MLX5_SQC_STATE_RDY;
1849 msp.next_state = MLX5_SQC_STATE_RDY;
1850 msp.rl_index = rl_index;
1851 msp.rl_update = true;
1852 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1854 netdev_err(dev, "Failed configuring rate %u: %d\n",
1856 /* remove the rate from the table */
1858 mlx5_rl_remove_rate(mdev, &rl);
1862 sq->rate_limit = rate;
1866 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1868 struct mlx5e_priv *priv = netdev_priv(dev);
1869 struct mlx5_core_dev *mdev = priv->mdev;
1870 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1873 if (!mlx5_rl_is_supported(mdev)) {
1874 netdev_err(dev, "Rate limiting is not supported on this device\n");
1878 /* rate is given in Mb/sec, HW config is in Kb/sec */
1881 /* Check whether rate in valid range, 0 is always valid */
1882 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1883 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1887 mutex_lock(&priv->state_lock);
1888 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1889 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1891 priv->tx_rates[index] = rate;
1892 mutex_unlock(&priv->state_lock);
1897 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1898 struct mlx5e_params *params,
1899 struct mlx5e_channel_param *cparam,
1900 struct mlx5e_channel **cp)
1902 struct net_dim_cq_moder icocq_moder = {0, 0};
1903 struct net_device *netdev = priv->netdev;
1904 int cpu = mlx5e_get_cpu(priv, ix);
1905 struct mlx5e_channel *c;
1910 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1915 c->mdev = priv->mdev;
1916 c->tstamp = &priv->tstamp;
1919 c->pdev = &priv->mdev->pdev->dev;
1920 c->netdev = priv->netdev;
1921 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1922 c->num_tc = params->num_tc;
1923 c->xdp = !!params->xdp_prog;
1924 c->stats = &priv->channel_stats[ix].ch;
1926 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1927 c->irq_desc = irq_to_desc(irq);
1929 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1931 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1935 err = mlx5e_open_tx_cqs(c, params, cparam);
1937 goto err_close_icosq_cq;
1939 err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1941 goto err_close_tx_cqs;
1943 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1945 goto err_close_xdp_tx_cqs;
1947 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1948 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1949 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1951 goto err_close_rx_cq;
1953 napi_enable(&c->napi);
1955 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1957 goto err_disable_napi;
1959 err = mlx5e_open_sqs(c, params, cparam);
1961 goto err_close_icosq;
1963 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1967 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1969 goto err_close_xdp_sq;
1971 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1980 mlx5e_close_rq(&c->rq);
1984 mlx5e_close_xdpsq(&c->rq.xdpsq);
1990 mlx5e_close_icosq(&c->icosq);
1993 napi_disable(&c->napi);
1995 mlx5e_close_cq(&c->rq.xdpsq.cq);
1998 mlx5e_close_cq(&c->rq.cq);
2000 err_close_xdp_tx_cqs:
2001 mlx5e_close_cq(&c->xdpsq.cq);
2004 mlx5e_close_tx_cqs(c);
2007 mlx5e_close_cq(&c->icosq.cq);
2010 netif_napi_del(&c->napi);
2016 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2020 for (tc = 0; tc < c->num_tc; tc++)
2021 mlx5e_activate_txqsq(&c->sq[tc]);
2022 mlx5e_activate_rq(&c->rq);
2023 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
2026 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2030 mlx5e_deactivate_rq(&c->rq);
2031 for (tc = 0; tc < c->num_tc; tc++)
2032 mlx5e_deactivate_txqsq(&c->sq[tc]);
2035 static void mlx5e_close_channel(struct mlx5e_channel *c)
2037 mlx5e_close_xdpsq(&c->xdpsq);
2038 mlx5e_close_rq(&c->rq);
2040 mlx5e_close_xdpsq(&c->rq.xdpsq);
2042 mlx5e_close_icosq(&c->icosq);
2043 napi_disable(&c->napi);
2045 mlx5e_close_cq(&c->rq.xdpsq.cq);
2046 mlx5e_close_cq(&c->rq.cq);
2047 mlx5e_close_cq(&c->xdpsq.cq);
2048 mlx5e_close_tx_cqs(c);
2049 mlx5e_close_cq(&c->icosq.cq);
2050 netif_napi_del(&c->napi);
2055 #define DEFAULT_FRAG_SIZE (2048)
2057 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2058 struct mlx5e_params *params,
2059 struct mlx5e_rq_frags_info *info)
2061 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2062 int frag_size_max = DEFAULT_FRAG_SIZE;
2066 #ifdef CONFIG_MLX5_EN_IPSEC
2067 if (MLX5_IPSEC_DEV(mdev))
2068 byte_count += MLX5E_METADATA_ETHER_LEN;
2071 if (mlx5e_rx_is_linear_skb(mdev, params)) {
2074 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2075 frag_stride = roundup_pow_of_two(frag_stride);
2077 info->arr[0].frag_size = byte_count;
2078 info->arr[0].frag_stride = frag_stride;
2079 info->num_frags = 1;
2080 info->wqe_bulk = PAGE_SIZE / frag_stride;
2084 if (byte_count > PAGE_SIZE +
2085 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2086 frag_size_max = PAGE_SIZE;
2089 while (buf_size < byte_count) {
2090 int frag_size = byte_count - buf_size;
2092 if (i < MLX5E_MAX_RX_FRAGS - 1)
2093 frag_size = min(frag_size, frag_size_max);
2095 info->arr[i].frag_size = frag_size;
2096 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2098 buf_size += frag_size;
2101 info->num_frags = i;
2102 /* number of different wqes sharing a page */
2103 info->wqe_bulk = 1 + (info->num_frags % 2);
2106 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2107 info->log_num_frags = order_base_2(info->num_frags);
2110 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2112 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2115 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2116 sz += sizeof(struct mlx5e_rx_wqe_ll);
2118 default: /* MLX5_WQ_TYPE_CYCLIC */
2119 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2122 return order_base_2(sz);
2125 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2126 struct mlx5e_params *params,
2127 struct mlx5e_rq_param *param)
2129 struct mlx5_core_dev *mdev = priv->mdev;
2130 void *rqc = param->rqc;
2131 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2134 switch (params->rq_wq_type) {
2135 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2136 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2137 mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2138 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2139 MLX5_SET(wq, wq, log_wqe_stride_size,
2140 mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2141 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2142 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2144 default: /* MLX5_WQ_TYPE_CYCLIC */
2145 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2146 mlx5e_build_rq_frags_info(mdev, params, ¶m->frags_info);
2147 ndsegs = param->frags_info.num_frags;
2150 MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
2151 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2152 MLX5_SET(wq, wq, log_wq_stride,
2153 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2154 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
2155 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2156 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
2157 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
2159 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2162 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2163 struct mlx5e_rq_param *param)
2165 struct mlx5_core_dev *mdev = priv->mdev;
2166 void *rqc = param->rqc;
2167 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2169 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2170 MLX5_SET(wq, wq, log_wq_stride,
2171 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2172 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2174 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2177 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2178 struct mlx5e_sq_param *param)
2180 void *sqc = param->sqc;
2181 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2183 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2184 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
2186 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2189 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2190 struct mlx5e_params *params,
2191 struct mlx5e_sq_param *param)
2193 void *sqc = param->sqc;
2194 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2196 mlx5e_build_sq_param_common(priv, param);
2197 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2198 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2201 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2202 struct mlx5e_cq_param *param)
2204 void *cqc = param->cqc;
2206 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2209 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2210 struct mlx5e_params *params,
2211 struct mlx5e_cq_param *param)
2213 struct mlx5_core_dev *mdev = priv->mdev;
2214 void *cqc = param->cqc;
2217 switch (params->rq_wq_type) {
2218 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2219 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2220 mlx5e_mpwqe_get_log_num_strides(mdev, params);
2222 default: /* MLX5_WQ_TYPE_CYCLIC */
2223 log_cq_size = params->log_rq_mtu_frames;
2226 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2227 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2228 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2229 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2232 mlx5e_build_common_cq_param(priv, param);
2233 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2236 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2237 struct mlx5e_params *params,
2238 struct mlx5e_cq_param *param)
2240 void *cqc = param->cqc;
2242 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2244 mlx5e_build_common_cq_param(priv, param);
2245 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2248 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2250 struct mlx5e_cq_param *param)
2252 void *cqc = param->cqc;
2254 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2256 mlx5e_build_common_cq_param(priv, param);
2258 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2261 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2263 struct mlx5e_sq_param *param)
2265 void *sqc = param->sqc;
2266 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2268 mlx5e_build_sq_param_common(priv, param);
2270 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2271 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2274 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2275 struct mlx5e_params *params,
2276 struct mlx5e_sq_param *param)
2278 void *sqc = param->sqc;
2279 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2281 mlx5e_build_sq_param_common(priv, param);
2282 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2285 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2286 struct mlx5e_params *params,
2287 struct mlx5e_channel_param *cparam)
2289 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2291 mlx5e_build_rq_param(priv, params, &cparam->rq);
2292 mlx5e_build_sq_param(priv, params, &cparam->sq);
2293 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2294 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2295 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2296 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2297 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2300 int mlx5e_open_channels(struct mlx5e_priv *priv,
2301 struct mlx5e_channels *chs)
2303 struct mlx5e_channel_param *cparam;
2307 chs->num = chs->params.num_channels;
2309 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2310 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2311 if (!chs->c || !cparam)
2314 mlx5e_build_channel_param(priv, &chs->params, cparam);
2315 for (i = 0; i < chs->num; i++) {
2316 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2318 goto err_close_channels;
2325 for (i--; i >= 0; i--)
2326 mlx5e_close_channel(chs->c[i]);
2335 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2339 for (i = 0; i < chs->num; i++)
2340 mlx5e_activate_channel(chs->c[i]);
2343 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2348 for (i = 0; i < chs->num; i++)
2349 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2352 return err ? -ETIMEDOUT : 0;
2355 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2359 for (i = 0; i < chs->num; i++)
2360 mlx5e_deactivate_channel(chs->c[i]);
2363 void mlx5e_close_channels(struct mlx5e_channels *chs)
2367 for (i = 0; i < chs->num; i++)
2368 mlx5e_close_channel(chs->c[i]);
2375 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2377 struct mlx5_core_dev *mdev = priv->mdev;
2384 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2385 in = kvzalloc(inlen, GFP_KERNEL);
2389 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2391 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2392 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2394 for (i = 0; i < sz; i++)
2395 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2397 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2399 rqt->enabled = true;
2405 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2407 rqt->enabled = false;
2408 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2411 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2413 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2416 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2418 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2422 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2424 struct mlx5e_rqt *rqt;
2428 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2429 rqt = &priv->direct_tir[ix].rqt;
2430 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2432 goto err_destroy_rqts;
2438 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2439 for (ix--; ix >= 0; ix--)
2440 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2445 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2449 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2450 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2453 static int mlx5e_rx_hash_fn(int hfunc)
2455 return (hfunc == ETH_RSS_HASH_TOP) ?
2456 MLX5_RX_HASH_FN_TOEPLITZ :
2457 MLX5_RX_HASH_FN_INVERTED_XOR8;
2460 int mlx5e_bits_invert(unsigned long a, int size)
2465 for (i = 0; i < size; i++)
2466 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2471 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2472 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2476 for (i = 0; i < sz; i++) {
2482 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2483 ix = mlx5e_bits_invert(i, ilog2(sz));
2485 ix = priv->channels.params.indirection_rqt[ix];
2486 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2490 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2494 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2495 struct mlx5e_redirect_rqt_param rrp)
2497 struct mlx5_core_dev *mdev = priv->mdev;
2503 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2504 in = kvzalloc(inlen, GFP_KERNEL);
2508 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2510 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2511 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2512 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2513 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2519 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2520 struct mlx5e_redirect_rqt_param rrp)
2525 if (ix >= rrp.rss.channels->num)
2526 return priv->drop_rq.rqn;
2528 return rrp.rss.channels->c[ix]->rq.rqn;
2531 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2532 struct mlx5e_redirect_rqt_param rrp)
2537 if (priv->indir_rqt.enabled) {
2539 rqtn = priv->indir_rqt.rqtn;
2540 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2543 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2544 struct mlx5e_redirect_rqt_param direct_rrp = {
2547 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2551 /* Direct RQ Tables */
2552 if (!priv->direct_tir[ix].rqt.enabled)
2555 rqtn = priv->direct_tir[ix].rqt.rqtn;
2556 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2560 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2561 struct mlx5e_channels *chs)
2563 struct mlx5e_redirect_rqt_param rrp = {
2568 .hfunc = chs->params.rss_hfunc,
2573 mlx5e_redirect_rqts(priv, rrp);
2576 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2578 struct mlx5e_redirect_rqt_param drop_rrp = {
2581 .rqn = priv->drop_rq.rqn,
2585 mlx5e_redirect_rqts(priv, drop_rrp);
2588 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2590 if (!params->lro_en)
2593 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2595 MLX5_SET(tirc, tirc, lro_enable_mask,
2596 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2597 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2598 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2599 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2600 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2603 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2604 enum mlx5e_traffic_types tt,
2605 void *tirc, bool inner)
2607 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2608 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2610 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2611 MLX5_HASH_FIELD_SEL_DST_IP)
2613 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2614 MLX5_HASH_FIELD_SEL_DST_IP |\
2615 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2616 MLX5_HASH_FIELD_SEL_L4_DPORT)
2618 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2619 MLX5_HASH_FIELD_SEL_DST_IP |\
2620 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2622 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2623 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2624 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2625 rx_hash_toeplitz_key);
2626 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2627 rx_hash_toeplitz_key);
2629 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2630 memcpy(rss_key, params->toeplitz_hash_key, len);
2634 case MLX5E_TT_IPV4_TCP:
2635 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2636 MLX5_L3_PROT_TYPE_IPV4);
2637 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2638 MLX5_L4_PROT_TYPE_TCP);
2639 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2640 MLX5_HASH_IP_L4PORTS);
2643 case MLX5E_TT_IPV6_TCP:
2644 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2645 MLX5_L3_PROT_TYPE_IPV6);
2646 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2647 MLX5_L4_PROT_TYPE_TCP);
2648 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2649 MLX5_HASH_IP_L4PORTS);
2652 case MLX5E_TT_IPV4_UDP:
2653 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2654 MLX5_L3_PROT_TYPE_IPV4);
2655 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2656 MLX5_L4_PROT_TYPE_UDP);
2657 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2658 MLX5_HASH_IP_L4PORTS);
2661 case MLX5E_TT_IPV6_UDP:
2662 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2663 MLX5_L3_PROT_TYPE_IPV6);
2664 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2665 MLX5_L4_PROT_TYPE_UDP);
2666 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2667 MLX5_HASH_IP_L4PORTS);
2670 case MLX5E_TT_IPV4_IPSEC_AH:
2671 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2672 MLX5_L3_PROT_TYPE_IPV4);
2673 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2674 MLX5_HASH_IP_IPSEC_SPI);
2677 case MLX5E_TT_IPV6_IPSEC_AH:
2678 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2679 MLX5_L3_PROT_TYPE_IPV6);
2680 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2681 MLX5_HASH_IP_IPSEC_SPI);
2684 case MLX5E_TT_IPV4_IPSEC_ESP:
2685 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2686 MLX5_L3_PROT_TYPE_IPV4);
2687 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2688 MLX5_HASH_IP_IPSEC_SPI);
2691 case MLX5E_TT_IPV6_IPSEC_ESP:
2692 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2693 MLX5_L3_PROT_TYPE_IPV6);
2694 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2695 MLX5_HASH_IP_IPSEC_SPI);
2699 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2700 MLX5_L3_PROT_TYPE_IPV4);
2701 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2706 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2707 MLX5_L3_PROT_TYPE_IPV6);
2708 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2712 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2716 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2718 struct mlx5_core_dev *mdev = priv->mdev;
2727 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2728 in = kvzalloc(inlen, GFP_KERNEL);
2732 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2733 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2735 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2737 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2738 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2744 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2745 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2757 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2758 enum mlx5e_traffic_types tt,
2761 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2763 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2765 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2766 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2767 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2769 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2772 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2773 struct mlx5e_params *params, u16 mtu)
2775 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2778 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2782 /* Update vport context MTU */
2783 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2787 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2788 struct mlx5e_params *params, u16 *mtu)
2793 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2794 if (err || !hw_mtu) /* fallback to port oper mtu */
2795 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2797 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2800 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2802 struct mlx5e_params *params = &priv->channels.params;
2803 struct net_device *netdev = priv->netdev;
2804 struct mlx5_core_dev *mdev = priv->mdev;
2808 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2812 mlx5e_query_mtu(mdev, params, &mtu);
2813 if (mtu != params->sw_mtu)
2814 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2815 __func__, mtu, params->sw_mtu);
2817 params->sw_mtu = mtu;
2821 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2823 struct mlx5e_priv *priv = netdev_priv(netdev);
2824 int nch = priv->channels.params.num_channels;
2825 int ntc = priv->channels.params.num_tc;
2828 netdev_reset_tc(netdev);
2833 netdev_set_num_tc(netdev, ntc);
2835 /* Map netdev TCs to offset 0
2836 * We have our own UP to TXQ mapping for QoS
2838 for (tc = 0; tc < ntc; tc++)
2839 netdev_set_tc_queue(netdev, tc, nch, 0);
2842 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2844 int max_nch = priv->profile->max_nch(priv->mdev);
2847 for (i = 0; i < max_nch; i++)
2848 for (tc = 0; tc < priv->profile->max_tc; tc++)
2849 priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2852 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2854 struct mlx5e_channel *c;
2855 struct mlx5e_txqsq *sq;
2858 for (i = 0; i < priv->channels.num; i++) {
2859 c = priv->channels.c[i];
2860 for (tc = 0; tc < c->num_tc; tc++) {
2862 priv->txq2sq[sq->txq_ix] = sq;
2867 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2869 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2870 struct net_device *netdev = priv->netdev;
2872 mlx5e_netdev_set_tcs(netdev);
2873 netif_set_real_num_tx_queues(netdev, num_txqs);
2874 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2876 mlx5e_build_tx2sq_maps(priv);
2877 mlx5e_activate_channels(&priv->channels);
2878 netif_tx_start_all_queues(priv->netdev);
2880 if (MLX5_ESWITCH_MANAGER(priv->mdev))
2881 mlx5e_add_sqs_fwd_rules(priv);
2883 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2884 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2887 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2889 mlx5e_redirect_rqts_to_drop(priv);
2891 if (MLX5_ESWITCH_MANAGER(priv->mdev))
2892 mlx5e_remove_sqs_fwd_rules(priv);
2894 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2895 * polling for inactive tx queues.
2897 netif_tx_stop_all_queues(priv->netdev);
2898 netif_tx_disable(priv->netdev);
2899 mlx5e_deactivate_channels(&priv->channels);
2902 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2903 struct mlx5e_channels *new_chs,
2904 mlx5e_fp_hw_modify hw_modify)
2906 struct net_device *netdev = priv->netdev;
2909 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2911 carrier_ok = netif_carrier_ok(netdev);
2912 netif_carrier_off(netdev);
2914 if (new_num_txqs < netdev->real_num_tx_queues)
2915 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2917 mlx5e_deactivate_priv_channels(priv);
2918 mlx5e_close_channels(&priv->channels);
2920 priv->channels = *new_chs;
2922 /* New channels are ready to roll, modify HW settings if needed */
2926 mlx5e_refresh_tirs(priv, false);
2927 mlx5e_activate_priv_channels(priv);
2929 /* return carrier back if needed */
2931 netif_carrier_on(netdev);
2934 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2936 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2937 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2940 int mlx5e_open_locked(struct net_device *netdev)
2942 struct mlx5e_priv *priv = netdev_priv(netdev);
2945 set_bit(MLX5E_STATE_OPENED, &priv->state);
2947 err = mlx5e_open_channels(priv, &priv->channels);
2949 goto err_clear_state_opened_flag;
2951 mlx5e_refresh_tirs(priv, false);
2952 mlx5e_activate_priv_channels(priv);
2953 if (priv->profile->update_carrier)
2954 priv->profile->update_carrier(priv);
2956 if (priv->profile->update_stats)
2957 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2961 err_clear_state_opened_flag:
2962 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2966 int mlx5e_open(struct net_device *netdev)
2968 struct mlx5e_priv *priv = netdev_priv(netdev);
2971 mutex_lock(&priv->state_lock);
2972 err = mlx5e_open_locked(netdev);
2974 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2975 mutex_unlock(&priv->state_lock);
2977 if (mlx5_vxlan_allowed(priv->mdev->vxlan))
2978 udp_tunnel_get_rx_info(netdev);
2983 int mlx5e_close_locked(struct net_device *netdev)
2985 struct mlx5e_priv *priv = netdev_priv(netdev);
2987 /* May already be CLOSED in case a previous configuration operation
2988 * (e.g RX/TX queue size change) that involves close&open failed.
2990 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2993 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2995 netif_carrier_off(priv->netdev);
2996 mlx5e_deactivate_priv_channels(priv);
2997 mlx5e_close_channels(&priv->channels);
3002 int mlx5e_close(struct net_device *netdev)
3004 struct mlx5e_priv *priv = netdev_priv(netdev);
3007 if (!netif_device_present(netdev))
3010 mutex_lock(&priv->state_lock);
3011 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3012 err = mlx5e_close_locked(netdev);
3013 mutex_unlock(&priv->state_lock);
3018 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3019 struct mlx5e_rq *rq,
3020 struct mlx5e_rq_param *param)
3022 void *rqc = param->rqc;
3023 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3026 param->wq.db_numa_node = param->wq.buf_numa_node;
3028 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
3033 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3034 xdp_rxq_info_unused(&rq->xdp_rxq);
3041 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3042 struct mlx5e_cq *cq,
3043 struct mlx5e_cq_param *param)
3045 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3046 param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev);
3048 return mlx5e_alloc_cq_common(mdev, param, cq);
3051 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3052 struct mlx5e_rq *drop_rq)
3054 struct mlx5_core_dev *mdev = priv->mdev;
3055 struct mlx5e_cq_param cq_param = {};
3056 struct mlx5e_rq_param rq_param = {};
3057 struct mlx5e_cq *cq = &drop_rq->cq;
3060 mlx5e_build_drop_rq_param(priv, &rq_param);
3062 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3066 err = mlx5e_create_cq(cq, &cq_param);
3070 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3072 goto err_destroy_cq;
3074 err = mlx5e_create_rq(drop_rq, &rq_param);
3078 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3080 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3085 mlx5e_free_rq(drop_rq);
3088 mlx5e_destroy_cq(cq);
3096 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3098 mlx5e_destroy_rq(drop_rq);
3099 mlx5e_free_rq(drop_rq);
3100 mlx5e_destroy_cq(&drop_rq->cq);
3101 mlx5e_free_cq(&drop_rq->cq);
3104 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3105 u32 underlay_qpn, u32 *tisn)
3107 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3108 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3110 MLX5_SET(tisc, tisc, prio, tc << 1);
3111 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3112 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3114 if (mlx5_lag_is_lacp_owner(mdev))
3115 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3117 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3120 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3122 mlx5_core_destroy_tis(mdev, tisn);
3125 int mlx5e_create_tises(struct mlx5e_priv *priv)
3130 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3131 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3133 goto err_close_tises;
3139 for (tc--; tc >= 0; tc--)
3140 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3145 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3149 for (tc = 0; tc < priv->profile->max_tc; tc++)
3150 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3153 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3154 enum mlx5e_traffic_types tt,
3157 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3159 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3161 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3162 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3163 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
3166 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3168 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3170 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3172 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3173 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3174 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3177 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
3179 struct mlx5e_tir *tir;
3187 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3188 in = kvzalloc(inlen, GFP_KERNEL);
3192 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3193 memset(in, 0, inlen);
3194 tir = &priv->indir_tir[tt];
3195 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3196 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3197 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3199 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3200 goto err_destroy_inner_tirs;
3204 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3207 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3208 memset(in, 0, inlen);
3209 tir = &priv->inner_indir_tir[i];
3210 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3211 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3212 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3214 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3215 goto err_destroy_inner_tirs;
3224 err_destroy_inner_tirs:
3225 for (i--; i >= 0; i--)
3226 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3228 for (tt--; tt >= 0; tt--)
3229 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3236 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3238 int nch = priv->profile->max_nch(priv->mdev);
3239 struct mlx5e_tir *tir;
3246 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3247 in = kvzalloc(inlen, GFP_KERNEL);
3251 for (ix = 0; ix < nch; ix++) {
3252 memset(in, 0, inlen);
3253 tir = &priv->direct_tir[ix];
3254 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3255 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3256 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3258 goto err_destroy_ch_tirs;
3265 err_destroy_ch_tirs:
3266 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3267 for (ix--; ix >= 0; ix--)
3268 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3275 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3279 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3280 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3282 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3285 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3286 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3289 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3291 int nch = priv->profile->max_nch(priv->mdev);
3294 for (i = 0; i < nch; i++)
3295 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3298 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3303 for (i = 0; i < chs->num; i++) {
3304 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3312 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3317 for (i = 0; i < chs->num; i++) {
3318 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3326 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3327 struct tc_mqprio_qopt *mqprio)
3329 struct mlx5e_priv *priv = netdev_priv(netdev);
3330 struct mlx5e_channels new_channels = {};
3331 u8 tc = mqprio->num_tc;
3334 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3336 if (tc && tc != MLX5E_MAX_NUM_TC)
3339 mutex_lock(&priv->state_lock);
3341 new_channels.params = priv->channels.params;
3342 new_channels.params.num_tc = tc ? tc : 1;
3344 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3345 priv->channels.params = new_channels.params;
3349 err = mlx5e_open_channels(priv, &new_channels);
3353 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3354 new_channels.params.num_tc);
3355 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3357 mutex_unlock(&priv->state_lock);
3361 #ifdef CONFIG_MLX5_ESWITCH
3362 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3363 struct tc_cls_flower_offload *cls_flower,
3366 switch (cls_flower->command) {
3367 case TC_CLSFLOWER_REPLACE:
3368 return mlx5e_configure_flower(priv, cls_flower, flags);
3369 case TC_CLSFLOWER_DESTROY:
3370 return mlx5e_delete_flower(priv, cls_flower, flags);
3371 case TC_CLSFLOWER_STATS:
3372 return mlx5e_stats_flower(priv, cls_flower, flags);
3378 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3381 struct mlx5e_priv *priv = cb_priv;
3383 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3387 case TC_SETUP_CLSFLOWER:
3388 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS);
3394 static int mlx5e_setup_tc_block(struct net_device *dev,
3395 struct tc_block_offload *f)
3397 struct mlx5e_priv *priv = netdev_priv(dev);
3399 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3402 switch (f->command) {
3404 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3405 priv, priv, f->extack);
3406 case TC_BLOCK_UNBIND:
3407 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3416 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3420 #ifdef CONFIG_MLX5_ESWITCH
3421 case TC_SETUP_BLOCK:
3422 return mlx5e_setup_tc_block(dev, type_data);
3424 case TC_SETUP_QDISC_MQPRIO:
3425 return mlx5e_setup_tc_mqprio(dev, type_data);
3432 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3434 struct mlx5e_priv *priv = netdev_priv(dev);
3435 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3436 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3437 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3439 /* update HW stats in background for next time */
3440 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
3442 if (mlx5e_is_uplink_rep(priv)) {
3443 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3444 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3445 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3446 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3448 mlx5e_grp_sw_update_stats(priv);
3449 stats->rx_packets = sstats->rx_packets;
3450 stats->rx_bytes = sstats->rx_bytes;
3451 stats->tx_packets = sstats->tx_packets;
3452 stats->tx_bytes = sstats->tx_bytes;
3453 stats->tx_dropped = sstats->tx_queue_dropped;
3456 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3458 stats->rx_length_errors =
3459 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3460 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3461 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3462 stats->rx_crc_errors =
3463 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3464 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3465 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3466 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3467 stats->rx_frame_errors;
3468 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3470 /* vport multicast also counts packets that are dropped due to steering
3471 * or rx out of buffer
3474 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3477 static void mlx5e_set_rx_mode(struct net_device *dev)
3479 struct mlx5e_priv *priv = netdev_priv(dev);
3481 queue_work(priv->wq, &priv->set_rx_mode_work);
3484 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3486 struct mlx5e_priv *priv = netdev_priv(netdev);
3487 struct sockaddr *saddr = addr;
3489 if (!is_valid_ether_addr(saddr->sa_data))
3490 return -EADDRNOTAVAIL;
3492 netif_addr_lock_bh(netdev);
3493 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3494 netif_addr_unlock_bh(netdev);
3496 queue_work(priv->wq, &priv->set_rx_mode_work);
3501 #define MLX5E_SET_FEATURE(features, feature, enable) \
3504 *features |= feature; \
3506 *features &= ~feature; \
3509 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3511 static int set_feature_lro(struct net_device *netdev, bool enable)
3513 struct mlx5e_priv *priv = netdev_priv(netdev);
3514 struct mlx5_core_dev *mdev = priv->mdev;
3515 struct mlx5e_channels new_channels = {};
3516 struct mlx5e_params *old_params;
3520 mutex_lock(&priv->state_lock);
3522 old_params = &priv->channels.params;
3523 if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3524 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3529 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3531 new_channels.params = *old_params;
3532 new_channels.params.lro_en = enable;
3534 if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3535 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3536 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3541 *old_params = new_channels.params;
3542 err = mlx5e_modify_tirs_lro(priv);
3546 err = mlx5e_open_channels(priv, &new_channels);
3550 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3552 mutex_unlock(&priv->state_lock);
3556 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3558 struct mlx5e_priv *priv = netdev_priv(netdev);
3561 mlx5e_enable_cvlan_filter(priv);
3563 mlx5e_disable_cvlan_filter(priv);
3568 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3570 struct mlx5e_priv *priv = netdev_priv(netdev);
3572 if (!enable && mlx5e_tc_num_filters(priv)) {
3574 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3581 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3583 struct mlx5e_priv *priv = netdev_priv(netdev);
3584 struct mlx5_core_dev *mdev = priv->mdev;
3586 return mlx5_set_port_fcs(mdev, !enable);
3589 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3591 struct mlx5e_priv *priv = netdev_priv(netdev);
3594 mutex_lock(&priv->state_lock);
3596 priv->channels.params.scatter_fcs_en = enable;
3597 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3599 priv->channels.params.scatter_fcs_en = !enable;
3601 mutex_unlock(&priv->state_lock);
3606 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3608 struct mlx5e_priv *priv = netdev_priv(netdev);
3611 mutex_lock(&priv->state_lock);
3613 priv->channels.params.vlan_strip_disable = !enable;
3614 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3617 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3619 priv->channels.params.vlan_strip_disable = enable;
3622 mutex_unlock(&priv->state_lock);
3627 #ifdef CONFIG_RFS_ACCEL
3628 static int set_feature_arfs(struct net_device *netdev, bool enable)
3630 struct mlx5e_priv *priv = netdev_priv(netdev);
3634 err = mlx5e_arfs_enable(priv);
3636 err = mlx5e_arfs_disable(priv);
3642 static int mlx5e_handle_feature(struct net_device *netdev,
3643 netdev_features_t *features,
3644 netdev_features_t wanted_features,
3645 netdev_features_t feature,
3646 mlx5e_feature_handler feature_handler)
3648 netdev_features_t changes = wanted_features ^ netdev->features;
3649 bool enable = !!(wanted_features & feature);
3652 if (!(changes & feature))
3655 err = feature_handler(netdev, enable);
3657 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3658 enable ? "Enable" : "Disable", &feature, err);
3662 MLX5E_SET_FEATURE(features, feature, enable);
3666 static int mlx5e_set_features(struct net_device *netdev,
3667 netdev_features_t features)
3669 netdev_features_t oper_features = netdev->features;
3672 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3673 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3675 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3676 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3677 set_feature_cvlan_filter);
3678 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3679 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3680 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3681 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3682 #ifdef CONFIG_RFS_ACCEL
3683 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3687 netdev->features = oper_features;
3694 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3695 netdev_features_t features)
3697 struct mlx5e_priv *priv = netdev_priv(netdev);
3698 struct mlx5e_params *params;
3700 mutex_lock(&priv->state_lock);
3701 params = &priv->channels.params;
3702 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3703 /* HW strips the outer C-tag header, this is a problem
3704 * for S-tag traffic.
3706 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3707 if (!params->vlan_strip_disable)
3708 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3710 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3711 features &= ~NETIF_F_LRO;
3713 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3716 mutex_unlock(&priv->state_lock);
3721 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3722 change_hw_mtu_cb set_mtu_cb)
3724 struct mlx5e_priv *priv = netdev_priv(netdev);
3725 struct mlx5e_channels new_channels = {};
3726 struct mlx5e_params *params;
3730 mutex_lock(&priv->state_lock);
3732 params = &priv->channels.params;
3734 reset = !params->lro_en;
3735 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3737 new_channels.params = *params;
3738 new_channels.params.sw_mtu = new_mtu;
3740 if (params->xdp_prog &&
3741 !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3742 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3743 new_mtu, MLX5E_XDP_MAX_MTU);
3748 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3749 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3750 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3752 reset = reset && (ppw_old != ppw_new);
3756 params->sw_mtu = new_mtu;
3759 netdev->mtu = params->sw_mtu;
3763 err = mlx5e_open_channels(priv, &new_channels);
3767 mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
3768 netdev->mtu = new_channels.params.sw_mtu;
3771 mutex_unlock(&priv->state_lock);
3775 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3777 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3780 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3782 struct hwtstamp_config config;
3785 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3788 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3791 /* TX HW timestamp */
3792 switch (config.tx_type) {
3793 case HWTSTAMP_TX_OFF:
3794 case HWTSTAMP_TX_ON:
3800 mutex_lock(&priv->state_lock);
3801 /* RX HW timestamp */
3802 switch (config.rx_filter) {
3803 case HWTSTAMP_FILTER_NONE:
3804 /* Reset CQE compression to Admin default */
3805 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3807 case HWTSTAMP_FILTER_ALL:
3808 case HWTSTAMP_FILTER_SOME:
3809 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3810 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3811 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3812 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3813 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3814 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3815 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3816 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3817 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3818 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3819 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3820 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3821 case HWTSTAMP_FILTER_NTP_ALL:
3822 /* Disable CQE compression */
3823 netdev_warn(priv->netdev, "Disabling cqe compression");
3824 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3826 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3827 mutex_unlock(&priv->state_lock);
3830 config.rx_filter = HWTSTAMP_FILTER_ALL;
3833 mutex_unlock(&priv->state_lock);
3837 memcpy(&priv->tstamp, &config, sizeof(config));
3838 mutex_unlock(&priv->state_lock);
3840 return copy_to_user(ifr->ifr_data, &config,
3841 sizeof(config)) ? -EFAULT : 0;
3844 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3846 struct hwtstamp_config *cfg = &priv->tstamp;
3848 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3851 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3854 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3856 struct mlx5e_priv *priv = netdev_priv(dev);
3860 return mlx5e_hwstamp_set(priv, ifr);
3862 return mlx5e_hwstamp_get(priv, ifr);
3868 #ifdef CONFIG_MLX5_ESWITCH
3869 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3871 struct mlx5e_priv *priv = netdev_priv(dev);
3872 struct mlx5_core_dev *mdev = priv->mdev;
3874 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3877 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3880 struct mlx5e_priv *priv = netdev_priv(dev);
3881 struct mlx5_core_dev *mdev = priv->mdev;
3883 if (vlan_proto != htons(ETH_P_8021Q))
3884 return -EPROTONOSUPPORT;
3886 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3890 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3892 struct mlx5e_priv *priv = netdev_priv(dev);
3893 struct mlx5_core_dev *mdev = priv->mdev;
3895 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3898 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3900 struct mlx5e_priv *priv = netdev_priv(dev);
3901 struct mlx5_core_dev *mdev = priv->mdev;
3903 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3906 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3909 struct mlx5e_priv *priv = netdev_priv(dev);
3910 struct mlx5_core_dev *mdev = priv->mdev;
3912 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3913 max_tx_rate, min_tx_rate);
3916 static int mlx5_vport_link2ifla(u8 esw_link)
3919 case MLX5_VPORT_ADMIN_STATE_DOWN:
3920 return IFLA_VF_LINK_STATE_DISABLE;
3921 case MLX5_VPORT_ADMIN_STATE_UP:
3922 return IFLA_VF_LINK_STATE_ENABLE;
3924 return IFLA_VF_LINK_STATE_AUTO;
3927 static int mlx5_ifla_link2vport(u8 ifla_link)
3929 switch (ifla_link) {
3930 case IFLA_VF_LINK_STATE_DISABLE:
3931 return MLX5_VPORT_ADMIN_STATE_DOWN;
3932 case IFLA_VF_LINK_STATE_ENABLE:
3933 return MLX5_VPORT_ADMIN_STATE_UP;
3935 return MLX5_VPORT_ADMIN_STATE_AUTO;
3938 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3941 struct mlx5e_priv *priv = netdev_priv(dev);
3942 struct mlx5_core_dev *mdev = priv->mdev;
3944 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3945 mlx5_ifla_link2vport(link_state));
3948 static int mlx5e_get_vf_config(struct net_device *dev,
3949 int vf, struct ifla_vf_info *ivi)
3951 struct mlx5e_priv *priv = netdev_priv(dev);
3952 struct mlx5_core_dev *mdev = priv->mdev;
3955 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3958 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3962 static int mlx5e_get_vf_stats(struct net_device *dev,
3963 int vf, struct ifla_vf_stats *vf_stats)
3965 struct mlx5e_priv *priv = netdev_priv(dev);
3966 struct mlx5_core_dev *mdev = priv->mdev;
3968 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3973 struct mlx5e_vxlan_work {
3974 struct work_struct work;
3975 struct mlx5e_priv *priv;
3979 static void mlx5e_vxlan_add_work(struct work_struct *work)
3981 struct mlx5e_vxlan_work *vxlan_work =
3982 container_of(work, struct mlx5e_vxlan_work, work);
3983 struct mlx5e_priv *priv = vxlan_work->priv;
3984 u16 port = vxlan_work->port;
3986 mutex_lock(&priv->state_lock);
3987 mlx5_vxlan_add_port(priv->mdev->vxlan, port);
3988 mutex_unlock(&priv->state_lock);
3993 static void mlx5e_vxlan_del_work(struct work_struct *work)
3995 struct mlx5e_vxlan_work *vxlan_work =
3996 container_of(work, struct mlx5e_vxlan_work, work);
3997 struct mlx5e_priv *priv = vxlan_work->priv;
3998 u16 port = vxlan_work->port;
4000 mutex_lock(&priv->state_lock);
4001 mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4002 mutex_unlock(&priv->state_lock);
4006 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4008 struct mlx5e_vxlan_work *vxlan_work;
4010 vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4015 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4017 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4019 vxlan_work->priv = priv;
4020 vxlan_work->port = port;
4021 queue_work(priv->wq, &vxlan_work->work);
4024 static void mlx5e_add_vxlan_port(struct net_device *netdev,
4025 struct udp_tunnel_info *ti)
4027 struct mlx5e_priv *priv = netdev_priv(netdev);
4029 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4032 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4035 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4038 static void mlx5e_del_vxlan_port(struct net_device *netdev,
4039 struct udp_tunnel_info *ti)
4041 struct mlx5e_priv *priv = netdev_priv(netdev);
4043 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4046 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4049 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4052 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4053 struct sk_buff *skb,
4054 netdev_features_t features)
4056 unsigned int offset = 0;
4057 struct udphdr *udph;
4061 switch (vlan_get_protocol(skb)) {
4062 case htons(ETH_P_IP):
4063 proto = ip_hdr(skb)->protocol;
4065 case htons(ETH_P_IPV6):
4066 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4076 udph = udp_hdr(skb);
4077 port = be16_to_cpu(udph->dest);
4079 /* Verify if UDP port is being offloaded by HW */
4080 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4085 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4086 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4089 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4090 struct net_device *netdev,
4091 netdev_features_t features)
4093 struct mlx5e_priv *priv = netdev_priv(netdev);
4095 features = vlan_features_check(skb, features);
4096 features = vxlan_features_check(skb, features);
4098 #ifdef CONFIG_MLX5_EN_IPSEC
4099 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4103 /* Validate if the tunneled packet is being offloaded by HW */
4104 if (skb->encapsulation &&
4105 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4106 return mlx5e_tunnel_features_check(priv, skb, features);
4111 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4112 struct mlx5e_txqsq *sq)
4114 struct mlx5_eq *eq = sq->cq.mcq.eq;
4117 netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
4118 eq->eqn, eq->cons_index, eq->irqn);
4120 eqe_count = mlx5_eq_poll_irq_disabled(eq);
4124 netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
4125 sq->channel->stats->eq_rearm++;
4129 static void mlx5e_tx_timeout_work(struct work_struct *work)
4131 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4133 struct net_device *dev = priv->netdev;
4134 bool reopen_channels = false;
4138 mutex_lock(&priv->state_lock);
4140 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4143 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4144 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
4145 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4147 if (!netif_xmit_stopped(dev_queue))
4151 "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
4152 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4153 jiffies_to_usecs(jiffies - dev_queue->trans_start));
4155 /* If we recover a lost interrupt, most likely TX timeout will
4156 * be resolved, skip reopening channels
4158 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4159 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4160 reopen_channels = true;
4164 if (!reopen_channels)
4167 mlx5e_close_locked(dev);
4168 err = mlx5e_open_locked(dev);
4170 netdev_err(priv->netdev,
4171 "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4175 mutex_unlock(&priv->state_lock);
4179 static void mlx5e_tx_timeout(struct net_device *dev)
4181 struct mlx5e_priv *priv = netdev_priv(dev);
4183 netdev_err(dev, "TX timeout detected\n");
4184 queue_work(priv->wq, &priv->tx_timeout_work);
4187 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4189 struct net_device *netdev = priv->netdev;
4190 struct mlx5e_channels new_channels = {};
4192 if (priv->channels.params.lro_en) {
4193 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4197 if (MLX5_IPSEC_DEV(priv->mdev)) {
4198 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4202 new_channels.params = priv->channels.params;
4203 new_channels.params.xdp_prog = prog;
4205 if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4206 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4207 new_channels.params.sw_mtu, MLX5E_XDP_MAX_MTU);
4214 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4216 struct mlx5e_priv *priv = netdev_priv(netdev);
4217 struct bpf_prog *old_prog;
4218 bool reset, was_opened;
4222 mutex_lock(&priv->state_lock);
4225 err = mlx5e_xdp_allowed(priv, prog);
4230 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4231 /* no need for full reset when exchanging programs */
4232 reset = (!priv->channels.params.xdp_prog || !prog);
4234 if (was_opened && reset)
4235 mlx5e_close_locked(netdev);
4236 if (was_opened && !reset) {
4237 /* num_channels is invariant here, so we can take the
4238 * batched reference right upfront.
4240 prog = bpf_prog_add(prog, priv->channels.num);
4242 err = PTR_ERR(prog);
4247 /* exchange programs, extra prog reference we got from caller
4248 * as long as we don't fail from this point onwards.
4250 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4252 bpf_prog_put(old_prog);
4254 if (reset) /* change RQ type according to priv->xdp_prog */
4255 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4257 if (was_opened && reset)
4258 mlx5e_open_locked(netdev);
4260 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4263 /* exchanging programs w/o reset, we update ref counts on behalf
4264 * of the channels RQs here.
4266 for (i = 0; i < priv->channels.num; i++) {
4267 struct mlx5e_channel *c = priv->channels.c[i];
4269 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4270 napi_synchronize(&c->napi);
4271 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4273 old_prog = xchg(&c->rq.xdp_prog, prog);
4275 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4276 /* napi_schedule in case we have missed anything */
4277 napi_schedule(&c->napi);
4280 bpf_prog_put(old_prog);
4284 mutex_unlock(&priv->state_lock);
4288 static u32 mlx5e_xdp_query(struct net_device *dev)
4290 struct mlx5e_priv *priv = netdev_priv(dev);
4291 const struct bpf_prog *xdp_prog;
4294 mutex_lock(&priv->state_lock);
4295 xdp_prog = priv->channels.params.xdp_prog;
4297 prog_id = xdp_prog->aux->id;
4298 mutex_unlock(&priv->state_lock);
4303 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4305 switch (xdp->command) {
4306 case XDP_SETUP_PROG:
4307 return mlx5e_xdp_set(dev, xdp->prog);
4308 case XDP_QUERY_PROG:
4309 xdp->prog_id = mlx5e_xdp_query(dev);
4316 #ifdef CONFIG_NET_POLL_CONTROLLER
4317 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
4318 * reenabling interrupts.
4320 static void mlx5e_netpoll(struct net_device *dev)
4322 struct mlx5e_priv *priv = netdev_priv(dev);
4323 struct mlx5e_channels *chs = &priv->channels;
4327 for (i = 0; i < chs->num; i++)
4328 napi_schedule(&chs->c[i]->napi);
4332 static const struct net_device_ops mlx5e_netdev_ops = {
4333 .ndo_open = mlx5e_open,
4334 .ndo_stop = mlx5e_close,
4335 .ndo_start_xmit = mlx5e_xmit,
4336 .ndo_setup_tc = mlx5e_setup_tc,
4337 .ndo_select_queue = mlx5e_select_queue,
4338 .ndo_get_stats64 = mlx5e_get_stats,
4339 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4340 .ndo_set_mac_address = mlx5e_set_mac,
4341 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4342 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4343 .ndo_set_features = mlx5e_set_features,
4344 .ndo_fix_features = mlx5e_fix_features,
4345 .ndo_change_mtu = mlx5e_change_nic_mtu,
4346 .ndo_do_ioctl = mlx5e_ioctl,
4347 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4348 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
4349 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
4350 .ndo_features_check = mlx5e_features_check,
4351 #ifdef CONFIG_RFS_ACCEL
4352 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4354 .ndo_tx_timeout = mlx5e_tx_timeout,
4355 .ndo_bpf = mlx5e_xdp,
4356 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4357 #ifdef CONFIG_NET_POLL_CONTROLLER
4358 .ndo_poll_controller = mlx5e_netpoll,
4360 #ifdef CONFIG_MLX5_ESWITCH
4361 /* SRIOV E-Switch NDOs */
4362 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4363 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4364 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4365 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4366 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4367 .ndo_get_vf_config = mlx5e_get_vf_config,
4368 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4369 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4370 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4371 .ndo_get_offload_stats = mlx5e_get_offload_stats,
4375 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4377 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4379 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4380 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4381 !MLX5_CAP_ETH(mdev, csum_cap) ||
4382 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4383 !MLX5_CAP_ETH(mdev, vlan_cap) ||
4384 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4385 MLX5_CAP_FLOWTABLE(mdev,
4386 flow_table_properties_nic_receive.max_ft_level)
4388 mlx5_core_warn(mdev,
4389 "Not creating net device, some required device capabilities are missing\n");
4392 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4393 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4394 if (!MLX5_CAP_GEN(mdev, cq_moderation))
4395 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4400 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4405 for (i = 0; i < len; i++)
4406 indirection_rqt[i] = i % num_channels;
4409 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4414 mlx5e_port_max_linkspeed(mdev, &link_speed);
4415 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4416 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4417 link_speed, pci_bw);
4419 #define MLX5E_SLOW_PCI_RATIO (2)
4421 return link_speed && pci_bw &&
4422 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4425 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4427 struct net_dim_cq_moder moder;
4429 moder.cq_period_mode = cq_period_mode;
4430 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4431 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4432 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4433 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4438 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4440 struct net_dim_cq_moder moder;
4442 moder.cq_period_mode = cq_period_mode;
4443 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4444 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4445 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4446 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4451 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4453 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4454 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4455 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4458 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4460 if (params->tx_dim_enabled) {
4461 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4463 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4465 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4468 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4469 params->tx_cq_moderation.cq_period_mode ==
4470 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4473 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4475 if (params->rx_dim_enabled) {
4476 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4478 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4480 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4483 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4484 params->rx_cq_moderation.cq_period_mode ==
4485 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4488 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4492 /* The supported periods are organized in ascending order */
4493 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4494 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4497 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4500 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4501 struct mlx5e_params *params,
4502 u16 max_channels, u16 mtu)
4504 u8 rx_cq_period_mode;
4506 params->sw_mtu = mtu;
4507 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4508 params->num_channels = max_channels;
4512 params->log_sq_size = is_kdump_kernel() ?
4513 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4514 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4516 /* set CQE compression */
4517 params->rx_cqe_compress_def = false;
4518 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4519 MLX5_CAP_GEN(mdev, vport_group_manager))
4520 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4522 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4525 /* Prefer Striding RQ, unless any of the following holds:
4526 * - Striding RQ configuration is not possible/supported.
4527 * - Slow PCI heuristic.
4528 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4530 if (!slow_pci_heuristic(mdev) &&
4531 mlx5e_striding_rq_possible(mdev, params) &&
4532 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4533 !mlx5e_rx_is_linear_skb(mdev, params)))
4534 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4535 mlx5e_set_rq_type(mdev, params);
4536 mlx5e_init_rq_type_params(mdev, params);
4540 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4541 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4542 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4543 params->lro_en = !slow_pci_heuristic(mdev);
4544 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4546 /* CQ moderation params */
4547 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4548 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4549 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4550 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4551 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4552 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4553 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4556 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4559 params->rss_hfunc = ETH_RSS_HASH_XOR;
4560 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4561 mlx5e_build_default_indir_rqt(params->indirection_rqt,
4562 MLX5E_INDIR_RQT_SIZE, max_channels);
4565 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4566 struct net_device *netdev,
4567 const struct mlx5e_profile *profile,
4570 struct mlx5e_priv *priv = netdev_priv(netdev);
4573 priv->netdev = netdev;
4574 priv->profile = profile;
4575 priv->ppriv = ppriv;
4576 priv->msglevel = MLX5E_MSG_LEVEL;
4577 priv->max_opened_tc = 1;
4579 mlx5e_build_nic_params(mdev, &priv->channels.params,
4580 profile->max_nch(mdev), netdev->mtu);
4582 mutex_init(&priv->state_lock);
4584 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4585 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4586 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4587 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4589 mlx5e_timestamp_init(priv);
4592 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4594 struct mlx5e_priv *priv = netdev_priv(netdev);
4596 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4597 if (is_zero_ether_addr(netdev->dev_addr) &&
4598 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4599 eth_hw_addr_random(netdev);
4600 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4604 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4605 static const struct switchdev_ops mlx5e_switchdev_ops = {
4606 .switchdev_port_attr_get = mlx5e_attr_get,
4610 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4612 struct mlx5e_priv *priv = netdev_priv(netdev);
4613 struct mlx5_core_dev *mdev = priv->mdev;
4617 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4619 netdev->netdev_ops = &mlx5e_netdev_ops;
4621 #ifdef CONFIG_MLX5_CORE_EN_DCB
4622 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4623 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4626 netdev->watchdog_timeo = 15 * HZ;
4628 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4630 netdev->vlan_features |= NETIF_F_SG;
4631 netdev->vlan_features |= NETIF_F_IP_CSUM;
4632 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4633 netdev->vlan_features |= NETIF_F_GRO;
4634 netdev->vlan_features |= NETIF_F_TSO;
4635 netdev->vlan_features |= NETIF_F_TSO6;
4636 netdev->vlan_features |= NETIF_F_RXCSUM;
4637 netdev->vlan_features |= NETIF_F_RXHASH;
4639 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4640 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4642 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4643 mlx5e_check_fragmented_striding_rq_cap(mdev))
4644 netdev->vlan_features |= NETIF_F_LRO;
4646 netdev->hw_features = netdev->vlan_features;
4647 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4648 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4649 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4650 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4652 if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4653 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4654 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4655 netdev->hw_enc_features |= NETIF_F_TSO;
4656 netdev->hw_enc_features |= NETIF_F_TSO6;
4657 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4660 if (mlx5_vxlan_allowed(mdev->vxlan)) {
4661 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4662 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4663 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4664 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4665 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4668 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4669 netdev->hw_features |= NETIF_F_GSO_GRE |
4670 NETIF_F_GSO_GRE_CSUM;
4671 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4672 NETIF_F_GSO_GRE_CSUM;
4673 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4674 NETIF_F_GSO_GRE_CSUM;
4677 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4678 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4679 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4680 netdev->features |= NETIF_F_GSO_UDP_L4;
4682 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4685 netdev->hw_features |= NETIF_F_RXALL;
4687 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4688 netdev->hw_features |= NETIF_F_RXFCS;
4690 netdev->features = netdev->hw_features;
4691 if (!priv->channels.params.lro_en)
4692 netdev->features &= ~NETIF_F_LRO;
4695 netdev->features &= ~NETIF_F_RXALL;
4697 if (!priv->channels.params.scatter_fcs_en)
4698 netdev->features &= ~NETIF_F_RXFCS;
4700 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4701 if (FT_CAP(flow_modify_en) &&
4702 FT_CAP(modify_root) &&
4703 FT_CAP(identified_miss_table_mode) &&
4704 FT_CAP(flow_table_modify)) {
4705 netdev->hw_features |= NETIF_F_HW_TC;
4706 #ifdef CONFIG_RFS_ACCEL
4707 netdev->hw_features |= NETIF_F_NTUPLE;
4711 netdev->features |= NETIF_F_HIGHDMA;
4712 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4714 netdev->priv_flags |= IFF_UNICAST_FLT;
4716 mlx5e_set_netdev_dev_addr(netdev);
4718 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4719 if (MLX5_ESWITCH_MANAGER(mdev))
4720 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4723 mlx5e_ipsec_build_netdev(priv);
4724 mlx5e_tls_build_netdev(priv);
4727 static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4729 struct mlx5_core_dev *mdev = priv->mdev;
4732 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4734 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4735 priv->q_counter = 0;
4738 err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4740 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4741 priv->drop_rq_q_counter = 0;
4745 static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4747 if (priv->q_counter)
4748 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4750 if (priv->drop_rq_q_counter)
4751 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4754 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4755 struct net_device *netdev,
4756 const struct mlx5e_profile *profile,
4759 struct mlx5e_priv *priv = netdev_priv(netdev);
4762 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4763 err = mlx5e_ipsec_init(priv);
4765 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4766 err = mlx5e_tls_init(priv);
4768 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4769 mlx5e_build_nic_netdev(netdev);
4770 mlx5e_build_tc2txq_maps(priv);
4773 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4775 mlx5e_tls_cleanup(priv);
4776 mlx5e_ipsec_cleanup(priv);
4779 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4781 struct mlx5_core_dev *mdev = priv->mdev;
4784 err = mlx5e_create_indirect_rqt(priv);
4788 err = mlx5e_create_direct_rqts(priv);
4790 goto err_destroy_indirect_rqts;
4792 err = mlx5e_create_indirect_tirs(priv);
4794 goto err_destroy_direct_rqts;
4796 err = mlx5e_create_direct_tirs(priv);
4798 goto err_destroy_indirect_tirs;
4800 err = mlx5e_create_flow_steering(priv);
4802 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4803 goto err_destroy_direct_tirs;
4806 err = mlx5e_tc_nic_init(priv);
4808 goto err_destroy_flow_steering;
4812 err_destroy_flow_steering:
4813 mlx5e_destroy_flow_steering(priv);
4814 err_destroy_direct_tirs:
4815 mlx5e_destroy_direct_tirs(priv);
4816 err_destroy_indirect_tirs:
4817 mlx5e_destroy_indirect_tirs(priv);
4818 err_destroy_direct_rqts:
4819 mlx5e_destroy_direct_rqts(priv);
4820 err_destroy_indirect_rqts:
4821 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4825 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4827 mlx5e_tc_nic_cleanup(priv);
4828 mlx5e_destroy_flow_steering(priv);
4829 mlx5e_destroy_direct_tirs(priv);
4830 mlx5e_destroy_indirect_tirs(priv);
4831 mlx5e_destroy_direct_rqts(priv);
4832 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4835 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4839 err = mlx5e_create_tises(priv);
4841 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4845 #ifdef CONFIG_MLX5_CORE_EN_DCB
4846 mlx5e_dcbnl_initialize(priv);
4851 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4853 struct net_device *netdev = priv->netdev;
4854 struct mlx5_core_dev *mdev = priv->mdev;
4857 mlx5e_init_l2_addr(priv);
4859 /* Marking the link as currently not needed by the Driver */
4860 if (!netif_running(netdev))
4861 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4863 /* MTU range: 68 - hw-specific max */
4864 netdev->min_mtu = ETH_MIN_MTU;
4865 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4866 netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4867 mlx5e_set_dev_port_mtu(priv);
4869 mlx5_lag_add(mdev, netdev);
4871 mlx5e_enable_async_events(priv);
4873 if (MLX5_ESWITCH_MANAGER(priv->mdev))
4874 mlx5e_register_vport_reps(priv);
4876 if (netdev->reg_state != NETREG_REGISTERED)
4878 #ifdef CONFIG_MLX5_CORE_EN_DCB
4879 mlx5e_dcbnl_init_app(priv);
4882 queue_work(priv->wq, &priv->set_rx_mode_work);
4885 if (netif_running(netdev))
4887 netif_device_attach(netdev);
4891 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4893 struct mlx5_core_dev *mdev = priv->mdev;
4895 #ifdef CONFIG_MLX5_CORE_EN_DCB
4896 if (priv->netdev->reg_state == NETREG_REGISTERED)
4897 mlx5e_dcbnl_delete_app(priv);
4901 if (netif_running(priv->netdev))
4902 mlx5e_close(priv->netdev);
4903 netif_device_detach(priv->netdev);
4906 queue_work(priv->wq, &priv->set_rx_mode_work);
4908 if (MLX5_ESWITCH_MANAGER(priv->mdev))
4909 mlx5e_unregister_vport_reps(priv);
4911 mlx5e_disable_async_events(priv);
4912 mlx5_lag_remove(mdev);
4915 static const struct mlx5e_profile mlx5e_nic_profile = {
4916 .init = mlx5e_nic_init,
4917 .cleanup = mlx5e_nic_cleanup,
4918 .init_rx = mlx5e_init_nic_rx,
4919 .cleanup_rx = mlx5e_cleanup_nic_rx,
4920 .init_tx = mlx5e_init_nic_tx,
4921 .cleanup_tx = mlx5e_cleanup_nic_tx,
4922 .enable = mlx5e_nic_enable,
4923 .disable = mlx5e_nic_disable,
4924 .update_stats = mlx5e_update_ndo_stats,
4925 .max_nch = mlx5e_get_max_num_channels,
4926 .update_carrier = mlx5e_update_carrier,
4927 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4928 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4929 .max_tc = MLX5E_MAX_NUM_TC,
4932 /* mlx5e generic netdev management API (move to en_common.c) */
4934 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4935 const struct mlx5e_profile *profile,
4938 int nch = profile->max_nch(mdev);
4939 struct net_device *netdev;
4940 struct mlx5e_priv *priv;
4942 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4943 nch * profile->max_tc,
4946 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4950 #ifdef CONFIG_RFS_ACCEL
4951 netdev->rx_cpu_rmap = mdev->rmap;
4954 profile->init(mdev, netdev, profile, ppriv);
4956 netif_carrier_off(netdev);
4958 priv = netdev_priv(netdev);
4960 priv->wq = create_singlethread_workqueue("mlx5e");
4962 goto err_cleanup_nic;
4967 if (profile->cleanup)
4968 profile->cleanup(priv);
4969 free_netdev(netdev);
4974 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4976 struct mlx5_core_dev *mdev = priv->mdev;
4977 const struct mlx5e_profile *profile;
4980 profile = priv->profile;
4981 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4983 err = profile->init_tx(priv);
4987 mlx5e_create_q_counters(priv);
4989 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4991 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4992 goto err_destroy_q_counters;
4995 err = profile->init_rx(priv);
4997 goto err_close_drop_rq;
4999 if (profile->enable)
5000 profile->enable(priv);
5005 mlx5e_close_drop_rq(&priv->drop_rq);
5007 err_destroy_q_counters:
5008 mlx5e_destroy_q_counters(priv);
5009 profile->cleanup_tx(priv);
5015 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5017 const struct mlx5e_profile *profile = priv->profile;
5019 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5021 if (profile->disable)
5022 profile->disable(priv);
5023 flush_workqueue(priv->wq);
5025 profile->cleanup_rx(priv);
5026 mlx5e_close_drop_rq(&priv->drop_rq);
5027 mlx5e_destroy_q_counters(priv);
5028 profile->cleanup_tx(priv);
5029 cancel_delayed_work_sync(&priv->update_stats_work);
5032 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5034 const struct mlx5e_profile *profile = priv->profile;
5035 struct net_device *netdev = priv->netdev;
5037 destroy_workqueue(priv->wq);
5038 if (profile->cleanup)
5039 profile->cleanup(priv);
5040 free_netdev(netdev);
5043 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5044 * hardware contexts and to connect it to the current netdev.
5046 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5048 struct mlx5e_priv *priv = vpriv;
5049 struct net_device *netdev = priv->netdev;
5052 if (netif_device_present(netdev))
5055 err = mlx5e_create_mdev_resources(mdev);
5059 err = mlx5e_attach_netdev(priv);
5061 mlx5e_destroy_mdev_resources(mdev);
5068 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5070 struct mlx5e_priv *priv = vpriv;
5071 struct net_device *netdev = priv->netdev;
5073 if (!netif_device_present(netdev))
5076 mlx5e_detach_netdev(priv);
5077 mlx5e_destroy_mdev_resources(mdev);
5080 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5082 struct net_device *netdev;
5087 err = mlx5e_check_required_hca_cap(mdev);
5091 #ifdef CONFIG_MLX5_ESWITCH
5092 if (MLX5_ESWITCH_MANAGER(mdev)) {
5093 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
5095 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
5101 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
5103 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5104 goto err_free_rpriv;
5107 priv = netdev_priv(netdev);
5109 err = mlx5e_attach(mdev, priv);
5111 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5112 goto err_destroy_netdev;
5115 err = register_netdev(netdev);
5117 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5121 #ifdef CONFIG_MLX5_CORE_EN_DCB
5122 mlx5e_dcbnl_init_app(priv);
5127 mlx5e_detach(mdev, priv);
5129 mlx5e_destroy_netdev(priv);
5135 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5137 struct mlx5e_priv *priv = vpriv;
5138 void *ppriv = priv->ppriv;
5140 #ifdef CONFIG_MLX5_CORE_EN_DCB
5141 mlx5e_dcbnl_delete_app(priv);
5143 unregister_netdev(priv->netdev);
5144 mlx5e_detach(mdev, vpriv);
5145 mlx5e_destroy_netdev(priv);
5149 static void *mlx5e_get_netdev(void *vpriv)
5151 struct mlx5e_priv *priv = vpriv;
5153 return priv->netdev;
5156 static struct mlx5_interface mlx5e_interface = {
5158 .remove = mlx5e_remove,
5159 .attach = mlx5e_attach,
5160 .detach = mlx5e_detach,
5161 .event = mlx5e_async_event,
5162 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5163 .get_dev = mlx5e_get_netdev,
5166 void mlx5e_init(void)
5168 mlx5e_ipsec_build_inverse_table();
5169 mlx5e_build_ptys2ethtool_map();
5170 mlx5_register_interface(&mlx5e_interface);
5173 void mlx5e_cleanup(void)
5175 mlx5_unregister_interface(&mlx5e_interface);