net/mlx5e: Adjust to max number of channles when re-attaching
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include <net/page_pool.h>
39 #include "eswitch.h"
40 #include "en.h"
41 #include "en_tc.h"
42 #include "en_rep.h"
43 #include "en_accel/ipsec.h"
44 #include "en_accel/ipsec_rxtx.h"
45 #include "en_accel/tls.h"
46 #include "accel/ipsec.h"
47 #include "accel/tls.h"
48 #include "lib/vxlan.h"
49 #include "lib/clock.h"
50 #include "en/port.h"
51 #include "en/xdp.h"
52
53 struct mlx5e_rq_param {
54         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
55         struct mlx5_wq_param    wq;
56         struct mlx5e_rq_frags_info frags_info;
57 };
58
59 struct mlx5e_sq_param {
60         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
61         struct mlx5_wq_param       wq;
62 };
63
64 struct mlx5e_cq_param {
65         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
66         struct mlx5_wq_param       wq;
67         u16                        eq_ix;
68         u8                         cq_period_mode;
69 };
70
71 struct mlx5e_channel_param {
72         struct mlx5e_rq_param      rq;
73         struct mlx5e_sq_param      sq;
74         struct mlx5e_sq_param      xdp_sq;
75         struct mlx5e_sq_param      icosq;
76         struct mlx5e_cq_param      rx_cq;
77         struct mlx5e_cq_param      tx_cq;
78         struct mlx5e_cq_param      icosq_cq;
79 };
80
81 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
82 {
83         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
84                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
85                 MLX5_CAP_ETH(mdev, reg_umr_sq);
86         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
87         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
88
89         if (!striding_rq_umr)
90                 return false;
91         if (!inline_umr) {
92                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
93                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
94                 return false;
95         }
96         return true;
97 }
98
99 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
100 {
101         u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
102         u16 linear_rq_headroom = params->xdp_prog ?
103                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
104         u32 frag_sz;
105
106         linear_rq_headroom += NET_IP_ALIGN;
107
108         frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
109
110         if (params->xdp_prog && frag_sz < PAGE_SIZE)
111                 frag_sz = PAGE_SIZE;
112
113         return frag_sz;
114 }
115
116 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
117 {
118         u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
119
120         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
121 }
122
123 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
124                                    struct mlx5e_params *params)
125 {
126         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
127
128         return !params->lro_en && frag_sz <= PAGE_SIZE;
129 }
130
131 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
132                                          struct mlx5e_params *params)
133 {
134         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
135         s8 signed_log_num_strides_param;
136         u8 log_num_strides;
137
138         if (!mlx5e_rx_is_linear_skb(mdev, params))
139                 return false;
140
141         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
142                 return true;
143
144         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
145         signed_log_num_strides_param =
146                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
147
148         return signed_log_num_strides_param >= 0;
149 }
150
151 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
152 {
153         if (params->log_rq_mtu_frames <
154             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
155                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
156
157         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
158 }
159
160 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
161                                           struct mlx5e_params *params)
162 {
163         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
164                 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
165
166         return MLX5E_MPWQE_STRIDE_SZ(mdev,
167                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
168 }
169
170 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
171                                           struct mlx5e_params *params)
172 {
173         return MLX5_MPWRQ_LOG_WQE_SZ -
174                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
175 }
176
177 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
178                                  struct mlx5e_params *params)
179 {
180         u16 linear_rq_headroom = params->xdp_prog ?
181                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
182         bool is_linear_skb;
183
184         linear_rq_headroom += NET_IP_ALIGN;
185
186         is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
187                 mlx5e_rx_is_linear_skb(mdev, params) :
188                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
189
190         return is_linear_skb ? linear_rq_headroom : 0;
191 }
192
193 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
194                                struct mlx5e_params *params)
195 {
196         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
197         params->log_rq_mtu_frames = is_kdump_kernel() ?
198                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
199                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
200
201         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
202                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
203                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
204                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
205                        BIT(params->log_rq_mtu_frames),
206                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
207                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
208 }
209
210 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
211                                 struct mlx5e_params *params)
212 {
213         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
214                 !MLX5_IPSEC_DEV(mdev) &&
215                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
216 }
217
218 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
219 {
220         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
221                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
222                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
223                 MLX5_WQ_TYPE_CYCLIC;
224 }
225
226 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
227 {
228         struct mlx5_core_dev *mdev = priv->mdev;
229         u8 port_state;
230
231         port_state = mlx5_query_vport_state(mdev,
232                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
233                                             0);
234
235         if (port_state == VPORT_STATE_UP) {
236                 netdev_info(priv->netdev, "Link up\n");
237                 netif_carrier_on(priv->netdev);
238         } else {
239                 netdev_info(priv->netdev, "Link down\n");
240                 netif_carrier_off(priv->netdev);
241         }
242 }
243
244 static void mlx5e_update_carrier_work(struct work_struct *work)
245 {
246         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
247                                                update_carrier_work);
248
249         mutex_lock(&priv->state_lock);
250         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
251                 if (priv->profile->update_carrier)
252                         priv->profile->update_carrier(priv);
253         mutex_unlock(&priv->state_lock);
254 }
255
256 void mlx5e_update_stats(struct mlx5e_priv *priv)
257 {
258         int i;
259
260         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
261                 if (mlx5e_stats_grps[i].update_stats)
262                         mlx5e_stats_grps[i].update_stats(priv);
263 }
264
265 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
266 {
267         int i;
268
269         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
270                 if (mlx5e_stats_grps[i].update_stats_mask &
271                     MLX5E_NDO_UPDATE_STATS)
272                         mlx5e_stats_grps[i].update_stats(priv);
273 }
274
275 static void mlx5e_update_stats_work(struct work_struct *work)
276 {
277         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
278                                                update_stats_work);
279
280         mutex_lock(&priv->state_lock);
281         priv->profile->update_stats(priv);
282         mutex_unlock(&priv->state_lock);
283 }
284
285 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
286 {
287         if (!priv->profile->update_stats)
288                 return;
289
290         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
291                 return;
292
293         queue_work(priv->wq, &priv->update_stats_work);
294 }
295
296 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
297                               enum mlx5_dev_event event, unsigned long param)
298 {
299         struct mlx5e_priv *priv = vpriv;
300
301         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
302                 return;
303
304         switch (event) {
305         case MLX5_DEV_EVENT_PORT_UP:
306         case MLX5_DEV_EVENT_PORT_DOWN:
307                 queue_work(priv->wq, &priv->update_carrier_work);
308                 break;
309         default:
310                 break;
311         }
312 }
313
314 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
315 {
316         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
317 }
318
319 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
320 {
321         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
322         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
323 }
324
325 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
326                                        struct mlx5e_icosq *sq,
327                                        struct mlx5e_umr_wqe *wqe)
328 {
329         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
330         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
331         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
332
333         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
334                                       ds_cnt);
335         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
336         cseg->imm       = rq->mkey_be;
337
338         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
339         ucseg->xlt_octowords =
340                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
341         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
342 }
343
344 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
345 {
346         switch (rq->wq_type) {
347         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
348                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
349         default:
350                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
351         }
352 }
353
354 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
355 {
356         switch (rq->wq_type) {
357         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
358                 return rq->mpwqe.wq.cur_sz;
359         default:
360                 return rq->wqe.wq.cur_sz;
361         }
362 }
363
364 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
365                                      struct mlx5e_channel *c)
366 {
367         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
368
369         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
370                                                   sizeof(*rq->mpwqe.info)),
371                                        GFP_KERNEL, cpu_to_node(c->cpu));
372         if (!rq->mpwqe.info)
373                 return -ENOMEM;
374
375         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
376
377         return 0;
378 }
379
380 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
381                                  u64 npages, u8 page_shift,
382                                  struct mlx5_core_mkey *umr_mkey)
383 {
384         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
385         void *mkc;
386         u32 *in;
387         int err;
388
389         in = kvzalloc(inlen, GFP_KERNEL);
390         if (!in)
391                 return -ENOMEM;
392
393         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
394
395         MLX5_SET(mkc, mkc, free, 1);
396         MLX5_SET(mkc, mkc, umr_en, 1);
397         MLX5_SET(mkc, mkc, lw, 1);
398         MLX5_SET(mkc, mkc, lr, 1);
399         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
400
401         MLX5_SET(mkc, mkc, qpn, 0xffffff);
402         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
403         MLX5_SET64(mkc, mkc, len, npages << page_shift);
404         MLX5_SET(mkc, mkc, translations_octword_size,
405                  MLX5_MTT_OCTW(npages));
406         MLX5_SET(mkc, mkc, log_page_size, page_shift);
407
408         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
409
410         kvfree(in);
411         return err;
412 }
413
414 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
415 {
416         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
417
418         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
419 }
420
421 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
422 {
423         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
424 }
425
426 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
427 {
428         struct mlx5e_wqe_frag_info next_frag, *prev;
429         int i;
430
431         next_frag.di = &rq->wqe.di[0];
432         next_frag.offset = 0;
433         prev = NULL;
434
435         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
436                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
437                 struct mlx5e_wqe_frag_info *frag =
438                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
439                 int f;
440
441                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
442                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
443                                 next_frag.di++;
444                                 next_frag.offset = 0;
445                                 if (prev)
446                                         prev->last_in_page = true;
447                         }
448                         *frag = next_frag;
449
450                         /* prepare next */
451                         next_frag.offset += frag_info[f].frag_stride;
452                         prev = frag;
453                 }
454         }
455
456         if (prev)
457                 prev->last_in_page = true;
458 }
459
460 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
461                               struct mlx5e_params *params,
462                               int wq_sz, int cpu)
463 {
464         int len = wq_sz << rq->wqe.info.log_num_frags;
465
466         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
467                                    GFP_KERNEL, cpu_to_node(cpu));
468         if (!rq->wqe.di)
469                 return -ENOMEM;
470
471         mlx5e_init_frags_partition(rq);
472
473         return 0;
474 }
475
476 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
477 {
478         kvfree(rq->wqe.di);
479 }
480
481 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
482                           struct mlx5e_params *params,
483                           struct mlx5e_rq_param *rqp,
484                           struct mlx5e_rq *rq)
485 {
486         struct page_pool_params pp_params = { 0 };
487         struct mlx5_core_dev *mdev = c->mdev;
488         void *rqc = rqp->rqc;
489         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
490         u32 pool_size;
491         int wq_sz;
492         int err;
493         int i;
494
495         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
496
497         rq->wq_type = params->rq_wq_type;
498         rq->pdev    = c->pdev;
499         rq->netdev  = c->netdev;
500         rq->tstamp  = c->tstamp;
501         rq->clock   = &mdev->clock;
502         rq->channel = c;
503         rq->ix      = c->ix;
504         rq->mdev    = mdev;
505         rq->stats   = &c->priv->channel_stats[c->ix].rq;
506
507         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
508         if (IS_ERR(rq->xdp_prog)) {
509                 err = PTR_ERR(rq->xdp_prog);
510                 rq->xdp_prog = NULL;
511                 goto err_rq_wq_destroy;
512         }
513
514         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
515         if (err < 0)
516                 goto err_rq_wq_destroy;
517
518         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
519         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
520         pool_size = 1 << params->log_rq_mtu_frames;
521
522         switch (rq->wq_type) {
523         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
524                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
525                                         &rq->wq_ctrl);
526                 if (err)
527                         return err;
528
529                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
530
531                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
532
533                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
534
535                 rq->post_wqes = mlx5e_post_rx_mpwqes;
536                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
537
538                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
539 #ifdef CONFIG_MLX5_EN_IPSEC
540                 if (MLX5_IPSEC_DEV(mdev)) {
541                         err = -EINVAL;
542                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
543                         goto err_rq_wq_destroy;
544                 }
545 #endif
546                 if (!rq->handle_rx_cqe) {
547                         err = -EINVAL;
548                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
549                         goto err_rq_wq_destroy;
550                 }
551
552                 rq->mpwqe.skb_from_cqe_mpwrq =
553                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
554                         mlx5e_skb_from_cqe_mpwrq_linear :
555                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
556                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
557                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
558
559                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
560                 if (err)
561                         goto err_rq_wq_destroy;
562                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
563
564                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
565                 if (err)
566                         goto err_free;
567                 break;
568         default: /* MLX5_WQ_TYPE_CYCLIC */
569                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
570                                          &rq->wq_ctrl);
571                 if (err)
572                         return err;
573
574                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
575
576                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
577
578                 rq->wqe.info = rqp->frags_info;
579                 rq->wqe.frags =
580                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
581                                         (wq_sz << rq->wqe.info.log_num_frags)),
582                                       GFP_KERNEL, cpu_to_node(c->cpu));
583                 if (!rq->wqe.frags) {
584                         err = -ENOMEM;
585                         goto err_free;
586                 }
587
588                 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
589                 if (err)
590                         goto err_free;
591                 rq->post_wqes = mlx5e_post_rx_wqes;
592                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
593
594 #ifdef CONFIG_MLX5_EN_IPSEC
595                 if (c->priv->ipsec)
596                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
597                 else
598 #endif
599                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
600                 if (!rq->handle_rx_cqe) {
601                         err = -EINVAL;
602                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
603                         goto err_free;
604                 }
605
606                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
607                         mlx5e_skb_from_cqe_linear :
608                         mlx5e_skb_from_cqe_nonlinear;
609                 rq->mkey_be = c->mkey_be;
610         }
611
612         /* Create a page_pool and register it with rxq */
613         pp_params.order     = 0;
614         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
615         pp_params.pool_size = pool_size;
616         pp_params.nid       = cpu_to_node(c->cpu);
617         pp_params.dev       = c->pdev;
618         pp_params.dma_dir   = rq->buff.map_dir;
619
620         /* page_pool can be used even when there is no rq->xdp_prog,
621          * given page_pool does not handle DMA mapping there is no
622          * required state to clear. And page_pool gracefully handle
623          * elevated refcnt.
624          */
625         rq->page_pool = page_pool_create(&pp_params);
626         if (IS_ERR(rq->page_pool)) {
627                 err = PTR_ERR(rq->page_pool);
628                 rq->page_pool = NULL;
629                 goto err_free;
630         }
631         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
632                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
633         if (err)
634                 goto err_free;
635
636         for (i = 0; i < wq_sz; i++) {
637                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
638                         struct mlx5e_rx_wqe_ll *wqe =
639                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
640                         u32 byte_count =
641                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
642                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
643
644                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
645                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
646                         wqe->data[0].lkey = rq->mkey_be;
647                 } else {
648                         struct mlx5e_rx_wqe_cyc *wqe =
649                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
650                         int f;
651
652                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
653                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
654                                         MLX5_HW_START_PADDING;
655
656                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
657                                 wqe->data[f].lkey = rq->mkey_be;
658                         }
659                         /* check if num_frags is not a pow of two */
660                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
661                                 wqe->data[f].byte_count = 0;
662                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
663                                 wqe->data[f].addr = 0;
664                         }
665                 }
666         }
667
668         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
669
670         switch (params->rx_cq_moderation.cq_period_mode) {
671         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
672                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
673                 break;
674         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
675         default:
676                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
677         }
678
679         rq->page_cache.head = 0;
680         rq->page_cache.tail = 0;
681
682         return 0;
683
684 err_free:
685         switch (rq->wq_type) {
686         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
687                 kvfree(rq->mpwqe.info);
688                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
689                 break;
690         default: /* MLX5_WQ_TYPE_CYCLIC */
691                 kvfree(rq->wqe.frags);
692                 mlx5e_free_di_list(rq);
693         }
694
695 err_rq_wq_destroy:
696         if (rq->xdp_prog)
697                 bpf_prog_put(rq->xdp_prog);
698         xdp_rxq_info_unreg(&rq->xdp_rxq);
699         if (rq->page_pool)
700                 page_pool_destroy(rq->page_pool);
701         mlx5_wq_destroy(&rq->wq_ctrl);
702
703         return err;
704 }
705
706 static void mlx5e_free_rq(struct mlx5e_rq *rq)
707 {
708         int i;
709
710         if (rq->xdp_prog)
711                 bpf_prog_put(rq->xdp_prog);
712
713         xdp_rxq_info_unreg(&rq->xdp_rxq);
714         if (rq->page_pool)
715                 page_pool_destroy(rq->page_pool);
716
717         switch (rq->wq_type) {
718         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
719                 kvfree(rq->mpwqe.info);
720                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
721                 break;
722         default: /* MLX5_WQ_TYPE_CYCLIC */
723                 kvfree(rq->wqe.frags);
724                 mlx5e_free_di_list(rq);
725         }
726
727         for (i = rq->page_cache.head; i != rq->page_cache.tail;
728              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
729                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
730
731                 mlx5e_page_release(rq, dma_info, false);
732         }
733         mlx5_wq_destroy(&rq->wq_ctrl);
734 }
735
736 static int mlx5e_create_rq(struct mlx5e_rq *rq,
737                            struct mlx5e_rq_param *param)
738 {
739         struct mlx5_core_dev *mdev = rq->mdev;
740
741         void *in;
742         void *rqc;
743         void *wq;
744         int inlen;
745         int err;
746
747         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
748                 sizeof(u64) * rq->wq_ctrl.buf.npages;
749         in = kvzalloc(inlen, GFP_KERNEL);
750         if (!in)
751                 return -ENOMEM;
752
753         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
754         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
755
756         memcpy(rqc, param->rqc, sizeof(param->rqc));
757
758         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
759         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
760         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
761                                                 MLX5_ADAPTER_PAGE_SHIFT);
762         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
763
764         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
765                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
766
767         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
768
769         kvfree(in);
770
771         return err;
772 }
773
774 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
775                                  int next_state)
776 {
777         struct mlx5_core_dev *mdev = rq->mdev;
778
779         void *in;
780         void *rqc;
781         int inlen;
782         int err;
783
784         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
785         in = kvzalloc(inlen, GFP_KERNEL);
786         if (!in)
787                 return -ENOMEM;
788
789         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
790
791         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
792         MLX5_SET(rqc, rqc, state, next_state);
793
794         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
795
796         kvfree(in);
797
798         return err;
799 }
800
801 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
802 {
803         struct mlx5e_channel *c = rq->channel;
804         struct mlx5e_priv *priv = c->priv;
805         struct mlx5_core_dev *mdev = priv->mdev;
806
807         void *in;
808         void *rqc;
809         int inlen;
810         int err;
811
812         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
813         in = kvzalloc(inlen, GFP_KERNEL);
814         if (!in)
815                 return -ENOMEM;
816
817         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
818
819         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
820         MLX5_SET64(modify_rq_in, in, modify_bitmask,
821                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
822         MLX5_SET(rqc, rqc, scatter_fcs, enable);
823         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
824
825         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
826
827         kvfree(in);
828
829         return err;
830 }
831
832 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
833 {
834         struct mlx5e_channel *c = rq->channel;
835         struct mlx5_core_dev *mdev = c->mdev;
836         void *in;
837         void *rqc;
838         int inlen;
839         int err;
840
841         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
842         in = kvzalloc(inlen, GFP_KERNEL);
843         if (!in)
844                 return -ENOMEM;
845
846         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
847
848         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
849         MLX5_SET64(modify_rq_in, in, modify_bitmask,
850                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
851         MLX5_SET(rqc, rqc, vsd, vsd);
852         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
853
854         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
855
856         kvfree(in);
857
858         return err;
859 }
860
861 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
862 {
863         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
864 }
865
866 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
867 {
868         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
869         struct mlx5e_channel *c = rq->channel;
870
871         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
872
873         do {
874                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
875                         return 0;
876
877                 msleep(20);
878         } while (time_before(jiffies, exp_time));
879
880         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
881                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
882
883         return -ETIMEDOUT;
884 }
885
886 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
887 {
888         __be16 wqe_ix_be;
889         u16 wqe_ix;
890
891         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
892                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
893
894                 /* UMR WQE (if in progress) is always at wq->head */
895                 if (rq->mpwqe.umr_in_progress)
896                         rq->dealloc_wqe(rq, wq->head);
897
898                 while (!mlx5_wq_ll_is_empty(wq)) {
899                         struct mlx5e_rx_wqe_ll *wqe;
900
901                         wqe_ix_be = *wq->tail_next;
902                         wqe_ix    = be16_to_cpu(wqe_ix_be);
903                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
904                         rq->dealloc_wqe(rq, wqe_ix);
905                         mlx5_wq_ll_pop(wq, wqe_ix_be,
906                                        &wqe->next.next_wqe_index);
907                 }
908         } else {
909                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
910
911                 while (!mlx5_wq_cyc_is_empty(wq)) {
912                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
913                         rq->dealloc_wqe(rq, wqe_ix);
914                         mlx5_wq_cyc_pop(wq);
915                 }
916         }
917
918 }
919
920 static int mlx5e_open_rq(struct mlx5e_channel *c,
921                          struct mlx5e_params *params,
922                          struct mlx5e_rq_param *param,
923                          struct mlx5e_rq *rq)
924 {
925         int err;
926
927         err = mlx5e_alloc_rq(c, params, param, rq);
928         if (err)
929                 return err;
930
931         err = mlx5e_create_rq(rq, param);
932         if (err)
933                 goto err_free_rq;
934
935         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
936         if (err)
937                 goto err_destroy_rq;
938
939         if (params->rx_dim_enabled)
940                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
941
942         if (params->pflags & MLX5E_PFLAG_RX_NO_CSUM_COMPLETE)
943                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
944
945         return 0;
946
947 err_destroy_rq:
948         mlx5e_destroy_rq(rq);
949 err_free_rq:
950         mlx5e_free_rq(rq);
951
952         return err;
953 }
954
955 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
956 {
957         struct mlx5e_icosq *sq = &rq->channel->icosq;
958         struct mlx5_wq_cyc *wq = &sq->wq;
959         struct mlx5e_tx_wqe *nopwqe;
960
961         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
962
963         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
964         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
965         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
966         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
967 }
968
969 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
970 {
971         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
972         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
973 }
974
975 static void mlx5e_close_rq(struct mlx5e_rq *rq)
976 {
977         cancel_work_sync(&rq->dim.work);
978         mlx5e_destroy_rq(rq);
979         mlx5e_free_rx_descs(rq);
980         mlx5e_free_rq(rq);
981 }
982
983 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
984 {
985         kvfree(sq->db.xdpi);
986 }
987
988 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
989 {
990         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
991
992         sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)),
993                                     GFP_KERNEL, numa);
994         if (!sq->db.xdpi) {
995                 mlx5e_free_xdpsq_db(sq);
996                 return -ENOMEM;
997         }
998
999         return 0;
1000 }
1001
1002 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1003                              struct mlx5e_params *params,
1004                              struct mlx5e_sq_param *param,
1005                              struct mlx5e_xdpsq *sq,
1006                              bool is_redirect)
1007 {
1008         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1009         struct mlx5_core_dev *mdev = c->mdev;
1010         struct mlx5_wq_cyc *wq = &sq->wq;
1011         int err;
1012
1013         sq->pdev      = c->pdev;
1014         sq->mkey_be   = c->mkey_be;
1015         sq->channel   = c;
1016         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1017         sq->min_inline_mode = params->tx_min_inline_mode;
1018         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1019         sq->stats     = is_redirect ?
1020                 &c->priv->channel_stats[c->ix].xdpsq :
1021                 &c->priv->channel_stats[c->ix].rq_xdpsq;
1022
1023         param->wq.db_numa_node = cpu_to_node(c->cpu);
1024         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1025         if (err)
1026                 return err;
1027         wq->db = &wq->db[MLX5_SND_DBR];
1028
1029         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1030         if (err)
1031                 goto err_sq_wq_destroy;
1032
1033         return 0;
1034
1035 err_sq_wq_destroy:
1036         mlx5_wq_destroy(&sq->wq_ctrl);
1037
1038         return err;
1039 }
1040
1041 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1042 {
1043         mlx5e_free_xdpsq_db(sq);
1044         mlx5_wq_destroy(&sq->wq_ctrl);
1045 }
1046
1047 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1048 {
1049         kvfree(sq->db.ico_wqe);
1050 }
1051
1052 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1053 {
1054         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1055
1056         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1057                                                   sizeof(*sq->db.ico_wqe)),
1058                                        GFP_KERNEL, numa);
1059         if (!sq->db.ico_wqe)
1060                 return -ENOMEM;
1061
1062         return 0;
1063 }
1064
1065 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1066                              struct mlx5e_sq_param *param,
1067                              struct mlx5e_icosq *sq)
1068 {
1069         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1070         struct mlx5_core_dev *mdev = c->mdev;
1071         struct mlx5_wq_cyc *wq = &sq->wq;
1072         int err;
1073
1074         sq->channel   = c;
1075         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1076
1077         param->wq.db_numa_node = cpu_to_node(c->cpu);
1078         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1079         if (err)
1080                 return err;
1081         wq->db = &wq->db[MLX5_SND_DBR];
1082
1083         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1084         if (err)
1085                 goto err_sq_wq_destroy;
1086
1087         return 0;
1088
1089 err_sq_wq_destroy:
1090         mlx5_wq_destroy(&sq->wq_ctrl);
1091
1092         return err;
1093 }
1094
1095 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1096 {
1097         mlx5e_free_icosq_db(sq);
1098         mlx5_wq_destroy(&sq->wq_ctrl);
1099 }
1100
1101 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1102 {
1103         kvfree(sq->db.wqe_info);
1104         kvfree(sq->db.dma_fifo);
1105 }
1106
1107 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1108 {
1109         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1110         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1111
1112         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1113                                                    sizeof(*sq->db.dma_fifo)),
1114                                         GFP_KERNEL, numa);
1115         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1116                                                    sizeof(*sq->db.wqe_info)),
1117                                         GFP_KERNEL, numa);
1118         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1119                 mlx5e_free_txqsq_db(sq);
1120                 return -ENOMEM;
1121         }
1122
1123         sq->dma_fifo_mask = df_sz - 1;
1124
1125         return 0;
1126 }
1127
1128 static void mlx5e_sq_recover(struct work_struct *work);
1129 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1130                              int txq_ix,
1131                              struct mlx5e_params *params,
1132                              struct mlx5e_sq_param *param,
1133                              struct mlx5e_txqsq *sq,
1134                              int tc)
1135 {
1136         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1137         struct mlx5_core_dev *mdev = c->mdev;
1138         struct mlx5_wq_cyc *wq = &sq->wq;
1139         int err;
1140
1141         sq->pdev      = c->pdev;
1142         sq->tstamp    = c->tstamp;
1143         sq->clock     = &mdev->clock;
1144         sq->mkey_be   = c->mkey_be;
1145         sq->channel   = c;
1146         sq->txq_ix    = txq_ix;
1147         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1148         sq->min_inline_mode = params->tx_min_inline_mode;
1149         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1150         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1151         if (MLX5_IPSEC_DEV(c->priv->mdev))
1152                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1153         if (mlx5_accel_is_tls_device(c->priv->mdev))
1154                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1155
1156         param->wq.db_numa_node = cpu_to_node(c->cpu);
1157         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1158         if (err)
1159                 return err;
1160         wq->db    = &wq->db[MLX5_SND_DBR];
1161
1162         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1163         if (err)
1164                 goto err_sq_wq_destroy;
1165
1166         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1167         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1168
1169         return 0;
1170
1171 err_sq_wq_destroy:
1172         mlx5_wq_destroy(&sq->wq_ctrl);
1173
1174         return err;
1175 }
1176
1177 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1178 {
1179         mlx5e_free_txqsq_db(sq);
1180         mlx5_wq_destroy(&sq->wq_ctrl);
1181 }
1182
1183 struct mlx5e_create_sq_param {
1184         struct mlx5_wq_ctrl        *wq_ctrl;
1185         u32                         cqn;
1186         u32                         tisn;
1187         u8                          tis_lst_sz;
1188         u8                          min_inline_mode;
1189 };
1190
1191 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1192                            struct mlx5e_sq_param *param,
1193                            struct mlx5e_create_sq_param *csp,
1194                            u32 *sqn)
1195 {
1196         void *in;
1197         void *sqc;
1198         void *wq;
1199         int inlen;
1200         int err;
1201
1202         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1203                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1204         in = kvzalloc(inlen, GFP_KERNEL);
1205         if (!in)
1206                 return -ENOMEM;
1207
1208         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1209         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1210
1211         memcpy(sqc, param->sqc, sizeof(param->sqc));
1212         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1213         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1214         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1215
1216         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1217                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1218
1219         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1220         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1221
1222         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1223         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1224         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1225                                           MLX5_ADAPTER_PAGE_SHIFT);
1226         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1227
1228         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1229                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1230
1231         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1232
1233         kvfree(in);
1234
1235         return err;
1236 }
1237
1238 struct mlx5e_modify_sq_param {
1239         int curr_state;
1240         int next_state;
1241         bool rl_update;
1242         int rl_index;
1243 };
1244
1245 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1246                            struct mlx5e_modify_sq_param *p)
1247 {
1248         void *in;
1249         void *sqc;
1250         int inlen;
1251         int err;
1252
1253         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1254         in = kvzalloc(inlen, GFP_KERNEL);
1255         if (!in)
1256                 return -ENOMEM;
1257
1258         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1259
1260         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1261         MLX5_SET(sqc, sqc, state, p->next_state);
1262         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1263                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1264                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1265         }
1266
1267         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1268
1269         kvfree(in);
1270
1271         return err;
1272 }
1273
1274 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1275 {
1276         mlx5_core_destroy_sq(mdev, sqn);
1277 }
1278
1279 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1280                                struct mlx5e_sq_param *param,
1281                                struct mlx5e_create_sq_param *csp,
1282                                u32 *sqn)
1283 {
1284         struct mlx5e_modify_sq_param msp = {0};
1285         int err;
1286
1287         err = mlx5e_create_sq(mdev, param, csp, sqn);
1288         if (err)
1289                 return err;
1290
1291         msp.curr_state = MLX5_SQC_STATE_RST;
1292         msp.next_state = MLX5_SQC_STATE_RDY;
1293         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1294         if (err)
1295                 mlx5e_destroy_sq(mdev, *sqn);
1296
1297         return err;
1298 }
1299
1300 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1301                                 struct mlx5e_txqsq *sq, u32 rate);
1302
1303 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1304                             u32 tisn,
1305                             int txq_ix,
1306                             struct mlx5e_params *params,
1307                             struct mlx5e_sq_param *param,
1308                             struct mlx5e_txqsq *sq,
1309                             int tc)
1310 {
1311         struct mlx5e_create_sq_param csp = {};
1312         u32 tx_rate;
1313         int err;
1314
1315         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1316         if (err)
1317                 return err;
1318
1319         csp.tisn            = tisn;
1320         csp.tis_lst_sz      = 1;
1321         csp.cqn             = sq->cq.mcq.cqn;
1322         csp.wq_ctrl         = &sq->wq_ctrl;
1323         csp.min_inline_mode = sq->min_inline_mode;
1324         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1325         if (err)
1326                 goto err_free_txqsq;
1327
1328         tx_rate = c->priv->tx_rates[sq->txq_ix];
1329         if (tx_rate)
1330                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1331
1332         if (params->tx_dim_enabled)
1333                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1334
1335         return 0;
1336
1337 err_free_txqsq:
1338         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1339         mlx5e_free_txqsq(sq);
1340
1341         return err;
1342 }
1343
1344 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1345 {
1346         WARN_ONCE(sq->cc != sq->pc,
1347                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1348                   sq->sqn, sq->cc, sq->pc);
1349         sq->cc = 0;
1350         sq->dma_fifo_cc = 0;
1351         sq->pc = 0;
1352 }
1353
1354 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1355 {
1356         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1357         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1358         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1359         netdev_tx_reset_queue(sq->txq);
1360         netif_tx_start_queue(sq->txq);
1361 }
1362
1363 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1364 {
1365         __netif_tx_lock_bh(txq);
1366         netif_tx_stop_queue(txq);
1367         __netif_tx_unlock_bh(txq);
1368 }
1369
1370 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1371 {
1372         struct mlx5e_channel *c = sq->channel;
1373         struct mlx5_wq_cyc *wq = &sq->wq;
1374
1375         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1376         /* prevent netif_tx_wake_queue */
1377         napi_synchronize(&c->napi);
1378
1379         netif_tx_disable_queue(sq->txq);
1380
1381         /* last doorbell out, godspeed .. */
1382         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1383                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1384                 struct mlx5e_tx_wqe *nop;
1385
1386                 sq->db.wqe_info[pi].skb = NULL;
1387                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1388                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1389         }
1390 }
1391
1392 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1393 {
1394         struct mlx5e_channel *c = sq->channel;
1395         struct mlx5_core_dev *mdev = c->mdev;
1396         struct mlx5_rate_limit rl = {0};
1397
1398         mlx5e_destroy_sq(mdev, sq->sqn);
1399         if (sq->rate_limit) {
1400                 rl.rate = sq->rate_limit;
1401                 mlx5_rl_remove_rate(mdev, &rl);
1402         }
1403         mlx5e_free_txqsq_descs(sq);
1404         mlx5e_free_txqsq(sq);
1405 }
1406
1407 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1408 {
1409         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1410
1411         while (time_before(jiffies, exp_time)) {
1412                 if (sq->cc == sq->pc)
1413                         return 0;
1414
1415                 msleep(20);
1416         }
1417
1418         netdev_err(sq->channel->netdev,
1419                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1420                    sq->sqn, sq->cc, sq->pc);
1421
1422         return -ETIMEDOUT;
1423 }
1424
1425 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1426 {
1427         struct mlx5_core_dev *mdev = sq->channel->mdev;
1428         struct net_device *dev = sq->channel->netdev;
1429         struct mlx5e_modify_sq_param msp = {0};
1430         int err;
1431
1432         msp.curr_state = curr_state;
1433         msp.next_state = MLX5_SQC_STATE_RST;
1434
1435         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1436         if (err) {
1437                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1438                 return err;
1439         }
1440
1441         memset(&msp, 0, sizeof(msp));
1442         msp.curr_state = MLX5_SQC_STATE_RST;
1443         msp.next_state = MLX5_SQC_STATE_RDY;
1444
1445         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1446         if (err) {
1447                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1448                 return err;
1449         }
1450
1451         return 0;
1452 }
1453
1454 static void mlx5e_sq_recover(struct work_struct *work)
1455 {
1456         struct mlx5e_txqsq_recover *recover =
1457                 container_of(work, struct mlx5e_txqsq_recover,
1458                              recover_work);
1459         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1460                                               recover);
1461         struct mlx5_core_dev *mdev = sq->channel->mdev;
1462         struct net_device *dev = sq->channel->netdev;
1463         u8 state;
1464         int err;
1465
1466         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1467         if (err) {
1468                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1469                            sq->sqn, err);
1470                 return;
1471         }
1472
1473         if (state != MLX5_RQC_STATE_ERR) {
1474                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1475                 return;
1476         }
1477
1478         netif_tx_disable_queue(sq->txq);
1479
1480         if (mlx5e_wait_for_sq_flush(sq))
1481                 return;
1482
1483         /* If the interval between two consecutive recovers per SQ is too
1484          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1485          * If we reached this state, there is probably a bug that needs to be
1486          * fixed. let's keep the queue close and let tx timeout cleanup.
1487          */
1488         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1489             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1490                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1491                            sq->sqn);
1492                 return;
1493         }
1494
1495         /* At this point, no new packets will arrive from the stack as TXQ is
1496          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1497          * pending WQEs.  SQ can safely reset the SQ.
1498          */
1499         if (mlx5e_sq_to_ready(sq, state))
1500                 return;
1501
1502         mlx5e_reset_txqsq_cc_pc(sq);
1503         sq->stats->recover++;
1504         recover->last_recover = jiffies;
1505         mlx5e_activate_txqsq(sq);
1506 }
1507
1508 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1509                             struct mlx5e_params *params,
1510                             struct mlx5e_sq_param *param,
1511                             struct mlx5e_icosq *sq)
1512 {
1513         struct mlx5e_create_sq_param csp = {};
1514         int err;
1515
1516         err = mlx5e_alloc_icosq(c, param, sq);
1517         if (err)
1518                 return err;
1519
1520         csp.cqn             = sq->cq.mcq.cqn;
1521         csp.wq_ctrl         = &sq->wq_ctrl;
1522         csp.min_inline_mode = params->tx_min_inline_mode;
1523         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1524         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1525         if (err)
1526                 goto err_free_icosq;
1527
1528         return 0;
1529
1530 err_free_icosq:
1531         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1532         mlx5e_free_icosq(sq);
1533
1534         return err;
1535 }
1536
1537 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1538 {
1539         struct mlx5e_channel *c = sq->channel;
1540
1541         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1542         napi_synchronize(&c->napi);
1543
1544         mlx5e_destroy_sq(c->mdev, sq->sqn);
1545         mlx5e_free_icosq(sq);
1546 }
1547
1548 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1549                             struct mlx5e_params *params,
1550                             struct mlx5e_sq_param *param,
1551                             struct mlx5e_xdpsq *sq,
1552                             bool is_redirect)
1553 {
1554         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1555         struct mlx5e_create_sq_param csp = {};
1556         unsigned int inline_hdr_sz = 0;
1557         int err;
1558         int i;
1559
1560         err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1561         if (err)
1562                 return err;
1563
1564         csp.tis_lst_sz      = 1;
1565         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1566         csp.cqn             = sq->cq.mcq.cqn;
1567         csp.wq_ctrl         = &sq->wq_ctrl;
1568         csp.min_inline_mode = sq->min_inline_mode;
1569         if (is_redirect)
1570                 set_bit(MLX5E_SQ_STATE_REDIRECT, &sq->state);
1571         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1572         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1573         if (err)
1574                 goto err_free_xdpsq;
1575
1576         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1577                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1578                 ds_cnt++;
1579         }
1580
1581         /* Pre initialize fixed WQE fields */
1582         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1583                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1584                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1585                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1586                 struct mlx5_wqe_data_seg *dseg;
1587
1588                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1589                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1590
1591                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1592                 dseg->lkey = sq->mkey_be;
1593         }
1594
1595         return 0;
1596
1597 err_free_xdpsq:
1598         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1599         mlx5e_free_xdpsq(sq);
1600
1601         return err;
1602 }
1603
1604 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1605 {
1606         struct mlx5e_channel *c = sq->channel;
1607
1608         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1609         napi_synchronize(&c->napi);
1610
1611         mlx5e_destroy_sq(c->mdev, sq->sqn);
1612         mlx5e_free_xdpsq_descs(sq);
1613         mlx5e_free_xdpsq(sq);
1614 }
1615
1616 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1617                                  struct mlx5e_cq_param *param,
1618                                  struct mlx5e_cq *cq)
1619 {
1620         struct mlx5_core_cq *mcq = &cq->mcq;
1621         int eqn_not_used;
1622         unsigned int irqn;
1623         int err;
1624         u32 i;
1625
1626         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1627         if (err)
1628                 return err;
1629
1630         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1631                                &cq->wq_ctrl);
1632         if (err)
1633                 return err;
1634
1635         mcq->cqe_sz     = 64;
1636         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1637         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1638         *mcq->set_ci_db = 0;
1639         *mcq->arm_db    = 0;
1640         mcq->vector     = param->eq_ix;
1641         mcq->comp       = mlx5e_completion_event;
1642         mcq->event      = mlx5e_cq_error_event;
1643         mcq->irqn       = irqn;
1644
1645         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1646                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1647
1648                 cqe->op_own = 0xf1;
1649         }
1650
1651         cq->mdev = mdev;
1652
1653         return 0;
1654 }
1655
1656 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1657                           struct mlx5e_cq_param *param,
1658                           struct mlx5e_cq *cq)
1659 {
1660         struct mlx5_core_dev *mdev = c->priv->mdev;
1661         int err;
1662
1663         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1664         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1665         param->eq_ix   = c->ix;
1666
1667         err = mlx5e_alloc_cq_common(mdev, param, cq);
1668
1669         cq->napi    = &c->napi;
1670         cq->channel = c;
1671
1672         return err;
1673 }
1674
1675 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1676 {
1677         mlx5_wq_destroy(&cq->wq_ctrl);
1678 }
1679
1680 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1681 {
1682         struct mlx5_core_dev *mdev = cq->mdev;
1683         struct mlx5_core_cq *mcq = &cq->mcq;
1684
1685         void *in;
1686         void *cqc;
1687         int inlen;
1688         unsigned int irqn_not_used;
1689         int eqn;
1690         int err;
1691
1692         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1693         if (err)
1694                 return err;
1695
1696         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1697                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1698         in = kvzalloc(inlen, GFP_KERNEL);
1699         if (!in)
1700                 return -ENOMEM;
1701
1702         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1703
1704         memcpy(cqc, param->cqc, sizeof(param->cqc));
1705
1706         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1707                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1708
1709         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1710         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1711         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1712         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1713                                             MLX5_ADAPTER_PAGE_SHIFT);
1714         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1715
1716         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1717
1718         kvfree(in);
1719
1720         if (err)
1721                 return err;
1722
1723         mlx5e_cq_arm(cq);
1724
1725         return 0;
1726 }
1727
1728 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1729 {
1730         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1731 }
1732
1733 static int mlx5e_open_cq(struct mlx5e_channel *c,
1734                          struct net_dim_cq_moder moder,
1735                          struct mlx5e_cq_param *param,
1736                          struct mlx5e_cq *cq)
1737 {
1738         struct mlx5_core_dev *mdev = c->mdev;
1739         int err;
1740
1741         err = mlx5e_alloc_cq(c, param, cq);
1742         if (err)
1743                 return err;
1744
1745         err = mlx5e_create_cq(cq, param);
1746         if (err)
1747                 goto err_free_cq;
1748
1749         if (MLX5_CAP_GEN(mdev, cq_moderation))
1750                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1751         return 0;
1752
1753 err_free_cq:
1754         mlx5e_free_cq(cq);
1755
1756         return err;
1757 }
1758
1759 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1760 {
1761         mlx5e_destroy_cq(cq);
1762         mlx5e_free_cq(cq);
1763 }
1764
1765 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1766 {
1767         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1768 }
1769
1770 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1771                              struct mlx5e_params *params,
1772                              struct mlx5e_channel_param *cparam)
1773 {
1774         int err;
1775         int tc;
1776
1777         for (tc = 0; tc < c->num_tc; tc++) {
1778                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1779                                     &cparam->tx_cq, &c->sq[tc].cq);
1780                 if (err)
1781                         goto err_close_tx_cqs;
1782         }
1783
1784         return 0;
1785
1786 err_close_tx_cqs:
1787         for (tc--; tc >= 0; tc--)
1788                 mlx5e_close_cq(&c->sq[tc].cq);
1789
1790         return err;
1791 }
1792
1793 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1794 {
1795         int tc;
1796
1797         for (tc = 0; tc < c->num_tc; tc++)
1798                 mlx5e_close_cq(&c->sq[tc].cq);
1799 }
1800
1801 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1802                           struct mlx5e_params *params,
1803                           struct mlx5e_channel_param *cparam)
1804 {
1805         struct mlx5e_priv *priv = c->priv;
1806         int err, tc, max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1807
1808         for (tc = 0; tc < params->num_tc; tc++) {
1809                 int txq_ix = c->ix + tc * max_nch;
1810
1811                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1812                                        params, &cparam->sq, &c->sq[tc], tc);
1813                 if (err)
1814                         goto err_close_sqs;
1815         }
1816
1817         return 0;
1818
1819 err_close_sqs:
1820         for (tc--; tc >= 0; tc--)
1821                 mlx5e_close_txqsq(&c->sq[tc]);
1822
1823         return err;
1824 }
1825
1826 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1827 {
1828         int tc;
1829
1830         for (tc = 0; tc < c->num_tc; tc++)
1831                 mlx5e_close_txqsq(&c->sq[tc]);
1832 }
1833
1834 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1835                                 struct mlx5e_txqsq *sq, u32 rate)
1836 {
1837         struct mlx5e_priv *priv = netdev_priv(dev);
1838         struct mlx5_core_dev *mdev = priv->mdev;
1839         struct mlx5e_modify_sq_param msp = {0};
1840         struct mlx5_rate_limit rl = {0};
1841         u16 rl_index = 0;
1842         int err;
1843
1844         if (rate == sq->rate_limit)
1845                 /* nothing to do */
1846                 return 0;
1847
1848         if (sq->rate_limit) {
1849                 rl.rate = sq->rate_limit;
1850                 /* remove current rl index to free space to next ones */
1851                 mlx5_rl_remove_rate(mdev, &rl);
1852         }
1853
1854         sq->rate_limit = 0;
1855
1856         if (rate) {
1857                 rl.rate = rate;
1858                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1859                 if (err) {
1860                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1861                                    rate, err);
1862                         return err;
1863                 }
1864         }
1865
1866         msp.curr_state = MLX5_SQC_STATE_RDY;
1867         msp.next_state = MLX5_SQC_STATE_RDY;
1868         msp.rl_index   = rl_index;
1869         msp.rl_update  = true;
1870         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1871         if (err) {
1872                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1873                            rate, err);
1874                 /* remove the rate from the table */
1875                 if (rate)
1876                         mlx5_rl_remove_rate(mdev, &rl);
1877                 return err;
1878         }
1879
1880         sq->rate_limit = rate;
1881         return 0;
1882 }
1883
1884 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1885 {
1886         struct mlx5e_priv *priv = netdev_priv(dev);
1887         struct mlx5_core_dev *mdev = priv->mdev;
1888         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1889         int err = 0;
1890
1891         if (!mlx5_rl_is_supported(mdev)) {
1892                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1893                 return -EINVAL;
1894         }
1895
1896         /* rate is given in Mb/sec, HW config is in Kb/sec */
1897         rate = rate << 10;
1898
1899         /* Check whether rate in valid range, 0 is always valid */
1900         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1901                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1902                 return -ERANGE;
1903         }
1904
1905         mutex_lock(&priv->state_lock);
1906         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1907                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1908         if (!err)
1909                 priv->tx_rates[index] = rate;
1910         mutex_unlock(&priv->state_lock);
1911
1912         return err;
1913 }
1914
1915 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1916                               struct mlx5e_params *params,
1917                               struct mlx5e_channel_param *cparam,
1918                               struct mlx5e_channel **cp)
1919 {
1920         struct net_dim_cq_moder icocq_moder = {0, 0};
1921         struct net_device *netdev = priv->netdev;
1922         int cpu = mlx5e_get_cpu(priv, ix);
1923         struct mlx5e_channel *c;
1924         unsigned int irq;
1925         int err;
1926         int eqn;
1927
1928         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1929         if (err)
1930                 return err;
1931
1932         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1933         if (!c)
1934                 return -ENOMEM;
1935
1936         c->priv     = priv;
1937         c->mdev     = priv->mdev;
1938         c->tstamp   = &priv->tstamp;
1939         c->ix       = ix;
1940         c->cpu      = cpu;
1941         c->pdev     = &priv->mdev->pdev->dev;
1942         c->netdev   = priv->netdev;
1943         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1944         c->num_tc   = params->num_tc;
1945         c->xdp      = !!params->xdp_prog;
1946         c->stats    = &priv->channel_stats[ix].ch;
1947
1948         c->irq_desc = irq_to_desc(irq);
1949
1950         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1951
1952         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1953         if (err)
1954                 goto err_napi_del;
1955
1956         err = mlx5e_open_tx_cqs(c, params, cparam);
1957         if (err)
1958                 goto err_close_icosq_cq;
1959
1960         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1961         if (err)
1962                 goto err_close_tx_cqs;
1963
1964         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1965         if (err)
1966                 goto err_close_xdp_tx_cqs;
1967
1968         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1969         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1970                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1971         if (err)
1972                 goto err_close_rx_cq;
1973
1974         napi_enable(&c->napi);
1975
1976         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1977         if (err)
1978                 goto err_disable_napi;
1979
1980         err = mlx5e_open_sqs(c, params, cparam);
1981         if (err)
1982                 goto err_close_icosq;
1983
1984         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1985         if (err)
1986                 goto err_close_sqs;
1987
1988         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1989         if (err)
1990                 goto err_close_xdp_sq;
1991
1992         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1993         if (err)
1994                 goto err_close_rq;
1995
1996         *cp = c;
1997
1998         return 0;
1999
2000 err_close_rq:
2001         mlx5e_close_rq(&c->rq);
2002
2003 err_close_xdp_sq:
2004         if (c->xdp)
2005                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2006
2007 err_close_sqs:
2008         mlx5e_close_sqs(c);
2009
2010 err_close_icosq:
2011         mlx5e_close_icosq(&c->icosq);
2012
2013 err_disable_napi:
2014         napi_disable(&c->napi);
2015         if (c->xdp)
2016                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2017
2018 err_close_rx_cq:
2019         mlx5e_close_cq(&c->rq.cq);
2020
2021 err_close_xdp_tx_cqs:
2022         mlx5e_close_cq(&c->xdpsq.cq);
2023
2024 err_close_tx_cqs:
2025         mlx5e_close_tx_cqs(c);
2026
2027 err_close_icosq_cq:
2028         mlx5e_close_cq(&c->icosq.cq);
2029
2030 err_napi_del:
2031         netif_napi_del(&c->napi);
2032         kvfree(c);
2033
2034         return err;
2035 }
2036
2037 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2038 {
2039         int tc;
2040
2041         for (tc = 0; tc < c->num_tc; tc++)
2042                 mlx5e_activate_txqsq(&c->sq[tc]);
2043         mlx5e_activate_rq(&c->rq);
2044         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
2045 }
2046
2047 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2048 {
2049         int tc;
2050
2051         mlx5e_deactivate_rq(&c->rq);
2052         for (tc = 0; tc < c->num_tc; tc++)
2053                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2054 }
2055
2056 static void mlx5e_close_channel(struct mlx5e_channel *c)
2057 {
2058         mlx5e_close_xdpsq(&c->xdpsq);
2059         mlx5e_close_rq(&c->rq);
2060         if (c->xdp)
2061                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2062         mlx5e_close_sqs(c);
2063         mlx5e_close_icosq(&c->icosq);
2064         napi_disable(&c->napi);
2065         if (c->xdp)
2066                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2067         mlx5e_close_cq(&c->rq.cq);
2068         mlx5e_close_cq(&c->xdpsq.cq);
2069         mlx5e_close_tx_cqs(c);
2070         mlx5e_close_cq(&c->icosq.cq);
2071         netif_napi_del(&c->napi);
2072
2073         kvfree(c);
2074 }
2075
2076 #define DEFAULT_FRAG_SIZE (2048)
2077
2078 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2079                                       struct mlx5e_params *params,
2080                                       struct mlx5e_rq_frags_info *info)
2081 {
2082         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2083         int frag_size_max = DEFAULT_FRAG_SIZE;
2084         u32 buf_size = 0;
2085         int i;
2086
2087 #ifdef CONFIG_MLX5_EN_IPSEC
2088         if (MLX5_IPSEC_DEV(mdev))
2089                 byte_count += MLX5E_METADATA_ETHER_LEN;
2090 #endif
2091
2092         if (mlx5e_rx_is_linear_skb(mdev, params)) {
2093                 int frag_stride;
2094
2095                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2096                 frag_stride = roundup_pow_of_two(frag_stride);
2097
2098                 info->arr[0].frag_size = byte_count;
2099                 info->arr[0].frag_stride = frag_stride;
2100                 info->num_frags = 1;
2101                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2102                 goto out;
2103         }
2104
2105         if (byte_count > PAGE_SIZE +
2106             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2107                 frag_size_max = PAGE_SIZE;
2108
2109         i = 0;
2110         while (buf_size < byte_count) {
2111                 int frag_size = byte_count - buf_size;
2112
2113                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2114                         frag_size = min(frag_size, frag_size_max);
2115
2116                 info->arr[i].frag_size = frag_size;
2117                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2118
2119                 buf_size += frag_size;
2120                 i++;
2121         }
2122         info->num_frags = i;
2123         /* number of different wqes sharing a page */
2124         info->wqe_bulk = 1 + (info->num_frags % 2);
2125
2126 out:
2127         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2128         info->log_num_frags = order_base_2(info->num_frags);
2129 }
2130
2131 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2132 {
2133         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2134
2135         switch (wq_type) {
2136         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2137                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2138                 break;
2139         default: /* MLX5_WQ_TYPE_CYCLIC */
2140                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2141         }
2142
2143         return order_base_2(sz);
2144 }
2145
2146 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2147                                  struct mlx5e_params *params,
2148                                  struct mlx5e_rq_param *param)
2149 {
2150         struct mlx5_core_dev *mdev = priv->mdev;
2151         void *rqc = param->rqc;
2152         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2153         int ndsegs = 1;
2154
2155         switch (params->rq_wq_type) {
2156         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2157                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2158                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2159                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2160                 MLX5_SET(wq, wq, log_wqe_stride_size,
2161                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2162                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2163                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2164                 break;
2165         default: /* MLX5_WQ_TYPE_CYCLIC */
2166                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2167                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2168                 ndsegs = param->frags_info.num_frags;
2169         }
2170
2171         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2172         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2173         MLX5_SET(wq, wq, log_wq_stride,
2174                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2175         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2176         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2177         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2178         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2179
2180         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2181 }
2182
2183 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2184                                       struct mlx5e_rq_param *param)
2185 {
2186         struct mlx5_core_dev *mdev = priv->mdev;
2187         void *rqc = param->rqc;
2188         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2189
2190         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2191         MLX5_SET(wq, wq, log_wq_stride,
2192                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2193         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2194
2195         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2196 }
2197
2198 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2199                                         struct mlx5e_sq_param *param)
2200 {
2201         void *sqc = param->sqc;
2202         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2203
2204         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2205         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2206
2207         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2208 }
2209
2210 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2211                                  struct mlx5e_params *params,
2212                                  struct mlx5e_sq_param *param)
2213 {
2214         void *sqc = param->sqc;
2215         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2216
2217         mlx5e_build_sq_param_common(priv, param);
2218         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2219         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2220 }
2221
2222 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2223                                         struct mlx5e_cq_param *param)
2224 {
2225         void *cqc = param->cqc;
2226
2227         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2228 }
2229
2230 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2231                                     struct mlx5e_params *params,
2232                                     struct mlx5e_cq_param *param)
2233 {
2234         struct mlx5_core_dev *mdev = priv->mdev;
2235         void *cqc = param->cqc;
2236         u8 log_cq_size;
2237
2238         switch (params->rq_wq_type) {
2239         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2240                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2241                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2242                 break;
2243         default: /* MLX5_WQ_TYPE_CYCLIC */
2244                 log_cq_size = params->log_rq_mtu_frames;
2245         }
2246
2247         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2248         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2249                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2250                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2251         }
2252
2253         mlx5e_build_common_cq_param(priv, param);
2254         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2255 }
2256
2257 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2258                                     struct mlx5e_params *params,
2259                                     struct mlx5e_cq_param *param)
2260 {
2261         void *cqc = param->cqc;
2262
2263         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2264
2265         mlx5e_build_common_cq_param(priv, param);
2266         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2267 }
2268
2269 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2270                                      u8 log_wq_size,
2271                                      struct mlx5e_cq_param *param)
2272 {
2273         void *cqc = param->cqc;
2274
2275         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2276
2277         mlx5e_build_common_cq_param(priv, param);
2278
2279         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2280 }
2281
2282 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2283                                     u8 log_wq_size,
2284                                     struct mlx5e_sq_param *param)
2285 {
2286         void *sqc = param->sqc;
2287         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2288
2289         mlx5e_build_sq_param_common(priv, param);
2290
2291         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2292         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2293 }
2294
2295 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2296                                     struct mlx5e_params *params,
2297                                     struct mlx5e_sq_param *param)
2298 {
2299         void *sqc = param->sqc;
2300         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2301
2302         mlx5e_build_sq_param_common(priv, param);
2303         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2304 }
2305
2306 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2307                                       struct mlx5e_params *params,
2308                                       struct mlx5e_channel_param *cparam)
2309 {
2310         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2311
2312         mlx5e_build_rq_param(priv, params, &cparam->rq);
2313         mlx5e_build_sq_param(priv, params, &cparam->sq);
2314         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2315         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2316         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2317         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2318         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2319 }
2320
2321 int mlx5e_open_channels(struct mlx5e_priv *priv,
2322                         struct mlx5e_channels *chs)
2323 {
2324         struct mlx5e_channel_param *cparam;
2325         int err = -ENOMEM;
2326         int i;
2327
2328         chs->num = chs->params.num_channels;
2329
2330         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2331         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2332         if (!chs->c || !cparam)
2333                 goto err_free;
2334
2335         mlx5e_build_channel_param(priv, &chs->params, cparam);
2336         for (i = 0; i < chs->num; i++) {
2337                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2338                 if (err)
2339                         goto err_close_channels;
2340         }
2341
2342         kvfree(cparam);
2343         return 0;
2344
2345 err_close_channels:
2346         for (i--; i >= 0; i--)
2347                 mlx5e_close_channel(chs->c[i]);
2348
2349 err_free:
2350         kfree(chs->c);
2351         kvfree(cparam);
2352         chs->num = 0;
2353         return err;
2354 }
2355
2356 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2357 {
2358         int i;
2359
2360         for (i = 0; i < chs->num; i++)
2361                 mlx5e_activate_channel(chs->c[i]);
2362 }
2363
2364 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2365 {
2366         int err = 0;
2367         int i;
2368
2369         for (i = 0; i < chs->num; i++)
2370                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2371                                                   err ? 0 : 20000);
2372
2373         return err ? -ETIMEDOUT : 0;
2374 }
2375
2376 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2377 {
2378         int i;
2379
2380         for (i = 0; i < chs->num; i++)
2381                 mlx5e_deactivate_channel(chs->c[i]);
2382 }
2383
2384 void mlx5e_close_channels(struct mlx5e_channels *chs)
2385 {
2386         int i;
2387
2388         for (i = 0; i < chs->num; i++)
2389                 mlx5e_close_channel(chs->c[i]);
2390
2391         kfree(chs->c);
2392         chs->num = 0;
2393 }
2394
2395 static int
2396 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2397 {
2398         struct mlx5_core_dev *mdev = priv->mdev;
2399         void *rqtc;
2400         int inlen;
2401         int err;
2402         u32 *in;
2403         int i;
2404
2405         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2406         in = kvzalloc(inlen, GFP_KERNEL);
2407         if (!in)
2408                 return -ENOMEM;
2409
2410         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2411
2412         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2413         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2414
2415         for (i = 0; i < sz; i++)
2416                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2417
2418         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2419         if (!err)
2420                 rqt->enabled = true;
2421
2422         kvfree(in);
2423         return err;
2424 }
2425
2426 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2427 {
2428         rqt->enabled = false;
2429         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2430 }
2431
2432 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2433 {
2434         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2435         int err;
2436
2437         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2438         if (err)
2439                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2440         return err;
2441 }
2442
2443 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2444 {
2445         struct mlx5e_rqt *rqt;
2446         int err;
2447         int ix;
2448
2449         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2450                 rqt = &priv->direct_tir[ix].rqt;
2451                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2452                 if (err)
2453                         goto err_destroy_rqts;
2454         }
2455
2456         return 0;
2457
2458 err_destroy_rqts:
2459         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2460         for (ix--; ix >= 0; ix--)
2461                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2462
2463         return err;
2464 }
2465
2466 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2467 {
2468         int i;
2469
2470         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++)
2471                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2472 }
2473
2474 static int mlx5e_rx_hash_fn(int hfunc)
2475 {
2476         return (hfunc == ETH_RSS_HASH_TOP) ?
2477                MLX5_RX_HASH_FN_TOEPLITZ :
2478                MLX5_RX_HASH_FN_INVERTED_XOR8;
2479 }
2480
2481 int mlx5e_bits_invert(unsigned long a, int size)
2482 {
2483         int inv = 0;
2484         int i;
2485
2486         for (i = 0; i < size; i++)
2487                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2488
2489         return inv;
2490 }
2491
2492 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2493                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2494 {
2495         int i;
2496
2497         for (i = 0; i < sz; i++) {
2498                 u32 rqn;
2499
2500                 if (rrp.is_rss) {
2501                         int ix = i;
2502
2503                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2504                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2505
2506                         ix = priv->channels.params.indirection_rqt[ix];
2507                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2508                 } else {
2509                         rqn = rrp.rqn;
2510                 }
2511                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2512         }
2513 }
2514
2515 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2516                        struct mlx5e_redirect_rqt_param rrp)
2517 {
2518         struct mlx5_core_dev *mdev = priv->mdev;
2519         void *rqtc;
2520         int inlen;
2521         u32 *in;
2522         int err;
2523
2524         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2525         in = kvzalloc(inlen, GFP_KERNEL);
2526         if (!in)
2527                 return -ENOMEM;
2528
2529         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2530
2531         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2532         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2533         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2534         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2535
2536         kvfree(in);
2537         return err;
2538 }
2539
2540 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2541                                 struct mlx5e_redirect_rqt_param rrp)
2542 {
2543         if (!rrp.is_rss)
2544                 return rrp.rqn;
2545
2546         if (ix >= rrp.rss.channels->num)
2547                 return priv->drop_rq.rqn;
2548
2549         return rrp.rss.channels->c[ix]->rq.rqn;
2550 }
2551
2552 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2553                                 struct mlx5e_redirect_rqt_param rrp)
2554 {
2555         u32 rqtn;
2556         int ix;
2557
2558         if (priv->indir_rqt.enabled) {
2559                 /* RSS RQ table */
2560                 rqtn = priv->indir_rqt.rqtn;
2561                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2562         }
2563
2564         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2565                 struct mlx5e_redirect_rqt_param direct_rrp = {
2566                         .is_rss = false,
2567                         {
2568                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2569                         },
2570                 };
2571
2572                 /* Direct RQ Tables */
2573                 if (!priv->direct_tir[ix].rqt.enabled)
2574                         continue;
2575
2576                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2577                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2578         }
2579 }
2580
2581 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2582                                             struct mlx5e_channels *chs)
2583 {
2584         struct mlx5e_redirect_rqt_param rrp = {
2585                 .is_rss        = true,
2586                 {
2587                         .rss = {
2588                                 .channels  = chs,
2589                                 .hfunc     = chs->params.rss_hfunc,
2590                         }
2591                 },
2592         };
2593
2594         mlx5e_redirect_rqts(priv, rrp);
2595 }
2596
2597 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2598 {
2599         struct mlx5e_redirect_rqt_param drop_rrp = {
2600                 .is_rss = false,
2601                 {
2602                         .rqn = priv->drop_rq.rqn,
2603                 },
2604         };
2605
2606         mlx5e_redirect_rqts(priv, drop_rrp);
2607 }
2608
2609 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2610 {
2611         if (!params->lro_en)
2612                 return;
2613
2614 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2615
2616         MLX5_SET(tirc, tirc, lro_enable_mask,
2617                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2618                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2619         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2620                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2621         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2622 }
2623
2624 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2625                                     enum mlx5e_traffic_types tt,
2626                                     void *tirc, bool inner)
2627 {
2628         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2629                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2630
2631 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2632                                  MLX5_HASH_FIELD_SEL_DST_IP)
2633
2634 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2635                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2636                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2637                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2638
2639 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2640                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2641                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2642
2643         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2644         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2645                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2646                                              rx_hash_toeplitz_key);
2647                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2648                                                rx_hash_toeplitz_key);
2649
2650                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2651                 memcpy(rss_key, params->toeplitz_hash_key, len);
2652         }
2653
2654         switch (tt) {
2655         case MLX5E_TT_IPV4_TCP:
2656                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2657                          MLX5_L3_PROT_TYPE_IPV4);
2658                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2659                          MLX5_L4_PROT_TYPE_TCP);
2660                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2661                          MLX5_HASH_IP_L4PORTS);
2662                 break;
2663
2664         case MLX5E_TT_IPV6_TCP:
2665                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2666                          MLX5_L3_PROT_TYPE_IPV6);
2667                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2668                          MLX5_L4_PROT_TYPE_TCP);
2669                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2670                          MLX5_HASH_IP_L4PORTS);
2671                 break;
2672
2673         case MLX5E_TT_IPV4_UDP:
2674                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2675                          MLX5_L3_PROT_TYPE_IPV4);
2676                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2677                          MLX5_L4_PROT_TYPE_UDP);
2678                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2679                          MLX5_HASH_IP_L4PORTS);
2680                 break;
2681
2682         case MLX5E_TT_IPV6_UDP:
2683                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2684                          MLX5_L3_PROT_TYPE_IPV6);
2685                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2686                          MLX5_L4_PROT_TYPE_UDP);
2687                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2688                          MLX5_HASH_IP_L4PORTS);
2689                 break;
2690
2691         case MLX5E_TT_IPV4_IPSEC_AH:
2692                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2693                          MLX5_L3_PROT_TYPE_IPV4);
2694                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2695                          MLX5_HASH_IP_IPSEC_SPI);
2696                 break;
2697
2698         case MLX5E_TT_IPV6_IPSEC_AH:
2699                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2700                          MLX5_L3_PROT_TYPE_IPV6);
2701                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2702                          MLX5_HASH_IP_IPSEC_SPI);
2703                 break;
2704
2705         case MLX5E_TT_IPV4_IPSEC_ESP:
2706                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2707                          MLX5_L3_PROT_TYPE_IPV4);
2708                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2709                          MLX5_HASH_IP_IPSEC_SPI);
2710                 break;
2711
2712         case MLX5E_TT_IPV6_IPSEC_ESP:
2713                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2714                          MLX5_L3_PROT_TYPE_IPV6);
2715                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2716                          MLX5_HASH_IP_IPSEC_SPI);
2717                 break;
2718
2719         case MLX5E_TT_IPV4:
2720                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2721                          MLX5_L3_PROT_TYPE_IPV4);
2722                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2723                          MLX5_HASH_IP);
2724                 break;
2725
2726         case MLX5E_TT_IPV6:
2727                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2728                          MLX5_L3_PROT_TYPE_IPV6);
2729                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2730                          MLX5_HASH_IP);
2731                 break;
2732         default:
2733                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2734         }
2735 }
2736
2737 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2738 {
2739         struct mlx5_core_dev *mdev = priv->mdev;
2740
2741         void *in;
2742         void *tirc;
2743         int inlen;
2744         int err;
2745         int tt;
2746         int ix;
2747
2748         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2749         in = kvzalloc(inlen, GFP_KERNEL);
2750         if (!in)
2751                 return -ENOMEM;
2752
2753         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2754         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2755
2756         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2757
2758         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2759                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2760                                            inlen);
2761                 if (err)
2762                         goto free_in;
2763         }
2764
2765         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2766                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2767                                            in, inlen);
2768                 if (err)
2769                         goto free_in;
2770         }
2771
2772 free_in:
2773         kvfree(in);
2774
2775         return err;
2776 }
2777
2778 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2779                                             enum mlx5e_traffic_types tt,
2780                                             u32 *tirc)
2781 {
2782         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2783
2784         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2785
2786         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2787         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2788         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2789
2790         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2791 }
2792
2793 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2794                          struct mlx5e_params *params, u16 mtu)
2795 {
2796         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2797         int err;
2798
2799         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2800         if (err)
2801                 return err;
2802
2803         /* Update vport context MTU */
2804         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2805         return 0;
2806 }
2807
2808 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2809                             struct mlx5e_params *params, u16 *mtu)
2810 {
2811         u16 hw_mtu = 0;
2812         int err;
2813
2814         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2815         if (err || !hw_mtu) /* fallback to port oper mtu */
2816                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2817
2818         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2819 }
2820
2821 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2822 {
2823         struct mlx5e_params *params = &priv->channels.params;
2824         struct net_device *netdev = priv->netdev;
2825         struct mlx5_core_dev *mdev = priv->mdev;
2826         u16 mtu;
2827         int err;
2828
2829         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2830         if (err)
2831                 return err;
2832
2833         mlx5e_query_mtu(mdev, params, &mtu);
2834         if (mtu != params->sw_mtu)
2835                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2836                             __func__, mtu, params->sw_mtu);
2837
2838         params->sw_mtu = mtu;
2839         return 0;
2840 }
2841
2842 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2843 {
2844         struct mlx5e_priv *priv = netdev_priv(netdev);
2845         int nch = priv->channels.params.num_channels;
2846         int ntc = priv->channels.params.num_tc;
2847         int tc;
2848
2849         netdev_reset_tc(netdev);
2850
2851         if (ntc == 1)
2852                 return;
2853
2854         netdev_set_num_tc(netdev, ntc);
2855
2856         /* Map netdev TCs to offset 0
2857          * We have our own UP to TXQ mapping for QoS
2858          */
2859         for (tc = 0; tc < ntc; tc++)
2860                 netdev_set_tc_queue(netdev, tc, nch, 0);
2861 }
2862
2863 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2864 {
2865         int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2866         int i, tc;
2867
2868         for (i = 0; i < max_nch; i++)
2869                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2870                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2871 }
2872
2873 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2874 {
2875         struct mlx5e_channel *c;
2876         struct mlx5e_txqsq *sq;
2877         int i, tc;
2878
2879         for (i = 0; i < priv->channels.num; i++) {
2880                 c = priv->channels.c[i];
2881                 for (tc = 0; tc < c->num_tc; tc++) {
2882                         sq = &c->sq[tc];
2883                         priv->txq2sq[sq->txq_ix] = sq;
2884                 }
2885         }
2886 }
2887
2888 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2889 {
2890         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2891         struct net_device *netdev = priv->netdev;
2892
2893         mlx5e_netdev_set_tcs(netdev);
2894         netif_set_real_num_tx_queues(netdev, num_txqs);
2895         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2896
2897         mlx5e_build_tx2sq_maps(priv);
2898         mlx5e_activate_channels(&priv->channels);
2899         netif_tx_start_all_queues(priv->netdev);
2900
2901         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2902                 mlx5e_add_sqs_fwd_rules(priv);
2903
2904         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2905         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2906 }
2907
2908 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2909 {
2910         mlx5e_redirect_rqts_to_drop(priv);
2911
2912         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2913                 mlx5e_remove_sqs_fwd_rules(priv);
2914
2915         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2916          * polling for inactive tx queues.
2917          */
2918         netif_tx_stop_all_queues(priv->netdev);
2919         netif_tx_disable(priv->netdev);
2920         mlx5e_deactivate_channels(&priv->channels);
2921 }
2922
2923 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2924                                 struct mlx5e_channels *new_chs,
2925                                 mlx5e_fp_hw_modify hw_modify)
2926 {
2927         struct net_device *netdev = priv->netdev;
2928         int new_num_txqs;
2929         int carrier_ok;
2930         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2931
2932         carrier_ok = netif_carrier_ok(netdev);
2933         netif_carrier_off(netdev);
2934
2935         if (new_num_txqs < netdev->real_num_tx_queues)
2936                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2937
2938         mlx5e_deactivate_priv_channels(priv);
2939         mlx5e_close_channels(&priv->channels);
2940
2941         priv->channels = *new_chs;
2942
2943         /* New channels are ready to roll, modify HW settings if needed */
2944         if (hw_modify)
2945                 hw_modify(priv);
2946
2947         mlx5e_refresh_tirs(priv, false);
2948         mlx5e_activate_priv_channels(priv);
2949
2950         /* return carrier back if needed */
2951         if (carrier_ok)
2952                 netif_carrier_on(netdev);
2953 }
2954
2955 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2956 {
2957         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2958         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2959 }
2960
2961 int mlx5e_open_locked(struct net_device *netdev)
2962 {
2963         struct mlx5e_priv *priv = netdev_priv(netdev);
2964         int err;
2965
2966         set_bit(MLX5E_STATE_OPENED, &priv->state);
2967
2968         err = mlx5e_open_channels(priv, &priv->channels);
2969         if (err)
2970                 goto err_clear_state_opened_flag;
2971
2972         mlx5e_refresh_tirs(priv, false);
2973         mlx5e_activate_priv_channels(priv);
2974         if (priv->profile->update_carrier)
2975                 priv->profile->update_carrier(priv);
2976
2977         mlx5e_queue_update_stats(priv);
2978         return 0;
2979
2980 err_clear_state_opened_flag:
2981         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2982         return err;
2983 }
2984
2985 int mlx5e_open(struct net_device *netdev)
2986 {
2987         struct mlx5e_priv *priv = netdev_priv(netdev);
2988         int err;
2989
2990         mutex_lock(&priv->state_lock);
2991         err = mlx5e_open_locked(netdev);
2992         if (!err)
2993                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2994         mutex_unlock(&priv->state_lock);
2995
2996         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
2997                 udp_tunnel_get_rx_info(netdev);
2998
2999         return err;
3000 }
3001
3002 int mlx5e_close_locked(struct net_device *netdev)
3003 {
3004         struct mlx5e_priv *priv = netdev_priv(netdev);
3005
3006         /* May already be CLOSED in case a previous configuration operation
3007          * (e.g RX/TX queue size change) that involves close&open failed.
3008          */
3009         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3010                 return 0;
3011
3012         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3013
3014         netif_carrier_off(priv->netdev);
3015         mlx5e_deactivate_priv_channels(priv);
3016         mlx5e_close_channels(&priv->channels);
3017
3018         return 0;
3019 }
3020
3021 int mlx5e_close(struct net_device *netdev)
3022 {
3023         struct mlx5e_priv *priv = netdev_priv(netdev);
3024         int err;
3025
3026         if (!netif_device_present(netdev))
3027                 return -ENODEV;
3028
3029         mutex_lock(&priv->state_lock);
3030         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3031         err = mlx5e_close_locked(netdev);
3032         mutex_unlock(&priv->state_lock);
3033
3034         return err;
3035 }
3036
3037 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3038                                struct mlx5e_rq *rq,
3039                                struct mlx5e_rq_param *param)
3040 {
3041         void *rqc = param->rqc;
3042         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3043         int err;
3044
3045         param->wq.db_numa_node = param->wq.buf_numa_node;
3046
3047         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3048                                  &rq->wq_ctrl);
3049         if (err)
3050                 return err;
3051
3052         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3053         xdp_rxq_info_unused(&rq->xdp_rxq);
3054
3055         rq->mdev = mdev;
3056
3057         return 0;
3058 }
3059
3060 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3061                                struct mlx5e_cq *cq,
3062                                struct mlx5e_cq_param *param)
3063 {
3064         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3065         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
3066
3067         return mlx5e_alloc_cq_common(mdev, param, cq);
3068 }
3069
3070 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3071                        struct mlx5e_rq *drop_rq)
3072 {
3073         struct mlx5_core_dev *mdev = priv->mdev;
3074         struct mlx5e_cq_param cq_param = {};
3075         struct mlx5e_rq_param rq_param = {};
3076         struct mlx5e_cq *cq = &drop_rq->cq;
3077         int err;
3078
3079         mlx5e_build_drop_rq_param(priv, &