drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include "en.h"
  39 #include "en_tc.h"
  40 #include "eswitch.h"
  41 #include "vxlan.h"
  42
  43 struct mlx5e_rq_param {
  44         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  45         struct mlx5_wq_param    wq;
  46         bool                    am_enabled;
  47 };
  48
  49 struct mlx5e_sq_param {
  50         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  51         struct mlx5_wq_param       wq;
  52         u16                        max_inline;
  53         u8                         min_inline_mode;
  54         enum mlx5e_sq_type         type;
  55 };
  56
  57 struct mlx5e_cq_param {
  58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  59         struct mlx5_wq_param       wq;
  60         u16                        eq_ix;
  61         u8                         cq_period_mode;
  62 };
  63
  64 struct mlx5e_channel_param {
  65         struct mlx5e_rq_param      rq;
  66         struct mlx5e_sq_param      sq;
  67         struct mlx5e_sq_param      xdp_sq;
  68         struct mlx5e_sq_param      icosq;
  69         struct mlx5e_cq_param      rx_cq;
  70         struct mlx5e_cq_param      tx_cq;
  71         struct mlx5e_cq_param      icosq_cq;
  72 };
  73
  74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  75 {
  76         return MLX5_CAP_GEN(mdev, striding_rq) &&
  77                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  78                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  79 }
  80
  81 static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
  82 {
  83         priv->params.rq_wq_type = rq_type;
  84         switch (priv->params.rq_wq_type) {
  85         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
  86                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
  87                 priv->params.mpwqe_log_stride_sz = priv->params.rx_cqe_compress ?
  88                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
  89                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
  90                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
  91                         priv->params.mpwqe_log_stride_sz;
  92                 break;
  93         default: /* MLX5_WQ_TYPE_LINKED_LIST */
  94                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  95         }
  96         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
  97                                                BIT(priv->params.log_rq_size));
  98
  99         mlx5_core_info(priv->mdev,
 100                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 101                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 102                        BIT(priv->params.log_rq_size),
 103                        BIT(priv->params.mpwqe_log_stride_sz),
 104                        priv->params.rx_cqe_compress_admin);
 105 }
 106
 107 static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
 108 {
 109         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
 110                     !priv->xdp_prog ?
 111                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 112                     MLX5_WQ_TYPE_LINKED_LIST;
 113         mlx5e_set_rq_type_params(priv, rq_type);
 114 }
 115
 116 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 117 {
 118         struct mlx5_core_dev *mdev = priv->mdev;
 119         u8 port_state;
 120
 121         port_state = mlx5_query_vport_state(mdev,
 122                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 123
 124         if (port_state == VPORT_STATE_UP) {
 125                 netdev_info(priv->netdev, "Link up\n");
 126                 netif_carrier_on(priv->netdev);
 127         } else {
 128                 netdev_info(priv->netdev, "Link down\n");
 129                 netif_carrier_off(priv->netdev);
 130         }
 131 }
 132
 133 static void mlx5e_update_carrier_work(struct work_struct *work)
 134 {
 135         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 136                                                update_carrier_work);
 137
 138         mutex_lock(&priv->state_lock);
 139         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 140                 mlx5e_update_carrier(priv);
 141         mutex_unlock(&priv->state_lock);
 142 }
 143
 144 static void mlx5e_tx_timeout_work(struct work_struct *work)
 145 {
 146         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 147                                                tx_timeout_work);
 148         int err;
 149
 150         rtnl_lock();
 151         mutex_lock(&priv->state_lock);
 152         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 153                 goto unlock;
 154         mlx5e_close_locked(priv->netdev);
 155         err = mlx5e_open_locked(priv->netdev);
 156         if (err)
 157                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 158                            err);
 159 unlock:
 160         mutex_unlock(&priv->state_lock);
 161         rtnl_unlock();
 162 }
 163
 164 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 165 {
 166         struct mlx5e_sw_stats *s = &priv->stats.sw;
 167         struct mlx5e_rq_stats *rq_stats;
 168         struct mlx5e_sq_stats *sq_stats;
 169         u64 tx_offload_none = 0;
 170         int i, j;
 171
 172         memset(s, 0, sizeof(*s));
 173         for (i = 0; i < priv->params.num_channels; i++) {
 174                 rq_stats = &priv->channel[i]->rq.stats;
 175
 176                 s->rx_packets   += rq_stats->packets;
 177                 s->rx_bytes     += rq_stats->bytes;
 178                 s->rx_lro_packets += rq_stats->lro_packets;
 179                 s->rx_lro_bytes += rq_stats->lro_bytes;
 180                 s->rx_csum_none += rq_stats->csum_none;
 181                 s->rx_csum_complete += rq_stats->csum_complete;
 182                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 183                 s->rx_xdp_drop += rq_stats->xdp_drop;
 184                 s->rx_xdp_tx += rq_stats->xdp_tx;
 185                 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
 186                 s->rx_wqe_err   += rq_stats->wqe_err;
 187                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 188                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 189                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 190                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 191                 s->rx_cache_reuse += rq_stats->cache_reuse;
 192                 s->rx_cache_full  += rq_stats->cache_full;
 193                 s->rx_cache_empty += rq_stats->cache_empty;
 194                 s->rx_cache_busy  += rq_stats->cache_busy;
 195
 196                 for (j = 0; j < priv->params.num_tc; j++) {
 197                         sq_stats = &priv->channel[i]->sq[j].stats;
 198
 199                         s->tx_packets           += sq_stats->packets;
 200                         s->tx_bytes             += sq_stats->bytes;
 201                         s->tx_tso_packets       += sq_stats->tso_packets;
 202                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 203                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 204                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 205                         s->tx_queue_stopped     += sq_stats->stopped;
 206                         s->tx_queue_wake        += sq_stats->wake;
 207                         s->tx_queue_dropped     += sq_stats->dropped;
 208                         s->tx_xmit_more         += sq_stats->xmit_more;
 209                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 210                         tx_offload_none         += sq_stats->csum_none;
 211                 }
 212         }
 213
 214         /* Update calculated offload counters */
 215         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 216         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 217
 218         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 219                                 priv->stats.pport.phy_counters,
 220                                 counter_set.phys_layer_cntrs.link_down_events);
 221 }
 222
 223 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 224 {
 225         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 226         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 227         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 228         struct mlx5_core_dev *mdev = priv->mdev;
 229
 230         MLX5_SET(query_vport_counter_in, in, opcode,
 231                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 232         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 233         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 234
 235         memset(out, 0, outlen);
 236         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 237 }
 238
 239 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 240 {
 241         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 242         struct mlx5_core_dev *mdev = priv->mdev;
 243         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 244         int prio;
 245         void *out;
 246         u32 *in;
 247
 248         in = mlx5_vzalloc(sz);
 249         if (!in)
 250                 goto free_out;
 251
 252         MLX5_SET(ppcnt_reg, in, local_port, 1);
 253
 254         out = pstats->IEEE_802_3_counters;
 255         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 256         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 257
 258         out = pstats->RFC_2863_counters;
 259         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 260         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 261
 262         out = pstats->RFC_2819_counters;
 263         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 264         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 265
 266         out = pstats->phy_counters;
 267         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 268         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 269
 270         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 271         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 272                 out = pstats->per_prio_counters[prio];
 273                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 274                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 275                                      MLX5_REG_PPCNT, 0, 0);
 276         }
 277
 278 free_out:
 279         kvfree(in);
 280 }
 281
 282 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 283 {
 284         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 285
 286         if (!priv->q_counter)
 287                 return;
 288
 289         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 290                                       &qcnt->rx_out_of_buffer);
 291 }
 292
 293 void mlx5e_update_stats(struct mlx5e_priv *priv)
 294 {
 295         mlx5e_update_q_counter(priv);
 296         mlx5e_update_vport_counters(priv);
 297         mlx5e_update_pport_counters(priv);
 298         mlx5e_update_sw_counters(priv);
 299 }
 300
 301 void mlx5e_update_stats_work(struct work_struct *work)
 302 {
 303         struct delayed_work *dwork = to_delayed_work(work);
 304         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 305                                                update_stats_work);
 306         mutex_lock(&priv->state_lock);
 307         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 308                 priv->profile->update_stats(priv);
 309                 queue_delayed_work(priv->wq, dwork,
 310                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 311         }
 312         mutex_unlock(&priv->state_lock);
 313 }
 314
 315 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 316                               enum mlx5_dev_event event, unsigned long param)
 317 {
 318         struct mlx5e_priv *priv = vpriv;
 319
 320         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 321                 return;
 322
 323         switch (event) {
 324         case MLX5_DEV_EVENT_PORT_UP:
 325         case MLX5_DEV_EVENT_PORT_DOWN:
 326                 queue_work(priv->wq, &priv->update_carrier_work);
 327                 break;
 328
 329         default:
 330                 break;
 331         }
 332 }
 333
 334 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 335 {
 336         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 337 }
 338
 339 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 340 {
 341         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 342         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 343 }
 344
 345 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 346 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 347
 348 static inline int mlx5e_get_wqe_mtt_sz(void)
 349 {
 350         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 351          * To avoid copying garbage after the mtt array, we allocate
 352          * a little more.
 353          */
 354         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 355                      MLX5_UMR_MTT_ALIGNMENT);
 356 }
 357
 358 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
 359                                        struct mlx5e_umr_wqe *wqe, u16 ix)
 360 {
 361         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 362         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 363         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 364         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 365         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 366         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 367
 368         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 369                                       ds_cnt);
 370         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 371         cseg->imm       = rq->mkey_be;
 372
 373         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 374         ucseg->klm_octowords =
 375                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 376         ucseg->bsf_octowords =
 377                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 378         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 379
 380         dseg->lkey = sq->mkey_be;
 381         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 382 }
 383
 384 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 385                                      struct mlx5e_channel *c)
 386 {
 387         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 388         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 389         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
 390         int i;
 391
 392         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 393                                       GFP_KERNEL, cpu_to_node(c->cpu));
 394         if (!rq->mpwqe.info)
 395                 goto err_out;
 396
 397         /* We allocate more than mtt_sz as we will align the pointer */
 398         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
 399                                         cpu_to_node(c->cpu));
 400         if (unlikely(!rq->mpwqe.mtt_no_align))
 401                 goto err_free_wqe_info;
 402
 403         for (i = 0; i < wq_sz; i++) {
 404                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 405
 406                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
 407                                         MLX5_UMR_ALIGN);
 408                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
 409                                                   PCI_DMA_TODEVICE);
 410                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
 411                         goto err_unmap_mtts;
 412
 413                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 414         }
 415
 416         return 0;
 417
 418 err_unmap_mtts:
 419         while (--i >= 0) {
 420                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 421
 422                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
 423                                  PCI_DMA_TODEVICE);
 424         }
 425         kfree(rq->mpwqe.mtt_no_align);
 426 err_free_wqe_info:
 427         kfree(rq->mpwqe.info);
 428
 429 err_out:
 430         return -ENOMEM;
 431 }
 432
 433 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
 434 {
 435         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 436         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 437         int i;
 438
 439         for (i = 0; i < wq_sz; i++) {
 440                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 441
 442                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
 443                                  PCI_DMA_TODEVICE);
 444         }
 445         kfree(rq->mpwqe.mtt_no_align);
 446         kfree(rq->mpwqe.info);
 447 }
 448
 449 static bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv)
 450 {
 451         struct mlx5_eswitch_rep *rep = (struct mlx5_eswitch_rep *)priv->ppriv;
 452
 453         if (rep && rep->vport != FDB_UPLINK_VPORT)
 454                 return true;
 455
 456         return false;
 457 }
 458
 459 static int mlx5e_create_rq(struct mlx5e_channel *c,
 460                            struct mlx5e_rq_param *param,
 461                            struct mlx5e_rq *rq)
 462 {
 463         struct mlx5e_priv *priv = c->priv;
 464         struct mlx5_core_dev *mdev = priv->mdev;
 465         void *rqc = param->rqc;
 466         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 467         u32 byte_count;
 468         u32 frag_sz;
 469         int npages;
 470         int wq_sz;
 471         int err;
 472         int i;
 473
 474         param->wq.db_numa_node = cpu_to_node(c->cpu);
 475
 476         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 477                                 &rq->wq_ctrl);
 478         if (err)
 479                 return err;
 480
 481         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 482
 483         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 484
 485         rq->wq_type = priv->params.rq_wq_type;
 486         rq->pdev    = c->pdev;
 487         rq->netdev  = c->netdev;
 488         rq->tstamp  = &priv->tstamp;
 489         rq->channel = c;
 490         rq->ix      = c->ix;
 491         rq->priv    = c->priv;
 492         rq->xdp_prog = priv->xdp_prog;
 493
 494         rq->buff.map_dir = DMA_FROM_DEVICE;
 495         if (rq->xdp_prog)
 496                 rq->buff.map_dir = DMA_BIDIRECTIONAL;
 497
 498         switch (priv->params.rq_wq_type) {
 499         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 500                 if (mlx5e_is_vf_vport_rep(priv)) {
 501                         err = -EINVAL;
 502                         goto err_rq_wq_destroy;
 503                 }
 504
 505                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 506                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 507                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 508
 509                 rq->mpwqe.mtt_offset = c->ix *
 510                         MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
 511
 512                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 513                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 514
 515                 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 516                 byte_count = rq->buff.wqe_sz;
 517                 rq->mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 518                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 519                 if (err)
 520                         goto err_rq_wq_destroy;
 521                 break;
 522         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 523                 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
 524                                             GFP_KERNEL, cpu_to_node(c->cpu));
 525                 if (!rq->dma_info) {
 526                         err = -ENOMEM;
 527                         goto err_rq_wq_destroy;
 528                 }
 529
 530                 if (mlx5e_is_vf_vport_rep(priv))
 531                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
 532                 else
 533                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 534
 535                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 536                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 537
 538                 rq->buff.wqe_sz = (priv->params.lro_en) ?
 539                                 priv->params.lro_wqe_sz :
 540                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 541                 byte_count = rq->buff.wqe_sz;
 542
 543                 /* calc the required page order */
 544                 frag_sz = MLX5_RX_HEADROOM +
 545                           byte_count /* packet data */ +
 546                           SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 547                 frag_sz = SKB_DATA_ALIGN(frag_sz);
 548
 549                 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
 550                 rq->buff.page_order = order_base_2(npages);
 551
 552                 byte_count |= MLX5_HW_START_PADDING;
 553                 rq->mkey_be = c->mkey_be;
 554         }
 555
 556         for (i = 0; i < wq_sz; i++) {
 557                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 558
 559                 wqe->data.byte_count = cpu_to_be32(byte_count);
 560                 wqe->data.lkey = rq->mkey_be;
 561         }
 562
 563         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 564         rq->am.mode = priv->params.rx_cq_period_mode;
 565
 566         rq->page_cache.head = 0;
 567         rq->page_cache.tail = 0;
 568
 569         if (rq->xdp_prog)
 570                 bpf_prog_add(rq->xdp_prog, 1);
 571
 572         return 0;
 573
 574 err_rq_wq_destroy:
 575         mlx5_wq_destroy(&rq->wq_ctrl);
 576
 577         return err;
 578 }
 579
 580 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 581 {
 582         int i;
 583
 584         if (rq->xdp_prog)
 585                 bpf_prog_put(rq->xdp_prog);
 586
 587         switch (rq->wq_type) {
 588         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 589                 mlx5e_rq_free_mpwqe_info(rq);
 590                 break;
 591         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 592                 kfree(rq->dma_info);
 593         }
 594
 595         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 596              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 597                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 598
 599                 mlx5e_page_release(rq, dma_info, false);
 600         }
 601         mlx5_wq_destroy(&rq->wq_ctrl);
 602 }
 603
 604 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 605 {
 606         struct mlx5e_priv *priv = rq->priv;
 607         struct mlx5_core_dev *mdev = priv->mdev;
 608
 609         void *in;
 610         void *rqc;
 611         void *wq;
 612         int inlen;
 613         int err;
 614
 615         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 616                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 617         in = mlx5_vzalloc(inlen);
 618         if (!in)
 619                 return -ENOMEM;
 620
 621         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 622         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 623
 624         memcpy(rqc, param->rqc, sizeof(param->rqc));
 625
 626         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 627         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 628         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 629         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 630                                                 MLX5_ADAPTER_PAGE_SHIFT);
 631         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 632
 633         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 634                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 635
 636         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 637
 638         kvfree(in);
 639
 640         return err;
 641 }
 642
 643 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 644                                  int next_state)
 645 {
 646         struct mlx5e_channel *c = rq->channel;
 647         struct mlx5e_priv *priv = c->priv;
 648         struct mlx5_core_dev *mdev = priv->mdev;
 649
 650         void *in;
 651         void *rqc;
 652         int inlen;
 653         int err;
 654
 655         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 656         in = mlx5_vzalloc(inlen);
 657         if (!in)
 658                 return -ENOMEM;
 659
 660         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 661
 662         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 663         MLX5_SET(rqc, rqc, state, next_state);
 664
 665         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 666
 667         kvfree(in);
 668
 669         return err;
 670 }
 671
 672 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 673 {
 674         struct mlx5e_channel *c = rq->channel;
 675         struct mlx5e_priv *priv = c->priv;
 676         struct mlx5_core_dev *mdev = priv->mdev;
 677
 678         void *in;
 679         void *rqc;
 680         int inlen;
 681         int err;
 682
 683         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 684         in = mlx5_vzalloc(inlen);
 685         if (!in)
 686                 return -ENOMEM;
 687
 688         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 689
 690         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 691         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 692                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 693         MLX5_SET(rqc, rqc, vsd, vsd);
 694         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 695
 696         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 697
 698         kvfree(in);
 699
 700         return err;
 701 }
 702
 703 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 704 {
 705         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 706 }
 707
 708 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 709 {
 710         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 711         struct mlx5e_channel *c = rq->channel;
 712         struct mlx5e_priv *priv = c->priv;
 713         struct mlx5_wq_ll *wq = &rq->wq;
 714
 715         while (time_before(jiffies, exp_time)) {
 716                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 717                         return 0;
 718
 719                 msleep(20);
 720         }
 721
 722         return -ETIMEDOUT;
 723 }
 724
 725 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 726 {
 727         struct mlx5_wq_ll *wq = &rq->wq;
 728         struct mlx5e_rx_wqe *wqe;
 729         __be16 wqe_ix_be;
 730         u16 wqe_ix;
 731
 732         /* UMR WQE (if in progress) is always at wq->head */
 733         if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 734                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 735
 736         while (!mlx5_wq_ll_is_empty(wq)) {
 737                 wqe_ix_be = *wq->tail_next;
 738                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 739                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 740                 rq->dealloc_wqe(rq, wqe_ix);
 741                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 742                                &wqe->next.next_wqe_index);
 743         }
 744 }
 745
 746 static int mlx5e_open_rq(struct mlx5e_channel *c,
 747                          struct mlx5e_rq_param *param,
 748                          struct mlx5e_rq *rq)
 749 {
 750         struct mlx5e_sq *sq = &c->icosq;
 751         u16 pi = sq->pc & sq->wq.sz_m1;
 752         int err;
 753
 754         err = mlx5e_create_rq(c, param, rq);
 755         if (err)
 756                 return err;
 757
 758         err = mlx5e_enable_rq(rq, param);
 759         if (err)
 760                 goto err_destroy_rq;
 761
 762         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 763         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 764         if (err)
 765                 goto err_disable_rq;
 766
 767         if (param->am_enabled)
 768                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 769
 770         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 771         sq->db.ico_wqe[pi].num_wqebbs = 1;
 772         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 773
 774         return 0;
 775
 776 err_disable_rq:
 777         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 778         mlx5e_disable_rq(rq);
 779 err_destroy_rq:
 780         mlx5e_destroy_rq(rq);
 781
 782         return err;
 783 }
 784
 785 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 786 {
 787         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 788         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 789         cancel_work_sync(&rq->am.work);
 790
 791         mlx5e_disable_rq(rq);
 792         mlx5e_free_rx_descs(rq);
 793         mlx5e_destroy_rq(rq);
 794 }
 795
 796 static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
 797 {
 798         kfree(sq->db.xdp.di);
 799         kfree(sq->db.xdp.wqe_info);
 800 }
 801
 802 static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
 803 {
 804         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 805
 806         sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
 807                                      GFP_KERNEL, numa);
 808         sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
 809                                            GFP_KERNEL, numa);
 810         if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
 811                 mlx5e_free_sq_xdp_db(sq);
 812                 return -ENOMEM;
 813         }
 814
 815         return 0;
 816 }
 817
 818 static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
 819 {
 820         kfree(sq->db.ico_wqe);
 821 }
 822
 823 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
 824 {
 825         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 826
 827         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 828                                       GFP_KERNEL, numa);
 829         if (!sq->db.ico_wqe)
 830                 return -ENOMEM;
 831
 832         return 0;
 833 }
 834
 835 static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
 836 {
 837         kfree(sq->db.txq.wqe_info);
 838         kfree(sq->db.txq.dma_fifo);
 839         kfree(sq->db.txq.skb);
 840 }
 841
 842 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
 843 {
 844         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 845         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 846
 847         sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
 848                                       GFP_KERNEL, numa);
 849         sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
 850                                            GFP_KERNEL, numa);
 851         sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
 852                                            GFP_KERNEL, numa);
 853         if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
 854                 mlx5e_free_sq_txq_db(sq);
 855                 return -ENOMEM;
 856         }
 857
 858         sq->dma_fifo_mask = df_sz - 1;
 859
 860         return 0;
 861 }
 862
 863 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 864 {
 865         switch (sq->type) {
 866         case MLX5E_SQ_TXQ:
 867                 mlx5e_free_sq_txq_db(sq);
 868                 break;
 869         case MLX5E_SQ_ICO:
 870                 mlx5e_free_sq_ico_db(sq);
 871                 break;
 872         case MLX5E_SQ_XDP:
 873                 mlx5e_free_sq_xdp_db(sq);
 874                 break;
 875         }
 876 }
 877
 878 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 879 {
 880         switch (sq->type) {
 881         case MLX5E_SQ_TXQ:
 882                 return mlx5e_alloc_sq_txq_db(sq, numa);
 883         case MLX5E_SQ_ICO:
 884                 return mlx5e_alloc_sq_ico_db(sq, numa);
 885         case MLX5E_SQ_XDP:
 886                 return mlx5e_alloc_sq_xdp_db(sq, numa);
 887         }
 888
 889         return 0;
 890 }
 891
 892 static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
 893 {
 894         switch (sq_type) {
 895         case MLX5E_SQ_ICO:
 896                 return MLX5E_ICOSQ_MAX_WQEBBS;
 897         case MLX5E_SQ_XDP:
 898                 return MLX5E_XDP_TX_WQEBBS;
 899         }
 900         return MLX5_SEND_WQE_MAX_WQEBBS;
 901 }
 902
 903 static int mlx5e_create_sq(struct mlx5e_channel *c,
 904                            int tc,
 905                            struct mlx5e_sq_param *param,
 906                            struct mlx5e_sq *sq)
 907 {
 908         struct mlx5e_priv *priv = c->priv;
 909         struct mlx5_core_dev *mdev = priv->mdev;
 910
 911         void *sqc = param->sqc;
 912         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 913         int err;
 914
 915         sq->type      = param->type;
 916         sq->pdev      = c->pdev;
 917         sq->tstamp    = &priv->tstamp;
 918         sq->mkey_be   = c->mkey_be;
 919         sq->channel   = c;
 920         sq->tc        = tc;
 921
 922         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 923         if (err)
 924                 return err;
 925
 926         param->wq.db_numa_node = cpu_to_node(c->cpu);
 927
 928         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 929                                  &sq->wq_ctrl);
 930         if (err)
 931                 goto err_unmap_free_uar;
 932
 933         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 934         if (sq->uar.bf_map) {
 935                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 936                 sq->uar_map = sq->uar.bf_map;
 937         } else {
 938                 sq->uar_map = sq->uar.map;
 939         }
 940         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 941         sq->max_inline  = param->max_inline;
 942         sq->min_inline_mode =
 943                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
 944                 param->min_inline_mode : 0;
 945
 946         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 947         if (err)
 948                 goto err_sq_wq_destroy;
 949
 950         if (sq->type == MLX5E_SQ_TXQ) {
 951                 int txq_ix;
 952
 953                 txq_ix = c->ix + tc * priv->params.num_channels;
 954                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 955                 priv->txq_to_sq_map[txq_ix] = sq;
 956         }
 957
 958         sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
 959         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 960
 961         return 0;
 962
 963 err_sq_wq_destroy:
 964         mlx5_wq_destroy(&sq->wq_ctrl);
 965
 966 err_unmap_free_uar:
 967         mlx5_unmap_free_uar(mdev, &sq->uar);
 968
 969         return err;
 970 }
 971
 972 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 973 {
 974         struct mlx5e_channel *c = sq->channel;
 975         struct mlx5e_priv *priv = c->priv;
 976
 977         mlx5e_free_sq_db(sq);
 978         mlx5_wq_destroy(&sq->wq_ctrl);
 979         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 980 }
 981
 982 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 983 {
 984         struct mlx5e_channel *c = sq->channel;
 985         struct mlx5e_priv *priv = c->priv;
 986         struct mlx5_core_dev *mdev = priv->mdev;
 987
 988         void *in;
 989         void *sqc;
 990         void *wq;
 991         int inlen;
 992         int err;
 993
 994         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 995                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 996         in = mlx5_vzalloc(inlen);
 997         if (!in)
 998                 return -ENOMEM;
 999
1000         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1001         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1002
1003         memcpy(sqc, param->sqc, sizeof(param->sqc));
1004
1005         MLX5_SET(sqc,  sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1006                                        0 : priv->tisn[sq->tc]);
1007         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
1008         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
1009         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
1010         MLX5_SET(sqc,  sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
1011
1012         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1013         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
1014         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
1015                                           MLX5_ADAPTER_PAGE_SHIFT);
1016         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
1017
1018         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1019                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1020
1021         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1022
1023         kvfree(in);
1024
1025         return err;
1026 }
1027
1028 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1029                            int next_state, bool update_rl, int rl_index)
1030 {
1031         struct mlx5e_channel *c = sq->channel;
1032         struct mlx5e_priv *priv = c->priv;
1033         struct mlx5_core_dev *mdev = priv->mdev;
1034
1035         void *in;
1036         void *sqc;
1037         int inlen;
1038         int err;
1039
1040         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1041         in = mlx5_vzalloc(inlen);
1042         if (!in)
1043                 return -ENOMEM;
1044
1045         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1046
1047         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1048         MLX5_SET(sqc, sqc, state, next_state);
1049         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1050                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1051                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
1052         }
1053
1054         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
1055
1056         kvfree(in);
1057
1058         return err;
1059 }
1060
1061 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1062 {
1063         struct mlx5e_channel *c = sq->channel;
1064         struct mlx5e_priv *priv = c->priv;
1065         struct mlx5_core_dev *mdev = priv->mdev;
1066
1067         mlx5_core_destroy_sq(mdev, sq->sqn);
1068         if (sq->rate_limit)
1069                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1070 }
1071
1072 static int mlx5e_open_sq(struct mlx5e_channel *c,
1073                          int tc,
1074                          struct mlx5e_sq_param *param,
1075                          struct mlx5e_sq *sq)
1076 {
1077         int err;
1078
1079         err = mlx5e_create_sq(c, tc, param, sq);
1080         if (err)
1081                 return err;
1082
1083         err = mlx5e_enable_sq(sq, param);
1084         if (err)
1085                 goto err_destroy_sq;
1086
1087         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1088         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1089                               false, 0);
1090         if (err)
1091                 goto err_disable_sq;
1092
1093         if (sq->txq) {
1094                 netdev_tx_reset_queue(sq->txq);
1095                 netif_tx_start_queue(sq->txq);
1096         }
1097
1098         return 0;
1099
1100 err_disable_sq:
1101         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1102         mlx5e_disable_sq(sq);
1103 err_destroy_sq:
1104         mlx5e_destroy_sq(sq);
1105
1106         return err;
1107 }
1108
1109 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1110 {
1111         __netif_tx_lock_bh(txq);
1112         netif_tx_stop_queue(txq);
1113         __netif_tx_unlock_bh(txq);
1114 }
1115
1116 static void mlx5e_close_sq(struct mlx5e_sq *sq)
1117 {
1118         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1119         /* prevent netif_tx_wake_queue */
1120         napi_synchronize(&sq->channel->napi);
1121
1122         if (sq->txq) {
1123                 netif_tx_disable_queue(sq->txq);
1124
1125                 /* last doorbell out, godspeed .. */
1126                 if (mlx5e_sq_has_room_for(sq, 1)) {
1127                         sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1128                         mlx5e_send_nop(sq, true);
1129                 }
1130         }
1131
1132         mlx5e_disable_sq(sq);
1133         mlx5e_free_sq_descs(sq);
1134         mlx5e_destroy_sq(sq);
1135 }
1136
1137 static int mlx5e_create_cq(struct mlx5e_channel *c,
1138                            struct mlx5e_cq_param *param,
1139                            struct mlx5e_cq *cq)
1140 {
1141         struct mlx5e_priv *priv = c->priv;
1142         struct mlx5_core_dev *mdev = priv->mdev;
1143         struct mlx5_core_cq *mcq = &cq->mcq;
1144         int eqn_not_used;
1145         unsigned int irqn;
1146         int err;
1147         u32 i;
1148
1149         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1150         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1151         param->eq_ix   = c->ix;
1152
1153         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1154                                &cq->wq_ctrl);
1155         if (err)
1156                 return err;
1157
1158         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1159
1160         cq->napi        = &c->napi;
1161
1162         mcq->cqe_sz     = 64;
1163         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1164         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1165         *mcq->set_ci_db = 0;
1166         *mcq->arm_db    = 0;
1167         mcq->vector     = param->eq_ix;
1168         mcq->comp       = mlx5e_completion_event;
1169         mcq->event      = mlx5e_cq_error_event;
1170         mcq->irqn       = irqn;
1171         mcq->uar        = &mdev->mlx5e_res.cq_uar;
1172
1173         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1174                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1175
1176                 cqe->op_own = 0xf1;
1177         }
1178
1179         cq->channel = c;
1180         cq->priv = priv;
1181
1182         return 0;
1183 }
1184
1185 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1186 {
1187         mlx5_wq_destroy(&cq->wq_ctrl);
1188 }
1189
1190 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1191 {
1192         struct mlx5e_priv *priv = cq->priv;
1193         struct mlx5_core_dev *mdev = priv->mdev;
1194         struct mlx5_core_cq *mcq = &cq->mcq;
1195
1196         void *in;
1197         void *cqc;
1198         int inlen;
1199         unsigned int irqn_not_used;
1200         int eqn;
1201         int err;
1202
1203         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1204                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1205         in = mlx5_vzalloc(inlen);
1206         if (!in)
1207                 return -ENOMEM;
1208
1209         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1210
1211         memcpy(cqc, param->cqc, sizeof(param->cqc));
1212
1213         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1214                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1215
1216         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1217
1218         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1219         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1220         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
1221         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1222                                             MLX5_ADAPTER_PAGE_SHIFT);
1223         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1224
1225         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1226
1227         kvfree(in);
1228
1229         if (err)
1230                 return err;
1231
1232         mlx5e_cq_arm(cq);
1233
1234         return 0;
1235 }
1236
1237 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1238 {
1239         struct mlx5e_priv *priv = cq->priv;
1240         struct mlx5_core_dev *mdev = priv->mdev;
1241
1242         mlx5_core_destroy_cq(mdev, &cq->mcq);
1243 }
1244
1245 static int mlx5e_open_cq(struct mlx5e_channel *c,
1246                          struct mlx5e_cq_param *param,
1247                          struct mlx5e_cq *cq,
1248                          struct mlx5e_cq_moder moderation)
1249 {
1250         int err;
1251         struct mlx5e_priv *priv = c->priv;
1252         struct mlx5_core_dev *mdev = priv->mdev;
1253
1254         err = mlx5e_create_cq(c, param, cq);
1255         if (err)
1256                 return err;
1257
1258         err = mlx5e_enable_cq(cq, param);
1259         if (err)
1260                 goto err_destroy_cq;
1261
1262         if (MLX5_CAP_GEN(mdev, cq_moderation))
1263                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1264                                                moderation.usec,
1265                                                moderation.pkts);
1266         return 0;
1267
1268 err_destroy_cq:
1269         mlx5e_destroy_cq(cq);
1270
1271         return err;
1272 }
1273
1274 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1275 {
1276         mlx5e_disable_cq(cq);
1277         mlx5e_destroy_cq(cq);
1278 }
1279
1280 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1281 {
1282         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1283 }
1284
1285 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1286                              struct mlx5e_channel_param *cparam)
1287 {
1288         struct mlx5e_priv *priv = c->priv;
1289         int err;
1290         int tc;
1291
1292         for (tc = 0; tc < c->num_tc; tc++) {
1293                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1294                                     priv->params.tx_cq_moderation);
1295                 if (err)
1296                         goto err_close_tx_cqs;
1297         }
1298
1299         return 0;
1300
1301 err_close_tx_cqs:
1302         for (tc--; tc >= 0; tc--)
1303                 mlx5e_close_cq(&c->sq[tc].cq);
1304
1305         return err;
1306 }
1307
1308 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1309 {
1310         int tc;
1311
1312         for (tc = 0; tc < c->num_tc; tc++)
1313                 mlx5e_close_cq(&c->sq[tc].cq);
1314 }
1315
1316 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1317                           struct mlx5e_channel_param *cparam)
1318 {
1319         int err;
1320         int tc;
1321
1322         for (tc = 0; tc < c->num_tc; tc++) {
1323                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1324                 if (err)
1325                         goto err_close_sqs;
1326         }
1327
1328         return 0;
1329
1330 err_close_sqs:
1331         for (tc--; tc >= 0; tc--)
1332                 mlx5e_close_sq(&c->sq[tc]);
1333
1334         return err;
1335 }
1336
1337 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1338 {
1339         int tc;
1340
1341         for (tc = 0; tc < c->num_tc; tc++)
1342                 mlx5e_close_sq(&c->sq[tc]);
1343 }
1344
1345 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1346 {
1347         int i;
1348
1349         for (i = 0; i < priv->profile->max_tc; i++)
1350                 priv->channeltc_to_txq_map[ix][i] =
1351                         ix + i * priv->params.num_channels;
1352 }
1353
1354 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1355                                 struct mlx5e_sq *sq, u32 rate)
1356 {
1357         struct mlx5e_priv *priv = netdev_priv(dev);
1358         struct mlx5_core_dev *mdev = priv->mdev;
1359         u16 rl_index = 0;
1360         int err;
1361
1362         if (rate == sq->rate_limit)
1363                 /* nothing to do */
1364                 return 0;
1365
1366         if (sq->rate_limit)
1367                 /* remove current rl index to free space to next ones */
1368                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1369
1370         sq->rate_limit = 0;
1371
1372         if (rate) {
1373                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1374                 if (err) {
1375                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1376                                    rate, err);
1377                         return err;
1378                 }
1379         }
1380
1381         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1382                               MLX5_SQC_STATE_RDY, true, rl_index);
1383         if (err) {
1384                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1385                            rate, err);
1386                 /* remove the rate from the table */
1387                 if (rate)
1388                         mlx5_rl_remove_rate(mdev, rate);
1389                 return err;
1390         }
1391
1392         sq->rate_limit = rate;
1393         return 0;
1394 }
1395
1396 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1397 {
1398         struct mlx5e_priv *priv = netdev_priv(dev);
1399         struct mlx5_core_dev *mdev = priv->mdev;
1400         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1401         int err = 0;
1402
1403         if (!mlx5_rl_is_supported(mdev)) {
1404                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1405                 return -EINVAL;
1406         }
1407
1408         /* rate is given in Mb/sec, HW config is in Kb/sec */
1409         rate = rate << 10;
1410
1411         /* Check whether rate in valid range, 0 is always valid */
1412         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1413                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1414                 return -ERANGE;
1415         }
1416
1417         mutex_lock(&priv->state_lock);
1418         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1419                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1420         if (!err)
1421                 priv->tx_rates[index] = rate;
1422         mutex_unlock(&priv->state_lock);
1423
1424         return err;
1425 }
1426
1427 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1428                               struct mlx5e_channel_param *cparam,
1429                               struct mlx5e_channel **cp)
1430 {
1431         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1432         struct net_device *netdev = priv->netdev;
1433         struct mlx5e_cq_moder rx_cq_profile;
1434         int cpu = mlx5e_get_cpu(priv, ix);
1435         struct mlx5e_channel *c;
1436         struct mlx5e_sq *sq;
1437         int err;
1438         int i;
1439
1440         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1441         if (!c)
1442                 return -ENOMEM;
1443
1444         c->priv     = priv;
1445         c->ix       = ix;
1446         c->cpu      = cpu;
1447         c->pdev     = &priv->mdev->pdev->dev;
1448         c->netdev   = priv->netdev;
1449         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1450         c->num_tc   = priv->params.num_tc;
1451         c->xdp      = !!priv->xdp_prog;
1452
1453         if (priv->params.rx_am_enabled)
1454                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1455         else
1456                 rx_cq_profile = priv->params.rx_cq_moderation;
1457
1458         mlx5e_build_channeltc_to_txq_map(priv, ix);
1459
1460         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1461
1462         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1463         if (err)
1464                 goto err_napi_del;
1465
1466         err = mlx5e_open_tx_cqs(c, cparam);
1467         if (err)
1468                 goto err_close_icosq_cq;
1469
1470         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1471                             rx_cq_profile);
1472         if (err)
1473                 goto err_close_tx_cqs;
1474
1475         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1476         err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1477                                      priv->params.tx_cq_moderation) : 0;
1478         if (err)
1479                 goto err_close_rx_cq;
1480
1481         napi_enable(&c->napi);
1482
1483         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1484         if (err)
1485                 goto err_disable_napi;
1486
1487         err = mlx5e_open_sqs(c, cparam);
1488         if (err)
1489                 goto err_close_icosq;
1490
1491         for (i = 0; i < priv->params.num_tc; i++) {
1492                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1493
1494                 if (priv->tx_rates[txq_ix]) {
1495                         sq = priv->txq_to_sq_map[txq_ix];
1496                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1497                                              priv->tx_rates[txq_ix]);
1498                 }
1499         }
1500
1501         err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1502         if (err)
1503                 goto err_close_sqs;
1504
1505         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1506         if (err)
1507                 goto err_close_xdp_sq;
1508
1509         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1510         *cp = c;
1511
1512         return 0;
1513 err_close_xdp_sq:
1514         if (c->xdp)
1515                 mlx5e_close_sq(&c->xdp_sq);
1516
1517 err_close_sqs:
1518         mlx5e_close_sqs(c);
1519
1520 err_close_icosq:
1521         mlx5e_close_sq(&c->icosq);
1522
1523 err_disable_napi:
1524         napi_disable(&c->napi);
1525         if (c->xdp)
1526                 mlx5e_close_cq(&c->xdp_sq.cq);
1527
1528 err_close_rx_cq:
1529         mlx5e_close_cq(&c->rq.cq);
1530
1531 err_close_tx_cqs:
1532         mlx5e_close_tx_cqs(c);
1533
1534 err_close_icosq_cq:
1535         mlx5e_close_cq(&c->icosq.cq);
1536
1537 err_napi_del:
1538         netif_napi_del(&c->napi);
1539         napi_hash_del(&c->napi);
1540         kfree(c);
1541
1542         return err;
1543 }
1544
1545 static void mlx5e_close_channel(struct mlx5e_channel *c)
1546 {
1547         mlx5e_close_rq(&c->rq);
1548         if (c->xdp)
1549                 mlx5e_close_sq(&c->xdp_sq);
1550         mlx5e_close_sqs(c);
1551         mlx5e_close_sq(&c->icosq);
1552         napi_disable(&c->napi);
1553         if (c->xdp)
1554                 mlx5e_close_cq(&c->xdp_sq.cq);
1555         mlx5e_close_cq(&c->rq.cq);
1556         mlx5e_close_tx_cqs(c);
1557         mlx5e_close_cq(&c->icosq.cq);
1558         netif_napi_del(&c->napi);
1559
1560         napi_hash_del(&c->napi);
1561         synchronize_rcu();
1562
1563         kfree(c);
1564 }
1565
1566 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1567                                  struct mlx5e_rq_param *param)
1568 {
1569         void *rqc = param->rqc;
1570         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1571
1572         switch (priv->params.rq_wq_type) {
1573         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1574                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1575                          priv->params.mpwqe_log_num_strides - 9);
1576                 MLX5_SET(wq, wq, log_wqe_stride_size,
1577                          priv->params.mpwqe_log_stride_sz - 6);
1578                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1579                 break;
1580         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1581                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1582         }
1583
1584         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1585         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1586         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1587         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1588         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1589
1590         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1591         param->wq.linear = 1;
1592
1593         param->am_enabled = priv->params.rx_am_enabled;
1594 }
1595
1596 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1597 {
1598         void *rqc = param->rqc;
1599         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1600
1601         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1602         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1603 }
1604
1605 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1606                                         struct mlx5e_sq_param *param)
1607 {
1608         void *sqc = param->sqc;
1609         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1610
1611         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1612         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1613
1614         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1615 }
1616
1617 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1618                                  struct mlx5e_sq_param *param)
1619 {
1620         void *sqc = param->sqc;
1621         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1622
1623         mlx5e_build_sq_param_common(priv, param);
1624         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1625
1626         param->max_inline = priv->params.tx_max_inline;
1627         param->min_inline_mode = priv->params.tx_min_inline_mode;
1628         param->type = MLX5E_SQ_TXQ;
1629 }
1630
1631 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1632                                         struct mlx5e_cq_param *param)
1633 {
1634         void *cqc = param->cqc;
1635
1636         MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1637 }
1638
1639 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1640                                     struct mlx5e_cq_param *param)
1641 {
1642         void *cqc = param->cqc;
1643         u8 log_cq_size;
1644
1645         switch (priv->params.rq_wq_type) {
1646         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1647                 log_cq_size = priv->params.log_rq_size +
1648                         priv->params.mpwqe_log_num_strides;
1649                 break;
1650         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1651                 log_cq_size = priv->params.log_rq_size;
1652         }
1653
1654         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1655         if (priv->params.rx_cqe_compress) {
1656                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1657                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1658         }
1659
1660         mlx5e_build_common_cq_param(priv, param);
1661
1662         param->cq_period_mode = priv->params.rx_cq_period_mode;
1663 }
1664
1665 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1666                                     struct mlx5e_cq_param *param)
1667 {
1668         void *cqc = param->cqc;
1669
1670         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1671
1672         mlx5e_build_common_cq_param(priv, param);
1673
1674         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1675 }
1676
1677 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1678                                      struct mlx5e_cq_param *param,
1679                                      u8 log_wq_size)
1680 {
1681         void *cqc = param->cqc;
1682
1683         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1684
1685         mlx5e_build_common_cq_param(priv, param);
1686
1687         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1688 }
1689
1690 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1691                                     struct mlx5e_sq_param *param,
1692                                     u8 log_wq_size)
1693 {
1694         void *sqc = param->sqc;
1695         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1696
1697         mlx5e_build_sq_param_common(priv, param);
1698
1699         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1700         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1701
1702         param->type = MLX5E_SQ_ICO;
1703 }
1704
1705 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1706                                     struct mlx5e_sq_param *param)
1707 {
1708         void *sqc = param->sqc;
1709         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1710
1711         mlx5e_build_sq_param_common(priv, param);
1712         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1713
1714         param->max_inline = priv->params.tx_max_inline;
1715         /* FOR XDP SQs will support only L2 inline mode */
1716         param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1717         param->type = MLX5E_SQ_XDP;
1718 }
1719
1720 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1721 {
1722         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1723
1724         mlx5e_build_rq_param(priv, &cparam->rq);
1725         mlx5e_build_sq_param(priv, &cparam->sq);
1726         mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
1727         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1728         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1729         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1730         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1731 }
1732
1733 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1734 {
1735         struct mlx5e_channel_param *cparam;
1736         int nch = priv->params.num_channels;
1737         int err = -ENOMEM;
1738         int i;
1739         int j;
1740
1741         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1742                                 GFP_KERNEL);
1743
1744         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1745                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1746
1747         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1748
1749         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1750                 goto err_free_txq_to_sq_map;
1751
1752         mlx5e_build_channel_param(priv, cparam);
1753
1754         for (i = 0; i < nch; i++) {
1755                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1756                 if (err)
1757                         goto err_close_channels;
1758         }
1759
1760         for (j = 0; j < nch; j++) {
1761                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1762                 if (err)
1763                         goto err_close_channels;
1764         }
1765
1766         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1767          * polling for inactive tx queues.
1768          */
1769         netif_tx_start_all_queues(priv->netdev);
1770
1771         kfree(cparam);
1772         return 0;
1773
1774 err_close_channels:
1775         for (i--; i >= 0; i--)
1776                 mlx5e_close_channel(priv->channel[i]);
1777
1778 err_free_txq_to_sq_map:
1779         kfree(priv->txq_to_sq_map);
1780         kfree(priv->channel);
1781         kfree(cparam);
1782
1783         return err;
1784 }
1785
1786 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1787 {
1788         int i;
1789
1790         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1791          * polling for inactive tx queues.
1792          */
1793         netif_tx_stop_all_queues(priv->netdev);
1794         netif_tx_disable(priv->netdev);
1795
1796         for (i = 0; i < priv->params.num_channels; i++)
1797                 mlx5e_close_channel(priv->channel[i]);
1798
1799         kfree(priv->txq_to_sq_map);
1800         kfree(priv->channel);
1801 }
1802
1803 static int mlx5e_rx_hash_fn(int hfunc)
1804 {
1805         return (hfunc == ETH_RSS_HASH_TOP) ?
1806                MLX5_RX_HASH_FN_TOEPLITZ :
1807                MLX5_RX_HASH_FN_INVERTED_XOR8;
1808 }
1809
1810 static int mlx5e_bits_invert(unsigned long a, int size)
1811 {
1812         int inv = 0;
1813         int i;
1814
1815         for (i = 0; i < size; i++)
1816                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1817
1818         return inv;
1819 }
1820
1821 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1822 {
1823         int i;
1824
1825         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1826                 int ix = i;
1827                 u32 rqn;
1828
1829                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1830                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1831
1832                 ix = priv->params.indirection_rqt[ix];
1833                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1834                                 priv->channel[ix]->rq.rqn :
1835                                 priv->drop_rq.rqn;
1836                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1837         }
1838 }
1839
1840 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1841                                       int ix)
1842 {
1843         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1844                         priv->channel[ix]->rq.rqn :
1845                         priv->drop_rq.rqn;
1846
1847         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1848 }
1849
1850 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1851                             int ix, struct mlx5e_rqt *rqt)
1852 {
1853         struct mlx5_core_dev *mdev = priv->mdev;
1854         void *rqtc;
1855         int inlen;
1856         int err;
1857         u32 *in;
1858
1859         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1860         in = mlx5_vzalloc(inlen);
1861         if (!in)
1862                 return -ENOMEM;
1863
1864         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1865
1866         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1867         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1868
1869         if (sz > 1) /* RSS */
1870                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1871         else
1872                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1873
1874         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1875         if (!err)
1876                 rqt->enabled = true;
1877
1878         kvfree(in);
1879         return err;
1880 }
1881
1882 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1883 {
1884         rqt->enabled = false;
1885         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1886 }
1887
1888 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1889 {
1890         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1891
1892         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1893 }
1894
1895 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1896 {
1897         struct mlx5e_rqt *rqt;
1898         int err;
1899         int ix;
1900
1901         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1902                 rqt = &priv->direct_tir[ix].rqt;
1903                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1904                 if (err)
1905                         goto err_destroy_rqts;
1906         }
1907
1908         return 0;
1909
1910 err_destroy_rqts:
1911         for (ix--; ix >= 0; ix--)
1912                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1913
1914         return err;
1915 }
1916
1917 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1918 {
1919         struct mlx5_core_dev *mdev = priv->mdev;
1920         void *rqtc;
1921         int inlen;
1922         u32 *in;
1923         int err;
1924
1925         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1926         in = mlx5_vzalloc(inlen);
1927         if (!in)
1928                 return -ENOMEM;
1929
1930         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1931
1932         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1933         if (sz > 1) /* RSS */
1934                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1935         else
1936                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1937
1938         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1939
1940         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1941
1942         kvfree(in);
1943
1944         return err;
1945 }
1946
1947 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1948 {
1949         u32 rqtn;
1950         int ix;
1951
1952         if (priv->indir_rqt.enabled) {
1953                 rqtn = priv->indir_rqt.rqtn;
1954                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1955         }
1956
1957         for (ix = 0; ix < priv->params.num_channels; ix++) {
1958                 if (!priv->direct_tir[ix].rqt.enabled)
1959                         continue;
1960                 rqtn = priv->direct_tir[ix].rqt.rqtn;
1961                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1962         }
1963 }
1964
1965 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1966 {
1967         if (!priv->params.lro_en)
1968                 return;
1969
1970 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1971
1972         MLX5_SET(tirc, tirc, lro_enable_mask,
1973                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1974                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1975         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1976                  (priv->params.lro_wqe_sz -
1977                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1978         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
1979 }
1980
1981 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1982 {
1983         MLX5_SET(tirc, tirc, rx_hash_fn,
1984                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1985         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1986                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1987                                              rx_hash_toeplitz_key);
1988                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1989                                                rx_hash_toeplitz_key);
1990
1991                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1992                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1993         }
1994 }
1995
1996 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1997 {
1998         struct mlx5_core_dev *mdev = priv->mdev;
1999
2000         void *in;
2001         void *tirc;
2002         int inlen;
2003         int err;
2004         int tt;
2005         int ix;
2006
2007         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2008         in = mlx5_vzalloc(inlen);
2009         if (!in)
2010                 return -ENOMEM;
2011
2012         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2013         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2014
2015         mlx5e_build_tir_ctx_lro(tirc, priv);
2016
2017         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2018                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2019                                            inlen);
2020                 if (err)
2021                         goto free_in;
2022         }
2023
2024         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2025                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2026                                            in, inlen);
2027                 if (err)
2028                         goto free_in;
2029         }
2030
2031 free_in:
2032         kvfree(in);
2033
2034         return err;
2035 }
2036
2037 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2038 {
2039         struct mlx5_core_dev *mdev = priv->mdev;
2040         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2041         int err;
2042
2043         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2044         if (err)
2045                 return err;
2046
2047         /* Update vport context MTU */
2048         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2049         return 0;
2050 }
2051
2052 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2053 {
2054         struct mlx5_core_dev *mdev = priv->mdev;
2055         u16 hw_mtu = 0;
2056         int err;
2057
2058         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2059         if (err || !hw_mtu) /* fallback to port oper mtu */
2060                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2061
2062         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2063 }
2064
2065 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2066 {
2067         struct mlx5e_priv *priv = netdev_priv(netdev);
2068         u16 mtu;
2069         int err;
2070
2071         err = mlx5e_set_mtu(priv, netdev->mtu);
2072         if (err)
2073                 return err;
2074
2075         mlx5e_query_mtu(priv, &mtu);
2076         if (mtu != netdev->mtu)
2077                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2078                             __func__, mtu, netdev->mtu);
2079
2080         netdev->mtu = mtu;
2081         return 0;
2082 }
2083
2084 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2085 {
2086         struct mlx5e_priv *priv = netdev_priv(netdev);
2087         int nch = priv->params.num_channels;
2088         int ntc = priv->params.num_tc;
2089         int tc;
2090
2091         netdev_reset_tc(netdev);
2092
2093         if (ntc == 1)
2094                 return;
2095
2096         netdev_set_num_tc(netdev, ntc);
2097
2098         /* Map netdev TCs to offset 0
2099          * We have our own UP to TXQ mapping for QoS
2100          */
2101         for (tc = 0; tc < ntc; tc++)
2102                 netdev_set_tc_queue(netdev, tc, nch, 0);
2103 }
2104
2105 int mlx5e_open_locked(struct net_device *netdev)
2106 {
2107         struct mlx5e_priv *priv = netdev_priv(netdev);
2108         struct mlx5_core_dev *mdev = priv->mdev;
2109         int num_txqs;
2110         int err;
2111
2112         set_bit(MLX5E_STATE_OPENED, &priv->state);
2113
2114         mlx5e_netdev_set_tcs(netdev);
2115
2116         num_txqs = priv->params.num_channels * priv->params.num_tc;
2117         netif_set_real_num_tx_queues(netdev, num_txqs);
2118         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2119
2120         err = mlx5e_open_channels(priv);
2121         if (err) {
2122                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2123                            __func__, err);
2124                 goto err_clear_state_opened_flag;
2125         }
2126
2127         err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
2128         if (err) {
2129                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2130                            __func__, err);
2131                 goto err_close_channels;
2132         }
2133
2134         mlx5e_redirect_rqts(priv);
2135         mlx5e_update_carrier(priv);
2136         mlx5e_timestamp_init(priv);
2137 #ifdef CONFIG_RFS_ACCEL
2138         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2139 #endif
2140         if (priv->profile->update_stats)
2141                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2142
2143         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2144                 err = mlx5e_add_sqs_fwd_rules(priv);
2145                 if (err)
2146                         goto err_close_channels;
2147         }
2148         return 0;
2149
2150 err_close_channels:
2151         mlx5e_close_channels(priv);
2152 err_clear_state_opened_flag:
2153         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2154         return err;
2155 }
2156
2157 int mlx5e_open(struct net_device *netdev)
2158 {
2159         struct mlx5e_priv *priv = netdev_priv(netdev);
2160         int err;
2161
2162         mutex_lock(&priv->state_lock);
2163         err = mlx5e_open_locked(netdev);
2164         mutex_unlock(&priv->state_lock);
2165
2166         return err;
2167 }
2168
2169 int mlx5e_close_locked(struct net_device *netdev)
2170 {
2171         struct mlx5e_priv *priv = netdev_priv(netdev);
2172         struct mlx5_core_dev *mdev = priv->mdev;
2173
2174         /* May already be CLOSED in case a previous configuration operation
2175          * (e.g RX/TX queue size change) that involves close&open failed.
2176          */
2177         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2178                 return 0;
2179
2180         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2181
2182         if (MLX5_CAP_GEN(mdev, vport_group_manager))
2183                 mlx5e_remove_sqs_fwd_rules(priv);
2184
2185         mlx5e_timestamp_cleanup(priv);
2186         netif_carrier_off(priv->netdev);
2187         mlx5e_redirect_rqts(priv);
2188         mlx5e_close_channels(priv);
2189
2190         return 0;
2191 }
2192
2193 int mlx5e_close(struct net_device *netdev)
2194 {
2195         struct mlx5e_priv *priv = netdev_priv(netdev);
2196         int err;
2197
2198         if (!netif_device_present(netdev))
2199                 return -ENODEV;
2200
2201         mutex_lock(&priv->state_lock);
2202         err = mlx5e_close_locked(netdev);
2203         mutex_unlock(&priv->state_lock);
2204
2205         return err;
2206 }
2207
2208 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2209                                 struct mlx5e_rq *rq,
2210                                 struct mlx5e_rq_param *param)
2211 {
2212         struct mlx5_core_dev *mdev = priv->mdev;
2213         void *rqc = param->rqc;
2214         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2215         int err;
2216
2217         param->wq.db_numa_node = param->wq.buf_numa_node;
2218
2219         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2220                                 &rq->wq_ctrl);
2221         if (err)
2222                 return err;
2223
2224         rq->priv = priv;
2225
2226         return 0;
2227 }
2228
2229 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2230                                 struct mlx5e_cq *cq,
2231                                 struct mlx5e_cq_param *param)
2232 {
2233         struct mlx5_core_dev *mdev = priv->mdev;
2234         struct mlx5_core_cq *mcq = &cq->mcq;
2235         int eqn_not_used;
2236         unsigned int irqn;
2237         int err;
2238
2239         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2240                                &cq->wq_ctrl);
2241         if (err)
2242                 return err;
2243
2244         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2245
2246         mcq->cqe_sz     = 64;
2247         mcq->set_ci_db  = cq->wq_ctrl.db.db;
2248         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
2249         *mcq->set_ci_db = 0;
2250         *mcq->arm_db    = 0;
2251         mcq->vector     = param->eq_ix;
2252         mcq->comp       = mlx5e_completion_event;
2253         mcq->event      = mlx5e_cq_error_event;
2254         mcq->irqn       = irqn;
2255         mcq->uar        = &mdev->mlx5e_res.cq_uar;
2256
2257         cq->priv = priv;
2258
2259         return 0;
2260 }
2261
2262 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2263 {
2264         struct mlx5e_cq_param cq_param;
2265         struct mlx5e_rq_param rq_param;
2266         struct mlx5e_rq *rq = &priv->drop_rq;
2267         struct mlx5e_cq *cq = &priv->drop_rq.cq;
2268         int err;
2269
2270         memset(&cq_param, 0, sizeof(cq_param));
2271         memset(&rq_param, 0, sizeof(rq_param));
2272         mlx5e_build_drop_rq_param(&rq_param);
2273
2274         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2275         if (err)
2276                 return err;
2277
2278         err = mlx5e_enable_cq(cq, &cq_param);
2279         if (err)
2280                 goto err_destroy_cq;
2281
2282         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2283         if (err)
2284                 goto err_disable_cq;
2285
2286         err = mlx5e_enable_rq(rq, &rq_param);
2287         if (err)
2288                 goto err_destroy_rq;
2289
2290         return 0;
2291
2292 err_destroy_rq:
2293         mlx5e_destroy_rq(&priv->drop_rq);
2294
2295 err_disable_cq:
2296         mlx5e_disable_cq(&priv->drop_rq.cq);
2297
2298 err_destroy_cq:
2299         mlx5e_destroy_cq(&priv->drop_rq.cq);
2300
2301         return err;
2302 }
2303
2304 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2305 {
2306         mlx5e_disable_rq(&priv->drop_rq);
2307         mlx5e_destroy_rq(&priv->drop_rq);
2308         mlx5e_disable_cq(&priv->drop_rq.cq);
2309         mlx5e_destroy_cq(&priv->drop_rq.cq);
2310 }
2311
2312 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2313 {
2314         struct mlx5_core_dev *mdev = priv->mdev;
2315         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2316         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2317
2318         MLX5_SET(tisc, tisc, prio, tc << 1);
2319         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2320
2321         if (mlx5_lag_is_lacp_owner(mdev))
2322                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2323
2324         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2325 }
2326
2327 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2328 {
2329         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2330 }
2331
2332 int mlx5e_create_tises(struct mlx5e_priv *priv)
2333 {
2334         int err;
2335         int tc;
2336
2337         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2338                 err = mlx5e_create_tis(priv, tc);
2339                 if (err)
2340                         goto err_close_tises;
2341         }
2342
2343         return 0;
2344
2345 err_close_tises:
2346         for (tc--; tc >= 0; tc--)
2347                 mlx5e_destroy_tis(priv, tc);
2348
2349         return err;
2350 }
2351
2352 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2353 {
2354         int tc;
2355
2356         for (tc = 0; tc < priv->profile->max_tc; tc++)
2357                 mlx5e_destroy_tis(priv, tc);
2358 }
2359
2360 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2361                                       enum mlx5e_traffic_types tt)
2362 {
2363         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2364
2365         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2366
2367 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2368                                  MLX5_HASH_FIELD_SEL_DST_IP)
2369
2370 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2371                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2372                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2373                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2374
2375 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2376                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2377                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2378
2379         mlx5e_build_tir_ctx_lro(tirc, priv);
2380
2381         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2382         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2383         mlx5e_build_tir_ctx_hash(tirc, priv);
2384
2385         switch (tt) {
2386         case MLX5E_TT_IPV4_TCP:
2387                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2388                          MLX5_L3_PROT_TYPE_IPV4);
2389                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2390                          MLX5_L4_PROT_TYPE_TCP);
2391                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2392                          MLX5_HASH_IP_L4PORTS);
2393                 break;
2394
2395         case MLX5E_TT_IPV6_TCP:
2396                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2397                          MLX5_L3_PROT_TYPE_IPV6);
2398                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2399                          MLX5_L4_PROT_TYPE_TCP);
2400                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2401                          MLX5_HASH_IP_L4PORTS);
2402                 break;
2403
2404         case MLX5E_TT_IPV4_UDP:
2405                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2406                          MLX5_L3_PROT_TYPE_IPV4);
2407                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2408                          MLX5_L4_PROT_TYPE_UDP);
2409                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2410                          MLX5_HASH_IP_L4PORTS);
2411                 break;
2412
2413         case MLX5E_TT_IPV6_UDP:
2414                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2415                          MLX5_L3_PROT_TYPE_IPV6);
2416                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2417                          MLX5_L4_PROT_TYPE_UDP);
2418                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2419                          MLX5_HASH_IP_L4PORTS);
2420                 break;
2421
2422         case MLX5E_TT_IPV4_IPSEC_AH:
2423                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2424                          MLX5_L3_PROT_TYPE_IPV4);
2425                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2426                          MLX5_HASH_IP_IPSEC_SPI);
2427                 break;
2428
2429         case MLX5E_TT_IPV6_IPSEC_AH:
2430                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2431                          MLX5_L3_PROT_TYPE_IPV6);
2432                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2433                          MLX5_HASH_IP_IPSEC_SPI);
2434                 break;
2435
2436         case MLX5E_TT_IPV4_IPSEC_ESP:
2437                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2438                          MLX5_L3_PROT_TYPE_IPV4);
2439                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2440                          MLX5_HASH_IP_IPSEC_SPI);
2441                 break;
2442
2443         case MLX5E_TT_IPV6_IPSEC_ESP:
2444                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2445                          MLX5_L3_PROT_TYPE_IPV6);
2446                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2447                          MLX5_HASH_IP_IPSEC_SPI);
2448                 break;
2449
2450         case MLX5E_TT_IPV4:
2451                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2452                          MLX5_L3_PROT_TYPE_IPV4);
2453                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2454                          MLX5_HASH_IP);
2455                 break;
2456
2457         case MLX5E_TT_IPV6:
2458                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2459                          MLX5_L3_PROT_TYPE_IPV6);
2460                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2461                          MLX5_HASH_IP);
2462                 break;
2463         default:
2464                 WARN_ONCE(true,
2465                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2466         }
2467 }
2468
2469 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2470                                        u32 rqtn)
2471 {
2472         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2473
2474         mlx5e_build_tir_ctx_lro(tirc, priv);
2475
2476         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2477         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2478         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2479 }
2480
2481 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2482 {
2483         struct mlx5e_tir *tir;
2484         void *tirc;
2485         int inlen;
2486         int err;
2487         u32 *in;
2488         int tt;
2489
2490         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2491         in = mlx5_vzalloc(inlen);
2492         if (!in)
2493                 return -ENOMEM;
2494
2495         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2496                 memset(in, 0, inlen);
2497                 tir = &priv->indir_tir[tt];
2498                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2499                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2500                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2501                 if (err)
2502                         goto err_destroy_tirs;
2503         }
2504
2505         kvfree(in);
2506
2507         return 0;
2508
2509 err_destroy_tirs:
2510         for (tt--; tt >= 0; tt--)
2511                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2512
2513         kvfree(in);
2514
2515         return err;
2516 }
2517
2518 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2519 {
2520         int nch = priv->profile->max_nch(priv->mdev);
2521         struct mlx5e_tir *tir;
2522         void *tirc;
2523         int inlen;
2524         int err;
2525         u32 *in;
2526         int ix;
2527
2528         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2529         in = mlx5_vzalloc(inlen);
2530         if (!in)
2531                 return -ENOMEM;
2532
2533         for (ix = 0; ix < nch; ix++) {
2534                 memset(in, 0, inlen);
2535                 tir = &priv->direct_tir[ix];
2536                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2537                 mlx5e_build_direct_tir_ctx(priv, tirc,
2538                                            priv->direct_tir[ix].rqt.rqtn);
2539                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2540                 if (err)
2541                         goto err_destroy_ch_tirs;
2542         }
2543
2544         kvfree(in);
2545
2546         return 0;
2547
2548 err_destroy_ch_tirs:
2549         for (ix--; ix >= 0; ix--)
2550                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2551
2552         kvfree(in);
2553
2554         return err;
2555 }
2556
2557 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2558 {
2559         int i;
2560
2561         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2562                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2563 }
2564
2565 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2566 {
2567         int nch = priv->profile->max_nch(priv->mdev);
2568         int i;
2569
2570         for (i = 0; i < nch; i++)
2571                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2572 }
2573
2574 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2575 {
2576         int err = 0;
2577         int i;
2578
2579         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2580                 return 0;
2581
2582         for (i = 0; i < priv->params.num_channels; i++) {
2583                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2584                 if (err)
2585                         return err;
2586         }
2587
2588         return 0;
2589 }
2590
2591 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2592 {
2593         struct mlx5e_priv *priv = netdev_priv(netdev);
2594         bool was_opened;
2595         int err = 0;
2596
2597         if (tc && tc != MLX5E_MAX_NUM_TC)
2598                 return -EINVAL;
2599
2600         mutex_lock(&priv->state_lock);
2601
2602         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2603         if (was_opened)
2604                 mlx5e_close_locked(priv->netdev);
2605
2606         priv->params.num_tc = tc ? tc : 1;
2607
2608         if (was_opened)
2609                 err = mlx5e_open_locked(priv->netdev);
2610
2611         mutex_unlock(&priv->state_lock);
2612
2613         return err;
2614 }
2615
2616 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2617                               __be16 proto, struct tc_to_netdev *tc)
2618 {
2619         struct mlx5e_priv *priv = netdev_priv(dev);
2620
2621         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2622                 goto mqprio;
2623
2624         switch (tc->type) {
2625         case TC_SETUP_CLSFLOWER:
2626                 switch (tc->cls_flower->command) {
2627                 case TC_CLSFLOWER_REPLACE:
2628                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2629                 case TC_CLSFLOWER_DESTROY:
2630                         return mlx5e_delete_flower(priv, tc->cls_flower);
2631                 case TC_CLSFLOWER_STATS:
2632                         return mlx5e_stats_flower(priv, tc->cls_flower);
2633                 }
2634         default:
2635                 return -EOPNOTSUPP;
2636         }
2637
2638 mqprio:
2639         if (tc->type != TC_SETUP_MQPRIO)
2640                 return -EINVAL;
2641
2642         return mlx5e_setup_tc(dev, tc->tc);
2643 }
2644
2645 struct rtnl_link_stats64 *
2646 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2647 {
2648         struct mlx5e_priv *priv = netdev_priv(dev);
2649         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2650         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2651         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2652
2653         stats->rx_packets = sstats->rx_packets;
2654         stats->rx_bytes   = sstats->rx_bytes;
2655         stats->tx_packets = sstats->tx_packets;
2656         stats->tx_bytes   = sstats->tx_bytes;
2657
2658         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2659         stats->tx_dropped = sstats->tx_queue_dropped;
2660
2661         stats->rx_length_errors =
2662                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2663                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2664                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2665         stats->rx_crc_errors =
2666                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2667         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2668         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2669         stats->tx_carrier_errors =
2670                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2671         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2672                            stats->rx_frame_errors;
2673         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2674
2675         /* vport multicast also counts packets that are dropped due to steering
2676          * or rx out of buffer
2677          */
2678         stats->multicast =
2679                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2680
2681         return stats;
2682 }
2683
2684 static void mlx5e_set_rx_mode(struct net_device *dev)
2685 {
2686         struct mlx5e_priv *priv = netdev_priv(dev);
2687
2688         queue_work(priv->wq, &priv->set_rx_mode_work);
2689 }
2690
2691 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2692 {
2693         struct mlx5e_priv *priv = netdev_priv(netdev);
2694         struct sockaddr *saddr = addr;
2695
2696         if (!is_valid_ether_addr(saddr->sa_data))
2697                 return -EADDRNOTAVAIL;
2698
2699         netif_addr_lock_bh(netdev);
2700         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2701         netif_addr_unlock_bh(netdev);
2702
2703         queue_work(priv->wq, &priv->set_rx_mode_work);
2704
2705         return 0;
2706 }
2707
2708 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2709         do {                                            \
2710                 if (enable)                             \
2711                         netdev->features |= feature;    \
2712                 else                                    \
2713                         netdev->features &= ~feature;   \
2714         } while (0)
2715
2716 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2717
2718 static int set_feature_lro(struct net_device *netdev, bool enable)
2719 {
2720         struct mlx5e_priv *priv = netdev_priv(netdev);
2721         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2722         int err;
2723
2724         mutex_lock(&priv->state_lock);
2725
2726         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2727                 mlx5e_close_locked(priv->netdev);
2728
2729         priv->params.lro_en = enable;
2730         err = mlx5e_modify_tirs_lro(priv);
2731         if (err) {
2732                 netdev_err(netdev, "lro modify failed, %d\n", err);
2733                 priv->params.lro_en = !enable;
2734         }
2735
2736         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2737                 mlx5e_open_locked(priv->netdev);
2738
2739         mutex_unlock(&priv->state_lock);
2740
2741         return err;
2742 }
2743
2744 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2745 {
2746         struct mlx5e_priv *priv = netdev_priv(netdev);
2747
2748         if (enable)
2749                 mlx5e_enable_vlan_filter(priv);
2750         else
2751                 mlx5e_disable_vlan_filter(priv);
2752
2753         return 0;
2754 }
2755
2756 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2757 {
2758         struct mlx5e_priv *priv = netdev_priv(netdev);
2759
2760         if (!enable && mlx5e_tc_num_filters(priv)) {
2761                 netdev_err(netdev,
2762                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2763                 return -EINVAL;
2764         }
2765
2766         return 0;
2767 }
2768
2769 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2770 {
2771         struct mlx5e_priv *priv = netdev_priv(netdev);
2772         struct mlx5_core_dev *mdev = priv->mdev;
2773
2774         return mlx5_set_port_fcs(mdev, !enable);
2775 }
2776
2777 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2778 {
2779         struct mlx5e_priv *priv = netdev_priv(netdev);
2780         int err;
2781
2782         mutex_lock(&priv->state_lock);
2783
2784         priv->params.vlan_strip_disable = !enable;
2785         err = mlx5e_modify_rqs_vsd(priv, !enable);
2786         if (err)
2787                 priv->params.vlan_strip_disable = enable;
2788
2789         mutex_unlock(&priv->state_lock);
2790
2791         return err;
2792 }
2793
2794 #ifdef CONFIG_RFS_ACCEL
2795 static int set_feature_arfs(struct net_device *netdev, bool enable)
2796 {
2797         struct mlx5e_priv *priv = netdev_priv(netdev);
2798         int err;
2799
2800         if (enable)
2801                 err = mlx5e_arfs_enable(priv);
2802         else
2803                 err = mlx5e_arfs_disable(priv);
2804
2805         return err;
2806 }
2807 #endif
2808
2809 static int mlx5e_handle_feature(struct net_device *netdev,
2810                                 netdev_features_t wanted_features,
2811                                 netdev_features_t feature,
2812                                 mlx5e_feature_handler feature_handler)
2813 {
2814         netdev_features_t changes = wanted_features ^ netdev->features;
2815         bool enable = !!(wanted_features & feature);
2816         int err;
2817
2818         if (!(changes & feature))
2819                 return 0;
2820
2821         err = feature_handler(netdev, enable);
2822         if (err) {
2823                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2824                            enable ? "Enable" : "Disable", feature, err);
2825                 return err;
2826         }
2827
2828         MLX5E_SET_FEATURE(netdev, feature, enable);
2829         return 0;
2830 }
2831
2832 static int mlx5e_set_features(struct net_device *netdev,
2833                               netdev_features_t features)
2834 {
2835         int err;
2836
2837         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2838                                     set_feature_lro);
2839         err |= mlx5e_handle_feature(netdev, features,
2840                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2841                                     set_feature_vlan_filter);
2842         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2843                                     set_feature_tc_num_filters);
2844         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2845                                     set_feature_rx_all);
2846         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2847                                     set_feature_rx_vlan);
2848 #ifdef CONFIG_RFS_ACCEL
2849         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2850                                     set_feature_arfs);
2851 #endif
2852
2853         return err ? -EINVAL : 0;
2854 }
2855
2856 #define MXL5_HW_MIN_MTU 64
2857 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2858
2859 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2860 {
2861         struct mlx5e_priv *priv = netdev_priv(netdev);
2862         struct mlx5_core_dev *mdev = priv->mdev;
2863         bool was_opened;
2864         u16 max_mtu;
2865         u16 min_mtu;
2866         int err = 0;
2867         bool reset;
2868
2869         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2870
2871         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2872         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2873
2874         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2875                 netdev_err(netdev,
2876                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2877                            __func__, new_mtu, min_mtu, max_mtu);
2878                 return -EINVAL;
2879         }
2880
2881         mutex_lock(&priv->state_lock);
2882
2883         reset = !priv->params.lro_en &&
2884                 (priv->params.rq_wq_type !=
2885                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2886
2887         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2888         if (was_opened && reset)
2889                 mlx5e_close_locked(netdev);
2890
2891         netdev->mtu = new_mtu;
2892         mlx5e_set_dev_port_mtu(netdev);
2893
2894         if (was_opened && reset)
2895                 err = mlx5e_open_locked(netdev);
2896
2897         mutex_unlock(&priv->state_lock);
2898
2899         return err;
2900 }
2901
2902 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2903 {
2904         switch (cmd) {
2905         case SIOCSHWTSTAMP:
2906                 return mlx5e_hwstamp_set(dev, ifr);
2907         case SIOCGHWTSTAMP:
2908                 return mlx5e_hwstamp_get(dev, ifr);
2909         default:
2910                 return -EOPNOTSUPP;
2911         }
2912 }
2913
2914 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2915 {
2916         struct mlx5e_priv *priv = netdev_priv(dev);
2917         struct mlx5_core_dev *mdev = priv->mdev;
2918
2919         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2920 }
2921
2922 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2923                              __be16 vlan_proto)
2924 {
2925         struct mlx5e_priv *priv = netdev_priv(dev);
2926         struct mlx5_core_dev *mdev = priv->mdev;
2927
2928         if (vlan_proto != htons(ETH_P_8021Q))
2929                 return -EPROTONOSUPPORT;
2930
2931         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2932                                            vlan, qos);
2933 }
2934
2935 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2936 {
2937         struct mlx5e_priv *priv = netdev_priv(dev);
2938         struct mlx5_core_dev *mdev = priv->mdev;
2939
2940         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2941 }
2942
2943 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2944 {
2945         struct mlx5e_priv *priv = netdev_priv(dev);
2946         struct mlx5_core_dev *mdev = priv->mdev;
2947
2948         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2949 }
2950 static int mlx5_vport_link2ifla(u8 esw_link)
2951 {
2952         switch (esw_link) {
2953         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2954                 return IFLA_VF_LINK_STATE_DISABLE;
2955         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2956                 return IFLA_VF_LINK_STATE_ENABLE;
2957         }
2958         return IFLA_VF_LINK_STATE_AUTO;
2959 }
2960
2961 static int mlx5_ifla_link2vport(u8 ifla_link)
2962 {
2963         switch (ifla_link) {
2964         case IFLA_VF_LINK_STATE_DISABLE:
2965                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2966         case IFLA_VF_LINK_STATE_ENABLE:
2967                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2968         }
2969         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2970 }
2971
2972 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2973                                    int link_state)
2974 {
2975         struct mlx5e_priv *priv = netdev_priv(dev);
2976         struct mlx5_core_dev *mdev = priv->mdev;
2977
2978         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2979                                             mlx5_ifla_link2vport(link_state));
2980 }
2981
2982 static int mlx5e_get_vf_config(struct net_device *dev,
2983                                int vf, struct ifla_vf_info *ivi)
2984 {
2985         struct mlx5e_priv *priv = netdev_priv(dev);
2986         struct mlx5_core_dev *mdev = priv->mdev;
2987         int err;
2988
2989         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2990         if (err)
2991                 return err;
2992         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2993         return 0;
2994 }
2995
2996 static int mlx5e_get_vf_stats(struct net_device *dev,
2997                               int vf, struct ifla_vf_stats *vf_stats)
2998 {
2999         struct mlx5e_priv *priv = netdev_priv(dev);
3000         struct mlx5_core_dev *mdev = priv->mdev;
3001
3002         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3003                                             vf_stats);
3004 }
3005
3006 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3007                                  struct udp_tunnel_info *ti)
3008 {
3009         struct mlx5e_priv *priv = netdev_priv(netdev);
3010
3011         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3012                 return;
3013
3014         if (!mlx5e_vxlan_allowed(priv->mdev))
3015                 return;
3016
3017         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3018 }
3019
3020 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3021                                  struct udp_tunnel_info *ti)
3022 {
3023         struct mlx5e_priv *priv = netdev_priv(netdev);
3024
3025         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3026                 return;
3027
3028         if (!mlx5e_vxlan_allowed(priv->mdev))
3029                 return;
3030
3031         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3032 }
3033
3034 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3035                                                     struct sk_buff *skb,
3036                                                     netdev_features_t features)
3037 {
3038         struct udphdr *udph;
3039         u16 proto;
3040         u16 port = 0;
3041
3042         switch (vlan_get_protocol(skb)) {
3043         case htons(ETH_P_IP):
3044                 proto = ip_hdr(skb)->protocol;
3045                 break;
3046         case htons(ETH_P_IPV6):
3047                 proto = ipv6_hdr(skb)->nexthdr;
3048                 break;
3049         default:
3050                 goto out;
3051         }
3052
3053         if (proto == IPPROTO_UDP) {
3054                 udph = udp_hdr(skb);
3055                 port = be16_to_cpu(udph->dest);
3056         }
3057
3058         /* Verify if UDP port is being offloaded by HW */
3059         if (port && mlx5e_vxlan_lookup_port(priv, port))
3060                 return features;
3061
3062 out:
3063         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3064         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3065 }
3066
3067 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3068                                               struct net_device *netdev,
3069                                               netdev_features_t features)
3070 {
3071         struct mlx5e_priv *priv = netdev_priv(netdev);
3072
3073         features = vlan_features_check(skb, features);
3074         features = vxlan_features_check(skb, features);
3075
3076         /* Validate if the tunneled packet is being offloaded by HW */
3077         if (skb->encapsulation &&
3078             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3079                 return mlx5e_vxlan_features_check(priv, skb, features);
3080
3081         return features;
3082 }
3083
3084 static void mlx5e_tx_timeout(struct net_device *dev)
3085 {
3086         struct mlx5e_priv *priv = netdev_priv(dev);
3087         bool sched_work = false;
3088         int i;
3089
3090         netdev_err(dev, "TX timeout detected\n");
3091
3092         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3093                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3094
3095                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3096                         continue;
3097                 sched_work = true;
3098                 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3099                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3100                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3101         }
3102
3103         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3104                 schedule_work(&priv->tx_timeout_work);
3105 }
3106
3107 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3108 {
3109         struct mlx5e_priv *priv = netdev_priv(netdev);
3110         struct bpf_prog *old_prog;
3111         int err = 0;
3112         bool reset, was_opened;
3113         int i;
3114
3115         mutex_lock(&priv->state_lock);
3116
3117         if ((netdev->features & NETIF_F_LRO) && prog) {
3118                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3119                 err = -EINVAL;
3120                 goto unlock;
3121         }
3122
3123         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3124         /* no need for full reset when exchanging programs */
3125         reset = (!priv->xdp_prog || !prog);
3126
3127         if (was_opened && reset)
3128                 mlx5e_close_locked(netdev);
3129
3130         /* exchange programs */
3131         old_prog = xchg(&priv->xdp_prog, prog);
3132         if (prog)
3133                 bpf_prog_add(prog, 1);
3134         if (old_prog)
3135                 bpf_prog_put(old_prog);
3136
3137         if (reset) /* change RQ type according to priv->xdp_prog */
3138                 mlx5e_set_rq_priv_params(priv);
3139
3140         if (was_opened && reset)
3141                 mlx5e_open_locked(netdev);
3142
3143         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3144                 goto unlock;
3145
3146         /* exchanging programs w/o reset, we update ref counts on behalf
3147          * of the channels RQs here.
3148          */
3149         bpf_prog_add(prog, priv->params.num_channels);
3150         for (i = 0; i < priv->params.num_channels; i++) {
3151                 struct mlx5e_channel *c = priv->channel[i];
3152
3153                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3154                 napi_synchronize(&c->napi);
3155                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3156
3157                 old_prog = xchg(&c->rq.xdp_prog, prog);
3158
3159                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3160                 /* napi_schedule in case we have missed anything */
3161                 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3162                 napi_schedule(&c->napi);
3163
3164                 if (old_prog)
3165                         bpf_prog_put(old_prog);
3166         }
3167
3168 unlock:
3169         mutex_unlock(&priv->state_lock);
3170         return err;
3171 }
3172
3173 static bool mlx5e_xdp_attached(struct net_device *dev)
3174 {
3175         struct mlx5e_priv *priv = netdev_priv(dev);
3176
3177         return !!priv->xdp_prog;
3178 }
3179
3180 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3181 {
3182         switch (xdp->command) {
3183         case XDP_SETUP_PROG:
3184                 return mlx5e_xdp_set(dev, xdp->prog);
3185         case XDP_QUERY_PROG:
3186                 xdp->prog_attached = mlx5e_xdp_attached(dev);
3187                 return 0;
3188         default:
3189                 return -EINVAL;
3190         }
3191 }
3192
3193 #ifdef CONFIG_NET_POLL_CONTROLLER
3194 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3195  * reenabling interrupts.
3196  */
3197 static void mlx5e_netpoll(struct net_device *dev)
3198 {
3199         struct mlx5e_priv *priv = netdev_priv(dev);
3200         int i;
3201
3202         for (i = 0; i < priv->params.num_channels; i++)
3203                 napi_schedule(&priv->channel[i]->napi);
3204 }
3205 #endif
3206
3207 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3208         .ndo_open                = mlx5e_open,
3209         .ndo_stop                = mlx5e_close,
3210         .ndo_start_xmit          = mlx5e_xmit,
3211         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3212         .ndo_select_queue        = mlx5e_select_queue,
3213         .ndo_get_stats64         = mlx5e_get_stats,
3214         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3215         .ndo_set_mac_address     = mlx5e_set_mac,
3216         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3217         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3218         .ndo_set_features        = mlx5e_set_features,
3219         .ndo_change_mtu          = mlx5e_change_mtu,
3220         .ndo_do_ioctl            = mlx5e_ioctl,
3221         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3222 #ifdef CONFIG_RFS_ACCEL
3223         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3224 #endif
3225         .ndo_tx_timeout          = mlx5e_tx_timeout,
3226         .ndo_xdp                 = mlx5e_xdp,
3227 #ifdef CONFIG_NET_POLL_CONTROLLER
3228         .ndo_poll_controller     = mlx5e_netpoll,
3229 #endif
3230 };
3231
3232 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3233         .ndo_open                = mlx5e_open,
3234         .ndo_stop                = mlx5e_close,
3235         .ndo_start_xmit          = mlx5e_xmit,
3236         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3237         .ndo_select_queue        = mlx5e_select_queue,
3238         .ndo_get_stats64         = mlx5e_get_stats,
3239         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3240         .ndo_set_mac_address     = mlx5e_set_mac,
3241         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3242         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3243         .ndo_set_features        = mlx5e_set_features,
3244         .ndo_change_mtu          = mlx5e_change_mtu,
3245         .ndo_do_ioctl            = mlx5e_ioctl,
3246         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
3247         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
3248         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3249         .ndo_features_check      = mlx5e_features_check,
3250 #ifdef CONFIG_RFS_ACCEL
3251         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3252 #endif
3253         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
3254         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
3255         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
3256         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
3257         .ndo_get_vf_config       = mlx5e_get_vf_config,
3258         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
3259         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
3260         .ndo_tx_timeout          = mlx5e_tx_timeout,
3261         .ndo_xdp                 = mlx5e_xdp,
3262 #ifdef CONFIG_NET_POLL_CONTROLLER
3263         .ndo_poll_controller     = mlx5e_netpoll,
3264 #endif
3265 };
3266
3267 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3268 {
3269         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3270                 return -ENOTSUPP;
3271         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3272             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3273             !MLX5_CAP_ETH(mdev, csum_cap) ||
3274             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3275             !MLX5_CAP_ETH(mdev, vlan_cap) ||
3276             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3277             MLX5_CAP_FLOWTABLE(mdev,
3278                                flow_table_properties_nic_receive.max_ft_level)
3279                                < 3) {
3280                 mlx5_core_warn(mdev,
3281                                "Not creating net device, some required device capabilities are missing\n");
3282                 return -ENOTSUPP;
3283         }
3284         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3285                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3286         if (!MLX5_CAP_GEN(mdev, cq_moderation))
3287                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3288
3289         return 0;
3290 }
3291
3292 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3293 {
3294         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3295
3296         return bf_buf_size -
3297                sizeof(struct mlx5e_tx_wqe) +
3298                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3299 }
3300
3301 #ifdef CONFIG_MLX5_CORE_EN_DCB
3302 static void mlx5e_ets_init(struct mlx5e_priv *priv)
3303 {
3304         int i;
3305
3306         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
3307         for (i = 0; i < priv->params.ets.ets_cap; i++) {
3308                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
3309                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
3310                 priv->params.ets.prio_tc[i] = i;
3311         }
3312
3313         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
3314         priv->params.ets.prio_tc[0] = 1;
3315         priv->params.ets.prio_tc[1] = 0;
3316 }
3317 #endif
3318
3319 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3320                                    u32 *indirection_rqt, int len,
3321                                    int num_channels)
3322 {
3323         int node = mdev->priv.numa_node;
3324         int node_num_of_cores;
3325         int i;
3326
3327         if (node == -1)
3328                 node = first_online_node;
3329
3330         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3331
3332         if (node_num_of_cores)
3333                 num_channels = min_t(int, num_channels, node_num_of_cores);
3334
3335         for (i = 0; i < len; i++)
3336                 indirection_rqt[i] = i % num_channels;
3337 }
3338
3339 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3340 {
3341         enum pcie_link_width width;
3342         enum pci_bus_speed speed;
3343         int err = 0;
3344
3345         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3346         if (err)
3347                 return err;
3348
3349         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3350                 return -EINVAL;
3351
3352         switch (speed) {
3353         case PCIE_SPEED_2_5GT:
3354                 *pci_bw = 2500 * width;
3355                 break;
3356         case PCIE_SPEED_5_0GT:
3357                 *pci_bw = 5000 * width;
3358                 break;
3359         case PCIE_SPEED_8_0GT:
3360                 *pci_bw = 8000 * width;
3361                 break;
3362         default:
3363                 return -EINVAL;
3364         }
3365
3366         return 0;
3367 }
3368
3369 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3370 {
3371         return (link_speed && pci_bw &&
3372                 (pci_bw < 40000) && (pci_bw < link_speed));
3373 }
3374
3375 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3376 {
3377         params->rx_cq_period_mode = cq_period_mode;
3378
3379         params->rx_cq_moderation.pkts =
3380                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3381         params->rx_cq_moderation.usec =
3382                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3383
3384         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3385                 params->rx_cq_moderation.usec =
3386                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3387 }
3388
3389 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3390                                    u8 *min_inline_mode)
3391 {
3392         switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
3393         case MLX5E_INLINE_MODE_L2:
3394                 *min_inline_mode = MLX5_INLINE_MODE_L2;
3395                 break;
3396         case MLX5E_INLINE_MODE_VPORT_CONTEXT:
3397                 mlx5_query_nic_vport_min_inline(mdev,
3398                                                 min_inline_mode);
3399                 break;
3400         case MLX5_INLINE_MODE_NOT_REQUIRED:
3401                 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3402                 break;
3403         }
3404 }
3405
3406 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3407 {
3408         int i;
3409
3410         /* The supported periods are organized in ascending order */
3411         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3412                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3413                         break;
3414
3415         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3416 }
3417
3418 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3419                                         struct net_device *netdev,
3420                                         const struct mlx5e_profile *profile,
3421                                         void *ppriv)
3422 {
3423         struct mlx5e_priv *priv = netdev_priv(netdev);
3424         u32 link_speed = 0;
3425         u32 pci_bw = 0;
3426         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3427                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3428                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3429
3430         priv->mdev                         = mdev;
3431         priv->netdev                       = netdev;
3432         priv->params.num_channels          = profile->max_nch(mdev);
3433         priv->profile                      = profile;
3434         priv->ppriv                        = ppriv;
3435
3436         priv->params.lro_timeout =
3437                 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3438
3439         priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3440
3441         /* set CQE compression */
3442         priv->params.rx_cqe_compress_admin = false;
3443         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3444             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3445                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3446                 mlx5e_get_pci_bw(mdev, &pci_bw);
3447                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3448                               link_speed, pci_bw);
3449                 priv->params.rx_cqe_compress_admin =
3450                         cqe_compress_heuristic(link_speed, pci_bw);
3451         }
3452         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3453
3454         mlx5e_set_rq_priv_params(priv);
3455         if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3456                 priv->params.lro_en = true;
3457
3458         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3459         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3460
3461         priv->params.tx_cq_moderation.usec =
3462                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3463         priv->params.tx_cq_moderation.pkts =
3464                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3465         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3466         mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3467         priv->params.num_tc                = 1;
3468         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3469
3470         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3471                             sizeof(priv->params.toeplitz_hash_key));
3472
3473         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3474                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3475
3476         priv->params.lro_wqe_sz =
3477                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3478                 /* Extra room needed for build_skb */
3479                 MLX5_RX_HEADROOM -
3480                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3481
3482         /* Initialize pflags */
3483         MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3484                             priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3485
3486 #ifdef CONFIG_MLX5_CORE_EN_DCB
3487         mlx5e_ets_init(priv);
3488 #endif
3489
3490         mutex_init(&priv->state_lock);
3491
3492         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3493         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3494         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3495         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3496 }
3497
3498 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3499 {
3500         struct mlx5e_priv *priv = netdev_priv(netdev);
3501
3502         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3503         if (is_zero_ether_addr(netdev->dev_addr) &&
3504             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3505                 eth_hw_addr_random(netdev);
3506                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3507         }
3508 }
3509
3510 static const struct switchdev_ops mlx5e_switchdev_ops = {
3511         .switchdev_port_attr_get        = mlx5e_attr_get,
3512 };
3513
3514 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3515 {
3516         struct mlx5e_priv *priv = netdev_priv(netdev);
3517         struct mlx5_core_dev *mdev = priv->mdev;
3518         bool fcs_supported;
3519         bool fcs_enabled;
3520
3521         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3522
3523         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3524                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3525 #ifdef CONFIG_MLX5_CORE_EN_DCB
3526                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3527 #endif
3528         } else {
3529                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3530         }
3531
3532         netdev->watchdog_timeo    = 15 * HZ;
3533
3534         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3535
3536         netdev->vlan_features    |= NETIF_F_SG;
3537         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3538         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3539         netdev->vlan_features    |= NETIF_F_GRO;
3540         netdev->vlan_features    |= NETIF_F_TSO;
3541         netdev->vlan_features    |= NETIF_F_TSO6;
3542         netdev->vlan_features    |= NETIF_F_RXCSUM;
3543         netdev->vlan_features    |= NETIF_F_RXHASH;
3544
3545         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3546                 netdev->vlan_features    |= NETIF_F_LRO;
3547
3548         netdev->hw_features       = netdev->vlan_features;
3549         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3550         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3551         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3552
3553         if (mlx5e_vxlan_allowed(mdev)) {
3554                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3555                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3556                                            NETIF_F_GSO_PARTIAL;
3557                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3558                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3559                 netdev->hw_enc_features |= NETIF_F_TSO;
3560                 netdev->hw_enc_features |= NETIF_F_TSO6;
3561                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3562                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3563                                            NETIF_F_GSO_PARTIAL;
3564                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3565         }
3566
3567         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3568
3569         if (fcs_supported)
3570                 netdev->hw_features |= NETIF_F_RXALL;
3571
3572         netdev->features          = netdev->hw_features;
3573         if (!priv->params.lro_en)
3574                 netdev->features  &= ~NETIF_F_LRO;
3575
3576         if (fcs_enabled)
3577                 netdev->features  &= ~NETIF_F_RXALL;
3578
3579 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3580         if (FT_CAP(flow_modify_en) &&
3581             FT_CAP(modify_root) &&
3582             FT_CAP(identified_miss_table_mode) &&
3583             FT_CAP(flow_table_modify)) {
3584                 netdev->hw_features      |= NETIF_F_HW_TC;
3585 #ifdef CONFIG_RFS_ACCEL
3586                 netdev->hw_features      |= NETIF_F_NTUPLE;
3587 #endif
3588         }
3589
3590         netdev->features         |= NETIF_F_HIGHDMA;
3591
3592         netdev->priv_flags       |= IFF_UNICAST_FLT;
3593
3594         mlx5e_set_netdev_dev_addr(netdev);
3595
3596 #ifdef CONFIG_NET_SWITCHDEV
3597         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3598                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3599 #endif
3600 }
3601
3602 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3603 {
3604         struct mlx5_core_dev *mdev = priv->mdev;
3605         int err;
3606
3607         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3608         if (err) {
3609                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3610                 priv->q_counter = 0;
3611         }
3612 }
3613
3614 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3615 {
3616         if (!priv->q_counter)
3617                 return;
3618
3619         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3620 }
3621
3622 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3623 {
3624         struct mlx5_core_dev *mdev = priv->mdev;
3625         u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3626                                          BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
3627         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3628         void *mkc;
3629         u32 *in;
3630         int err;
3631
3632         in = mlx5_vzalloc(inlen);
3633         if (!in)
3634                 return -ENOMEM;
3635
3636         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3637
3638         npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3639
3640         MLX5_SET(mkc, mkc, free, 1);
3641         MLX5_SET(mkc, mkc, umr_en, 1);
3642         MLX5_SET(mkc, mkc, lw, 1);
3643         MLX5_SET(mkc, mkc, lr, 1);
3644         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
3645
3646         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3647         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3648         MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3649         MLX5_SET(mkc, mkc, translations_octword_size,
3650                  MLX5_MTT_OCTW(npages));
3651         MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
3652
3653         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
3654
3655         kvfree(in);
3656         return err;
3657 }
3658
3659 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3660                            struct net_device *netdev,
3661                            const struct mlx5e_profile *profile,
3662                            void *ppriv)
3663 {
3664         struct mlx5e_priv *priv = netdev_priv(netdev);
3665
3666         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3667         mlx5e_build_nic_netdev(netdev);
3668         mlx5e_vxlan_init(priv);
3669 }
3670
3671 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3672 {
3673         struct mlx5_core_dev *mdev = priv->mdev;
3674         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3675
3676         mlx5e_vxlan_cleanup(priv);
3677
3678         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3679                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3680 }
3681
3682 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3683 {
3684         struct mlx5_core_dev *mdev = priv->mdev;
3685         int err;
3686         int i;
3687
3688         err = mlx5e_create_indirect_rqts(priv);
3689         if (err) {
3690                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3691                 return err;
3692         }
3693
3694         err = mlx5e_create_direct_rqts(priv);
3695         if (err) {
3696                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3697                 goto err_destroy_indirect_rqts;
3698         }
3699
3700         err = mlx5e_create_indirect_tirs(priv);
3701         if (err) {
3702                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3703                 goto err_destroy_direct_rqts;
3704         }
3705
3706         err = mlx5e_create_direct_tirs(priv);
3707         if (err) {
3708                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3709                 goto err_destroy_indirect_tirs;
3710         }
3711
3712         err = mlx5e_create_flow_steering(priv);
3713         if (err) {
3714                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3715                 goto err_destroy_direct_tirs;
3716         }
3717
3718         err = mlx5e_tc_init(priv);
3719         if (err)
3720                 goto err_destroy_flow_steering;
3721
3722         return 0;
3723
3724 err_destroy_flow_steering:
3725         mlx5e_destroy_flow_steering(priv);
3726 err_destroy_direct_tirs:
3727         mlx5e_destroy_direct_tirs(priv);
3728 err_destroy_indirect_tirs:
3729         mlx5e_destroy_indirect_tirs(priv);
3730 err_destroy_direct_rqts:
3731         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3732                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3733 err_destroy_indirect_rqts:
3734         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3735         return err;
3736 }
3737
3738 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3739 {
3740         int i;
3741
3742         mlx5e_tc_cleanup(priv);
3743         mlx5e_destroy_flow_steering(priv);
3744         mlx5e_destroy_direct_tirs(priv);
3745         mlx5e_destroy_indirect_tirs(priv);
3746         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3747                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3748         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3749 }
3750
3751 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3752 {
3753         int err;
3754
3755         err = mlx5e_create_tises(priv);
3756         if (err) {
3757                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3758                 return err;
3759         }
3760
3761 #ifdef CONFIG_MLX5_CORE_EN_DCB
3762         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3763 #endif
3764         return 0;
3765 }
3766
3767 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3768 {
3769         struct net_device *netdev = priv->netdev;
3770         struct mlx5_core_dev *mdev = priv->mdev;
3771         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3772         struct mlx5_eswitch_rep rep;
3773
3774         mlx5_lag_add(mdev, netdev);
3775
3776         if (mlx5e_vxlan_allowed(mdev)) {
3777                 rtnl_lock();
3778                 udp_tunnel_get_rx_info(netdev);
3779                 rtnl_unlock();
3780         }
3781
3782         mlx5e_enable_async_events(priv);
3783         queue_work(priv->wq, &priv->set_rx_mode_work);
3784
3785         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3786                 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3787                 rep.load = mlx5e_nic_rep_load;
3788                 rep.unload = mlx5e_nic_rep_unload;
3789                 rep.vport = FDB_UPLINK_VPORT;
3790                 rep.priv_data = priv;
3791                 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
3792         }
3793 }
3794
3795 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3796 {
3797         queue_work(priv->wq, &priv->set_rx_mode_work);
3798         mlx5e_disable_async_events(priv);
3799         mlx5_lag_remove(priv->mdev);
3800 }
3801
3802 static const struct mlx5e_profile mlx5e_nic_profile = {
3803         .init              = mlx5e_nic_init,
3804         .cleanup           = mlx5e_nic_cleanup,
3805         .init_rx           = mlx5e_init_nic_rx,
3806         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3807         .init_tx           = mlx5e_init_nic_tx,
3808         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3809         .enable            = mlx5e_nic_enable,
3810         .disable           = mlx5e_nic_disable,
3811         .update_stats      = mlx5e_update_stats,
3812         .max_nch           = mlx5e_get_max_num_channels,
3813         .max_tc            = MLX5E_MAX_NUM_TC,
3814 };
3815
3816 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3817                                        const struct mlx5e_profile *profile,
3818                                        void *ppriv)
3819 {
3820         int nch = profile->max_nch(mdev);
3821         struct net_device *netdev;
3822         struct mlx5e_priv *priv;
3823
3824         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3825                                     nch * profile->max_tc,
3826                                     nch);
3827         if (!netdev) {
3828                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3829                 return NULL;
3830         }
3831
3832         profile->init(mdev, netdev, profile, ppriv);
3833
3834         netif_carrier_off(netdev);
3835
3836         priv = netdev_priv(netdev);
3837
3838         priv->wq = create_singlethread_workqueue("mlx5e");
3839         if (!priv->wq)
3840                 goto err_cleanup_nic;
3841
3842         return netdev;
3843
3844 err_cleanup_nic:
3845         profile->cleanup(priv);
3846         free_netdev(netdev);
3847
3848         return NULL;
3849 }
3850
3851 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3852 {
3853         const struct mlx5e_profile *profile;
3854         struct mlx5e_priv *priv;
3855         int err;
3856
3857         priv = netdev_priv(netdev);
3858         profile = priv->profile;
3859         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
3860
3861         err = mlx5e_create_umr_mkey(priv);
3862         if (err) {
3863                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3864                 goto out;
3865         }
3866
3867         err = profile->init_tx(priv);
3868         if (err)
3869                 goto err_destroy_umr_mkey;
3870
3871         err = mlx5e_open_drop_rq(priv);
3872         if (err) {
3873                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3874                 goto err_cleanup_tx;
3875         }
3876
3877         err = profile->init_rx(priv);
3878         if (err)
3879                 goto err_close_drop_rq;
3880
3881         mlx5e_create_q_counter(priv);
3882
3883         mlx5e_init_l2_addr(priv);
3884
3885         mlx5e_set_dev_port_mtu(netdev);
3886
3887         if (profile->enable)
3888                 profile->enable(priv);
3889
3890         rtnl_lock();
3891         if (netif_running(netdev))
3892                 mlx5e_open(netdev);
3893         netif_device_attach(netdev);
3894         rtnl_unlock();
3895
3896         return 0;
3897
3898 err_close_drop_rq:
3899         mlx5e_close_drop_rq(priv);
3900
3901 err_cleanup_tx:
3902         profile->cleanup_tx(priv);
3903
3904 err_destroy_umr_mkey:
3905         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3906
3907 out:
3908         return err;
3909 }
3910
3911 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3912 {
3913         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3914         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3915         int vport;
3916         u8 mac[ETH_ALEN];
3917
3918         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3919                 return;
3920
3921         mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3922
3923         for (vport = 1; vport < total_vfs; vport++) {
3924                 struct mlx5_eswitch_rep rep;
3925
3926                 rep.load = mlx5e_vport_rep_load;
3927                 rep.unload = mlx5e_vport_rep_unload;
3928                 rep.vport = vport;
3929                 ether_addr_copy(rep.hw_id, mac);
3930                 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
3931         }
3932 }
3933
3934 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3935 {
3936         struct mlx5e_priv *priv = netdev_priv(netdev);
3937         const struct mlx5e_profile *profile = priv->profile;
3938
3939         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3940         if (profile->disable)
3941                 profile->disable(priv);
3942
3943         flush_workqueue(priv->wq);
3944
3945         rtnl_lock();
3946         if (netif_running(netdev))
3947                 mlx5e_close(netdev);
3948         netif_device_detach(netdev);
3949         rtnl_unlock();
3950
3951         mlx5e_destroy_q_counter(priv);
3952         profile->cleanup_rx(priv);
3953         mlx5e_close_drop_rq(priv);
3954         profile->cleanup_tx(priv);
3955         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3956         cancel_delayed_work_sync(&priv->update_stats_work);
3957 }
3958
3959 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3960  * hardware contexts and to connect it to the current netdev.
3961  */
3962 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3963 {
3964         struct mlx5e_priv *priv = vpriv;
3965         struct net_device *netdev = priv->netdev;
3966         int err;
3967
3968         if (netif_device_present(netdev))
3969                 return 0;
3970
3971         err = mlx5e_create_mdev_resources(mdev);
3972         if (err)
3973                 return err;
3974
3975         err = mlx5e_attach_netdev(mdev, netdev);
3976         if (err) {
3977                 mlx5e_destroy_mdev_resources(mdev);
3978                 return err;
3979         }
3980
3981         return 0;
3982 }
3983
3984 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
3985 {
3986         struct mlx5e_priv *priv = vpriv;
3987         struct net_device *netdev = priv->netdev;
3988
3989         if (!netif_device_present(netdev))
3990                 return;
3991
3992         mlx5e_detach_netdev(mdev, netdev);
3993         mlx5e_destroy_mdev_resources(mdev);
3994 }
3995
3996 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3997 {
3998         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3999         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4000         void *ppriv = NULL;
4001         void *priv;
4002         int vport;
4003         int err;
4004         struct net_device *netdev;
4005
4006         err = mlx5e_check_required_hca_cap(mdev);
4007         if (err)
4008                 return NULL;
4009
4010         mlx5e_register_vport_rep(mdev);
4011
4012         if (MLX5_CAP_GEN(mdev, vport_group_manager))
4013                 ppriv = &esw->offloads.vport_reps[0];
4014
4015         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4016         if (!netdev) {
4017                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4018                 goto err_unregister_reps;
4019         }
4020
4021         priv = netdev_priv(netdev);
4022
4023         err = mlx5e_attach(mdev, priv);
4024         if (err) {
4025                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4026                 goto err_destroy_netdev;
4027         }
4028
4029         err = register_netdev(netdev);
4030         if (err) {
4031                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4032                 goto err_detach;
4033         }
4034
4035         return priv;
4036
4037 err_detach:
4038         mlx5e_detach(mdev, priv);
4039
4040 err_destroy_netdev:
4041         mlx5e_destroy_netdev(mdev, priv);
4042
4043 err_unregister_reps:
4044         for (vport = 1; vport < total_vfs; vport++)
4045                 mlx5_eswitch_unregister_vport_rep(esw, vport);
4046
4047         return NULL;
4048 }
4049
4050 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
4051 {
4052         const struct mlx5e_profile *profile = priv->profile;
4053         struct net_device *netdev = priv->netdev;
4054
4055         destroy_workqueue(priv->wq);
4056         if (profile->cleanup)
4057                 profile->cleanup(priv);
4058         free_netdev(netdev);
4059 }
4060
4061 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4062 {
4063         struct mlx5_eswitch *esw = mdev->priv.eswitch;
4064         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4065         struct mlx5e_priv *priv = vpriv;
4066         int vport;
4067
4068         for (vport = 1; vport < total_vfs; vport++)
4069                 mlx5_eswitch_unregister_vport_rep(esw, vport);
4070
4071         unregister_netdev(priv->netdev);
4072         mlx5e_detach(mdev, vpriv);
4073         mlx5e_destroy_netdev(mdev, priv);
4074 }
4075
4076 static void *mlx5e_get_netdev(void *vpriv)
4077 {
4078         struct mlx5e_priv *priv = vpriv;
4079
4080         return priv->netdev;
4081 }
4082
4083 static struct mlx5_interface mlx5e_interface = {
4084         .add       = mlx5e_add,
4085         .remove    = mlx5e_remove,
4086         .attach    = mlx5e_attach,
4087         .detach    = mlx5e_detach,
4088         .event     = mlx5e_async_event,
4089         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
4090         .get_dev   = mlx5e_get_netdev,
4091 };
4092
4093 void mlx5e_init(void)
4094 {
4095         mlx5e_build_ptys2ethtool_map();
4096         mlx5_register_interface(&mlx5e_interface);
4097 }
4098
4099 void mlx5e_cleanup(void)
4100 {
4101         mlx5_unregister_interface(&mlx5e_interface);
4102 }