drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <linux/crash_dump.h>
  35 #include <net/pkt_cls.h>
  36 #include <linux/mlx5/fs.h>
  37 #include <net/vxlan.h>
  38 #include <linux/bpf.h>
  39 #include "en.h"
  40 #include "en_tc.h"
  41 #include "eswitch.h"
  42 #include "vxlan.h"
  43
  44 struct mlx5e_rq_param {
  45         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  46         struct mlx5_wq_param    wq;
  47         bool                    am_enabled;
  48 };
  49
  50 struct mlx5e_sq_param {
  51         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  52         struct mlx5_wq_param       wq;
  53         u16                        max_inline;
  54         u8                         min_inline_mode;
  55         enum mlx5e_sq_type         type;
  56 };
  57
  58 struct mlx5e_cq_param {
  59         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  60         struct mlx5_wq_param       wq;
  61         u16                        eq_ix;
  62         u8                         cq_period_mode;
  63 };
  64
  65 struct mlx5e_channel_param {
  66         struct mlx5e_rq_param      rq;
  67         struct mlx5e_sq_param      sq;
  68         struct mlx5e_sq_param      xdp_sq;
  69         struct mlx5e_sq_param      icosq;
  70         struct mlx5e_cq_param      rx_cq;
  71         struct mlx5e_cq_param      tx_cq;
  72         struct mlx5e_cq_param      icosq_cq;
  73 };
  74
  75 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  76 {
  77         return MLX5_CAP_GEN(mdev, striding_rq) &&
  78                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  79                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  80 }
  81
  82 static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
  83 {
  84         priv->params.rq_wq_type = rq_type;
  85         switch (priv->params.rq_wq_type) {
  86         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
  87                 priv->params.log_rq_size = is_kdump_kernel() ?
  88                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
  89                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
  90                 priv->params.mpwqe_log_stride_sz =
  91                         MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
  92                         MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(priv->mdev) :
  93                         MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(priv->mdev);
  94                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
  95                         priv->params.mpwqe_log_stride_sz;
  96                 break;
  97         default: /* MLX5_WQ_TYPE_LINKED_LIST */
  98                 priv->params.log_rq_size = is_kdump_kernel() ?
  99                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 100                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 101         }
 102         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
 103                                                BIT(priv->params.log_rq_size));
 104
 105         mlx5_core_info(priv->mdev,
 106                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 107                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 108                        BIT(priv->params.log_rq_size),
 109                        BIT(priv->params.mpwqe_log_stride_sz),
 110                        MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS));
 111 }
 112
 113 static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
 114 {
 115         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
 116                     !priv->xdp_prog ?
 117                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 118                     MLX5_WQ_TYPE_LINKED_LIST;
 119         mlx5e_set_rq_type_params(priv, rq_type);
 120 }
 121
 122 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 123 {
 124         struct mlx5_core_dev *mdev = priv->mdev;
 125         u8 port_state;
 126
 127         port_state = mlx5_query_vport_state(mdev,
 128                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 129
 130         if (port_state == VPORT_STATE_UP) {
 131                 netdev_info(priv->netdev, "Link up\n");
 132                 netif_carrier_on(priv->netdev);
 133         } else {
 134                 netdev_info(priv->netdev, "Link down\n");
 135                 netif_carrier_off(priv->netdev);
 136         }
 137 }
 138
 139 static void mlx5e_update_carrier_work(struct work_struct *work)
 140 {
 141         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 142                                                update_carrier_work);
 143
 144         mutex_lock(&priv->state_lock);
 145         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 146                 mlx5e_update_carrier(priv);
 147         mutex_unlock(&priv->state_lock);
 148 }
 149
 150 static void mlx5e_tx_timeout_work(struct work_struct *work)
 151 {
 152         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 153                                                tx_timeout_work);
 154         int err;
 155
 156         rtnl_lock();
 157         mutex_lock(&priv->state_lock);
 158         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 159                 goto unlock;
 160         mlx5e_close_locked(priv->netdev);
 161         err = mlx5e_open_locked(priv->netdev);
 162         if (err)
 163                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 164                            err);
 165 unlock:
 166         mutex_unlock(&priv->state_lock);
 167         rtnl_unlock();
 168 }
 169
 170 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 171 {
 172         struct mlx5e_sw_stats *s = &priv->stats.sw;
 173         struct mlx5e_rq_stats *rq_stats;
 174         struct mlx5e_sq_stats *sq_stats;
 175         u64 tx_offload_none = 0;
 176         int i, j;
 177
 178         memset(s, 0, sizeof(*s));
 179         for (i = 0; i < priv->params.num_channels; i++) {
 180                 rq_stats = &priv->channel[i]->rq.stats;
 181
 182                 s->rx_packets   += rq_stats->packets;
 183                 s->rx_bytes     += rq_stats->bytes;
 184                 s->rx_lro_packets += rq_stats->lro_packets;
 185                 s->rx_lro_bytes += rq_stats->lro_bytes;
 186                 s->rx_csum_none += rq_stats->csum_none;
 187                 s->rx_csum_complete += rq_stats->csum_complete;
 188                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 189                 s->rx_xdp_drop += rq_stats->xdp_drop;
 190                 s->rx_xdp_tx += rq_stats->xdp_tx;
 191                 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
 192                 s->rx_wqe_err   += rq_stats->wqe_err;
 193                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 194                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 195                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 196                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 197                 s->rx_cache_reuse += rq_stats->cache_reuse;
 198                 s->rx_cache_full  += rq_stats->cache_full;
 199                 s->rx_cache_empty += rq_stats->cache_empty;
 200                 s->rx_cache_busy  += rq_stats->cache_busy;
 201
 202                 for (j = 0; j < priv->params.num_tc; j++) {
 203                         sq_stats = &priv->channel[i]->sq[j].stats;
 204
 205                         s->tx_packets           += sq_stats->packets;
 206                         s->tx_bytes             += sq_stats->bytes;
 207                         s->tx_tso_packets       += sq_stats->tso_packets;
 208                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 209                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 210                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 211                         s->tx_queue_stopped     += sq_stats->stopped;
 212                         s->tx_queue_wake        += sq_stats->wake;
 213                         s->tx_queue_dropped     += sq_stats->dropped;
 214                         s->tx_xmit_more         += sq_stats->xmit_more;
 215                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 216                         tx_offload_none         += sq_stats->csum_none;
 217                 }
 218         }
 219
 220         /* Update calculated offload counters */
 221         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 222         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 223
 224         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 225                                 priv->stats.pport.phy_counters,
 226                                 counter_set.phys_layer_cntrs.link_down_events);
 227 }
 228
 229 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 230 {
 231         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 232         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 233         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 234         struct mlx5_core_dev *mdev = priv->mdev;
 235
 236         MLX5_SET(query_vport_counter_in, in, opcode,
 237                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 238         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 239         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 240
 241         memset(out, 0, outlen);
 242         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 243 }
 244
 245 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 246 {
 247         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 248         struct mlx5_core_dev *mdev = priv->mdev;
 249         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 250         int prio;
 251         void *out;
 252         u32 *in;
 253
 254         in = mlx5_vzalloc(sz);
 255         if (!in)
 256                 goto free_out;
 257
 258         MLX5_SET(ppcnt_reg, in, local_port, 1);
 259
 260         out = pstats->IEEE_802_3_counters;
 261         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 262         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 263
 264         out = pstats->RFC_2863_counters;
 265         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 266         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 267
 268         out = pstats->RFC_2819_counters;
 269         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 270         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 271
 272         out = pstats->phy_counters;
 273         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 274         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 275
 276         if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
 277                 out = pstats->phy_statistical_counters;
 278                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
 279                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 280         }
 281
 282         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 283         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 284                 out = pstats->per_prio_counters[prio];
 285                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 286                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 287                                      MLX5_REG_PPCNT, 0, 0);
 288         }
 289
 290 free_out:
 291         kvfree(in);
 292 }
 293
 294 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 295 {
 296         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 297
 298         if (!priv->q_counter)
 299                 return;
 300
 301         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 302                                       &qcnt->rx_out_of_buffer);
 303 }
 304
 305 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 306 {
 307         struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
 308         struct mlx5_core_dev *mdev = priv->mdev;
 309         int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 310         void *out;
 311         u32 *in;
 312
 313         if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
 314                 return;
 315
 316         in = mlx5_vzalloc(sz);
 317         if (!in)
 318                 return;
 319
 320         out = pcie_stats->pcie_perf_counters;
 321         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 322         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 323
 324         kvfree(in);
 325 }
 326
 327 void mlx5e_update_stats(struct mlx5e_priv *priv)
 328 {
 329         mlx5e_update_pcie_counters(priv);
 330         mlx5e_update_pport_counters(priv);
 331         mlx5e_update_vport_counters(priv);
 332         mlx5e_update_q_counter(priv);
 333         mlx5e_update_sw_counters(priv);
 334 }
 335
 336 void mlx5e_update_stats_work(struct work_struct *work)
 337 {
 338         struct delayed_work *dwork = to_delayed_work(work);
 339         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 340                                                update_stats_work);
 341         mutex_lock(&priv->state_lock);
 342         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 343                 priv->profile->update_stats(priv);
 344                 queue_delayed_work(priv->wq, dwork,
 345                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 346         }
 347         mutex_unlock(&priv->state_lock);
 348 }
 349
 350 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 351                               enum mlx5_dev_event event, unsigned long param)
 352 {
 353         struct mlx5e_priv *priv = vpriv;
 354         struct ptp_clock_event ptp_event;
 355         struct mlx5_eqe *eqe = NULL;
 356
 357         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 358                 return;
 359
 360         switch (event) {
 361         case MLX5_DEV_EVENT_PORT_UP:
 362         case MLX5_DEV_EVENT_PORT_DOWN:
 363                 queue_work(priv->wq, &priv->update_carrier_work);
 364                 break;
 365         case MLX5_DEV_EVENT_PPS:
 366                 eqe = (struct mlx5_eqe *)param;
 367                 ptp_event.type = PTP_CLOCK_EXTTS;
 368                 ptp_event.index = eqe->data.pps.pin;
 369                 ptp_event.timestamp =
 370                         timecounter_cyc2time(&priv->tstamp.clock,
 371                                              be64_to_cpu(eqe->data.pps.time_stamp));
 372                 mlx5e_pps_event_handler(vpriv, &ptp_event);
 373                 break;
 374         default:
 375                 break;
 376         }
 377 }
 378
 379 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 380 {
 381         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 382 }
 383
 384 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 385 {
 386         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 387         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 388 }
 389
 390 static inline int mlx5e_get_wqe_mtt_sz(void)
 391 {
 392         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 393          * To avoid copying garbage after the mtt array, we allocate
 394          * a little more.
 395          */
 396         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 397                      MLX5_UMR_MTT_ALIGNMENT);
 398 }
 399
 400 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
 401                                        struct mlx5e_umr_wqe *wqe, u16 ix)
 402 {
 403         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 404         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 405         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 406         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 407         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 408         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 409
 410         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 411                                       ds_cnt);
 412         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 413         cseg->imm       = rq->mkey_be;
 414
 415         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 416         ucseg->xlt_octowords =
 417                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 418         ucseg->bsf_octowords =
 419                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 420         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 421
 422         dseg->lkey = sq->mkey_be;
 423         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 424 }
 425
 426 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 427                                      struct mlx5e_channel *c)
 428 {
 429         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 430         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 431         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
 432         int i;
 433
 434         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 435                                       GFP_KERNEL, cpu_to_node(c->cpu));
 436         if (!rq->mpwqe.info)
 437                 goto err_out;
 438
 439         /* We allocate more than mtt_sz as we will align the pointer */
 440         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
 441                                         cpu_to_node(c->cpu));
 442         if (unlikely(!rq->mpwqe.mtt_no_align))
 443                 goto err_free_wqe_info;
 444
 445         for (i = 0; i < wq_sz; i++) {
 446                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 447
 448                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
 449                                         MLX5_UMR_ALIGN);
 450                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
 451                                                   PCI_DMA_TODEVICE);
 452                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
 453                         goto err_unmap_mtts;
 454
 455                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 456         }
 457
 458         return 0;
 459
 460 err_unmap_mtts:
 461         while (--i >= 0) {
 462                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 463
 464                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
 465                                  PCI_DMA_TODEVICE);
 466         }
 467         kfree(rq->mpwqe.mtt_no_align);
 468 err_free_wqe_info:
 469         kfree(rq->mpwqe.info);
 470
 471 err_out:
 472         return -ENOMEM;
 473 }
 474
 475 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
 476 {
 477         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 478         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 479         int i;
 480
 481         for (i = 0; i < wq_sz; i++) {
 482                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 483
 484                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
 485                                  PCI_DMA_TODEVICE);
 486         }
 487         kfree(rq->mpwqe.mtt_no_align);
 488         kfree(rq->mpwqe.info);
 489 }
 490
 491 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv,
 492                                  u64 npages, u8 page_shift,
 493                                  struct mlx5_core_mkey *umr_mkey)
 494 {
 495         struct mlx5_core_dev *mdev = priv->mdev;
 496         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 497         void *mkc;
 498         u32 *in;
 499         int err;
 500
 501         if (!MLX5E_VALID_NUM_MTTS(npages))
 502                 return -EINVAL;
 503
 504         in = mlx5_vzalloc(inlen);
 505         if (!in)
 506                 return -ENOMEM;
 507
 508         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 509
 510         MLX5_SET(mkc, mkc, free, 1);
 511         MLX5_SET(mkc, mkc, umr_en, 1);
 512         MLX5_SET(mkc, mkc, lw, 1);
 513         MLX5_SET(mkc, mkc, lr, 1);
 514         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
 515
 516         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 517         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 518         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 519         MLX5_SET(mkc, mkc, translations_octword_size,
 520                  MLX5_MTT_OCTW(npages));
 521         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 522
 523         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 524
 525         kvfree(in);
 526         return err;
 527 }
 528
 529 static int mlx5e_create_rq_umr_mkey(struct mlx5e_rq *rq)
 530 {
 531         struct mlx5e_priv *priv = rq->priv;
 532         u64 num_mtts = MLX5E_REQUIRED_MTTS(BIT(priv->params.log_rq_size));
 533
 534         return mlx5e_create_umr_mkey(priv, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 535 }
 536
 537 static int mlx5e_create_rq(struct mlx5e_channel *c,
 538                            struct mlx5e_rq_param *param,
 539                            struct mlx5e_rq *rq)
 540 {
 541         struct mlx5e_priv *priv = c->priv;
 542         struct mlx5_core_dev *mdev = priv->mdev;
 543         void *rqc = param->rqc;
 544         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 545         u32 byte_count;
 546         u32 frag_sz;
 547         int npages;
 548         int wq_sz;
 549         int err;
 550         int i;
 551
 552         param->wq.db_numa_node = cpu_to_node(c->cpu);
 553
 554         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 555                                 &rq->wq_ctrl);
 556         if (err)
 557                 return err;
 558
 559         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 560
 561         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 562
 563         rq->wq_type = priv->params.rq_wq_type;
 564         rq->pdev    = c->pdev;
 565         rq->netdev  = c->netdev;
 566         rq->tstamp  = &priv->tstamp;
 567         rq->channel = c;
 568         rq->ix      = c->ix;
 569         rq->priv    = c->priv;
 570
 571         rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
 572         if (IS_ERR(rq->xdp_prog)) {
 573                 err = PTR_ERR(rq->xdp_prog);
 574                 rq->xdp_prog = NULL;
 575                 goto err_rq_wq_destroy;
 576         }
 577
 578         if (rq->xdp_prog) {
 579                 rq->buff.map_dir = DMA_BIDIRECTIONAL;
 580                 rq->rx_headroom = XDP_PACKET_HEADROOM;
 581         } else {
 582                 rq->buff.map_dir = DMA_FROM_DEVICE;
 583                 rq->rx_headroom = MLX5_RX_HEADROOM;
 584         }
 585
 586         switch (priv->params.rq_wq_type) {
 587         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 588                 if (mlx5e_is_vf_vport_rep(priv)) {
 589                         err = -EINVAL;
 590                         goto err_rq_wq_destroy;
 591                 }
 592
 593                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 594                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 595                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 596
 597                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 598                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 599
 600                 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 601                 byte_count = rq->buff.wqe_sz;
 602
 603                 err = mlx5e_create_rq_umr_mkey(rq);
 604                 if (err)
 605                         goto err_rq_wq_destroy;
 606                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 607
 608                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 609                 if (err)
 610                         goto err_destroy_umr_mkey;
 611                 break;
 612         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 613                 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
 614                                             GFP_KERNEL, cpu_to_node(c->cpu));
 615                 if (!rq->dma_info) {
 616                         err = -ENOMEM;
 617                         goto err_rq_wq_destroy;
 618                 }
 619
 620                 if (mlx5e_is_vf_vport_rep(priv))
 621                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
 622                 else
 623                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 624
 625                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 626                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 627
 628                 rq->buff.wqe_sz = (priv->params.lro_en) ?
 629                                 priv->params.lro_wqe_sz :
 630                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 631                 byte_count = rq->buff.wqe_sz;
 632
 633                 /* calc the required page order */
 634                 frag_sz = rq->rx_headroom +
 635                           byte_count /* packet data */ +
 636                           SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 637                 frag_sz = SKB_DATA_ALIGN(frag_sz);
 638
 639                 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
 640                 rq->buff.page_order = order_base_2(npages);
 641
 642                 byte_count |= MLX5_HW_START_PADDING;
 643                 rq->mkey_be = c->mkey_be;
 644         }
 645
 646         for (i = 0; i < wq_sz; i++) {
 647                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 648
 649                 wqe->data.byte_count = cpu_to_be32(byte_count);
 650                 wqe->data.lkey = rq->mkey_be;
 651         }
 652
 653         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 654         rq->am.mode = priv->params.rx_cq_period_mode;
 655
 656         rq->page_cache.head = 0;
 657         rq->page_cache.tail = 0;
 658
 659         return 0;
 660
 661 err_destroy_umr_mkey:
 662         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 663
 664 err_rq_wq_destroy:
 665         if (rq->xdp_prog)
 666                 bpf_prog_put(rq->xdp_prog);
 667         mlx5_wq_destroy(&rq->wq_ctrl);
 668
 669         return err;
 670 }
 671
 672 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 673 {
 674         int i;
 675
 676         if (rq->xdp_prog)
 677                 bpf_prog_put(rq->xdp_prog);
 678
 679         switch (rq->wq_type) {
 680         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 681                 mlx5e_rq_free_mpwqe_info(rq);
 682                 mlx5_core_destroy_mkey(rq->priv->mdev, &rq->umr_mkey);
 683                 break;
 684         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 685                 kfree(rq->dma_info);
 686         }
 687
 688         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 689              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 690                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 691
 692                 mlx5e_page_release(rq, dma_info, false);
 693         }
 694         mlx5_wq_destroy(&rq->wq_ctrl);
 695 }
 696
 697 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 698 {
 699         struct mlx5e_priv *priv = rq->priv;
 700         struct mlx5_core_dev *mdev = priv->mdev;
 701
 702         void *in;
 703         void *rqc;
 704         void *wq;
 705         int inlen;
 706         int err;
 707
 708         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 709                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 710         in = mlx5_vzalloc(inlen);
 711         if (!in)
 712                 return -ENOMEM;
 713
 714         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 715         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 716
 717         memcpy(rqc, param->rqc, sizeof(param->rqc));
 718
 719         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 720         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 721         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 722         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 723                                                 MLX5_ADAPTER_PAGE_SHIFT);
 724         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 725
 726         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 727                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 728
 729         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 730
 731         kvfree(in);
 732
 733         return err;
 734 }
 735
 736 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 737                                  int next_state)
 738 {
 739         struct mlx5e_channel *c = rq->channel;
 740         struct mlx5e_priv *priv = c->priv;
 741         struct mlx5_core_dev *mdev = priv->mdev;
 742
 743         void *in;
 744         void *rqc;
 745         int inlen;
 746         int err;
 747
 748         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 749         in = mlx5_vzalloc(inlen);
 750         if (!in)
 751                 return -ENOMEM;
 752
 753         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 754
 755         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 756         MLX5_SET(rqc, rqc, state, next_state);
 757
 758         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 759
 760         kvfree(in);
 761
 762         return err;
 763 }
 764
 765 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 766 {
 767         struct mlx5e_channel *c = rq->channel;
 768         struct mlx5e_priv *priv = c->priv;
 769         struct mlx5_core_dev *mdev = priv->mdev;
 770
 771         void *in;
 772         void *rqc;
 773         int inlen;
 774         int err;
 775
 776         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 777         in = mlx5_vzalloc(inlen);
 778         if (!in)
 779                 return -ENOMEM;
 780
 781         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 782
 783         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 784         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 785                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 786         MLX5_SET(rqc, rqc, vsd, vsd);
 787         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 788
 789         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 790
 791         kvfree(in);
 792
 793         return err;
 794 }
 795
 796 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 797 {
 798         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 799 }
 800
 801 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 802 {
 803         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 804         struct mlx5e_channel *c = rq->channel;
 805         struct mlx5e_priv *priv = c->priv;
 806         struct mlx5_wq_ll *wq = &rq->wq;
 807
 808         while (time_before(jiffies, exp_time)) {
 809                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 810                         return 0;
 811
 812                 msleep(20);
 813         }
 814
 815         return -ETIMEDOUT;
 816 }
 817
 818 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 819 {
 820         struct mlx5_wq_ll *wq = &rq->wq;
 821         struct mlx5e_rx_wqe *wqe;
 822         __be16 wqe_ix_be;
 823         u16 wqe_ix;
 824
 825         /* UMR WQE (if in progress) is always at wq->head */
 826         if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 827                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 828
 829         while (!mlx5_wq_ll_is_empty(wq)) {
 830                 wqe_ix_be = *wq->tail_next;
 831                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 832                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 833                 rq->dealloc_wqe(rq, wqe_ix);
 834                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 835                                &wqe->next.next_wqe_index);
 836         }
 837 }
 838
 839 static int mlx5e_open_rq(struct mlx5e_channel *c,
 840                          struct mlx5e_rq_param *param,
 841                          struct mlx5e_rq *rq)
 842 {
 843         struct mlx5e_sq *sq = &c->icosq;
 844         u16 pi = sq->pc & sq->wq.sz_m1;
 845         int err;
 846
 847         err = mlx5e_create_rq(c, param, rq);
 848         if (err)
 849                 return err;
 850
 851         err = mlx5e_enable_rq(rq, param);
 852         if (err)
 853                 goto err_destroy_rq;
 854
 855         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 856         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 857         if (err)
 858                 goto err_disable_rq;
 859
 860         if (param->am_enabled)
 861                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 862
 863         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 864         sq->db.ico_wqe[pi].num_wqebbs = 1;
 865         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 866
 867         return 0;
 868
 869 err_disable_rq:
 870         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 871         mlx5e_disable_rq(rq);
 872 err_destroy_rq:
 873         mlx5e_destroy_rq(rq);
 874
 875         return err;
 876 }
 877
 878 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 879 {
 880         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 881         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 882         cancel_work_sync(&rq->am.work);
 883
 884         mlx5e_disable_rq(rq);
 885         mlx5e_free_rx_descs(rq);
 886         mlx5e_destroy_rq(rq);
 887 }
 888
 889 static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
 890 {
 891         kfree(sq->db.xdp.di);
 892         kfree(sq->db.xdp.wqe_info);
 893 }
 894
 895 static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
 896 {
 897         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 898
 899         sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
 900                                      GFP_KERNEL, numa);
 901         sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
 902                                            GFP_KERNEL, numa);
 903         if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
 904                 mlx5e_free_sq_xdp_db(sq);
 905                 return -ENOMEM;
 906         }
 907
 908         return 0;
 909 }
 910
 911 static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
 912 {
 913         kfree(sq->db.ico_wqe);
 914 }
 915
 916 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
 917 {
 918         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 919
 920         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 921                                       GFP_KERNEL, numa);
 922         if (!sq->db.ico_wqe)
 923                 return -ENOMEM;
 924
 925         return 0;
 926 }
 927
 928 static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
 929 {
 930         kfree(sq->db.txq.wqe_info);
 931         kfree(sq->db.txq.dma_fifo);
 932         kfree(sq->db.txq.skb);
 933 }
 934
 935 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
 936 {
 937         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 938         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 939
 940         sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
 941                                       GFP_KERNEL, numa);
 942         sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
 943                                            GFP_KERNEL, numa);
 944         sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
 945                                            GFP_KERNEL, numa);
 946         if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
 947                 mlx5e_free_sq_txq_db(sq);
 948                 return -ENOMEM;
 949         }
 950
 951         sq->dma_fifo_mask = df_sz - 1;
 952
 953         return 0;
 954 }
 955
 956 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 957 {
 958         switch (sq->type) {
 959         case MLX5E_SQ_TXQ:
 960                 mlx5e_free_sq_txq_db(sq);
 961                 break;
 962         case MLX5E_SQ_ICO:
 963                 mlx5e_free_sq_ico_db(sq);
 964                 break;
 965         case MLX5E_SQ_XDP:
 966                 mlx5e_free_sq_xdp_db(sq);
 967                 break;
 968         }
 969 }
 970
 971 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 972 {
 973         switch (sq->type) {
 974         case MLX5E_SQ_TXQ:
 975                 return mlx5e_alloc_sq_txq_db(sq, numa);
 976         case MLX5E_SQ_ICO:
 977                 return mlx5e_alloc_sq_ico_db(sq, numa);
 978         case MLX5E_SQ_XDP:
 979                 return mlx5e_alloc_sq_xdp_db(sq, numa);
 980         }
 981
 982         return 0;
 983 }
 984
 985 static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
 986 {
 987         switch (sq_type) {
 988         case MLX5E_SQ_ICO:
 989                 return MLX5E_ICOSQ_MAX_WQEBBS;
 990         case MLX5E_SQ_XDP:
 991                 return MLX5E_XDP_TX_WQEBBS;
 992         }
 993         return MLX5_SEND_WQE_MAX_WQEBBS;
 994 }
 995
 996 static int mlx5e_create_sq(struct mlx5e_channel *c,
 997                            int tc,
 998                            struct mlx5e_sq_param *param,
 999                            struct mlx5e_sq *sq)
1000 {
1001         struct mlx5e_priv *priv = c->priv;
1002         struct mlx5_core_dev *mdev = priv->mdev;
1003
1004         void *sqc = param->sqc;
1005         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1006         int err;
1007
1008         sq->type      = param->type;
1009         sq->pdev      = c->pdev;
1010         sq->tstamp    = &priv->tstamp;
1011         sq->mkey_be   = c->mkey_be;
1012         sq->channel   = c;
1013         sq->tc        = tc;
1014
1015         err = mlx5_alloc_bfreg(mdev, &sq->bfreg, MLX5_CAP_GEN(mdev, bf), false);
1016         if (err)
1017                 return err;
1018
1019         param->wq.db_numa_node = cpu_to_node(c->cpu);
1020
1021         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1022                                  &sq->wq_ctrl);
1023         if (err)
1024                 goto err_unmap_free_uar;
1025
1026         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
1027         if (sq->bfreg.wc)
1028                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
1029
1030         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1031         sq->max_inline  = param->max_inline;
1032         sq->min_inline_mode =
1033                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT ?
1034                 param->min_inline_mode : 0;
1035
1036         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
1037         if (err)
1038                 goto err_sq_wq_destroy;
1039
1040         if (sq->type == MLX5E_SQ_TXQ) {
1041                 int txq_ix;
1042
1043                 txq_ix = c->ix + tc * priv->params.num_channels;
1044                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
1045                 priv->txq_to_sq_map[txq_ix] = sq;
1046         }
1047
1048         sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
1049         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
1050
1051         return 0;
1052
1053 err_sq_wq_destroy:
1054         mlx5_wq_destroy(&sq->wq_ctrl);
1055
1056 err_unmap_free_uar:
1057         mlx5_free_bfreg(mdev, &sq->bfreg);
1058
1059         return err;
1060 }
1061
1062 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
1063 {
1064         struct mlx5e_channel *c = sq->channel;
1065         struct mlx5e_priv *priv = c->priv;
1066
1067         mlx5e_free_sq_db(sq);
1068         mlx5_wq_destroy(&sq->wq_ctrl);
1069         mlx5_free_bfreg(priv->mdev, &sq->bfreg);
1070 }
1071
1072 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1073 {
1074         struct mlx5e_channel *c = sq->channel;
1075         struct mlx5e_priv *priv = c->priv;
1076         struct mlx5_core_dev *mdev = priv->mdev;
1077
1078         void *in;
1079         void *sqc;
1080         void *wq;
1081         int inlen;
1082         int err;
1083
1084         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1085                 sizeof(u64) * sq->wq_ctrl.buf.npages;
1086         in = mlx5_vzalloc(inlen);
1087         if (!in)
1088                 return -ENOMEM;
1089
1090         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1091         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1092
1093         memcpy(sqc, param->sqc, sizeof(param->sqc));
1094
1095         MLX5_SET(sqc,  sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1096                                        0 : priv->tisn[sq->tc]);
1097         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
1098         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
1099         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
1100         MLX5_SET(sqc,  sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
1101
1102         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1103         MLX5_SET(wq,   wq, uar_page,      sq->bfreg.index);
1104         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
1105                                           MLX5_ADAPTER_PAGE_SHIFT);
1106         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
1107
1108         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1109                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1110
1111         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1112
1113         kvfree(in);
1114
1115         return err;
1116 }
1117
1118 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1119                            int next_state, bool update_rl, int rl_index)
1120 {
1121         struct mlx5e_channel *c = sq->channel;
1122         struct mlx5e_priv *priv = c->priv;
1123         struct mlx5_core_dev *mdev = priv->mdev;
1124
1125         void *in;
1126         void *sqc;
1127         int inlen;
1128         int err;
1129
1130         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1131         in = mlx5_vzalloc(inlen);
1132         if (!in)
1133                 return -ENOMEM;
1134
1135         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1136
1137         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1138         MLX5_SET(sqc, sqc, state, next_state);
1139         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1140                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1141                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
1142         }
1143
1144         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
1145
1146         kvfree(in);
1147
1148         return err;
1149 }
1150
1151 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1152 {
1153         struct mlx5e_channel *c = sq->channel;
1154         struct mlx5e_priv *priv = c->priv;
1155         struct mlx5_core_dev *mdev = priv->mdev;
1156
1157         mlx5_core_destroy_sq(mdev, sq->sqn);
1158         if (sq->rate_limit)
1159                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1160 }
1161
1162 static int mlx5e_open_sq(struct mlx5e_channel *c,
1163                          int tc,
1164                          struct mlx5e_sq_param *param,
1165                          struct mlx5e_sq *sq)
1166 {
1167         int err;
1168
1169         err = mlx5e_create_sq(c, tc, param, sq);
1170         if (err)
1171                 return err;
1172
1173         err = mlx5e_enable_sq(sq, param);
1174         if (err)
1175                 goto err_destroy_sq;
1176
1177         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1178         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1179                               false, 0);
1180         if (err)
1181                 goto err_disable_sq;
1182
1183         if (sq->txq) {
1184                 netdev_tx_reset_queue(sq->txq);
1185                 netif_tx_start_queue(sq->txq);
1186         }
1187
1188         return 0;
1189
1190 err_disable_sq:
1191         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1192         mlx5e_disable_sq(sq);
1193 err_destroy_sq:
1194         mlx5e_destroy_sq(sq);
1195
1196         return err;
1197 }
1198
1199 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1200 {
1201         __netif_tx_lock_bh(txq);
1202         netif_tx_stop_queue(txq);
1203         __netif_tx_unlock_bh(txq);
1204 }
1205
1206 static void mlx5e_close_sq(struct mlx5e_sq *sq)
1207 {
1208         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1209         /* prevent netif_tx_wake_queue */
1210         napi_synchronize(&sq->channel->napi);
1211
1212         if (sq->txq) {
1213                 netif_tx_disable_queue(sq->txq);
1214
1215                 /* last doorbell out, godspeed .. */
1216                 if (mlx5e_sq_has_room_for(sq, 1)) {
1217                         sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1218                         mlx5e_send_nop(sq, true);
1219                 }
1220         }
1221
1222         mlx5e_disable_sq(sq);
1223         mlx5e_free_sq_descs(sq);
1224         mlx5e_destroy_sq(sq);
1225 }
1226
1227 static int mlx5e_create_cq(struct mlx5e_channel *c,
1228                            struct mlx5e_cq_param *param,
1229                            struct mlx5e_cq *cq)
1230 {
1231         struct mlx5e_priv *priv = c->priv;
1232         struct mlx5_core_dev *mdev = priv->mdev;
1233         struct mlx5_core_cq *mcq = &cq->mcq;
1234         int eqn_not_used;
1235         unsigned int irqn;
1236         int err;
1237         u32 i;
1238
1239         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1240         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1241         param->eq_ix   = c->ix;
1242
1243         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1244                                &cq->wq_ctrl);
1245         if (err)
1246                 return err;
1247
1248         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1249
1250         cq->napi        = &c->napi;
1251
1252         mcq->cqe_sz     = 64;
1253         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1254         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1255         *mcq->set_ci_db = 0;
1256         *mcq->arm_db    = 0;
1257         mcq->vector     = param->eq_ix;
1258         mcq->comp       = mlx5e_completion_event;
1259         mcq->event      = mlx5e_cq_error_event;
1260         mcq->irqn       = irqn;
1261
1262         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1263                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1264
1265                 cqe->op_own = 0xf1;
1266         }
1267
1268         cq->channel = c;
1269         cq->priv = priv;
1270
1271         return 0;
1272 }
1273
1274 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1275 {
1276         mlx5_cqwq_destroy(&cq->wq_ctrl);
1277 }
1278
1279 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1280 {
1281         struct mlx5e_priv *priv = cq->priv;
1282         struct mlx5_core_dev *mdev = priv->mdev;
1283         struct mlx5_core_cq *mcq = &cq->mcq;
1284
1285         void *in;
1286         void *cqc;
1287         int inlen;
1288         unsigned int irqn_not_used;
1289         int eqn;
1290         int err;
1291
1292         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1293                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1294         in = mlx5_vzalloc(inlen);
1295         if (!in)
1296                 return -ENOMEM;
1297
1298         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1299
1300         memcpy(cqc, param->cqc, sizeof(param->cqc));
1301
1302         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1303                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1304
1305         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1306
1307         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1308         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1309         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1310         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1311                                             MLX5_ADAPTER_PAGE_SHIFT);
1312         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1313
1314         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1315
1316         kvfree(in);
1317
1318         if (err)
1319                 return err;
1320
1321         mlx5e_cq_arm(cq);
1322
1323         return 0;
1324 }
1325
1326 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1327 {
1328         struct mlx5e_priv *priv = cq->priv;
1329         struct mlx5_core_dev *mdev = priv->mdev;
1330
1331         mlx5_core_destroy_cq(mdev, &cq->mcq);
1332 }
1333
1334 static int mlx5e_open_cq(struct mlx5e_channel *c,
1335                          struct mlx5e_cq_param *param,
1336                          struct mlx5e_cq *cq,
1337                          struct mlx5e_cq_moder moderation)
1338 {
1339         int err;
1340         struct mlx5e_priv *priv = c->priv;
1341         struct mlx5_core_dev *mdev = priv->mdev;
1342
1343         err = mlx5e_create_cq(c, param, cq);
1344         if (err)
1345                 return err;
1346
1347         err = mlx5e_enable_cq(cq, param);
1348         if (err)
1349                 goto err_destroy_cq;
1350
1351         if (MLX5_CAP_GEN(mdev, cq_moderation))
1352                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1353                                                moderation.usec,
1354                                                moderation.pkts);
1355         return 0;
1356
1357 err_destroy_cq:
1358         mlx5e_destroy_cq(cq);
1359
1360         return err;
1361 }
1362
1363 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1364 {
1365         mlx5e_disable_cq(cq);
1366         mlx5e_destroy_cq(cq);
1367 }
1368
1369 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1370 {
1371         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1372 }
1373
1374 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1375                              struct mlx5e_channel_param *cparam)
1376 {
1377         struct mlx5e_priv *priv = c->priv;
1378         int err;
1379         int tc;
1380
1381         for (tc = 0; tc < c->num_tc; tc++) {
1382                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1383                                     priv->params.tx_cq_moderation);
1384                 if (err)
1385                         goto err_close_tx_cqs;
1386         }
1387
1388         return 0;
1389
1390 err_close_tx_cqs:
1391         for (tc--; tc >= 0; tc--)
1392                 mlx5e_close_cq(&c->sq[tc].cq);
1393
1394         return err;
1395 }
1396
1397 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1398 {
1399         int tc;
1400
1401         for (tc = 0; tc < c->num_tc; tc++)
1402                 mlx5e_close_cq(&c->sq[tc].cq);
1403 }
1404
1405 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1406                           struct mlx5e_channel_param *cparam)
1407 {
1408         int err;
1409         int tc;
1410
1411         for (tc = 0; tc < c->num_tc; tc++) {
1412                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1413                 if (err)
1414                         goto err_close_sqs;
1415         }
1416
1417         return 0;
1418
1419 err_close_sqs:
1420         for (tc--; tc >= 0; tc--)
1421                 mlx5e_close_sq(&c->sq[tc]);
1422
1423         return err;
1424 }
1425
1426 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1427 {
1428         int tc;
1429
1430         for (tc = 0; tc < c->num_tc; tc++)
1431                 mlx5e_close_sq(&c->sq[tc]);
1432 }
1433
1434 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1435 {
1436         int i;
1437
1438         for (i = 0; i < priv->profile->max_tc; i++)
1439                 priv->channeltc_to_txq_map[ix][i] =
1440                         ix + i * priv->params.num_channels;
1441 }
1442
1443 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1444                                 struct mlx5e_sq *sq, u32 rate)
1445 {
1446         struct mlx5e_priv *priv = netdev_priv(dev);
1447         struct mlx5_core_dev *mdev = priv->mdev;
1448         u16 rl_index = 0;
1449         int err;
1450
1451         if (rate == sq->rate_limit)
1452                 /* nothing to do */
1453                 return 0;
1454
1455         if (sq->rate_limit)
1456                 /* remove current rl index to free space to next ones */
1457                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1458
1459         sq->rate_limit = 0;
1460
1461         if (rate) {
1462                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1463                 if (err) {
1464                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1465                                    rate, err);
1466                         return err;
1467                 }
1468         }
1469
1470         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1471                               MLX5_SQC_STATE_RDY, true, rl_index);
1472         if (err) {
1473                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1474                            rate, err);
1475                 /* remove the rate from the table */
1476                 if (rate)
1477                         mlx5_rl_remove_rate(mdev, rate);
1478                 return err;
1479         }
1480
1481         sq->rate_limit = rate;
1482         return 0;
1483 }
1484
1485 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1486 {
1487         struct mlx5e_priv *priv = netdev_priv(dev);
1488         struct mlx5_core_dev *mdev = priv->mdev;
1489         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1490         int err = 0;
1491
1492         if (!mlx5_rl_is_supported(mdev)) {
1493                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1494                 return -EINVAL;
1495         }
1496
1497         /* rate is given in Mb/sec, HW config is in Kb/sec */
1498         rate = rate << 10;
1499
1500         /* Check whether rate in valid range, 0 is always valid */
1501         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1502                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1503                 return -ERANGE;
1504         }
1505
1506         mutex_lock(&priv->state_lock);
1507         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1508                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1509         if (!err)
1510                 priv->tx_rates[index] = rate;
1511         mutex_unlock(&priv->state_lock);
1512
1513         return err;
1514 }
1515
1516 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
1517 {
1518         return is_kdump_kernel() ?
1519                 MLX5E_MIN_NUM_CHANNELS :
1520                 min_t(int, mdev->priv.eq_table.num_comp_vectors,
1521                       MLX5E_MAX_NUM_CHANNELS);
1522 }
1523
1524 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1525                               struct mlx5e_channel_param *cparam,
1526                               struct mlx5e_channel **cp)
1527 {
1528         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1529         struct net_device *netdev = priv->netdev;
1530         struct mlx5e_cq_moder rx_cq_profile;
1531         int cpu = mlx5e_get_cpu(priv, ix);
1532         struct mlx5e_channel *c;
1533         struct mlx5e_sq *sq;
1534         int err;
1535         int i;
1536
1537         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1538         if (!c)
1539                 return -ENOMEM;
1540
1541         c->priv     = priv;
1542         c->ix       = ix;
1543         c->cpu      = cpu;
1544         c->pdev     = &priv->mdev->pdev->dev;
1545         c->netdev   = priv->netdev;
1546         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1547         c->num_tc   = priv->params.num_tc;
1548         c->xdp      = !!priv->xdp_prog;
1549
1550         if (priv->params.rx_am_enabled)
1551                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1552         else
1553                 rx_cq_profile = priv->params.rx_cq_moderation;
1554
1555         mlx5e_build_channeltc_to_txq_map(priv, ix);
1556
1557         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1558
1559         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1560         if (err)
1561                 goto err_napi_del;
1562
1563         err = mlx5e_open_tx_cqs(c, cparam);
1564         if (err)
1565                 goto err_close_icosq_cq;
1566
1567         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1568                             rx_cq_profile);
1569         if (err)
1570                 goto err_close_tx_cqs;
1571
1572         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1573         err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1574                                      priv->params.tx_cq_moderation) : 0;
1575         if (err)
1576                 goto err_close_rx_cq;
1577
1578         napi_enable(&c->napi);
1579
1580         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1581         if (err)
1582                 goto err_disable_napi;
1583
1584         err = mlx5e_open_sqs(c, cparam);
1585         if (err)
1586                 goto err_close_icosq;
1587
1588         for (i = 0; i < priv->params.num_tc; i++) {
1589                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1590
1591                 if (priv->tx_rates[txq_ix]) {
1592                         sq = priv->txq_to_sq_map[txq_ix];
1593                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1594                                              priv->tx_rates[txq_ix]);
1595                 }
1596         }
1597
1598         err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1599         if (err)
1600                 goto err_close_sqs;
1601
1602         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1603         if (err)
1604                 goto err_close_xdp_sq;
1605
1606         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1607         *cp = c;
1608
1609         return 0;
1610 err_close_xdp_sq:
1611         if (c->xdp)
1612                 mlx5e_close_sq(&c->xdp_sq);
1613
1614 err_close_sqs:
1615         mlx5e_close_sqs(c);
1616
1617 err_close_icosq:
1618         mlx5e_close_sq(&c->icosq);
1619
1620 err_disable_napi:
1621         napi_disable(&c->napi);
1622         if (c->xdp)
1623                 mlx5e_close_cq(&c->xdp_sq.cq);
1624
1625 err_close_rx_cq:
1626         mlx5e_close_cq(&c->rq.cq);
1627
1628 err_close_tx_cqs:
1629         mlx5e_close_tx_cqs(c);
1630
1631 err_close_icosq_cq:
1632         mlx5e_close_cq(&c->icosq.cq);
1633
1634 err_napi_del:
1635         netif_napi_del(&c->napi);
1636         kfree(c);
1637
1638         return err;
1639 }
1640
1641 static void mlx5e_close_channel(struct mlx5e_channel *c)
1642 {
1643         mlx5e_close_rq(&c->rq);
1644         if (c->xdp)
1645                 mlx5e_close_sq(&c->xdp_sq);
1646         mlx5e_close_sqs(c);
1647         mlx5e_close_sq(&c->icosq);
1648         napi_disable(&c->napi);
1649         if (c->xdp)
1650                 mlx5e_close_cq(&c->xdp_sq.cq);
1651         mlx5e_close_cq(&c->rq.cq);
1652         mlx5e_close_tx_cqs(c);
1653         mlx5e_close_cq(&c->icosq.cq);
1654         netif_napi_del(&c->napi);
1655
1656         kfree(c);
1657 }
1658
1659 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1660                                  struct mlx5e_rq_param *param)
1661 {
1662         void *rqc = param->rqc;
1663         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1664
1665         switch (priv->params.rq_wq_type) {
1666         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1667                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1668                          priv->params.mpwqe_log_num_strides - 9);
1669                 MLX5_SET(wq, wq, log_wqe_stride_size,
1670                          priv->params.mpwqe_log_stride_sz - 6);
1671                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1672                 break;
1673         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1674                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1675         }
1676
1677         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1678         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1679         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1680         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1681         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1682
1683         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1684         param->wq.linear = 1;
1685
1686         param->am_enabled = priv->params.rx_am_enabled;
1687 }
1688
1689 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1690 {
1691         void *rqc = param->rqc;
1692         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1693
1694         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1695         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1696 }
1697
1698 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1699                                         struct mlx5e_sq_param *param)
1700 {
1701         void *sqc = param->sqc;
1702         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1703
1704         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1705         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1706
1707         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1708 }
1709
1710 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1711                                  struct mlx5e_sq_param *param)
1712 {
1713         void *sqc = param->sqc;
1714         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1715
1716         mlx5e_build_sq_param_common(priv, param);
1717         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1718
1719         param->max_inline = priv->params.tx_max_inline;
1720         param->min_inline_mode = priv->params.tx_min_inline_mode;
1721         param->type = MLX5E_SQ_TXQ;
1722 }
1723
1724 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1725                                         struct mlx5e_cq_param *param)
1726 {
1727         void *cqc = param->cqc;
1728
1729         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1730 }
1731
1732 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1733                                     struct mlx5e_cq_param *param)
1734 {
1735         void *cqc = param->cqc;
1736         u8 log_cq_size;
1737
1738         switch (priv->params.rq_wq_type) {
1739         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1740                 log_cq_size = priv->params.log_rq_size +
1741                         priv->params.mpwqe_log_num_strides;
1742                 break;
1743         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1744                 log_cq_size = priv->params.log_rq_size;
1745         }
1746
1747         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1748         if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1749                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1750                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1751         }
1752
1753         mlx5e_build_common_cq_param(priv, param);
1754
1755         param->cq_period_mode = priv->params.rx_cq_period_mode;
1756 }
1757
1758 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1759                                     struct mlx5e_cq_param *param)
1760 {
1761         void *cqc = param->cqc;
1762
1763         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1764
1765         mlx5e_build_common_cq_param(priv, param);
1766
1767         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1768 }
1769
1770 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1771                                      struct mlx5e_cq_param *param,
1772                                      u8 log_wq_size)
1773 {
1774         void *cqc = param->cqc;
1775
1776         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1777
1778         mlx5e_build_common_cq_param(priv, param);
1779
1780         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1781 }
1782
1783 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1784                                     struct mlx5e_sq_param *param,
1785                                     u8 log_wq_size)
1786 {
1787         void *sqc = param->sqc;
1788         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1789
1790         mlx5e_build_sq_param_common(priv, param);
1791
1792         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1793         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1794
1795         param->type = MLX5E_SQ_ICO;
1796 }
1797
1798 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1799                                     struct mlx5e_sq_param *param)
1800 {
1801         void *sqc = param->sqc;
1802         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1803
1804         mlx5e_build_sq_param_common(priv, param);
1805         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1806
1807         param->max_inline = priv->params.tx_max_inline;
1808         /* FOR XDP SQs will support only L2 inline mode */
1809         param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1810         param->type = MLX5E_SQ_XDP;
1811 }
1812
1813 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1814 {
1815         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1816
1817         mlx5e_build_rq_param(priv, &cparam->rq);
1818         mlx5e_build_sq_param(priv, &cparam->sq);
1819         mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
1820         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1821         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1822         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1823         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1824 }
1825
1826 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1827 {
1828         struct mlx5e_channel_param *cparam;
1829         int nch = priv->params.num_channels;
1830         int err = -ENOMEM;
1831         int i;
1832         int j;
1833
1834         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1835                                 GFP_KERNEL);
1836
1837         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1838                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1839
1840         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1841
1842         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1843                 goto err_free_txq_to_sq_map;
1844
1845         mlx5e_build_channel_param(priv, cparam);
1846
1847         for (i = 0; i < nch; i++) {
1848                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1849                 if (err)
1850                         goto err_close_channels;
1851         }
1852
1853         for (j = 0; j < nch; j++) {
1854                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1855                 if (err)
1856                         goto err_close_channels;
1857         }
1858
1859         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1860          * polling for inactive tx queues.
1861          */
1862         netif_tx_start_all_queues(priv->netdev);
1863
1864         kfree(cparam);
1865         return 0;
1866
1867 err_close_channels:
1868         for (i--; i >= 0; i--)
1869                 mlx5e_close_channel(priv->channel[i]);
1870
1871 err_free_txq_to_sq_map:
1872         kfree(priv->txq_to_sq_map);
1873         kfree(priv->channel);
1874         kfree(cparam);
1875
1876         return err;
1877 }
1878
1879 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1880 {
1881         int i;
1882
1883         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1884          * polling for inactive tx queues.
1885          */
1886         netif_tx_stop_all_queues(priv->netdev);
1887         netif_tx_disable(priv->netdev);
1888
1889         for (i = 0; i < priv->params.num_channels; i++)
1890                 mlx5e_close_channel(priv->channel[i]);
1891
1892         kfree(priv->txq_to_sq_map);
1893         kfree(priv->channel);
1894 }
1895
1896 static int mlx5e_rx_hash_fn(int hfunc)
1897 {
1898         return (hfunc == ETH_RSS_HASH_TOP) ?
1899                MLX5_RX_HASH_FN_TOEPLITZ :
1900                MLX5_RX_HASH_FN_INVERTED_XOR8;
1901 }
1902
1903 static int mlx5e_bits_invert(unsigned long a, int size)
1904 {
1905         int inv = 0;
1906         int i;
1907
1908         for (i = 0; i < size; i++)
1909                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1910
1911         return inv;
1912 }
1913
1914 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1915 {
1916         int i;
1917
1918         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1919                 int ix = i;
1920                 u32 rqn;
1921
1922                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1923                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1924
1925                 ix = priv->params.indirection_rqt[ix];
1926                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1927                                 priv->channel[ix]->rq.rqn :
1928                                 priv->drop_rq.rqn;
1929                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1930         }
1931 }
1932
1933 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1934                                       int ix)
1935 {
1936         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1937                         priv->channel[ix]->rq.rqn :
1938                         priv->drop_rq.rqn;
1939
1940         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1941 }
1942
1943 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1944                             int ix, struct mlx5e_rqt *rqt)
1945 {
1946         struct mlx5_core_dev *mdev = priv->mdev;
1947         void *rqtc;
1948         int inlen;
1949         int err;
1950         u32 *in;
1951
1952         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1953         in = mlx5_vzalloc(inlen);
1954         if (!in)
1955                 return -ENOMEM;
1956
1957         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1958
1959         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1960         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1961
1962         if (sz > 1) /* RSS */
1963                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1964         else
1965                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1966
1967         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1968         if (!err)
1969                 rqt->enabled = true;
1970
1971         kvfree(in);
1972         return err;
1973 }
1974
1975 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1976 {
1977         rqt->enabled = false;
1978         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1979 }
1980
1981 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1982 {
1983         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1984
1985         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1986 }
1987
1988 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1989 {
1990         struct mlx5e_rqt *rqt;
1991         int err;
1992         int ix;
1993
1994         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1995                 rqt = &priv->direct_tir[ix].rqt;
1996                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1997                 if (err)
1998                         goto err_destroy_rqts;
1999         }
2000
2001         return 0;
2002
2003 err_destroy_rqts:
2004         for (ix--; ix >= 0; ix--)
2005                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2006
2007         return err;
2008 }
2009
2010 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
2011 {
2012         struct mlx5_core_dev *mdev = priv->mdev;
2013         void *rqtc;
2014         int inlen;
2015         u32 *in;
2016         int err;
2017
2018         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2019         in = mlx5_vzalloc(inlen);
2020         if (!in)
2021                 return -ENOMEM;
2022
2023         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2024
2025         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2026         if (sz > 1) /* RSS */
2027                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
2028         else
2029                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2030
2031         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2032
2033         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2034
2035         kvfree(in);
2036
2037         return err;
2038 }
2039
2040 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
2041 {
2042         u32 rqtn;
2043         int ix;
2044
2045         if (priv->indir_rqt.enabled) {
2046                 rqtn = priv->indir_rqt.rqtn;
2047                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
2048         }
2049
2050         for (ix = 0; ix < priv->params.num_channels; ix++) {
2051                 if (!priv->direct_tir[ix].rqt.enabled)
2052                         continue;
2053                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2054                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
2055         }
2056 }
2057
2058 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
2059 {
2060         if (!priv->params.lro_en)
2061                 return;
2062
2063 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2064
2065         MLX5_SET(tirc, tirc, lro_enable_mask,
2066                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2067                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2068         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2069                  (priv->params.lro_wqe_sz -
2070                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2071         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
2072 }
2073
2074 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc,
2075                                     enum mlx5e_traffic_types tt)
2076 {
2077         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2078
2079 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2080                                  MLX5_HASH_FIELD_SEL_DST_IP)
2081
2082 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2083                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2084                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2085                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2086
2087 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2088                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2089                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2090
2091         MLX5_SET(tirc, tirc, rx_hash_fn,
2092                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
2093         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
2094                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2095                                              rx_hash_toeplitz_key);
2096                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2097                                                rx_hash_toeplitz_key);
2098
2099                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2100                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2101         }
2102
2103         switch (tt) {
2104         case MLX5E_TT_IPV4_TCP:
2105                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2106                          MLX5_L3_PROT_TYPE_IPV4);
2107                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2108                          MLX5_L4_PROT_TYPE_TCP);
2109                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2110                          MLX5_HASH_IP_L4PORTS);
2111                 break;
2112
2113         case MLX5E_TT_IPV6_TCP:
2114                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2115                          MLX5_L3_PROT_TYPE_IPV6);
2116                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2117                          MLX5_L4_PROT_TYPE_TCP);
2118                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2119                          MLX5_HASH_IP_L4PORTS);
2120                 break;
2121
2122         case MLX5E_TT_IPV4_UDP:
2123                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2124                          MLX5_L3_PROT_TYPE_IPV4);
2125                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2126                          MLX5_L4_PROT_TYPE_UDP);
2127                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2128                          MLX5_HASH_IP_L4PORTS);
2129                 break;
2130
2131         case MLX5E_TT_IPV6_UDP:
2132                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2133                          MLX5_L3_PROT_TYPE_IPV6);
2134                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2135                          MLX5_L4_PROT_TYPE_UDP);
2136                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2137                          MLX5_HASH_IP_L4PORTS);
2138                 break;
2139
2140         case MLX5E_TT_IPV4_IPSEC_AH:
2141                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2142                          MLX5_L3_PROT_TYPE_IPV4);
2143                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2144                          MLX5_HASH_IP_IPSEC_SPI);
2145                 break;
2146
2147         case MLX5E_TT_IPV6_IPSEC_AH:
2148                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2149                          MLX5_L3_PROT_TYPE_IPV6);
2150                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2151                          MLX5_HASH_IP_IPSEC_SPI);
2152                 break;
2153
2154         case MLX5E_TT_IPV4_IPSEC_ESP:
2155                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2156                          MLX5_L3_PROT_TYPE_IPV4);
2157                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2158                          MLX5_HASH_IP_IPSEC_SPI);
2159                 break;
2160
2161         case MLX5E_TT_IPV6_IPSEC_ESP:
2162                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2163                          MLX5_L3_PROT_TYPE_IPV6);
2164                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2165                          MLX5_HASH_IP_IPSEC_SPI);
2166                 break;
2167
2168         case MLX5E_TT_IPV4:
2169                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2170                          MLX5_L3_PROT_TYPE_IPV4);
2171                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2172                          MLX5_HASH_IP);
2173                 break;
2174
2175         case MLX5E_TT_IPV6:
2176                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2177                          MLX5_L3_PROT_TYPE_IPV6);
2178                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2179                          MLX5_HASH_IP);
2180                 break;
2181         default:
2182                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2183         }
2184 }
2185
2186 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2187 {
2188         struct mlx5_core_dev *mdev = priv->mdev;
2189
2190         void *in;
2191         void *tirc;
2192         int inlen;
2193         int err;
2194         int tt;
2195         int ix;
2196
2197         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2198         in = mlx5_vzalloc(inlen);
2199         if (!in)
2200                 return -ENOMEM;
2201
2202         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2203         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2204
2205         mlx5e_build_tir_ctx_lro(tirc, priv);
2206
2207         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2208                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2209                                            inlen);
2210                 if (err)
2211                         goto free_in;
2212         }
2213
2214         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2215                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2216                                            in, inlen);
2217                 if (err)
2218                         goto free_in;
2219         }
2220
2221 free_in:
2222         kvfree(in);
2223
2224         return err;
2225 }
2226
2227 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2228 {
2229         struct mlx5_core_dev *mdev = priv->mdev;
2230         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2231         int err;
2232
2233         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2234         if (err)
2235                 return err;
2236
2237         /* Update vport context MTU */
2238         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2239         return 0;
2240 }
2241
2242 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2243 {
2244         struct mlx5_core_dev *mdev = priv->mdev;
2245         u16 hw_mtu = 0;
2246         int err;
2247
2248         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2249         if (err || !hw_mtu) /* fallback to port oper mtu */
2250                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2251
2252         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2253 }
2254
2255 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2256 {
2257         struct mlx5e_priv *priv = netdev_priv(netdev);
2258         u16 mtu;
2259         int err;
2260
2261         err = mlx5e_set_mtu(priv, netdev->mtu);
2262         if (err)
2263                 return err;
2264
2265         mlx5e_query_mtu(priv, &mtu);
2266         if (mtu != netdev->mtu)
2267                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2268                             __func__, mtu, netdev->mtu);
2269
2270         netdev->mtu = mtu;
2271         return 0;
2272 }
2273
2274 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2275 {
2276         struct mlx5e_priv *priv = netdev_priv(netdev);
2277         int nch = priv->params.num_channels;
2278         int ntc = priv->params.num_tc;
2279         int tc;
2280
2281         netdev_reset_tc(netdev);
2282
2283         if (ntc == 1)
2284                 return;
2285
2286         netdev_set_num_tc(netdev, ntc);
2287
2288         /* Map netdev TCs to offset 0
2289          * We have our own UP to TXQ mapping for QoS
2290          */
2291         for (tc = 0; tc < ntc; tc++)
2292                 netdev_set_tc_queue(netdev, tc, nch, 0);
2293 }
2294
2295 int mlx5e_open_locked(struct net_device *netdev)
2296 {
2297         struct mlx5e_priv *priv = netdev_priv(netdev);
2298         struct mlx5_core_dev *mdev = priv->mdev;
2299         int num_txqs;
2300         int err;
2301
2302         set_bit(MLX5E_STATE_OPENED, &priv->state);
2303
2304         mlx5e_netdev_set_tcs(netdev);
2305
2306         num_txqs = priv->params.num_channels * priv->params.num_tc;
2307         netif_set_real_num_tx_queues(netdev, num_txqs);
2308         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2309
2310         err = mlx5e_open_channels(priv);
2311         if (err) {
2312                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2313                            __func__, err);
2314                 goto err_clear_state_opened_flag;
2315         }
2316
2317         err = mlx5e_refresh_tirs_self_loopback(priv->mdev, false);
2318         if (err) {
2319                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2320                            __func__, err);
2321                 goto err_close_channels;
2322         }
2323
2324         mlx5e_redirect_rqts(priv);
2325         mlx5e_update_carrier(priv);
2326         mlx5e_timestamp_init(priv);
2327 #ifdef CONFIG_RFS_ACCEL
2328         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2329 #endif
2330         if (priv->profile->update_stats)
2331                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2332
2333         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2334                 err = mlx5e_add_sqs_fwd_rules(priv);
2335                 if (err)
2336                         goto err_close_channels;
2337         }
2338         return 0;
2339
2340 err_close_channels:
2341         mlx5e_close_channels(priv);
2342 err_clear_state_opened_flag:
2343         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2344         return err;
2345 }
2346
2347 int mlx5e_open(struct net_device *netdev)
2348 {
2349         struct mlx5e_priv *priv = netdev_priv(netdev);
2350         int err;
2351
2352         mutex_lock(&priv->state_lock);
2353         err = mlx5e_open_locked(netdev);
2354         mutex_unlock(&priv->state_lock);
2355
2356         return err;
2357 }
2358
2359 int mlx5e_close_locked(struct net_device *netdev)
2360 {
2361         struct mlx5e_priv *priv = netdev_priv(netdev);
2362         struct mlx5_core_dev *mdev = priv->mdev;
2363
2364         /* May already be CLOSED in case a previous configuration operation
2365          * (e.g RX/TX queue size change) that involves close&open failed.
2366          */
2367         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2368                 return 0;
2369
2370         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2371
2372         if (MLX5_CAP_GEN(mdev, vport_group_manager))
2373                 mlx5e_remove_sqs_fwd_rules(priv);
2374
2375         mlx5e_timestamp_cleanup(priv);
2376         netif_carrier_off(priv->netdev);
2377         mlx5e_redirect_rqts(priv);
2378         mlx5e_close_channels(priv);
2379
2380         return 0;
2381 }
2382
2383 int mlx5e_close(struct net_device *netdev)
2384 {
2385         struct mlx5e_priv *priv = netdev_priv(netdev);
2386         int err;
2387
2388         if (!netif_device_present(netdev))
2389                 return -ENODEV;
2390
2391         mutex_lock(&priv->state_lock);
2392         err = mlx5e_close_locked(netdev);
2393         mutex_unlock(&priv->state_lock);
2394
2395         return err;
2396 }
2397
2398 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2399                                 struct mlx5e_rq *rq,
2400                                 struct mlx5e_rq_param *param)
2401 {
2402         struct mlx5_core_dev *mdev = priv->mdev;
2403         void *rqc = param->rqc;
2404         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2405         int err;
2406
2407         param->wq.db_numa_node = param->wq.buf_numa_node;
2408
2409         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2410                                 &rq->wq_ctrl);
2411         if (err)
2412                 return err;
2413
2414         rq->priv = priv;
2415
2416         return 0;
2417 }
2418
2419 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2420                                 struct mlx5e_cq *cq,
2421                                 struct mlx5e_cq_param *param)
2422 {
2423         struct mlx5_core_dev *mdev = priv->mdev;
2424         struct mlx5_core_cq *mcq = &cq->mcq;
2425         int eqn_not_used;
2426         unsigned int irqn;
2427         int err;
2428
2429         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2430                                &cq->wq_ctrl);
2431         if (err)
2432                 return err;
2433
2434         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2435
2436         mcq->cqe_sz     = 64;
2437         mcq->set_ci_db  = cq->wq_ctrl.db.db;
2438         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
2439         *mcq->set_ci_db = 0;
2440         *mcq->arm_db    = 0;
2441         mcq->vector     = param->eq_ix;
2442         mcq->comp       = mlx5e_completion_event;
2443         mcq->event      = mlx5e_cq_error_event;
2444         mcq->irqn       = irqn;
2445
2446         cq->priv = priv;
2447
2448         return 0;
2449 }
2450
2451 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2452 {
2453         struct mlx5e_cq_param cq_param;
2454         struct mlx5e_rq_param rq_param;
2455         struct mlx5e_rq *rq = &priv->drop_rq;
2456         struct mlx5e_cq *cq = &priv->drop_rq.cq;
2457         int err;
2458
2459         memset(&cq_param, 0, sizeof(cq_param));
2460         memset(&rq_param, 0, sizeof(rq_param));
2461         mlx5e_build_drop_rq_param(&rq_param);
2462
2463         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2464         if (err)
2465                 return err;
2466
2467         err = mlx5e_enable_cq(cq, &cq_param);
2468         if (err)
2469                 goto err_destroy_cq;
2470
2471         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2472         if (err)
2473                 goto err_disable_cq;
2474
2475         err = mlx5e_enable_rq(rq, &rq_param);
2476         if (err)
2477                 goto err_destroy_rq;
2478
2479         return 0;
2480
2481 err_destroy_rq:
2482         mlx5e_destroy_rq(&priv->drop_rq);
2483
2484 err_disable_cq:
2485         mlx5e_disable_cq(&priv->drop_rq.cq);
2486
2487 err_destroy_cq:
2488         mlx5e_destroy_cq(&priv->drop_rq.cq);
2489
2490         return err;
2491 }
2492
2493 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2494 {
2495         mlx5e_disable_rq(&priv->drop_rq);
2496         mlx5e_destroy_rq(&priv->drop_rq);
2497         mlx5e_disable_cq(&priv->drop_rq.cq);
2498         mlx5e_destroy_cq(&priv->drop_rq.cq);
2499 }
2500
2501 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2502 {
2503         struct mlx5_core_dev *mdev = priv->mdev;
2504         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2505         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2506
2507         MLX5_SET(tisc, tisc, prio, tc << 1);
2508         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2509
2510         if (mlx5_lag_is_lacp_owner(mdev))
2511                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2512
2513         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2514 }
2515
2516 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2517 {
2518         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2519 }
2520
2521 int mlx5e_create_tises(struct mlx5e_priv *priv)
2522 {
2523         int err;
2524         int tc;
2525
2526         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2527                 err = mlx5e_create_tis(priv, tc);
2528                 if (err)
2529                         goto err_close_tises;
2530         }
2531
2532         return 0;
2533
2534 err_close_tises:
2535         for (tc--; tc >= 0; tc--)
2536                 mlx5e_destroy_tis(priv, tc);
2537
2538         return err;
2539 }
2540
2541 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2542 {
2543         int tc;
2544
2545         for (tc = 0; tc < priv->profile->max_tc; tc++)
2546                 mlx5e_destroy_tis(priv, tc);
2547 }
2548
2549 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2550                                       enum mlx5e_traffic_types tt)
2551 {
2552         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2553
2554         mlx5e_build_tir_ctx_lro(tirc, priv);
2555
2556         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2557         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2558         mlx5e_build_indir_tir_ctx_hash(priv, tirc, tt);
2559 }
2560
2561 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2562                                        u32 rqtn)
2563 {
2564         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2565
2566         mlx5e_build_tir_ctx_lro(tirc, priv);
2567
2568         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2569         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2570         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2571 }
2572
2573 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2574 {
2575         struct mlx5e_tir *tir;
2576         void *tirc;
2577         int inlen;
2578         int err;
2579         u32 *in;
2580         int tt;
2581
2582         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2583         in = mlx5_vzalloc(inlen);
2584         if (!in)
2585                 return -ENOMEM;
2586
2587         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2588                 memset(in, 0, inlen);
2589                 tir = &priv->indir_tir[tt];
2590                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2591                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2592                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2593                 if (err)
2594                         goto err_destroy_tirs;
2595         }
2596
2597         kvfree(in);
2598
2599         return 0;
2600
2601 err_destroy_tirs:
2602         for (tt--; tt >= 0; tt--)
2603                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2604
2605         kvfree(in);
2606
2607         return err;
2608 }
2609
2610 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2611 {
2612         int nch = priv->profile->max_nch(priv->mdev);
2613         struct mlx5e_tir *tir;
2614         void *tirc;
2615         int inlen;
2616         int err;
2617         u32 *in;
2618         int ix;
2619
2620         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2621         in = mlx5_vzalloc(inlen);
2622         if (!in)
2623                 return -ENOMEM;
2624
2625         for (ix = 0; ix < nch; ix++) {
2626                 memset(in, 0, inlen);
2627                 tir = &priv->direct_tir[ix];
2628                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2629                 mlx5e_build_direct_tir_ctx(priv, tirc,
2630                                            priv->direct_tir[ix].rqt.rqtn);
2631                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2632                 if (err)
2633                         goto err_destroy_ch_tirs;
2634         }
2635
2636         kvfree(in);
2637
2638         return 0;
2639
2640 err_destroy_ch_tirs:
2641         for (ix--; ix >= 0; ix--)
2642                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2643
2644         kvfree(in);
2645
2646         return err;
2647 }
2648
2649 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2650 {
2651         int i;
2652
2653         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2654                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2655 }
2656
2657 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2658 {
2659         int nch = priv->profile->max_nch(priv->mdev);
2660         int i;
2661
2662         for (i = 0; i < nch; i++)
2663                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2664 }
2665
2666 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2667 {
2668         int err = 0;
2669         int i;
2670
2671         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2672                 return 0;
2673
2674         for (i = 0; i < priv->params.num_channels; i++) {
2675                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2676                 if (err)
2677                         return err;
2678         }
2679
2680         return 0;
2681 }
2682
2683 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2684 {
2685         struct mlx5e_priv *priv = netdev_priv(netdev);
2686         bool was_opened;
2687         int err = 0;
2688
2689         if (tc && tc != MLX5E_MAX_NUM_TC)
2690                 return -EINVAL;
2691
2692         mutex_lock(&priv->state_lock);
2693
2694         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2695         if (was_opened)
2696                 mlx5e_close_locked(priv->netdev);
2697
2698         priv->params.num_tc = tc ? tc : 1;
2699
2700         if (was_opened)
2701                 err = mlx5e_open_locked(priv->netdev);
2702
2703         mutex_unlock(&priv->state_lock);
2704
2705         return err;
2706 }
2707
2708 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2709                               __be16 proto, struct tc_to_netdev *tc)
2710 {
2711         struct mlx5e_priv *priv = netdev_priv(dev);
2712
2713         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2714                 goto mqprio;
2715
2716         switch (tc->type) {
2717         case TC_SETUP_CLSFLOWER:
2718                 switch (tc->cls_flower->command) {
2719                 case TC_CLSFLOWER_REPLACE:
2720                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2721                 case TC_CLSFLOWER_DESTROY:
2722                         return mlx5e_delete_flower(priv, tc->cls_flower);
2723                 case TC_CLSFLOWER_STATS:
2724                         return mlx5e_stats_flower(priv, tc->cls_flower);
2725                 }
2726         default:
2727                 return -EOPNOTSUPP;
2728         }
2729
2730 mqprio:
2731         if (tc->type != TC_SETUP_MQPRIO)
2732                 return -EINVAL;
2733
2734         return mlx5e_setup_tc(dev, tc->tc);
2735 }
2736
2737 static void
2738 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2739 {
2740         struct mlx5e_priv *priv = netdev_priv(dev);
2741         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2742         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2743         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2744
2745         if (mlx5e_is_uplink_rep(priv)) {
2746                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2747                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
2748                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2749                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2750         } else {
2751                 stats->rx_packets = sstats->rx_packets;
2752                 stats->rx_bytes   = sstats->rx_bytes;
2753                 stats->tx_packets = sstats->tx_packets;
2754                 stats->tx_bytes   = sstats->tx_bytes;
2755                 stats->tx_dropped = sstats->tx_queue_dropped;
2756         }
2757
2758         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2759
2760         stats->rx_length_errors =
2761                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2762                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2763                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2764         stats->rx_crc_errors =
2765                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2766         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2767         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2768         stats->tx_carrier_errors =
2769                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2770         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2771                            stats->rx_frame_errors;
2772         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2773
2774         /* vport multicast also counts packets that are dropped due to steering
2775          * or rx out of buffer
2776          */
2777         stats->multicast =
2778                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2779
2780 }
2781
2782 static void mlx5e_set_rx_mode(struct net_device *dev)
2783 {
2784         struct mlx5e_priv *priv = netdev_priv(dev);
2785
2786         queue_work(priv->wq, &priv->set_rx_mode_work);
2787 }
2788
2789 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2790 {
2791         struct mlx5e_priv *priv = netdev_priv(netdev);
2792         struct sockaddr *saddr = addr;
2793
2794         if (!is_valid_ether_addr(saddr->sa_data))
2795                 return -EADDRNOTAVAIL;
2796
2797         netif_addr_lock_bh(netdev);
2798         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2799         netif_addr_unlock_bh(netdev);
2800
2801         queue_work(priv->wq, &priv->set_rx_mode_work);
2802
2803         return 0;
2804 }
2805
2806 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2807         do {                                            \
2808                 if (enable)                             \
2809                         netdev->features |= feature;    \
2810                 else                                    \
2811                         netdev->features &= ~feature;   \
2812         } while (0)
2813
2814 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2815
2816 static int set_feature_lro(struct net_device *netdev, bool enable)
2817 {
2818         struct mlx5e_priv *priv = netdev_priv(netdev);
2819         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2820         int err;
2821
2822         mutex_lock(&priv->state_lock);
2823
2824         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2825                 mlx5e_close_locked(priv->netdev);
2826
2827         priv->params.lro_en = enable;
2828         err = mlx5e_modify_tirs_lro(priv);
2829         if (err) {
2830                 netdev_err(netdev, "lro modify failed, %d\n", err);
2831                 priv->params.lro_en = !enable;
2832         }
2833
2834         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2835                 mlx5e_open_locked(priv->netdev);
2836
2837         mutex_unlock(&priv->state_lock);
2838
2839         return err;
2840 }
2841
2842 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2843 {
2844         struct mlx5e_priv *priv = netdev_priv(netdev);
2845
2846         if (enable)
2847                 mlx5e_enable_vlan_filter(priv);
2848         else
2849                 mlx5e_disable_vlan_filter(priv);
2850
2851         return 0;
2852 }
2853
2854 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2855 {
2856         struct mlx5e_priv *priv = netdev_priv(netdev);
2857
2858         if (!enable && mlx5e_tc_num_filters(priv)) {
2859                 netdev_err(netdev,
2860                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2861                 return -EINVAL;
2862         }
2863
2864         return 0;
2865 }
2866
2867 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2868 {
2869         struct mlx5e_priv *priv = netdev_priv(netdev);
2870         struct mlx5_core_dev *mdev = priv->mdev;
2871
2872         return mlx5_set_port_fcs(mdev, !enable);
2873 }
2874
2875 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2876 {
2877         struct mlx5e_priv *priv = netdev_priv(netdev);
2878         int err;
2879
2880         mutex_lock(&priv->state_lock);
2881
2882         priv->params.vlan_strip_disable = !enable;
2883         err = mlx5e_modify_rqs_vsd(priv, !enable);
2884         if (err)
2885                 priv->params.vlan_strip_disable = enable;
2886
2887         mutex_unlock(&priv->state_lock);
2888
2889         return err;
2890 }
2891
2892 #ifdef CONFIG_RFS_ACCEL
2893 static int set_feature_arfs(struct net_device *netdev, bool enable)
2894 {
2895         struct mlx5e_priv *priv = netdev_priv(netdev);
2896         int err;
2897
2898         if (enable)
2899                 err = mlx5e_arfs_enable(priv);
2900         else
2901                 err = mlx5e_arfs_disable(priv);
2902
2903         return err;
2904 }
2905 #endif
2906
2907 static int mlx5e_handle_feature(struct net_device *netdev,
2908                                 netdev_features_t wanted_features,
2909                                 netdev_features_t feature,
2910                                 mlx5e_feature_handler feature_handler)
2911 {
2912         netdev_features_t changes = wanted_features ^ netdev->features;
2913         bool enable = !!(wanted_features & feature);
2914         int err;
2915
2916         if (!(changes & feature))
2917                 return 0;
2918
2919         err = feature_handler(netdev, enable);
2920         if (err) {
2921                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2922                            enable ? "Enable" : "Disable", feature, err);
2923                 return err;
2924         }
2925
2926         MLX5E_SET_FEATURE(netdev, feature, enable);
2927         return 0;
2928 }
2929
2930 static int mlx5e_set_features(struct net_device *netdev,
2931                               netdev_features_t features)
2932 {
2933         int err;
2934
2935         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2936                                     set_feature_lro);
2937         err |= mlx5e_handle_feature(netdev, features,
2938                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2939                                     set_feature_vlan_filter);
2940         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2941                                     set_feature_tc_num_filters);
2942         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2943                                     set_feature_rx_all);
2944         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2945                                     set_feature_rx_vlan);
2946 #ifdef CONFIG_RFS_ACCEL
2947         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2948                                     set_feature_arfs);
2949 #endif
2950
2951         return err ? -EINVAL : 0;
2952 }
2953
2954 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2955 {
2956         struct mlx5e_priv *priv = netdev_priv(netdev);
2957         bool was_opened;
2958         int err = 0;
2959         bool reset;
2960
2961         mutex_lock(&priv->state_lock);
2962
2963         reset = !priv->params.lro_en &&
2964                 (priv->params.rq_wq_type !=
2965                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2966
2967         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2968         if (was_opened && reset)
2969                 mlx5e_close_locked(netdev);
2970
2971         netdev->mtu = new_mtu;
2972         mlx5e_set_dev_port_mtu(netdev);
2973
2974         if (was_opened && reset)
2975                 err = mlx5e_open_locked(netdev);
2976
2977         mutex_unlock(&priv->state_lock);
2978
2979         return err;
2980 }
2981
2982 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2983 {
2984         switch (cmd) {
2985         case SIOCSHWTSTAMP:
2986                 return mlx5e_hwstamp_set(dev, ifr);
2987         case SIOCGHWTSTAMP:
2988                 return mlx5e_hwstamp_get(dev, ifr);
2989         default:
2990                 return -EOPNOTSUPP;
2991         }
2992 }
2993
2994 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2995 {
2996         struct mlx5e_priv *priv = netdev_priv(dev);
2997         struct mlx5_core_dev *mdev = priv->mdev;
2998
2999         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3000 }
3001
3002 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3003                              __be16 vlan_proto)
3004 {
3005         struct mlx5e_priv *priv = netdev_priv(dev);
3006         struct mlx5_core_dev *mdev = priv->mdev;
3007
3008         if (vlan_proto != htons(ETH_P_8021Q))
3009                 return -EPROTONOSUPPORT;
3010
3011         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3012                                            vlan, qos);
3013 }
3014
3015 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3016 {
3017         struct mlx5e_priv *priv = netdev_priv(dev);
3018         struct mlx5_core_dev *mdev = priv->mdev;
3019
3020         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3021 }
3022
3023 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3024 {
3025         struct mlx5e_priv *priv = netdev_priv(dev);
3026         struct mlx5_core_dev *mdev = priv->mdev;
3027
3028         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3029 }
3030
3031 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3032                              int max_tx_rate)
3033 {
3034         struct mlx5e_priv *priv = netdev_priv(dev);
3035         struct mlx5_core_dev *mdev = priv->mdev;
3036
3037         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3038                                            max_tx_rate, min_tx_rate);
3039 }
3040
3041 static int mlx5_vport_link2ifla(u8 esw_link)
3042 {
3043         switch (esw_link) {
3044         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3045                 return IFLA_VF_LINK_STATE_DISABLE;
3046         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3047                 return IFLA_VF_LINK_STATE_ENABLE;
3048         }
3049         return IFLA_VF_LINK_STATE_AUTO;
3050 }
3051
3052 static int mlx5_ifla_link2vport(u8 ifla_link)
3053 {
3054         switch (ifla_link) {
3055         case IFLA_VF_LINK_STATE_DISABLE:
3056                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3057         case IFLA_VF_LINK_STATE_ENABLE:
3058                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3059         }
3060         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3061 }
3062
3063 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3064                                    int link_state)
3065 {
3066         struct mlx5e_priv *priv = netdev_priv(dev);
3067         struct mlx5_core_dev *mdev = priv->mdev;
3068
3069         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3070                                             mlx5_ifla_link2vport(link_state));
3071 }
3072
3073 static int mlx5e_get_vf_config(struct net_device *dev,
3074                                int vf, struct ifla_vf_info *ivi)
3075 {
3076         struct mlx5e_priv *priv = netdev_priv(dev);
3077         struct mlx5_core_dev *mdev = priv->mdev;
3078         int err;
3079
3080         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3081         if (err)
3082                 return err;
3083         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3084         return 0;
3085 }
3086
3087 static int mlx5e_get_vf_stats(struct net_device *dev,
3088                               int vf, struct ifla_vf_stats *vf_stats)
3089 {
3090         struct mlx5e_priv *priv = netdev_priv(dev);
3091         struct mlx5_core_dev *mdev = priv->mdev;
3092
3093         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3094                                             vf_stats);
3095 }
3096
3097 void mlx5e_add_vxlan_port(struct net_device *netdev,
3098                           struct udp_tunnel_info *ti)
3099 {
3100         struct mlx5e_priv *priv = netdev_priv(netdev);
3101
3102         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3103                 return;
3104
3105         if (!mlx5e_vxlan_allowed(priv->mdev))
3106                 return;
3107
3108         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3109 }
3110
3111 void mlx5e_del_vxlan_port(struct net_device *netdev,
3112                           struct udp_tunnel_info *ti)
3113 {
3114         struct mlx5e_priv *priv = netdev_priv(netdev);
3115
3116         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3117                 return;
3118
3119         if (!mlx5e_vxlan_allowed(priv->mdev))
3120                 return;
3121
3122         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3123 }
3124
3125 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3126                                                     struct sk_buff *skb,
3127                                                     netdev_features_t features)
3128 {
3129         struct udphdr *udph;
3130         u16 proto;
3131         u16 port = 0;
3132
3133         switch (vlan_get_protocol(skb)) {
3134         case htons(ETH_P_IP):
3135                 proto = ip_hdr(skb)->protocol;
3136                 break;
3137         case htons(ETH_P_IPV6):
3138                 proto = ipv6_hdr(skb)->nexthdr;
3139                 break;
3140         default:
3141                 goto out;
3142         }
3143
3144         if (proto == IPPROTO_UDP) {
3145                 udph = udp_hdr(skb);
3146                 port = be16_to_cpu(udph->dest);
3147         }
3148
3149         /* Verify if UDP port is being offloaded by HW */
3150         if (port && mlx5e_vxlan_lookup_port(priv, port))
3151                 return features;
3152
3153 out:
3154         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3155         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3156 }
3157
3158 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3159                                               struct net_device *netdev,
3160                                               netdev_features_t features)
3161 {
3162         struct mlx5e_priv *priv = netdev_priv(netdev);
3163
3164         features = vlan_features_check(skb, features);
3165         features = vxlan_features_check(skb, features);
3166
3167         /* Validate if the tunneled packet is being offloaded by HW */
3168         if (skb->encapsulation &&
3169             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3170                 return mlx5e_vxlan_features_check(priv, skb, features);
3171
3172         return features;
3173 }
3174
3175 static void mlx5e_tx_timeout(struct net_device *dev)
3176 {
3177         struct mlx5e_priv *priv = netdev_priv(dev);
3178         bool sched_work = false;
3179         int i;
3180
3181         netdev_err(dev, "TX timeout detected\n");
3182
3183         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3184                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3185
3186                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3187                         continue;
3188                 sched_work = true;
3189                 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3190                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3191                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3192         }
3193
3194         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3195                 schedule_work(&priv->tx_timeout_work);
3196 }
3197
3198 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3199 {
3200         struct mlx5e_priv *priv = netdev_priv(netdev);
3201         struct bpf_prog *old_prog;
3202         int err = 0;
3203         bool reset, was_opened;
3204         int i;
3205
3206         mutex_lock(&priv->state_lock);
3207
3208         if ((netdev->features & NETIF_F_LRO) && prog) {
3209                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3210                 err = -EINVAL;
3211                 goto unlock;
3212         }
3213
3214         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3215         /* no need for full reset when exchanging programs */
3216         reset = (!priv->xdp_prog || !prog);
3217
3218         if (was_opened && reset)
3219                 mlx5e_close_locked(netdev);
3220         if (was_opened && !reset) {
3221                 /* num_channels is invariant here, so we can take the
3222                  * batched reference right upfront.
3223                  */
3224                 prog = bpf_prog_add(prog, priv->params.num_channels);
3225                 if (IS_ERR(prog)) {
3226                         err = PTR_ERR(prog);
3227                         goto unlock;
3228                 }
3229         }
3230
3231         /* exchange programs, extra prog reference we got from caller
3232          * as long as we don't fail from this point onwards.
3233          */
3234         old_prog = xchg(&priv->xdp_prog, prog);
3235         if (old_prog)
3236                 bpf_prog_put(old_prog);
3237
3238         if (reset) /* change RQ type according to priv->xdp_prog */
3239                 mlx5e_set_rq_priv_params(priv);
3240
3241         if (was_opened && reset)
3242                 mlx5e_open_locked(netdev);
3243
3244         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3245                 goto unlock;
3246
3247         /* exchanging programs w/o reset, we update ref counts on behalf
3248          * of the channels RQs here.
3249          */
3250         for (i = 0; i < priv->params.num_channels; i++) {
3251                 struct mlx5e_channel *c = priv->channel[i];
3252
3253                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3254                 napi_synchronize(&c->napi);
3255                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3256
3257                 old_prog = xchg(&c->rq.xdp_prog, prog);
3258
3259                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3260                 /* napi_schedule in case we have missed anything */
3261                 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3262                 napi_schedule(&c->napi);
3263
3264                 if (old_prog)
3265                         bpf_prog_put(old_prog);
3266         }
3267
3268 unlock:
3269         mutex_unlock(&priv->state_lock);
3270         return err;
3271 }
3272
3273 static bool mlx5e_xdp_attached(struct net_device *dev)
3274 {
3275         struct mlx5e_priv *priv = netdev_priv(dev);
3276
3277         return !!priv->xdp_prog;
3278 }
3279
3280 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3281 {
3282         switch (xdp->command) {
3283         case XDP_SETUP_PROG:
3284                 return mlx5e_xdp_set(dev, xdp->prog);
3285         case XDP_QUERY_PROG:
3286                 xdp->prog_attached = mlx5e_xdp_attached(dev);
3287                 return 0;
3288         default:
3289                 return -EINVAL;
3290         }
3291 }
3292
3293 #ifdef CONFIG_NET_POLL_CONTROLLER
3294 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3295  * reenabling interrupts.
3296  */
3297 static void mlx5e_netpoll(struct net_device *dev)
3298 {
3299         struct mlx5e_priv *priv = netdev_priv(dev);
3300         int i;
3301
3302         for (i = 0; i < priv->params.num_channels; i++)
3303                 napi_schedule(&priv->channel[i]->napi);
3304 }
3305 #endif
3306
3307 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3308         .ndo_open                = mlx5e_open,
3309         .ndo_stop                = mlx5e_close,
3310         .ndo_start_xmit          = mlx5e_xmit,
3311         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3312         .ndo_select_queue        = mlx5e_select_queue,
3313         .ndo_get_stats64         = mlx5e_get_stats,
3314         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3315         .ndo_set_mac_address     = mlx5e_set_mac,
3316         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3317         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3318         .ndo_set_features        = mlx5e_set_features,
3319         .ndo_change_mtu          = mlx5e_change_mtu,
3320         .ndo_do_ioctl            = mlx5e_ioctl,
3321         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3322 #ifdef CONFIG_RFS_ACCEL
3323         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3324 #endif
3325         .ndo_tx_timeout          = mlx5e_tx_timeout,
3326         .ndo_xdp                 = mlx5e_xdp,
3327 #ifdef CONFIG_NET_POLL_CONTROLLER
3328         .ndo_poll_controller     = mlx5e_netpoll,
3329 #endif
3330 };
3331
3332 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3333         .ndo_open                = mlx5e_open,
3334         .ndo_stop                = mlx5e_close,
3335         .ndo_start_xmit          = mlx5e_xmit,
3336         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3337         .ndo_select_queue        = mlx5e_select_queue,
3338         .ndo_get_stats64         = mlx5e_get_stats,
3339         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3340         .ndo_set_mac_address     = mlx5e_set_mac,
3341         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3342         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3343         .ndo_set_features        = mlx5e_set_features,
3344         .ndo_change_mtu          = mlx5e_change_mtu,
3345         .ndo_do_ioctl            = mlx5e_ioctl,
3346         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
3347         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
3348         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3349         .ndo_features_check      = mlx5e_features_check,
3350 #ifdef CONFIG_RFS_ACCEL
3351         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3352 #endif
3353         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
3354         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
3355         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
3356         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
3357         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
3358         .ndo_get_vf_config       = mlx5e_get_vf_config,
3359         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
3360         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
3361         .ndo_tx_timeout          = mlx5e_tx_timeout,
3362         .ndo_xdp                 = mlx5e_xdp,
3363 #ifdef CONFIG_NET_POLL_CONTROLLER
3364         .ndo_poll_controller     = mlx5e_netpoll,
3365 #endif
3366         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
3367         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
3368 };
3369
3370 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3371 {
3372         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3373                 return -EOPNOTSUPP;
3374         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3375             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3376             !MLX5_CAP_ETH(mdev, csum_cap) ||
3377             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3378             !MLX5_CAP_ETH(mdev, vlan_cap) ||
3379             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3380             MLX5_CAP_FLOWTABLE(mdev,
3381                                flow_table_properties_nic_receive.max_ft_level)
3382                                < 3) {
3383                 mlx5_core_warn(mdev,
3384                                "Not creating net device, some required device capabilities are missing\n");
3385                 return -EOPNOTSUPP;
3386         }
3387         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3388                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3389         if (!MLX5_CAP_GEN(mdev, cq_moderation))
3390                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3391
3392         return 0;
3393 }
3394
3395 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3396 {
3397         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3398
3399         return bf_buf_size -
3400                sizeof(struct mlx5e_tx_wqe) +
3401                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3402 }
3403
3404 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3405                                    u32 *indirection_rqt, int len,
3406                                    int num_channels)
3407 {
3408         int node = mdev->priv.numa_node;
3409         int node_num_of_cores;
3410         int i;
3411
3412         if (node == -1)
3413                 node = first_online_node;
3414
3415         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3416
3417         if (node_num_of_cores)
3418                 num_channels = min_t(int, num_channels, node_num_of_cores);
3419
3420         for (i = 0; i < len; i++)
3421                 indirection_rqt[i] = i % num_channels;
3422 }
3423
3424 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3425 {
3426         enum pcie_link_width width;
3427         enum pci_bus_speed speed;
3428         int err = 0;
3429
3430         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3431         if (err)
3432                 return err;
3433
3434         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3435                 return -EINVAL;
3436
3437         switch (speed) {
3438         case PCIE_SPEED_2_5GT:
3439                 *pci_bw = 2500 * width;
3440                 break;
3441         case PCIE_SPEED_5_0GT:
3442                 *pci_bw = 5000 * width;
3443                 break;
3444         case PCIE_SPEED_8_0GT:
3445                 *pci_bw = 8000 * width;
3446                 break;
3447         default:
3448                 return -EINVAL;
3449         }
3450
3451         return 0;
3452 }
3453
3454 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3455 {
3456         return (link_speed && pci_bw &&
3457                 (pci_bw < 40000) && (pci_bw < link_speed));
3458 }
3459
3460 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3461 {
3462         params->rx_cq_period_mode = cq_period_mode;
3463
3464         params->rx_cq_moderation.pkts =
3465                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3466         params->rx_cq_moderation.usec =
3467                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3468
3469         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3470                 params->rx_cq_moderation.usec =
3471                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3472 }
3473
3474 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3475 {
3476         int i;
3477
3478         /* The supported periods are organized in ascending order */
3479         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3480                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3481                         break;
3482
3483         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3484 }
3485
3486 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3487                                         struct net_device *netdev,
3488                                         const struct mlx5e_profile *profile,
3489                                         void *ppriv)
3490 {
3491         struct mlx5e_priv *priv = netdev_priv(netdev);
3492         u32 link_speed = 0;
3493         u32 pci_bw = 0;
3494         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3495                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3496                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3497
3498         priv->mdev                         = mdev;
3499         priv->netdev                       = netdev;
3500         priv->params.num_channels          = profile->max_nch(mdev);
3501         priv->profile                      = profile;
3502         priv->ppriv                        = ppriv;
3503
3504         priv->params.lro_timeout =
3505                 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3506
3507         priv->params.log_sq_size = is_kdump_kernel() ?
3508                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3509                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3510
3511         /* set CQE compression */
3512         priv->params.rx_cqe_compress_def = false;
3513         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3514             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3515                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3516                 mlx5e_get_pci_bw(mdev, &pci_bw);
3517                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3518                               link_speed, pci_bw);
3519                 priv->params.rx_cqe_compress_def =
3520                         cqe_compress_heuristic(link_speed, pci_bw);
3521         }
3522
3523         mlx5e_set_rq_priv_params(priv);
3524         if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3525                 priv->params.lro_en = true;
3526
3527         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3528         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3529
3530         priv->params.tx_cq_moderation.usec =
3531                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3532         priv->params.tx_cq_moderation.pkts =
3533                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3534         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3535         mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3536         priv->params.num_tc                = 1;
3537         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3538
3539         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3540                             sizeof(priv->params.toeplitz_hash_key));
3541
3542         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3543                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3544
3545         priv->params.lro_wqe_sz =
3546                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3547                 /* Extra room needed for build_skb */
3548                 MLX5_RX_HEADROOM -
3549                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));