0c532367ff1318e3058e6b21ca8bf3f0c4ffbdd9
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include "en.h"
38 #include "en_tc.h"
39 #include "eswitch.h"
40 #include "vxlan.h"
41
42 struct mlx5e_rq_param {
43         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
44         struct mlx5_wq_param       wq;
45 };
46
47 struct mlx5e_sq_param {
48         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
49         struct mlx5_wq_param       wq;
50         u16                        max_inline;
51         bool                       icosq;
52 };
53
54 struct mlx5e_cq_param {
55         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
56         struct mlx5_wq_param       wq;
57         u16                        eq_ix;
58 };
59
60 struct mlx5e_channel_param {
61         struct mlx5e_rq_param      rq;
62         struct mlx5e_sq_param      sq;
63         struct mlx5e_sq_param      icosq;
64         struct mlx5e_cq_param      rx_cq;
65         struct mlx5e_cq_param      tx_cq;
66         struct mlx5e_cq_param      icosq_cq;
67 };
68
69 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
70 {
71         struct mlx5_core_dev *mdev = priv->mdev;
72         u8 port_state;
73
74         port_state = mlx5_query_vport_state(mdev,
75                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
76
77         if (port_state == VPORT_STATE_UP)
78                 netif_carrier_on(priv->netdev);
79         else
80                 netif_carrier_off(priv->netdev);
81 }
82
83 static void mlx5e_update_carrier_work(struct work_struct *work)
84 {
85         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
86                                                update_carrier_work);
87
88         mutex_lock(&priv->state_lock);
89         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
90                 mlx5e_update_carrier(priv);
91         mutex_unlock(&priv->state_lock);
92 }
93
94 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
95 {
96         struct mlx5e_sw_stats *s = &priv->stats.sw;
97         struct mlx5e_rq_stats *rq_stats;
98         struct mlx5e_sq_stats *sq_stats;
99         u64 tx_offload_none = 0;
100         int i, j;
101
102         memset(s, 0, sizeof(*s));
103         for (i = 0; i < priv->params.num_channels; i++) {
104                 rq_stats = &priv->channel[i]->rq.stats;
105
106                 s->rx_packets   += rq_stats->packets;
107                 s->rx_bytes     += rq_stats->bytes;
108                 s->lro_packets  += rq_stats->lro_packets;
109                 s->lro_bytes    += rq_stats->lro_bytes;
110                 s->rx_csum_none += rq_stats->csum_none;
111                 s->rx_csum_sw   += rq_stats->csum_sw;
112                 s->rx_wqe_err   += rq_stats->wqe_err;
113                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
114                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
115                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
116
117                 for (j = 0; j < priv->params.num_tc; j++) {
118                         sq_stats = &priv->channel[i]->sq[j].stats;
119
120                         s->tx_packets           += sq_stats->packets;
121                         s->tx_bytes             += sq_stats->bytes;
122                         s->tso_packets          += sq_stats->tso_packets;
123                         s->tso_bytes            += sq_stats->tso_bytes;
124                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
125                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
126                         s->tx_queue_stopped     += sq_stats->stopped;
127                         s->tx_queue_wake        += sq_stats->wake;
128                         s->tx_queue_dropped     += sq_stats->dropped;
129                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
130                         tx_offload_none         += sq_stats->csum_offload_none;
131                 }
132         }
133
134         /* Update calculated offload counters */
135         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
136         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
137                              s->rx_csum_sw;
138 }
139
140 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
141 {
142         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
143         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
144         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
145         struct mlx5_core_dev *mdev = priv->mdev;
146
147         memset(in, 0, sizeof(in));
148
149         MLX5_SET(query_vport_counter_in, in, opcode,
150                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
151         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
152         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
153
154         memset(out, 0, outlen);
155
156         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
157 }
158
159 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
160 {
161         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
162         struct mlx5_core_dev *mdev = priv->mdev;
163         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
164         void *out;
165         u32 *in;
166
167         in = mlx5_vzalloc(sz);
168         if (!in)
169                 goto free_out;
170
171         MLX5_SET(ppcnt_reg, in, local_port, 1);
172
173         out = pstats->IEEE_802_3_counters;
174         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
175         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
176
177         out = pstats->RFC_2863_counters;
178         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
179         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
180
181         out = pstats->RFC_2819_counters;
182         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
183         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
184
185 free_out:
186         kvfree(in);
187 }
188
189 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
190 {
191         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
192
193         if (!priv->q_counter)
194                 return;
195
196         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
197                                       &qcnt->rx_out_of_buffer);
198 }
199
200 void mlx5e_update_stats(struct mlx5e_priv *priv)
201 {
202         mlx5e_update_sw_counters(priv);
203         mlx5e_update_q_counter(priv);
204         mlx5e_update_vport_counters(priv);
205         mlx5e_update_pport_counters(priv);
206 }
207
208 static void mlx5e_update_stats_work(struct work_struct *work)
209 {
210         struct delayed_work *dwork = to_delayed_work(work);
211         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
212                                                update_stats_work);
213         mutex_lock(&priv->state_lock);
214         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
215                 mlx5e_update_stats(priv);
216                 schedule_delayed_work(dwork,
217                                       msecs_to_jiffies(
218                                               MLX5E_UPDATE_STATS_INTERVAL));
219         }
220         mutex_unlock(&priv->state_lock);
221 }
222
223 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
224                               enum mlx5_dev_event event, unsigned long param)
225 {
226         struct mlx5e_priv *priv = vpriv;
227
228         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
229                 return;
230
231         switch (event) {
232         case MLX5_DEV_EVENT_PORT_UP:
233         case MLX5_DEV_EVENT_PORT_DOWN:
234                 schedule_work(&priv->update_carrier_work);
235                 break;
236
237         default:
238                 break;
239         }
240 }
241
242 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
243 {
244         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
245 }
246
247 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
248 {
249         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
250         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
251 }
252
253 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
254 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
255
256 static int mlx5e_create_rq(struct mlx5e_channel *c,
257                            struct mlx5e_rq_param *param,
258                            struct mlx5e_rq *rq)
259 {
260         struct mlx5e_priv *priv = c->priv;
261         struct mlx5_core_dev *mdev = priv->mdev;
262         void *rqc = param->rqc;
263         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
264         u32 byte_count;
265         int wq_sz;
266         int err;
267         int i;
268
269         param->wq.db_numa_node = cpu_to_node(c->cpu);
270
271         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
272                                 &rq->wq_ctrl);
273         if (err)
274                 return err;
275
276         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
277
278         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
279
280         switch (priv->params.rq_wq_type) {
281         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
282                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
283                                             GFP_KERNEL, cpu_to_node(c->cpu));
284                 if (!rq->wqe_info) {
285                         err = -ENOMEM;
286                         goto err_rq_wq_destroy;
287                 }
288                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
289                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
290
291                 rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE;
292                 byte_count = rq->wqe_sz;
293                 break;
294         default: /* MLX5_WQ_TYPE_LINKED_LIST */
295                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
296                                        cpu_to_node(c->cpu));
297                 if (!rq->skb) {
298                         err = -ENOMEM;
299                         goto err_rq_wq_destroy;
300                 }
301                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
302                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
303
304                 rq->wqe_sz = (priv->params.lro_en) ?
305                                 priv->params.lro_wqe_sz :
306                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
307                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
308                 byte_count = rq->wqe_sz;
309                 byte_count |= MLX5_HW_START_PADDING;
310         }
311
312         for (i = 0; i < wq_sz; i++) {
313                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
314
315                 wqe->data.byte_count = cpu_to_be32(byte_count);
316         }
317
318         rq->wq_type = priv->params.rq_wq_type;
319         rq->pdev    = c->pdev;
320         rq->netdev  = c->netdev;
321         rq->tstamp  = &priv->tstamp;
322         rq->channel = c;
323         rq->ix      = c->ix;
324         rq->priv    = c->priv;
325         rq->mkey_be = c->mkey_be;
326         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
327
328         return 0;
329
330 err_rq_wq_destroy:
331         mlx5_wq_destroy(&rq->wq_ctrl);
332
333         return err;
334 }
335
336 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
337 {
338         switch (rq->wq_type) {
339         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
340                 kfree(rq->wqe_info);
341                 break;
342         default: /* MLX5_WQ_TYPE_LINKED_LIST */
343                 kfree(rq->skb);
344         }
345
346         mlx5_wq_destroy(&rq->wq_ctrl);
347 }
348
349 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
350 {
351         struct mlx5e_priv *priv = rq->priv;
352         struct mlx5_core_dev *mdev = priv->mdev;
353
354         void *in;
355         void *rqc;
356         void *wq;
357         int inlen;
358         int err;
359
360         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
361                 sizeof(u64) * rq->wq_ctrl.buf.npages;
362         in = mlx5_vzalloc(inlen);
363         if (!in)
364                 return -ENOMEM;
365
366         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
367         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
368
369         memcpy(rqc, param->rqc, sizeof(param->rqc));
370
371         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
372         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
373         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
374         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
375                                                 MLX5_ADAPTER_PAGE_SHIFT);
376         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
377
378         mlx5_fill_page_array(&rq->wq_ctrl.buf,
379                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
380
381         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
382
383         kvfree(in);
384
385         return err;
386 }
387
388 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
389 {
390         struct mlx5e_channel *c = rq->channel;
391         struct mlx5e_priv *priv = c->priv;
392         struct mlx5_core_dev *mdev = priv->mdev;
393
394         void *in;
395         void *rqc;
396         int inlen;
397         int err;
398
399         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
400         in = mlx5_vzalloc(inlen);
401         if (!in)
402                 return -ENOMEM;
403
404         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
405
406         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
407         MLX5_SET(rqc, rqc, state, next_state);
408
409         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
410
411         kvfree(in);
412
413         return err;
414 }
415
416 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
417 {
418         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
419 }
420
421 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
422 {
423         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
424         struct mlx5e_channel *c = rq->channel;
425         struct mlx5e_priv *priv = c->priv;
426         struct mlx5_wq_ll *wq = &rq->wq;
427
428         while (time_before(jiffies, exp_time)) {
429                 if (wq->cur_sz >= priv->params.min_rx_wqes)
430                         return 0;
431
432                 msleep(20);
433         }
434
435         return -ETIMEDOUT;
436 }
437
438 static int mlx5e_open_rq(struct mlx5e_channel *c,
439                          struct mlx5e_rq_param *param,
440                          struct mlx5e_rq *rq)
441 {
442         struct mlx5e_sq *sq = &c->icosq;
443         u16 pi = sq->pc & sq->wq.sz_m1;
444         int err;
445
446         err = mlx5e_create_rq(c, param, rq);
447         if (err)
448                 return err;
449
450         err = mlx5e_enable_rq(rq, param);
451         if (err)
452                 goto err_destroy_rq;
453
454         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
455         if (err)
456                 goto err_disable_rq;
457
458         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
459
460         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
461         sq->ico_wqe_info[pi].num_wqebbs = 1;
462         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
463
464         return 0;
465
466 err_disable_rq:
467         mlx5e_disable_rq(rq);
468 err_destroy_rq:
469         mlx5e_destroy_rq(rq);
470
471         return err;
472 }
473
474 static void mlx5e_close_rq(struct mlx5e_rq *rq)
475 {
476         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
477         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
478
479         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
480         while (!mlx5_wq_ll_is_empty(&rq->wq))
481                 msleep(20);
482
483         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
484         napi_synchronize(&rq->channel->napi);
485
486         mlx5e_disable_rq(rq);
487         mlx5e_destroy_rq(rq);
488 }
489
490 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
491 {
492         kfree(sq->wqe_info);
493         kfree(sq->dma_fifo);
494         kfree(sq->skb);
495 }
496
497 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
498 {
499         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
500         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
501
502         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
503         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
504                                     numa);
505         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
506                                     numa);
507
508         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
509                 mlx5e_free_sq_db(sq);
510                 return -ENOMEM;
511         }
512
513         sq->dma_fifo_mask = df_sz - 1;
514
515         return 0;
516 }
517
518 static int mlx5e_create_sq(struct mlx5e_channel *c,
519                            int tc,
520                            struct mlx5e_sq_param *param,
521                            struct mlx5e_sq *sq)
522 {
523         struct mlx5e_priv *priv = c->priv;
524         struct mlx5_core_dev *mdev = priv->mdev;
525
526         void *sqc = param->sqc;
527         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
528         int err;
529
530         err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
531         if (err)
532                 return err;
533
534         param->wq.db_numa_node = cpu_to_node(c->cpu);
535
536         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
537                                  &sq->wq_ctrl);
538         if (err)
539                 goto err_unmap_free_uar;
540
541         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
542         if (sq->uar.bf_map) {
543                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
544                 sq->uar_map = sq->uar.bf_map;
545         } else {
546                 sq->uar_map = sq->uar.map;
547         }
548         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
549         sq->max_inline  = param->max_inline;
550
551         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
552         if (err)
553                 goto err_sq_wq_destroy;
554
555         if (param->icosq) {
556                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
557
558                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
559                                                 wq_sz,
560                                                 GFP_KERNEL,
561                                                 cpu_to_node(c->cpu));
562                 if (!sq->ico_wqe_info) {
563                         err = -ENOMEM;
564                         goto err_free_sq_db;
565                 }
566         } else {
567                 int txq_ix;
568
569                 txq_ix = c->ix + tc * priv->params.num_channels;
570                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
571                 priv->txq_to_sq_map[txq_ix] = sq;
572         }
573
574         sq->pdev      = c->pdev;
575         sq->tstamp    = &priv->tstamp;
576         sq->mkey_be   = c->mkey_be;
577         sq->channel   = c;
578         sq->tc        = tc;
579         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
580         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
581
582         return 0;
583
584 err_free_sq_db:
585         mlx5e_free_sq_db(sq);
586
587 err_sq_wq_destroy:
588         mlx5_wq_destroy(&sq->wq_ctrl);
589
590 err_unmap_free_uar:
591         mlx5_unmap_free_uar(mdev, &sq->uar);
592
593         return err;
594 }
595
596 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
597 {
598         struct mlx5e_channel *c = sq->channel;
599         struct mlx5e_priv *priv = c->priv;
600
601         kfree(sq->ico_wqe_info);
602         mlx5e_free_sq_db(sq);
603         mlx5_wq_destroy(&sq->wq_ctrl);
604         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
605 }
606
607 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
608 {
609         struct mlx5e_channel *c = sq->channel;
610         struct mlx5e_priv *priv = c->priv;
611         struct mlx5_core_dev *mdev = priv->mdev;
612
613         void *in;
614         void *sqc;
615         void *wq;
616         int inlen;
617         int err;
618
619         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
620                 sizeof(u64) * sq->wq_ctrl.buf.npages;
621         in = mlx5_vzalloc(inlen);
622         if (!in)
623                 return -ENOMEM;
624
625         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
626         wq = MLX5_ADDR_OF(sqc, sqc, wq);
627
628         memcpy(sqc, param->sqc, sizeof(param->sqc));
629
630         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
631         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
632         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
633         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
634         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
635
636         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
637         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
638         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
639                                           MLX5_ADAPTER_PAGE_SHIFT);
640         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
641
642         mlx5_fill_page_array(&sq->wq_ctrl.buf,
643                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
644
645         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
646
647         kvfree(in);
648
649         return err;
650 }
651
652 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
653 {
654         struct mlx5e_channel *c = sq->channel;
655         struct mlx5e_priv *priv = c->priv;
656         struct mlx5_core_dev *mdev = priv->mdev;
657
658         void *in;
659         void *sqc;
660         int inlen;
661         int err;
662
663         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
664         in = mlx5_vzalloc(inlen);
665         if (!in)
666                 return -ENOMEM;
667
668         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
669
670         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
671         MLX5_SET(sqc, sqc, state, next_state);
672
673         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
674
675         kvfree(in);
676
677         return err;
678 }
679
680 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
681 {
682         struct mlx5e_channel *c = sq->channel;
683         struct mlx5e_priv *priv = c->priv;
684         struct mlx5_core_dev *mdev = priv->mdev;
685
686         mlx5_core_destroy_sq(mdev, sq->sqn);
687 }
688
689 static int mlx5e_open_sq(struct mlx5e_channel *c,
690                          int tc,
691                          struct mlx5e_sq_param *param,
692                          struct mlx5e_sq *sq)
693 {
694         int err;
695
696         err = mlx5e_create_sq(c, tc, param, sq);
697         if (err)
698                 return err;
699
700         err = mlx5e_enable_sq(sq, param);
701         if (err)
702                 goto err_destroy_sq;
703
704         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
705         if (err)
706                 goto err_disable_sq;
707
708         if (sq->txq) {
709                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
710                 netdev_tx_reset_queue(sq->txq);
711                 netif_tx_start_queue(sq->txq);
712         }
713
714         return 0;
715
716 err_disable_sq:
717         mlx5e_disable_sq(sq);
718 err_destroy_sq:
719         mlx5e_destroy_sq(sq);
720
721         return err;
722 }
723
724 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
725 {
726         __netif_tx_lock_bh(txq);
727         netif_tx_stop_queue(txq);
728         __netif_tx_unlock_bh(txq);
729 }
730
731 static void mlx5e_close_sq(struct mlx5e_sq *sq)
732 {
733         if (sq->txq) {
734                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
735                 /* prevent netif_tx_wake_queue */
736                 napi_synchronize(&sq->channel->napi);
737                 netif_tx_disable_queue(sq->txq);
738
739                 /* ensure hw is notified of all pending wqes */
740                 if (mlx5e_sq_has_room_for(sq, 1))
741                         mlx5e_send_nop(sq, true);
742
743                 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
744         }
745
746         while (sq->cc != sq->pc) /* wait till sq is empty */
747                 msleep(20);
748
749         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
750         napi_synchronize(&sq->channel->napi);
751
752         mlx5e_disable_sq(sq);
753         mlx5e_destroy_sq(sq);
754 }
755
756 static int mlx5e_create_cq(struct mlx5e_channel *c,
757                            struct mlx5e_cq_param *param,
758                            struct mlx5e_cq *cq)
759 {
760         struct mlx5e_priv *priv = c->priv;
761         struct mlx5_core_dev *mdev = priv->mdev;
762         struct mlx5_core_cq *mcq = &cq->mcq;
763         int eqn_not_used;
764         unsigned int irqn;
765         int err;
766         u32 i;
767
768         param->wq.buf_numa_node = cpu_to_node(c->cpu);
769         param->wq.db_numa_node  = cpu_to_node(c->cpu);
770         param->eq_ix   = c->ix;
771
772         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
773                                &cq->wq_ctrl);
774         if (err)
775                 return err;
776
777         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
778
779         cq->napi        = &c->napi;
780
781         mcq->cqe_sz     = 64;
782         mcq->set_ci_db  = cq->wq_ctrl.db.db;
783         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
784         *mcq->set_ci_db = 0;
785         *mcq->arm_db    = 0;
786         mcq->vector     = param->eq_ix;
787         mcq->comp       = mlx5e_completion_event;
788         mcq->event      = mlx5e_cq_error_event;
789         mcq->irqn       = irqn;
790         mcq->uar        = &priv->cq_uar;
791
792         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
793                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
794
795                 cqe->op_own = 0xf1;
796         }
797
798         cq->channel = c;
799         cq->priv = priv;
800
801         return 0;
802 }
803
804 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
805 {
806         mlx5_wq_destroy(&cq->wq_ctrl);
807 }
808
809 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
810 {
811         struct mlx5e_priv *priv = cq->priv;
812         struct mlx5_core_dev *mdev = priv->mdev;
813         struct mlx5_core_cq *mcq = &cq->mcq;
814
815         void *in;
816         void *cqc;
817         int inlen;
818         unsigned int irqn_not_used;
819         int eqn;
820         int err;
821
822         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
823                 sizeof(u64) * cq->wq_ctrl.buf.npages;
824         in = mlx5_vzalloc(inlen);
825         if (!in)
826                 return -ENOMEM;
827
828         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
829
830         memcpy(cqc, param->cqc, sizeof(param->cqc));
831
832         mlx5_fill_page_array(&cq->wq_ctrl.buf,
833                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
834
835         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
836
837         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
838         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
839         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
840                                             MLX5_ADAPTER_PAGE_SHIFT);
841         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
842
843         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
844
845         kvfree(in);
846
847         if (err)
848                 return err;
849
850         mlx5e_cq_arm(cq);
851
852         return 0;
853 }
854
855 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
856 {
857         struct mlx5e_priv *priv = cq->priv;
858         struct mlx5_core_dev *mdev = priv->mdev;
859
860         mlx5_core_destroy_cq(mdev, &cq->mcq);
861 }
862
863 static int mlx5e_open_cq(struct mlx5e_channel *c,
864                          struct mlx5e_cq_param *param,
865                          struct mlx5e_cq *cq,
866                          u16 moderation_usecs,
867                          u16 moderation_frames)
868 {
869         int err;
870         struct mlx5e_priv *priv = c->priv;
871         struct mlx5_core_dev *mdev = priv->mdev;
872
873         err = mlx5e_create_cq(c, param, cq);
874         if (err)
875                 return err;
876
877         err = mlx5e_enable_cq(cq, param);
878         if (err)
879                 goto err_destroy_cq;
880
881         if (MLX5_CAP_GEN(mdev, cq_moderation))
882                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
883                                                moderation_usecs,
884                                                moderation_frames);
885         return 0;
886
887 err_destroy_cq:
888         mlx5e_destroy_cq(cq);
889
890         return err;
891 }
892
893 static void mlx5e_close_cq(struct mlx5e_cq *cq)
894 {
895         mlx5e_disable_cq(cq);
896         mlx5e_destroy_cq(cq);
897 }
898
899 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
900 {
901         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
902 }
903
904 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
905                              struct mlx5e_channel_param *cparam)
906 {
907         struct mlx5e_priv *priv = c->priv;
908         int err;
909         int tc;
910
911         for (tc = 0; tc < c->num_tc; tc++) {
912                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
913                                     priv->params.tx_cq_moderation_usec,
914                                     priv->params.tx_cq_moderation_pkts);
915                 if (err)
916                         goto err_close_tx_cqs;
917         }
918
919         return 0;
920
921 err_close_tx_cqs:
922         for (tc--; tc >= 0; tc--)
923                 mlx5e_close_cq(&c->sq[tc].cq);
924
925         return err;
926 }
927
928 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
929 {
930         int tc;
931
932         for (tc = 0; tc < c->num_tc; tc++)
933                 mlx5e_close_cq(&c->sq[tc].cq);
934 }
935
936 static int mlx5e_open_sqs(struct mlx5e_channel *c,
937                           struct mlx5e_channel_param *cparam)
938 {
939         int err;
940         int tc;
941
942         for (tc = 0; tc < c->num_tc; tc++) {
943                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
944                 if (err)
945                         goto err_close_sqs;
946         }
947
948         return 0;
949
950 err_close_sqs:
951         for (tc--; tc >= 0; tc--)
952                 mlx5e_close_sq(&c->sq[tc]);
953
954         return err;
955 }
956
957 static void mlx5e_close_sqs(struct mlx5e_channel *c)
958 {
959         int tc;
960
961         for (tc = 0; tc < c->num_tc; tc++)
962                 mlx5e_close_sq(&c->sq[tc]);
963 }
964
965 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
966 {
967         int i;
968
969         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
970                 priv->channeltc_to_txq_map[ix][i] =
971                         ix + i * priv->params.num_channels;
972 }
973
974 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
975                               struct mlx5e_channel_param *cparam,
976                               struct mlx5e_channel **cp)
977 {
978         struct net_device *netdev = priv->netdev;
979         int cpu = mlx5e_get_cpu(priv, ix);
980         struct mlx5e_channel *c;
981         int err;
982
983         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
984         if (!c)
985                 return -ENOMEM;
986
987         c->priv     = priv;
988         c->ix       = ix;
989         c->cpu      = cpu;
990         c->pdev     = &priv->mdev->pdev->dev;
991         c->netdev   = priv->netdev;
992         c->mkey_be  = cpu_to_be32(priv->mkey.key);
993         c->num_tc   = priv->params.num_tc;
994
995         mlx5e_build_channeltc_to_txq_map(priv, ix);
996
997         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
998
999         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1000         if (err)
1001                 goto err_napi_del;
1002
1003         err = mlx5e_open_tx_cqs(c, cparam);
1004         if (err)
1005                 goto err_close_icosq_cq;
1006
1007         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1008                             priv->params.rx_cq_moderation_usec,
1009                             priv->params.rx_cq_moderation_pkts);
1010         if (err)
1011                 goto err_close_tx_cqs;
1012
1013         napi_enable(&c->napi);
1014
1015         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1016         if (err)
1017                 goto err_disable_napi;
1018
1019         err = mlx5e_open_sqs(c, cparam);
1020         if (err)
1021                 goto err_close_icosq;
1022
1023         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1024         if (err)
1025                 goto err_close_sqs;
1026
1027         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1028         *cp = c;
1029
1030         return 0;
1031
1032 err_close_sqs:
1033         mlx5e_close_sqs(c);
1034
1035 err_close_icosq:
1036         mlx5e_close_sq(&c->icosq);
1037
1038 err_disable_napi:
1039         napi_disable(&c->napi);
1040         mlx5e_close_cq(&c->rq.cq);
1041
1042 err_close_tx_cqs:
1043         mlx5e_close_tx_cqs(c);
1044
1045 err_close_icosq_cq:
1046         mlx5e_close_cq(&c->icosq.cq);
1047
1048 err_napi_del:
1049         netif_napi_del(&c->napi);
1050         napi_hash_del(&c->napi);
1051         kfree(c);
1052
1053         return err;
1054 }
1055
1056 static void mlx5e_close_channel(struct mlx5e_channel *c)
1057 {
1058         mlx5e_close_rq(&c->rq);
1059         mlx5e_close_sqs(c);
1060         mlx5e_close_sq(&c->icosq);
1061         napi_disable(&c->napi);
1062         mlx5e_close_cq(&c->rq.cq);
1063         mlx5e_close_tx_cqs(c);
1064         mlx5e_close_cq(&c->icosq.cq);
1065         netif_napi_del(&c->napi);
1066
1067         napi_hash_del(&c->napi);
1068         synchronize_rcu();
1069
1070         kfree(c);
1071 }
1072
1073 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1074                                  struct mlx5e_rq_param *param)
1075 {
1076         void *rqc = param->rqc;
1077         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1078
1079         switch (priv->params.rq_wq_type) {
1080         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1081                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1082                          MLX5_MPWRQ_LOG_NUM_STRIDES - 9);
1083                 MLX5_SET(wq, wq, log_wqe_stride_size,
1084                          MLX5_MPWRQ_LOG_STRIDE_SIZE - 6);
1085                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1086                 break;
1087         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1088                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1089         }
1090
1091         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1092         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1093         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1094         MLX5_SET(wq, wq, pd,               priv->pdn);
1095         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1096
1097         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1098         param->wq.linear = 1;
1099 }
1100
1101 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1102 {
1103         void *rqc = param->rqc;
1104         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1105
1106         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1107         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1108 }
1109
1110 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1111                                         struct mlx5e_sq_param *param)
1112 {
1113         void *sqc = param->sqc;
1114         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1115
1116         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1117         MLX5_SET(wq, wq, pd,            priv->pdn);
1118
1119         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1120 }
1121
1122 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1123                                  struct mlx5e_sq_param *param)
1124 {
1125         void *sqc = param->sqc;
1126         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1127
1128         mlx5e_build_sq_param_common(priv, param);
1129         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1130
1131         param->max_inline = priv->params.tx_max_inline;
1132 }
1133
1134 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1135                                         struct mlx5e_cq_param *param)
1136 {
1137         void *cqc = param->cqc;
1138
1139         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1140 }
1141
1142 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1143                                     struct mlx5e_cq_param *param)
1144 {
1145         void *cqc = param->cqc;
1146         u8 log_cq_size;
1147
1148         switch (priv->params.rq_wq_type) {
1149         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1150                 log_cq_size = priv->params.log_rq_size +
1151                         MLX5_MPWRQ_LOG_NUM_STRIDES;
1152                 break;
1153         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1154                 log_cq_size = priv->params.log_rq_size;
1155         }
1156
1157         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1158
1159         mlx5e_build_common_cq_param(priv, param);
1160 }
1161
1162 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1163                                     struct mlx5e_cq_param *param)
1164 {
1165         void *cqc = param->cqc;
1166
1167         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1168
1169         mlx5e_build_common_cq_param(priv, param);
1170 }
1171
1172 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1173                                      struct mlx5e_cq_param *param,
1174                                      u8 log_wq_size)
1175 {
1176         void *cqc = param->cqc;
1177
1178         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1179
1180         mlx5e_build_common_cq_param(priv, param);
1181 }
1182
1183 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1184                                     struct mlx5e_sq_param *param,
1185                                     u8 log_wq_size)
1186 {
1187         void *sqc = param->sqc;
1188         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1189
1190         mlx5e_build_sq_param_common(priv, param);
1191
1192         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1193         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1194
1195         param->icosq = true;
1196 }
1197
1198 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1199                                       struct mlx5e_channel_param *cparam)
1200 {
1201         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1202
1203         memset(cparam, 0, sizeof(*cparam));
1204
1205         mlx5e_build_rq_param(priv, &cparam->rq);
1206         mlx5e_build_sq_param(priv, &cparam->sq);
1207         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1208         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1209         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1210         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1211 }
1212
1213 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1214 {
1215         struct mlx5e_channel_param cparam;
1216         int nch = priv->params.num_channels;
1217         int err = -ENOMEM;
1218         int i;
1219         int j;
1220
1221         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1222                                 GFP_KERNEL);
1223
1224         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1225                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1226
1227         if (!priv->channel || !priv->txq_to_sq_map)
1228                 goto err_free_txq_to_sq_map;
1229
1230         mlx5e_build_channel_param(priv, &cparam);
1231         for (i = 0; i < nch; i++) {
1232                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1233                 if (err)
1234                         goto err_close_channels;
1235         }
1236
1237         for (j = 0; j < nch; j++) {
1238                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1239                 if (err)
1240                         goto err_close_channels;
1241         }
1242
1243         return 0;
1244
1245 err_close_channels:
1246         for (i--; i >= 0; i--)
1247                 mlx5e_close_channel(priv->channel[i]);
1248
1249 err_free_txq_to_sq_map:
1250         kfree(priv->txq_to_sq_map);
1251         kfree(priv->channel);
1252
1253         return err;
1254 }
1255
1256 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1257 {
1258         int i;
1259
1260         for (i = 0; i < priv->params.num_channels; i++)
1261                 mlx5e_close_channel(priv->channel[i]);
1262
1263         kfree(priv->txq_to_sq_map);
1264         kfree(priv->channel);
1265 }
1266
1267 static int mlx5e_rx_hash_fn(int hfunc)
1268 {
1269         return (hfunc == ETH_RSS_HASH_TOP) ?
1270                MLX5_RX_HASH_FN_TOEPLITZ :
1271                MLX5_RX_HASH_FN_INVERTED_XOR8;
1272 }
1273
1274 static int mlx5e_bits_invert(unsigned long a, int size)
1275 {
1276         int inv = 0;
1277         int i;
1278
1279         for (i = 0; i < size; i++)
1280                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1281
1282         return inv;
1283 }
1284
1285 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1286 {
1287         int i;
1288
1289         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1290                 int ix = i;
1291
1292                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1293                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1294
1295                 ix = priv->params.indirection_rqt[ix];
1296                 MLX5_SET(rqtc, rqtc, rq_num[i],
1297                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1298                          priv->channel[ix]->rq.rqn :
1299                          priv->drop_rq.rqn);
1300         }
1301 }
1302
1303 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1304                                 enum mlx5e_rqt_ix rqt_ix)
1305 {
1306
1307         switch (rqt_ix) {
1308         case MLX5E_INDIRECTION_RQT:
1309                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1310
1311                 break;
1312
1313         default: /* MLX5E_SINGLE_RQ_RQT */
1314                 MLX5_SET(rqtc, rqtc, rq_num[0],
1315                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1316                          priv->channel[0]->rq.rqn :
1317                          priv->drop_rq.rqn);
1318
1319                 break;
1320         }
1321 }
1322
1323 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1324 {
1325         struct mlx5_core_dev *mdev = priv->mdev;
1326         u32 *in;
1327         void *rqtc;
1328         int inlen;
1329         int sz;
1330         int err;
1331
1332         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1333
1334         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1335         in = mlx5_vzalloc(inlen);
1336         if (!in)
1337                 return -ENOMEM;
1338
1339         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1340
1341         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1342         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1343
1344         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1345
1346         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1347
1348         kvfree(in);
1349
1350         return err;
1351 }
1352
1353 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1354 {
1355         struct mlx5_core_dev *mdev = priv->mdev;
1356         u32 *in;
1357         void *rqtc;
1358         int inlen;
1359         int sz;
1360         int err;
1361
1362         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1363
1364         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1365         in = mlx5_vzalloc(inlen);
1366         if (!in)
1367                 return -ENOMEM;
1368
1369         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1370
1371         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1372
1373         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1374
1375         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1376
1377         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1378
1379         kvfree(in);
1380
1381         return err;
1382 }
1383
1384 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1385 {
1386         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1387 }
1388
1389 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1390 {
1391         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1392         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1393 }
1394
1395 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1396 {
1397         if (!priv->params.lro_en)
1398                 return;
1399
1400 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1401
1402         MLX5_SET(tirc, tirc, lro_enable_mask,
1403                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1404                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1405         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1406                  (priv->params.lro_wqe_sz -
1407                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1408         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1409                  MLX5_CAP_ETH(priv->mdev,
1410                               lro_timer_supported_periods[2]));
1411 }
1412
1413 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1414 {
1415         MLX5_SET(tirc, tirc, rx_hash_fn,
1416                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1417         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1418                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1419                                              rx_hash_toeplitz_key);
1420                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1421                                                rx_hash_toeplitz_key);
1422
1423                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1424                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1425         }
1426 }
1427
1428 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1429 {
1430         struct mlx5_core_dev *mdev = priv->mdev;
1431
1432         void *in;
1433         void *tirc;
1434         int inlen;
1435         int err;
1436         int tt;
1437
1438         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1439         in = mlx5_vzalloc(inlen);
1440         if (!in)
1441                 return -ENOMEM;
1442
1443         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1444         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1445
1446         mlx5e_build_tir_ctx_lro(tirc, priv);
1447
1448         for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1449                 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1450                 if (err)
1451                         break;
1452         }
1453
1454         kvfree(in);
1455
1456         return err;
1457 }
1458
1459 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1460                                                   u32 tirn)
1461 {
1462         void *in;
1463         int inlen;
1464         int err;
1465
1466         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1467         in = mlx5_vzalloc(inlen);
1468         if (!in)
1469                 return -ENOMEM;
1470
1471         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1472
1473         err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1474
1475         kvfree(in);
1476
1477         return err;
1478 }
1479
1480 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1481 {
1482         int err;
1483         int i;
1484
1485         for (i = 0; i < MLX5E_NUM_TT; i++) {
1486                 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1487                                                              priv->tirn[i]);
1488                 if (err)
1489                         return err;
1490         }
1491
1492         return 0;
1493 }
1494
1495 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1496 {
1497         struct mlx5e_priv *priv = netdev_priv(netdev);
1498         struct mlx5_core_dev *mdev = priv->mdev;
1499         int hw_mtu;
1500         int err;
1501
1502         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1503         if (err)
1504                 return err;
1505
1506         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1507
1508         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1509                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1510                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1511
1512         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1513         return 0;
1514 }
1515
1516 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1517 {
1518         struct mlx5e_priv *priv = netdev_priv(netdev);
1519         int nch = priv->params.num_channels;
1520         int ntc = priv->params.num_tc;
1521         int tc;
1522
1523         netdev_reset_tc(netdev);
1524
1525         if (ntc == 1)
1526                 return;
1527
1528         netdev_set_num_tc(netdev, ntc);
1529
1530         for (tc = 0; tc < ntc; tc++)
1531                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1532 }
1533
1534 int mlx5e_open_locked(struct net_device *netdev)
1535 {
1536         struct mlx5e_priv *priv = netdev_priv(netdev);
1537         int num_txqs;
1538         int err;
1539
1540         set_bit(MLX5E_STATE_OPENED, &priv->state);
1541
1542         mlx5e_netdev_set_tcs(netdev);
1543
1544         num_txqs = priv->params.num_channels * priv->params.num_tc;
1545         netif_set_real_num_tx_queues(netdev, num_txqs);
1546         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1547
1548         err = mlx5e_set_dev_port_mtu(netdev);
1549         if (err)
1550                 goto err_clear_state_opened_flag;
1551
1552         err = mlx5e_open_channels(priv);
1553         if (err) {
1554                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1555                            __func__, err);
1556                 goto err_clear_state_opened_flag;
1557         }
1558
1559         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1560         if (err) {
1561                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1562                            __func__, err);
1563                 goto err_close_channels;
1564         }
1565
1566         mlx5e_redirect_rqts(priv);
1567         mlx5e_update_carrier(priv);
1568         mlx5e_timestamp_init(priv);
1569
1570         schedule_delayed_work(&priv->update_stats_work, 0);
1571
1572         return 0;
1573
1574 err_close_channels:
1575         mlx5e_close_channels(priv);
1576 err_clear_state_opened_flag:
1577         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1578         return err;
1579 }
1580
1581 static int mlx5e_open(struct net_device *netdev)
1582 {
1583         struct mlx5e_priv *priv = netdev_priv(netdev);
1584         int err;
1585
1586         mutex_lock(&priv->state_lock);
1587         err = mlx5e_open_locked(netdev);
1588         mutex_unlock(&priv->state_lock);
1589
1590         return err;
1591 }
1592
1593 int mlx5e_close_locked(struct net_device *netdev)
1594 {
1595         struct mlx5e_priv *priv = netdev_priv(netdev);
1596
1597         /* May already be CLOSED in case a previous configuration operation
1598          * (e.g RX/TX queue size change) that involves close&open failed.
1599          */
1600         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1601                 return 0;
1602
1603         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1604
1605         mlx5e_timestamp_cleanup(priv);
1606         netif_carrier_off(priv->netdev);
1607         mlx5e_redirect_rqts(priv);
1608         mlx5e_close_channels(priv);
1609
1610         return 0;
1611 }
1612
1613 static int mlx5e_close(struct net_device *netdev)
1614 {
1615         struct mlx5e_priv *priv = netdev_priv(netdev);
1616         int err;
1617
1618         mutex_lock(&priv->state_lock);
1619         err = mlx5e_close_locked(netdev);
1620         mutex_unlock(&priv->state_lock);
1621
1622         return err;
1623 }
1624
1625 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1626                                 struct mlx5e_rq *rq,
1627                                 struct mlx5e_rq_param *param)
1628 {
1629         struct mlx5_core_dev *mdev = priv->mdev;
1630         void *rqc = param->rqc;
1631         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1632         int err;
1633
1634         param->wq.db_numa_node = param->wq.buf_numa_node;
1635
1636         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1637                                 &rq->wq_ctrl);
1638         if (err)
1639                 return err;
1640
1641         rq->priv = priv;
1642
1643         return 0;
1644 }
1645
1646 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1647                                 struct mlx5e_cq *cq,
1648                                 struct mlx5e_cq_param *param)
1649 {
1650         struct mlx5_core_dev *mdev = priv->mdev;
1651         struct mlx5_core_cq *mcq = &cq->mcq;
1652         int eqn_not_used;
1653         unsigned int irqn;
1654         int err;
1655
1656         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1657                                &cq->wq_ctrl);
1658         if (err)
1659                 return err;
1660
1661         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1662
1663         mcq->cqe_sz     = 64;
1664         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1665         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1666         *mcq->set_ci_db = 0;
1667         *mcq->arm_db    = 0;
1668         mcq->vector     = param->eq_ix;
1669         mcq->comp       = mlx5e_completion_event;
1670         mcq->event      = mlx5e_cq_error_event;
1671         mcq->irqn       = irqn;
1672         mcq->uar        = &priv->cq_uar;
1673
1674         cq->priv = priv;
1675
1676         return 0;
1677 }
1678
1679 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1680 {
1681         struct mlx5e_cq_param cq_param;
1682         struct mlx5e_rq_param rq_param;
1683         struct mlx5e_rq *rq = &priv->drop_rq;
1684         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1685         int err;
1686
1687         memset(&cq_param, 0, sizeof(cq_param));
1688         memset(&rq_param, 0, sizeof(rq_param));
1689         mlx5e_build_drop_rq_param(&rq_param);
1690
1691         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1692         if (err)
1693                 return err;
1694
1695         err = mlx5e_enable_cq(cq, &cq_param);
1696         if (err)
1697                 goto err_destroy_cq;
1698
1699         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1700         if (err)
1701                 goto err_disable_cq;
1702
1703         err = mlx5e_enable_rq(rq, &rq_param);
1704         if (err)
1705                 goto err_destroy_rq;
1706
1707         return 0;
1708
1709 err_destroy_rq:
1710         mlx5e_destroy_rq(&priv->drop_rq);
1711
1712 err_disable_cq:
1713         mlx5e_disable_cq(&priv->drop_rq.cq);
1714
1715 err_destroy_cq:
1716         mlx5e_destroy_cq(&priv->drop_rq.cq);
1717
1718         return err;
1719 }
1720
1721 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1722 {
1723         mlx5e_disable_rq(&priv->drop_rq);
1724         mlx5e_destroy_rq(&priv->drop_rq);
1725         mlx5e_disable_cq(&priv->drop_rq.cq);
1726         mlx5e_destroy_cq(&priv->drop_rq.cq);
1727 }
1728
1729 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1730 {
1731         struct mlx5_core_dev *mdev = priv->mdev;
1732         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1733         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1734
1735         memset(in, 0, sizeof(in));
1736
1737         MLX5_SET(tisc, tisc, prio, tc << 1);
1738         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1739
1740         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1741 }
1742
1743 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1744 {
1745         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1746 }
1747
1748 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1749 {
1750         int err;
1751         int tc;
1752
1753         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1754                 err = mlx5e_create_tis(priv, tc);
1755                 if (err)
1756                         goto err_close_tises;
1757         }
1758
1759         return 0;
1760
1761 err_close_tises:
1762         for (tc--; tc >= 0; tc--)
1763                 mlx5e_destroy_tis(priv, tc);
1764
1765         return err;
1766 }
1767
1768 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1769 {
1770         int tc;
1771
1772         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1773                 mlx5e_destroy_tis(priv, tc);
1774 }
1775
1776 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1777 {
1778         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1779
1780         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1781
1782 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1783                                  MLX5_HASH_FIELD_SEL_DST_IP)
1784
1785 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1786                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1787                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1788                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1789
1790 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1791                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1792                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1793
1794         mlx5e_build_tir_ctx_lro(tirc, priv);
1795
1796         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1797
1798         switch (tt) {
1799         case MLX5E_TT_ANY:
1800                 MLX5_SET(tirc, tirc, indirect_table,
1801                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1802                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1803                 break;
1804         default:
1805                 MLX5_SET(tirc, tirc, indirect_table,
1806                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1807                 mlx5e_build_tir_ctx_hash(tirc, priv);
1808                 break;
1809         }
1810
1811         switch (tt) {
1812         case MLX5E_TT_IPV4_TCP:
1813                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1814                          MLX5_L3_PROT_TYPE_IPV4);
1815                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1816                          MLX5_L4_PROT_TYPE_TCP);
1817                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1818                          MLX5_HASH_IP_L4PORTS);
1819                 break;
1820
1821         case MLX5E_TT_IPV6_TCP:
1822                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1823                          MLX5_L3_PROT_TYPE_IPV6);
1824                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1825                          MLX5_L4_PROT_TYPE_TCP);
1826                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1827                          MLX5_HASH_IP_L4PORTS);
1828                 break;
1829
1830         case MLX5E_TT_IPV4_UDP:
1831                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1832                          MLX5_L3_PROT_TYPE_IPV4);
1833                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1834                          MLX5_L4_PROT_TYPE_UDP);
1835                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1836                          MLX5_HASH_IP_L4PORTS);
1837                 break;
1838
1839         case MLX5E_TT_IPV6_UDP:
1840                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1841                          MLX5_L3_PROT_TYPE_IPV6);
1842                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1843                          MLX5_L4_PROT_TYPE_UDP);
1844                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1845                          MLX5_HASH_IP_L4PORTS);
1846                 break;
1847
1848         case MLX5E_TT_IPV4_IPSEC_AH:
1849                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1850                          MLX5_L3_PROT_TYPE_IPV4);
1851                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1852                          MLX5_HASH_IP_IPSEC_SPI);
1853                 break;
1854
1855         case MLX5E_TT_IPV6_IPSEC_AH:
1856                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1857                          MLX5_L3_PROT_TYPE_IPV6);
1858                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1859                          MLX5_HASH_IP_IPSEC_SPI);
1860                 break;
1861
1862         case MLX5E_TT_IPV4_IPSEC_ESP:
1863                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1864                          MLX5_L3_PROT_TYPE_IPV4);
1865                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1866                          MLX5_HASH_IP_IPSEC_SPI);
1867                 break;
1868
1869         case MLX5E_TT_IPV6_IPSEC_ESP:
1870                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1871                          MLX5_L3_PROT_TYPE_IPV6);
1872                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1873                          MLX5_HASH_IP_IPSEC_SPI);
1874                 break;
1875
1876         case MLX5E_TT_IPV4:
1877                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1878                          MLX5_L3_PROT_TYPE_IPV4);
1879                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1880                          MLX5_HASH_IP);
1881                 break;
1882
1883         case MLX5E_TT_IPV6:
1884                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1885                          MLX5_L3_PROT_TYPE_IPV6);
1886                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1887                          MLX5_HASH_IP);
1888                 break;
1889         }
1890 }
1891
1892 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1893 {
1894         struct mlx5_core_dev *mdev = priv->mdev;
1895         u32 *in;
1896         void *tirc;
1897         int inlen;
1898         int err;
1899
1900         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1901         in = mlx5_vzalloc(inlen);
1902         if (!in)
1903                 return -ENOMEM;
1904
1905         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1906
1907         mlx5e_build_tir_ctx(priv, tirc, tt);
1908
1909         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1910
1911         kvfree(in);
1912
1913         return err;
1914 }
1915
1916 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1917 {
1918         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1919 }
1920
1921 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1922 {
1923         int err;
1924         int i;
1925
1926         for (i = 0; i < MLX5E_NUM_TT; i++) {
1927                 err = mlx5e_create_tir(priv, i);
1928                 if (err)
1929                         goto err_destroy_tirs;
1930         }
1931
1932         return 0;
1933
1934 err_destroy_tirs:
1935         for (i--; i >= 0; i--)
1936                 mlx5e_destroy_tir(priv, i);
1937
1938         return err;
1939 }
1940
1941 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1942 {
1943         int i;
1944
1945         for (i = 0; i < MLX5E_NUM_TT; i++)
1946                 mlx5e_destroy_tir(priv, i);
1947 }
1948
1949 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1950 {
1951         struct mlx5e_priv *priv = netdev_priv(netdev);
1952         bool was_opened;
1953         int err = 0;
1954
1955         if (tc && tc != MLX5E_MAX_NUM_TC)
1956                 return -EINVAL;
1957
1958         mutex_lock(&priv->state_lock);
1959
1960         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1961         if (was_opened)
1962                 mlx5e_close_locked(priv->netdev);
1963
1964         priv->params.num_tc = tc ? tc : 1;
1965
1966         if (was_opened)
1967                 err = mlx5e_open_locked(priv->netdev);
1968
1969         mutex_unlock(&priv->state_lock);
1970
1971         return err;
1972 }
1973
1974 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1975                               __be16 proto, struct tc_to_netdev *tc)
1976 {
1977         struct mlx5e_priv *priv = netdev_priv(dev);
1978
1979         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
1980                 goto mqprio;
1981
1982         switch (tc->type) {
1983         case TC_SETUP_CLSFLOWER:
1984                 switch (tc->cls_flower->command) {
1985                 case TC_CLSFLOWER_REPLACE:
1986                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
1987                 case TC_CLSFLOWER_DESTROY:
1988                         return mlx5e_delete_flower(priv, tc->cls_flower);
1989                 }
1990         default:
1991                 return -EOPNOTSUPP;
1992         }
1993
1994 mqprio:
1995         if (tc->type != TC_SETUP_MQPRIO)
1996                 return -EINVAL;
1997
1998         return mlx5e_setup_tc(dev, tc->tc);
1999 }
2000
2001 static struct rtnl_link_stats64 *
2002 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2003 {
2004         struct mlx5e_priv *priv = netdev_priv(dev);
2005         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2006         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2007         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2008
2009         stats->rx_packets = sstats->rx_packets;
2010         stats->rx_bytes   = sstats->rx_bytes;
2011         stats->tx_packets = sstats->tx_packets;
2012         stats->tx_bytes   = sstats->tx_bytes;
2013
2014         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2015         stats->tx_dropped = sstats->tx_queue_dropped;
2016
2017         stats->rx_length_errors =
2018                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2019                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2020                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2021         stats->rx_crc_errors =
2022                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2023         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2024         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2025         stats->tx_carrier_errors =
2026                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2027         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2028                            stats->rx_frame_errors;
2029         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2030
2031         /* vport multicast also counts packets that are dropped due to steering
2032          * or rx out of buffer
2033          */
2034         stats->multicast =
2035                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2036
2037         return stats;
2038 }
2039
2040 static void mlx5e_set_rx_mode(struct net_device *dev)
2041 {
2042         struct mlx5e_priv *priv = netdev_priv(dev);
2043
2044         schedule_work(&priv->set_rx_mode_work);
2045 }
2046
2047 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2048 {
2049         struct mlx5e_priv *priv = netdev_priv(netdev);
2050         struct sockaddr *saddr = addr;
2051
2052         if (!is_valid_ether_addr(saddr->sa_data))
2053                 return -EADDRNOTAVAIL;
2054
2055         netif_addr_lock_bh(netdev);
2056         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2057         netif_addr_unlock_bh(netdev);
2058
2059         schedule_work(&priv->set_rx_mode_work);
2060
2061         return 0;
2062 }
2063
2064 static int mlx5e_set_features(struct net_device *netdev,
2065                               netdev_features_t features)
2066 {
2067         struct mlx5e_priv *priv = netdev_priv(netdev);
2068         int err = 0;
2069         netdev_features_t changes = features ^ netdev->features;
2070
2071         mutex_lock(&priv->state_lock);
2072
2073         if (changes & NETIF_F_LRO) {
2074                 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2075
2076                 if (was_opened && (priv->params.rq_wq_type ==
2077                                    MLX5_WQ_TYPE_LINKED_LIST))
2078                         mlx5e_close_locked(priv->netdev);
2079
2080                 priv->params.lro_en = !!(features & NETIF_F_LRO);
2081                 err = mlx5e_modify_tirs_lro(priv);
2082                 if (err)
2083                         mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
2084                                        err);
2085
2086                 if (was_opened && (priv->params.rq_wq_type ==
2087                                    MLX5_WQ_TYPE_LINKED_LIST))
2088                         err = mlx5e_open_locked(priv->netdev);
2089         }
2090
2091         mutex_unlock(&priv->state_lock);
2092
2093         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
2094                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
2095                         mlx5e_enable_vlan_filter(priv);
2096                 else
2097                         mlx5e_disable_vlan_filter(priv);
2098         }
2099
2100         if ((changes & NETIF_F_HW_TC) && !(features & NETIF_F_HW_TC) &&
2101             mlx5e_tc_num_filters(priv)) {
2102                 netdev_err(netdev,
2103                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2104                 return -EINVAL;
2105         }
2106
2107         return err;
2108 }
2109
2110 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2111 {
2112         struct mlx5e_priv *priv = netdev_priv(netdev);
2113         struct mlx5_core_dev *mdev = priv->mdev;
2114         bool was_opened;
2115         int max_mtu;
2116         int err = 0;
2117
2118         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2119
2120         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2121
2122         if (new_mtu > max_mtu) {
2123                 netdev_err(netdev,
2124                            "%s: Bad MTU (%d) > (%d) Max\n",
2125                            __func__, new_mtu, max_mtu);
2126                 return -EINVAL;
2127         }
2128
2129         mutex_lock(&priv->state_lock);
2130
2131         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2132         if (was_opened)
2133                 mlx5e_close_locked(netdev);
2134
2135         netdev->mtu = new_mtu;
2136
2137         if (was_opened)
2138                 err = mlx5e_open_locked(netdev);
2139
2140         mutex_unlock(&priv->state_lock);
2141
2142         return err;
2143 }
2144
2145 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2146 {
2147         switch (cmd) {
2148         case SIOCSHWTSTAMP:
2149                 return mlx5e_hwstamp_set(dev, ifr);
2150         case SIOCGHWTSTAMP:
2151                 return mlx5e_hwstamp_get(dev, ifr);
2152         default:
2153                 return -EOPNOTSUPP;
2154         }
2155 }
2156
2157 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2158 {
2159         struct mlx5e_priv *priv = netdev_priv(dev);
2160         struct mlx5_core_dev *mdev = priv->mdev;
2161
2162         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2163 }
2164
2165 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2166 {
2167         struct mlx5e_priv *priv = netdev_priv(dev);
2168         struct mlx5_core_dev *mdev = priv->mdev;
2169
2170         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2171                                            vlan, qos);
2172 }
2173
2174 static int mlx5_vport_link2ifla(u8 esw_link)
2175 {
2176         switch (esw_link) {
2177         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2178                 return IFLA_VF_LINK_STATE_DISABLE;
2179         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2180                 return IFLA_VF_LINK_STATE_ENABLE;
2181         }
2182         return IFLA_VF_LINK_STATE_AUTO;
2183 }
2184
2185 static int mlx5_ifla_link2vport(u8 ifla_link)
2186 {
2187         switch (ifla_link) {
2188         case IFLA_VF_LINK_STATE_DISABLE:
2189                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2190         case IFLA_VF_LINK_STATE_ENABLE:
2191                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2192         }
2193         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2194 }
2195
2196 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2197                                    int link_state)
2198 {
2199         struct mlx5e_priv *priv = netdev_priv(dev);
2200         struct mlx5_core_dev *mdev = priv->mdev;
2201
2202         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2203                                             mlx5_ifla_link2vport(link_state));
2204 }
2205
2206 static int mlx5e_get_vf_config(struct net_device *dev,
2207                                int vf, struct ifla_vf_info *ivi)
2208 {
2209         struct mlx5e_priv *priv = netdev_priv(dev);
2210         struct mlx5_core_dev *mdev = priv->mdev;
2211         int err;
2212
2213         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2214         if (err)
2215                 return err;
2216         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2217         return 0;
2218 }
2219
2220 static int mlx5e_get_vf_stats(struct net_device *dev,
2221                               int vf, struct ifla_vf_stats *vf_stats)
2222 {
2223         struct mlx5e_priv *priv = netdev_priv(dev);
2224         struct mlx5_core_dev *mdev = priv->mdev;
2225
2226         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2227                                             vf_stats);
2228 }
2229
2230 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2231                                  sa_family_t sa_family, __be16 port)
2232 {
2233         struct mlx5e_priv *priv = netdev_priv(netdev);
2234
2235         if (!mlx5e_vxlan_allowed(priv->mdev))
2236                 return;
2237
2238         mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2239 }
2240
2241 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2242                                  sa_family_t sa_family, __be16 port)
2243 {
2244         struct mlx5e_priv *priv = netdev_priv(netdev);
2245
2246         if (!mlx5e_vxlan_allowed(priv->mdev))
2247                 return;
2248
2249         mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2250 }
2251
2252 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2253                                                     struct sk_buff *skb,
2254                                                     netdev_features_t features)
2255 {
2256         struct udphdr *udph;
2257         u16 proto;
2258         u16 port = 0;
2259
2260         switch (vlan_get_protocol(skb)) {
2261         case htons(ETH_P_IP):
2262                 proto = ip_hdr(skb)->protocol;
2263                 break;
2264         case htons(ETH_P_IPV6):
2265                 proto = ipv6_hdr(skb)->nexthdr;
2266                 break;
2267         default:
2268                 goto out;
2269         }
2270
2271         if (proto == IPPROTO_UDP) {
2272                 udph = udp_hdr(skb);
2273                 port = be16_to_cpu(udph->dest);
2274         }
2275
2276         /* Verify if UDP port is being offloaded by HW */
2277         if (port && mlx5e_vxlan_lookup_port(priv, port))
2278                 return features;
2279
2280 out:
2281         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2282         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2283 }
2284
2285 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2286                                               struct net_device *netdev,
2287                                               netdev_features_t features)
2288 {
2289         struct mlx5e_priv *priv = netdev_priv(netdev);
2290
2291         features = vlan_features_check(skb, features);
2292         features = vxlan_features_check(skb, features);
2293
2294         /* Validate if the tunneled packet is being offloaded by HW */
2295         if (skb->encapsulation &&
2296             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2297                 return mlx5e_vxlan_features_check(priv, skb, features);
2298
2299         return features;
2300 }
2301
2302 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2303         .ndo_open                = mlx5e_open,
2304         .ndo_stop                = mlx5e_close,
2305         .ndo_start_xmit          = mlx5e_xmit,
2306         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2307         .ndo_select_queue        = mlx5e_select_queue,
2308         .ndo_get_stats64         = mlx5e_get_stats,
2309         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2310         .ndo_set_mac_address     = mlx5e_set_mac,
2311         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2312         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2313         .ndo_set_features        = mlx5e_set_features,
2314         .ndo_change_mtu          = mlx5e_change_mtu,
2315         .ndo_do_ioctl            = mlx5e_ioctl,
2316 };
2317
2318 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2319         .ndo_open                = mlx5e_open,
2320         .ndo_stop                = mlx5e_close,
2321         .ndo_start_xmit          = mlx5e_xmit,
2322         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2323         .ndo_select_queue        = mlx5e_select_queue,
2324         .ndo_get_stats64         = mlx5e_get_stats,
2325         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2326         .ndo_set_mac_address     = mlx5e_set_mac,
2327         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2328         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2329         .ndo_set_features        = mlx5e_set_features,
2330         .ndo_change_mtu          = mlx5e_change_mtu,
2331         .ndo_do_ioctl            = mlx5e_ioctl,
2332         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2333         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2334         .ndo_features_check      = mlx5e_features_check,
2335         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2336         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2337         .ndo_get_vf_config       = mlx5e_get_vf_config,
2338         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2339         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2340 };
2341
2342 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2343 {
2344         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2345                 return -ENOTSUPP;
2346         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2347             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2348             !MLX5_CAP_ETH(mdev, csum_cap) ||
2349             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2350             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2351             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2352             MLX5_CAP_FLOWTABLE(mdev,
2353                                flow_table_properties_nic_receive.max_ft_level)
2354                                < 3) {
2355                 mlx5_core_warn(mdev,
2356                                "Not creating net device, some required device capabilities are missing\n");
2357                 return -ENOTSUPP;
2358         }
2359         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2360                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2361         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2362                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2363
2364         return 0;
2365 }
2366
2367 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2368 {
2369         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2370
2371         return bf_buf_size -
2372                sizeof(struct mlx5e_tx_wqe) +
2373                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2374 }
2375
2376 #ifdef CONFIG_MLX5_CORE_EN_DCB
2377 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2378 {
2379         int i;
2380
2381         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2382         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2383                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2384                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2385                 priv->params.ets.prio_tc[i] = i;
2386         }
2387
2388         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2389         priv->params.ets.prio_tc[0] = 1;
2390         priv->params.ets.prio_tc[1] = 0;
2391 }
2392 #endif
2393
2394 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2395                                    u32 *indirection_rqt, int len,
2396                                    int num_channels)
2397 {
2398         int node = mdev->priv.numa_node;
2399         int node_num_of_cores;
2400         int i;
2401
2402         if (node == -1)
2403                 node = first_online_node;
2404
2405         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2406
2407         if (node_num_of_cores)
2408                 num_channels = min_t(int, num_channels, node_num_of_cores);
2409
2410         for (i = 0; i < len; i++)
2411                 indirection_rqt[i] = i % num_channels;
2412 }
2413
2414 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2415 {
2416         return MLX5_CAP_GEN(mdev, striding_rq) &&
2417                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2418                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2419 }
2420
2421 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2422                                     struct net_device *netdev,
2423                                     int num_channels)
2424 {
2425         struct mlx5e_priv *priv = netdev_priv(netdev);
2426
2427         priv->params.log_sq_size           =
2428                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2429         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2430                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2431                 MLX5_WQ_TYPE_LINKED_LIST;
2432
2433         switch (priv->params.rq_wq_type) {
2434         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2435                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2436                 priv->params.lro_en = true;
2437                 break;
2438         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2439                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2440         }
2441
2442         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2443                                             BIT(priv->params.log_rq_size));
2444         priv->params.rx_cq_moderation_usec =
2445                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2446         priv->params.rx_cq_moderation_pkts =
2447                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2448         priv->params.tx_cq_moderation_usec =
2449                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2450         priv->params.tx_cq_moderation_pkts =
2451                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2452         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2453         priv->params.num_tc                = 1;
2454         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2455
2456         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2457                             sizeof(priv->params.toeplitz_hash_key));
2458
2459         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2460                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2461
2462         priv->params.lro_wqe_sz            =
2463                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2464
2465         priv->mdev                         = mdev;
2466         priv->netdev                       = netdev;
2467         priv->params.num_channels          = num_channels;
2468
2469 #ifdef CONFIG_MLX5_CORE_EN_DCB
2470         mlx5e_ets_init(priv);
2471 #endif
2472
2473         mutex_init(&priv->state_lock);
2474
2475         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2476         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2477         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2478 }
2479
2480 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2481 {
2482         struct mlx5e_priv *priv = netdev_priv(netdev);
2483
2484         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2485         if (is_zero_ether_addr(netdev->dev_addr) &&
2486             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2487                 eth_hw_addr_random(netdev);
2488                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2489         }
2490 }
2491
2492 static void mlx5e_build_netdev(struct net_device *netdev)
2493 {
2494         struct mlx5e_priv *priv = netdev_priv(netdev);
2495         struct mlx5_core_dev *mdev = priv->mdev;
2496
2497         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2498
2499         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2500                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2501 #ifdef CONFIG_MLX5_CORE_EN_DCB
2502                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2503 #endif
2504         } else {
2505                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2506         }
2507
2508         netdev->watchdog_timeo    = 15 * HZ;
2509
2510         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2511
2512         netdev->vlan_features    |= NETIF_F_SG;
2513         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2514         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2515         netdev->vlan_features    |= NETIF_F_GRO;
2516         netdev->vlan_features    |= NETIF_F_TSO;
2517         netdev->vlan_features    |= NETIF_F_TSO6;
2518         netdev->vlan_features    |= NETIF_F_RXCSUM;
2519         netdev->vlan_features    |= NETIF_F_RXHASH;
2520
2521         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2522                 netdev->vlan_features    |= NETIF_F_LRO;
2523
2524         netdev->hw_features       = netdev->vlan_features;
2525         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2526         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2527         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2528
2529         if (mlx5e_vxlan_allowed(mdev)) {
2530                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
2531                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2532                 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2533                 netdev->hw_enc_features |= NETIF_F_TSO;
2534                 netdev->hw_enc_features |= NETIF_F_TSO6;
2535                 netdev->hw_enc_features |= NETIF_F_RXHASH;
2536                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2537         }
2538
2539         netdev->features          = netdev->hw_features;
2540         if (!priv->params.lro_en)
2541                 netdev->features  &= ~NETIF_F_LRO;
2542
2543 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2544         if (FT_CAP(flow_modify_en) &&
2545             FT_CAP(modify_root) &&
2546             FT_CAP(identified_miss_table_mode) &&
2547             FT_CAP(flow_table_modify))
2548                 priv->netdev->hw_features      |= NETIF_F_HW_TC;
2549
2550         netdev->features         |= NETIF_F_HIGHDMA;
2551
2552         netdev->priv_flags       |= IFF_UNICAST_FLT;
2553
2554         mlx5e_set_netdev_dev_addr(netdev);
2555 }
2556
2557 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2558                              struct mlx5_core_mkey *mkey)
2559 {
2560         struct mlx5_core_dev *mdev = priv->mdev;
2561         struct mlx5_create_mkey_mbox_in *in;
2562         int err;
2563
2564         in = mlx5_vzalloc(sizeof(*in));
2565         if (!in)
2566                 return -ENOMEM;
2567
2568         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2569                         MLX5_PERM_LOCAL_READ  |
2570                         MLX5_ACCESS_MODE_PA;
2571         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2572         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2573
2574         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2575                                     NULL);
2576
2577         kvfree(in);
2578
2579         return err;
2580 }
2581
2582 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2583 {
2584         struct mlx5_core_dev *mdev = priv->mdev;
2585         int err;
2586
2587         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2588         if (err) {
2589                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2590                 priv->q_counter = 0;
2591         }
2592 }
2593
2594 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2595 {
2596         if (!priv->q_counter)
2597                 return;
2598
2599         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2600 }
2601
2602 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2603 {
2604         struct mlx5_core_dev *mdev = priv->mdev;
2605         struct mlx5_create_mkey_mbox_in *in;
2606         struct mlx5_mkey_seg *mkc;
2607         int inlen = sizeof(*in);
2608         u64 npages =
2609                 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2610         int err;
2611
2612         in = mlx5_vzalloc(inlen);
2613         if (!in)
2614                 return -ENOMEM;
2615
2616         mkc = &in->seg;
2617         mkc->status = MLX5_MKEY_STATUS_FREE;
2618         mkc->flags = MLX5_PERM_UMR_EN |
2619                      MLX5_PERM_LOCAL_READ |
2620                      MLX5_PERM_LOCAL_WRITE |
2621                      MLX5_ACCESS_MODE_MTT;
2622
2623         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2624         mkc->flags_pd = cpu_to_be32(priv->pdn);
2625         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
2626         mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
2627         mkc->log2_page_size = PAGE_SHIFT;
2628
2629         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
2630                                     NULL, NULL);
2631
2632         kvfree(in);
2633
2634         return err;
2635 }
2636
2637 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2638 {
2639         struct net_device *netdev;
2640         struct mlx5e_priv *priv;
2641         int nch = mlx5e_get_max_num_channels(mdev);
2642         int err;
2643
2644         if (mlx5e_check_required_hca_cap(mdev))
2645                 return NULL;
2646
2647         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2648                                     nch * MLX5E_MAX_NUM_TC,
2649                                     nch);
2650         if (!netdev) {
2651                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2652                 return NULL;
2653         }
2654
2655         mlx5e_build_netdev_priv(mdev, netdev, nch);
2656         mlx5e_build_netdev(netdev);
2657
2658         netif_carrier_off(netdev);
2659
2660         priv = netdev_priv(netdev);
2661
2662         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2663         if (err) {
2664                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2665                 goto err_free_netdev;
2666         }
2667
2668         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2669         if (err) {
2670                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2671                 goto err_unmap_free_uar;
2672         }
2673
2674         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2675         if (err) {
2676                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2677                 goto err_dealloc_pd;
2678         }
2679
2680         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2681         if (err) {
2682                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2683                 goto err_dealloc_transport_domain;
2684         }
2685
2686         err = mlx5e_create_umr_mkey(priv);
2687         if (err) {
2688                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
2689                 goto err_destroy_mkey;
2690         }
2691
2692         err = mlx5e_create_tises(priv);
2693         if (err) {
2694                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2695                 goto err_destroy_umr_mkey;
2696         }
2697
2698         err = mlx5e_open_drop_rq(priv);
2699         if (err) {
2700                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2701                 goto err_destroy_tises;
2702         }
2703
2704         err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2705         if (err) {
2706                 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2707                 goto err_close_drop_rq;
2708         }
2709
2710         err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2711         if (err) {
2712                 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2713                 goto err_destroy_rqt_indir;
2714         }
2715
2716         err = mlx5e_create_tirs(priv);
2717         if (err) {
2718                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2719                 goto err_destroy_rqt_single;
2720         }
2721
2722         err = mlx5e_create_flow_tables(priv);
2723         if (err) {
2724                 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2725                 goto err_destroy_tirs;
2726         }
2727
2728         mlx5e_create_q_counter(priv);
2729
2730         mlx5e_init_eth_addr(priv);
2731
2732         mlx5e_vxlan_init(priv);
2733
2734         err = mlx5e_tc_init(priv);
2735         if (err)
2736                 goto err_dealloc_q_counters;
2737
2738 #ifdef CONFIG_MLX5_CORE_EN_DCB
2739         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2740 #endif
2741
2742         err = register_netdev(netdev);
2743         if (err) {
2744                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2745                 goto err_tc_cleanup;
2746         }
2747
2748         if (mlx5e_vxlan_allowed(mdev))
2749                 vxlan_get_rx_port(netdev);
2750
2751         mlx5e_enable_async_events(priv);
2752         schedule_work(&priv->set_rx_mode_work);
2753
2754         return priv;
2755
2756 err_tc_cleanup:
2757         mlx5e_tc_cleanup(priv);
2758
2759 err_dealloc_q_counters:
2760         mlx5e_destroy_q_counter(priv);
2761         mlx5e_destroy_flow_tables(priv);
2762
2763 err_destroy_tirs:
2764         mlx5e_destroy_tirs(priv);
2765
2766 err_destroy_rqt_single:
2767         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2768
2769 err_destroy_rqt_indir:
2770         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2771
2772 err_close_drop_rq:
2773         mlx5e_close_drop_rq(priv);
2774
2775 err_destroy_tises:
2776         mlx5e_destroy_tises(priv);
2777
2778 err_destroy_umr_mkey:
2779         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
2780
2781 err_destroy_mkey:
2782         mlx5_core_destroy_mkey(mdev, &priv->mkey);
2783
2784 err_dealloc_transport_domain:
2785         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2786
2787 err_dealloc_pd:
2788         mlx5_core_dealloc_pd(mdev, priv->pdn);
2789
2790 err_unmap_free_uar:
2791         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2792
2793 err_free_netdev:
2794         free_netdev(netdev);
2795
2796         return NULL;
2797 }
2798
2799 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2800 {
2801         struct mlx5e_priv *priv = vpriv;
2802         struct net_device *netdev = priv->netdev;
2803
2804         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2805
2806         schedule_work(&priv->set_rx_mode_work);
2807         mlx5e_disable_async_events(priv);
2808         flush_scheduled_work();
2809         unregister_netdev(netdev);
2810         mlx5e_tc_cleanup(priv);
2811         mlx5e_vxlan_cleanup(priv);
2812         mlx5e_destroy_q_counter(priv);
2813         mlx5e_destroy_flow_tables(priv);
2814         mlx5e_destroy_tirs(priv);
2815         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2816         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2817         mlx5e_close_drop_rq(priv);
2818         mlx5e_destroy_tises(priv);
2819         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
2820         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
2821         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2822         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2823         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2824         free_netdev(netdev);
2825 }
2826
2827 static void *mlx5e_get_netdev(void *vpriv)
2828 {
2829         struct mlx5e_priv *priv = vpriv;
2830
2831         return priv->netdev;
2832 }
2833
2834 static struct mlx5_interface mlx5e_interface = {
2835         .add       = mlx5e_create_netdev,
2836         .remove    = mlx5e_destroy_netdev,
2837         .event     = mlx5e_async_event,
2838         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2839         .get_dev   = mlx5e_get_netdev,
2840 };
2841
2842 void mlx5e_init(void)
2843 {
2844         mlx5_register_interface(&mlx5e_interface);
2845 }
2846
2847 void mlx5e_cleanup(void)
2848 {
2849         mlx5_unregister_interface(&mlx5e_interface);
2850 }