2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include "en_accel/ipsec.h"
36 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
37 struct ethtool_drvinfo *drvinfo)
39 struct mlx5_core_dev *mdev = priv->mdev;
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION,
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
48 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
49 sizeof(drvinfo->bus_info));
52 static void mlx5e_get_drvinfo(struct net_device *dev,
53 struct ethtool_drvinfo *drvinfo)
55 struct mlx5e_priv *priv = netdev_priv(dev);
57 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
60 struct ptys2ethtool_config {
61 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
62 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
66 static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
68 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
70 struct ptys2ethtool_config *cfg; \
71 const unsigned int modes[] = { __VA_ARGS__ }; \
73 cfg = &ptys2ethtool_table[reg_]; \
74 cfg->speed = speed_; \
75 bitmap_zero(cfg->supported, \
76 __ETHTOOL_LINK_MODE_MASK_NBITS); \
77 bitmap_zero(cfg->advertised, \
78 __ETHTOOL_LINK_MODE_MASK_NBITS); \
79 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
80 __set_bit(modes[i], cfg->supported); \
81 __set_bit(modes[i], cfg->advertised); \
85 void mlx5e_build_ptys2ethtool_map(void)
87 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
88 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
89 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
90 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
91 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
92 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
93 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
94 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
95 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
96 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
97 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
98 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
99 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
100 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
101 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
102 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
103 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
104 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
105 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
106 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
107 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
108 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
110 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
112 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
114 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
116 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
118 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
120 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
122 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
124 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
126 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
128 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
130 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
132 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
134 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
136 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
139 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
141 struct mlx5_core_dev *mdev = priv->mdev;
146 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
149 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
151 return err ? 0 : pfc_en_tx | pfc_en_rx;
154 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
156 struct mlx5_core_dev *mdev = priv->mdev;
161 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
164 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
166 return err ? false : rx_pause | tx_pause;
169 #define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
170 #define MLX5E_NUM_RQ_STATS(priv) (NUM_RQ_STATS * (priv)->channels.num)
171 #define MLX5E_NUM_SQ_STATS(priv) \
172 (NUM_SQ_STATS * (priv)->channels.num * (priv)->channels.params.num_tc)
173 #define MLX5E_NUM_PFC_COUNTERS(priv) \
174 ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
175 NUM_PPORT_PER_PRIO_PFC_COUNTERS)
177 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
182 return NUM_SW_COUNTERS +
183 MLX5E_NUM_Q_CNTRS(priv) +
184 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS(priv) +
185 NUM_PCIE_COUNTERS(priv) +
186 MLX5E_NUM_RQ_STATS(priv) +
187 MLX5E_NUM_SQ_STATS(priv) +
188 MLX5E_NUM_PFC_COUNTERS(priv) +
189 ARRAY_SIZE(mlx5e_pme_status_desc) +
190 ARRAY_SIZE(mlx5e_pme_error_desc) +
191 mlx5e_ipsec_get_count(priv);
193 case ETH_SS_PRIV_FLAGS:
194 return ARRAY_SIZE(mlx5e_priv_flags);
196 return mlx5e_self_test_num(priv);
203 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
205 struct mlx5e_priv *priv = netdev_priv(dev);
207 return mlx5e_ethtool_get_sset_count(priv, sset);
210 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
212 int i, j, tc, prio, idx = 0;
213 unsigned long pfc_combined;
216 for (i = 0; i < NUM_SW_COUNTERS; i++)
217 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
220 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
221 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
224 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
225 strcpy(data + (idx++) * ETH_GSTRING_LEN,
226 vport_stats_desc[i].format);
229 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
230 strcpy(data + (idx++) * ETH_GSTRING_LEN,
231 pport_802_3_stats_desc[i].format);
233 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
234 strcpy(data + (idx++) * ETH_GSTRING_LEN,
235 pport_2863_stats_desc[i].format);
237 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
238 strcpy(data + (idx++) * ETH_GSTRING_LEN,
239 pport_2819_stats_desc[i].format);
241 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
242 strcpy(data + (idx++) * ETH_GSTRING_LEN,
243 pport_phy_statistical_stats_desc[i].format);
245 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
246 strcpy(data + (idx++) * ETH_GSTRING_LEN,
247 pcie_perf_stats_desc[i].format);
249 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
250 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
251 sprintf(data + (idx++) * ETH_GSTRING_LEN,
252 pport_per_prio_traffic_stats_desc[i].format, prio);
255 pfc_combined = mlx5e_query_pfc_combined(priv);
256 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
257 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
258 char pfc_string[ETH_GSTRING_LEN];
260 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
261 sprintf(data + (idx++) * ETH_GSTRING_LEN,
262 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
266 if (mlx5e_query_global_pause_combined(priv)) {
267 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
268 sprintf(data + (idx++) * ETH_GSTRING_LEN,
269 pport_per_prio_pfc_stats_desc[i].format, "global");
273 /* port module event counters */
274 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
275 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
277 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
278 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
281 idx += mlx5e_ipsec_get_strings(priv, data + idx * ETH_GSTRING_LEN);
283 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
286 /* per channel counters */
287 for (i = 0; i < priv->channels.num; i++)
288 for (j = 0; j < NUM_RQ_STATS; j++)
289 sprintf(data + (idx++) * ETH_GSTRING_LEN,
290 rq_stats_desc[j].format, i);
292 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
293 for (i = 0; i < priv->channels.num; i++)
294 for (j = 0; j < NUM_SQ_STATS; j++)
295 sprintf(data + (idx++) * ETH_GSTRING_LEN,
296 sq_stats_desc[j].format,
297 priv->channel_tc2txq[i][tc]);
300 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
301 uint32_t stringset, uint8_t *data)
306 case ETH_SS_PRIV_FLAGS:
307 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
308 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
312 for (i = 0; i < mlx5e_self_test_num(priv); i++)
313 strcpy(data + i * ETH_GSTRING_LEN,
314 mlx5e_self_tests[i]);
318 mlx5e_fill_stats_strings(priv, data);
323 static void mlx5e_get_strings(struct net_device *dev,
324 uint32_t stringset, uint8_t *data)
326 struct mlx5e_priv *priv = netdev_priv(dev);
328 mlx5e_ethtool_get_strings(priv, stringset, data);
331 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
332 struct ethtool_stats *stats, u64 *data)
334 struct mlx5e_channels *channels;
335 struct mlx5_priv *mlx5_priv;
336 int i, j, tc, prio, idx = 0;
337 unsigned long pfc_combined;
342 mutex_lock(&priv->state_lock);
343 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
344 mlx5e_update_stats(priv, true);
345 channels = &priv->channels;
346 mutex_unlock(&priv->state_lock);
348 for (i = 0; i < NUM_SW_COUNTERS; i++)
349 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
352 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
353 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
356 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
357 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
358 vport_stats_desc, i);
360 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
361 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
362 pport_802_3_stats_desc, i);
364 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
365 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
366 pport_2863_stats_desc, i);
368 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
369 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
370 pport_2819_stats_desc, i);
372 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
373 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
374 pport_phy_statistical_stats_desc, i);
376 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
377 data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
378 pcie_perf_stats_desc, i);
380 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
381 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
382 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
383 pport_per_prio_traffic_stats_desc, i);
386 pfc_combined = mlx5e_query_pfc_combined(priv);
387 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
388 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
389 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
390 pport_per_prio_pfc_stats_desc, i);
394 if (mlx5e_query_global_pause_combined(priv)) {
395 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
396 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
397 pport_per_prio_pfc_stats_desc, i);
401 /* port module event counters */
402 mlx5_priv = &priv->mdev->priv;
403 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
404 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
405 mlx5e_pme_status_desc, i);
407 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
408 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
409 mlx5e_pme_error_desc, i);
412 idx += mlx5e_ipsec_get_stats(priv, data + idx);
414 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
417 /* per channel counters */
418 for (i = 0; i < channels->num; i++)
419 for (j = 0; j < NUM_RQ_STATS; j++)
421 MLX5E_READ_CTR64_CPU(&channels->c[i]->rq.stats,
424 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
425 for (i = 0; i < channels->num; i++)
426 for (j = 0; j < NUM_SQ_STATS; j++)
427 data[idx++] = MLX5E_READ_CTR64_CPU(&channels->c[i]->sq[tc].stats,
431 static void mlx5e_get_ethtool_stats(struct net_device *dev,
432 struct ethtool_stats *stats,
435 struct mlx5e_priv *priv = netdev_priv(dev);
437 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
440 static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
448 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
451 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
452 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
453 wqe_size = stride_size * num_strides;
455 packets_per_wqe = wqe_size /
456 ALIGN(ETH_DATA_LEN, stride_size);
457 return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
460 static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
469 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
472 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
473 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
474 wqe_size = stride_size * num_strides;
476 num_packets = (1 << order_base_2(num_packets));
478 packets_per_wqe = wqe_size /
479 ALIGN(ETH_DATA_LEN, stride_size);
480 num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
481 return 1 << (order_base_2(num_wqes));
484 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
485 struct ethtool_ringparam *param)
487 int rq_wq_type = priv->channels.params.rq_wq_type;
489 param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
490 1 << mlx5_max_log_rq_size(rq_wq_type));
491 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
492 param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
493 1 << priv->channels.params.log_rq_size);
494 param->tx_pending = 1 << priv->channels.params.log_sq_size;
497 static void mlx5e_get_ringparam(struct net_device *dev,
498 struct ethtool_ringparam *param)
500 struct mlx5e_priv *priv = netdev_priv(dev);
502 mlx5e_ethtool_get_ringparam(priv, param);
505 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
506 struct ethtool_ringparam *param)
508 int rq_wq_type = priv->channels.params.rq_wq_type;
509 struct mlx5e_channels new_channels = {};
518 if (param->rx_jumbo_pending) {
519 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
523 if (param->rx_mini_pending) {
524 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
529 min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
530 1 << mlx5_min_log_rq_size(rq_wq_type));
531 max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
532 1 << mlx5_max_log_rq_size(rq_wq_type));
533 rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
536 if (param->rx_pending < min_rq_size) {
537 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
538 __func__, param->rx_pending,
542 if (param->rx_pending > max_rq_size) {
543 netdev_info(priv->netdev, "%s: rx_pending (%d) > max (%d)\n",
544 __func__, param->rx_pending,
549 num_mtts = MLX5E_REQUIRED_MTTS(rx_pending_wqes);
550 if (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
551 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
552 netdev_info(priv->netdev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
553 __func__, param->rx_pending);
557 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
558 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
559 __func__, param->tx_pending,
560 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
563 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
564 netdev_info(priv->netdev, "%s: tx_pending (%d) > max (%d)\n",
565 __func__, param->tx_pending,
566 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
570 log_rq_size = order_base_2(rx_pending_wqes);
571 log_sq_size = order_base_2(param->tx_pending);
573 if (log_rq_size == priv->channels.params.log_rq_size &&
574 log_sq_size == priv->channels.params.log_sq_size)
577 mutex_lock(&priv->state_lock);
579 new_channels.params = priv->channels.params;
580 new_channels.params.log_rq_size = log_rq_size;
581 new_channels.params.log_sq_size = log_sq_size;
583 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
584 priv->channels.params = new_channels.params;
588 err = mlx5e_open_channels(priv, &new_channels);
592 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
595 mutex_unlock(&priv->state_lock);
600 static int mlx5e_set_ringparam(struct net_device *dev,
601 struct ethtool_ringparam *param)
603 struct mlx5e_priv *priv = netdev_priv(dev);
605 return mlx5e_ethtool_set_ringparam(priv, param);
608 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
609 struct ethtool_channels *ch)
611 ch->max_combined = priv->profile->max_nch(priv->mdev);
612 ch->combined_count = priv->channels.params.num_channels;
615 static void mlx5e_get_channels(struct net_device *dev,
616 struct ethtool_channels *ch)
618 struct mlx5e_priv *priv = netdev_priv(dev);
620 mlx5e_ethtool_get_channels(priv, ch);
623 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
624 struct ethtool_channels *ch)
626 unsigned int count = ch->combined_count;
627 struct mlx5e_channels new_channels = {};
632 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
637 if (priv->channels.params.num_channels == count)
640 mutex_lock(&priv->state_lock);
642 new_channels.params = priv->channels.params;
643 new_channels.params.num_channels = count;
644 mlx5e_build_default_indir_rqt(priv->mdev, new_channels.params.indirection_rqt,
645 MLX5E_INDIR_RQT_SIZE, count);
647 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
648 priv->channels.params = new_channels.params;
652 /* Create fresh channels with new parameters */
653 err = mlx5e_open_channels(priv, &new_channels);
657 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
659 mlx5e_arfs_disable(priv);
661 /* Switch to new channels, set new parameters and close old ones */
662 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
665 err = mlx5e_arfs_enable(priv);
667 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
672 mutex_unlock(&priv->state_lock);
677 static int mlx5e_set_channels(struct net_device *dev,
678 struct ethtool_channels *ch)
680 struct mlx5e_priv *priv = netdev_priv(dev);
682 return mlx5e_ethtool_set_channels(priv, ch);
685 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
686 struct ethtool_coalesce *coal)
688 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
691 coal->rx_coalesce_usecs = priv->channels.params.rx_cq_moderation.usec;
692 coal->rx_max_coalesced_frames = priv->channels.params.rx_cq_moderation.pkts;
693 coal->tx_coalesce_usecs = priv->channels.params.tx_cq_moderation.usec;
694 coal->tx_max_coalesced_frames = priv->channels.params.tx_cq_moderation.pkts;
695 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_am_enabled;
700 static int mlx5e_get_coalesce(struct net_device *netdev,
701 struct ethtool_coalesce *coal)
703 struct mlx5e_priv *priv = netdev_priv(netdev);
705 return mlx5e_ethtool_get_coalesce(priv, coal);
709 mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
711 struct mlx5_core_dev *mdev = priv->mdev;
715 for (i = 0; i < priv->channels.num; ++i) {
716 struct mlx5e_channel *c = priv->channels.c[i];
718 for (tc = 0; tc < c->num_tc; tc++) {
719 mlx5_core_modify_cq_moderation(mdev,
721 coal->tx_coalesce_usecs,
722 coal->tx_max_coalesced_frames);
725 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
726 coal->rx_coalesce_usecs,
727 coal->rx_max_coalesced_frames);
731 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
732 struct ethtool_coalesce *coal)
734 struct mlx5_core_dev *mdev = priv->mdev;
735 struct mlx5e_channels new_channels = {};
739 if (!MLX5_CAP_GEN(mdev, cq_moderation))
742 mutex_lock(&priv->state_lock);
743 new_channels.params = priv->channels.params;
745 new_channels.params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
746 new_channels.params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
747 new_channels.params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
748 new_channels.params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
749 new_channels.params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
751 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
752 priv->channels.params = new_channels.params;
757 reset = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_am_enabled;
759 mlx5e_set_priv_channels_coalesce(priv, coal);
760 priv->channels.params = new_channels.params;
764 /* open fresh channels with new coal parameters */
765 err = mlx5e_open_channels(priv, &new_channels);
769 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
772 mutex_unlock(&priv->state_lock);
776 static int mlx5e_set_coalesce(struct net_device *netdev,
777 struct ethtool_coalesce *coal)
779 struct mlx5e_priv *priv = netdev_priv(netdev);
781 return mlx5e_ethtool_set_coalesce(priv, coal);
784 static void ptys2ethtool_supported_link(unsigned long *supported_modes,
787 unsigned long proto_cap = eth_proto_cap;
790 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
791 bitmap_or(supported_modes, supported_modes,
792 ptys2ethtool_table[proto].supported,
793 __ETHTOOL_LINK_MODE_MASK_NBITS);
796 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
799 unsigned long proto_cap = eth_proto_cap;
802 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
803 bitmap_or(advertising_modes, advertising_modes,
804 ptys2ethtool_table[proto].advertised,
805 __ETHTOOL_LINK_MODE_MASK_NBITS);
808 static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
812 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
813 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
814 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
815 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
816 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
817 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
818 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
819 ethtool_link_ksettings_add_link_mode(link_ksettings,
822 ethtool_link_ksettings_add_link_mode(link_ksettings,
827 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
828 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
829 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
830 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
831 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
832 ethtool_link_ksettings_add_link_mode(link_ksettings,
835 ethtool_link_ksettings_add_link_mode(link_ksettings,
842 switch (connector_type) {
844 ethtool_link_ksettings_add_link_mode(link_ksettings,
846 ethtool_link_ksettings_add_link_mode(link_ksettings,
850 ethtool_link_ksettings_add_link_mode(link_ksettings,
852 ethtool_link_ksettings_add_link_mode(link_ksettings,
856 ethtool_link_ksettings_add_link_mode(link_ksettings,
858 ethtool_link_ksettings_add_link_mode(link_ksettings,
862 ethtool_link_ksettings_add_link_mode(link_ksettings,
864 ethtool_link_ksettings_add_link_mode(link_ksettings,
867 case MLX5E_PORT_FIBRE:
868 ethtool_link_ksettings_add_link_mode(link_ksettings,
870 ethtool_link_ksettings_add_link_mode(link_ksettings,
874 ethtool_link_ksettings_add_link_mode(link_ksettings,
875 supported, Backplane);
876 ethtool_link_ksettings_add_link_mode(link_ksettings,
877 advertising, Backplane);
879 case MLX5E_PORT_NONE:
880 case MLX5E_PORT_OTHER:
886 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
893 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
897 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
898 if (proto_cap & MLX5E_PROT_MASK(i))
899 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
905 static void get_speed_duplex(struct net_device *netdev,
907 struct ethtool_link_ksettings *link_ksettings)
910 u32 speed = SPEED_UNKNOWN;
911 u8 duplex = DUPLEX_UNKNOWN;
913 if (!netif_carrier_ok(netdev))
916 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
917 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
918 speed = ptys2ethtool_table[i].speed;
919 duplex = DUPLEX_FULL;
924 link_ksettings->base.speed = speed;
925 link_ksettings->base.duplex = duplex;
928 static void get_supported(u32 eth_proto_cap,
929 struct ethtool_link_ksettings *link_ksettings)
931 unsigned long *supported = link_ksettings->link_modes.supported;
933 ptys2ethtool_supported_link(supported, eth_proto_cap);
934 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
937 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
939 struct ethtool_link_ksettings *link_ksettings)
941 unsigned long *advertising = link_ksettings->link_modes.advertising;
943 ptys2ethtool_adver_link(advertising, eth_proto_cap);
945 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
946 if (tx_pause ^ rx_pause)
947 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
950 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
951 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
952 [MLX5E_PORT_NONE] = PORT_NONE,
953 [MLX5E_PORT_TP] = PORT_TP,
954 [MLX5E_PORT_AUI] = PORT_AUI,
955 [MLX5E_PORT_BNC] = PORT_BNC,
956 [MLX5E_PORT_MII] = PORT_MII,
957 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
958 [MLX5E_PORT_DA] = PORT_DA,
959 [MLX5E_PORT_OTHER] = PORT_OTHER,
962 static u8 get_connector_port(u32 eth_proto, u8 connector_type)
964 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
965 return ptys2connector_type[connector_type];
967 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
968 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
969 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
970 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
974 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
975 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
976 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
980 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
981 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
982 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
983 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
990 static void get_lp_advertising(u32 eth_proto_lp,
991 struct ethtool_link_ksettings *link_ksettings)
993 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
995 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
998 static int mlx5e_get_link_ksettings(struct net_device *netdev,
999 struct ethtool_link_ksettings *link_ksettings)
1001 struct mlx5e_priv *priv = netdev_priv(netdev);
1002 struct mlx5_core_dev *mdev = priv->mdev;
1003 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
1007 u32 eth_proto_admin;
1010 u8 an_disable_admin;
1015 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
1017 netdev_err(netdev, "%s: query port ptys failed: %d\n",
1019 goto err_query_ptys;
1022 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
1023 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
1024 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
1025 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
1026 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
1027 an_status = MLX5_GET(ptys_reg, out, an_status);
1028 connector_type = MLX5_GET(ptys_reg, out, connector_type);
1030 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
1032 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
1033 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
1035 get_supported(eth_proto_cap, link_ksettings);
1036 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings);
1037 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
1039 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1041 link_ksettings->base.port = get_connector_port(eth_proto_oper,
1043 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
1045 get_lp_advertising(eth_proto_lp, link_ksettings);
1047 if (an_status == MLX5_AN_COMPLETE)
1048 ethtool_link_ksettings_add_link_mode(link_ksettings,
1049 lp_advertising, Autoneg);
1051 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
1053 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
1055 if (!an_disable_admin)
1056 ethtool_link_ksettings_add_link_mode(link_ksettings,
1057 advertising, Autoneg);
1063 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
1065 u32 i, ptys_modes = 0;
1067 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
1068 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
1070 __ETHTOOL_LINK_MODE_MASK_NBITS))
1071 ptys_modes |= MLX5E_PROT_MASK(i);
1077 static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
1079 u32 i, speed_links = 0;
1081 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
1082 if (ptys2ethtool_table[i].speed == speed)
1083 speed_links |= MLX5E_PROT_MASK(i);
1089 static int mlx5e_set_link_ksettings(struct net_device *netdev,
1090 const struct ethtool_link_ksettings *link_ksettings)
1092 struct mlx5e_priv *priv = netdev_priv(netdev);
1093 struct mlx5_core_dev *mdev = priv->mdev;
1094 u32 eth_proto_cap, eth_proto_admin;
1095 bool an_changes = false;
1096 u8 an_disable_admin;
1104 speed = link_ksettings->base.speed;
1106 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
1107 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
1108 mlx5e_ethtool2ptys_speed_link(speed);
1110 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
1112 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
1117 link_modes = link_modes & eth_proto_cap;
1119 netdev_err(netdev, "%s: Not supported link mode(s) requested",
1125 err = mlx5_query_port_proto_admin(mdev, ð_proto_admin, MLX5_PTYS_EN);
1127 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
1132 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
1133 &an_disable_cap, &an_disable_admin);
1135 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
1136 an_changes = ((!an_disable && an_disable_admin) ||
1137 (an_disable && !an_disable_admin));
1139 if (!an_changes && link_modes == eth_proto_admin)
1142 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
1143 mlx5_toggle_port_link(mdev);
1149 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1151 struct mlx5e_priv *priv = netdev_priv(netdev);
1153 return sizeof(priv->channels.params.toeplitz_hash_key);
1156 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1158 return MLX5E_INDIR_RQT_SIZE;
1161 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1164 struct mlx5e_priv *priv = netdev_priv(netdev);
1167 memcpy(indir, priv->channels.params.indirection_rqt,
1168 sizeof(priv->channels.params.indirection_rqt));
1171 memcpy(key, priv->channels.params.toeplitz_hash_key,
1172 sizeof(priv->channels.params.toeplitz_hash_key));
1175 *hfunc = priv->channels.params.rss_hfunc;
1180 static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
1182 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1183 struct mlx5_core_dev *mdev = priv->mdev;
1184 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
1187 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
1189 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1190 memset(tirc, 0, ctxlen);
1191 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
1192 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
1196 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1197 const u8 *key, const u8 hfunc)
1199 struct mlx5e_priv *priv = netdev_priv(dev);
1200 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1201 bool hash_changed = false;
1204 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1205 (hfunc != ETH_RSS_HASH_XOR) &&
1206 (hfunc != ETH_RSS_HASH_TOP))
1209 in = kvzalloc(inlen, GFP_KERNEL);
1213 mutex_lock(&priv->state_lock);
1215 if (hfunc != ETH_RSS_HASH_NO_CHANGE &&
1216 hfunc != priv->channels.params.rss_hfunc) {
1217 priv->channels.params.rss_hfunc = hfunc;
1218 hash_changed = true;
1222 memcpy(priv->channels.params.indirection_rqt, indir,
1223 sizeof(priv->channels.params.indirection_rqt));
1225 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1226 u32 rqtn = priv->indir_rqt.rqtn;
1227 struct mlx5e_redirect_rqt_param rrp = {
1231 .hfunc = priv->channels.params.rss_hfunc,
1232 .channels = &priv->channels,
1237 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1242 memcpy(priv->channels.params.toeplitz_hash_key, key,
1243 sizeof(priv->channels.params.toeplitz_hash_key));
1244 hash_changed = hash_changed ||
1245 priv->channels.params.rss_hfunc == ETH_RSS_HASH_TOP;
1249 mlx5e_modify_tirs_hash(priv, in, inlen);
1251 mutex_unlock(&priv->state_lock);
1258 static int mlx5e_get_rxnfc(struct net_device *netdev,
1259 struct ethtool_rxnfc *info, u32 *rule_locs)
1261 struct mlx5e_priv *priv = netdev_priv(netdev);
1264 switch (info->cmd) {
1265 case ETHTOOL_GRXRINGS:
1266 info->data = priv->channels.params.num_channels;
1268 case ETHTOOL_GRXCLSRLCNT:
1269 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1271 case ETHTOOL_GRXCLSRULE:
1272 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1274 case ETHTOOL_GRXCLSRLALL:
1275 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1285 static int mlx5e_get_tunable(struct net_device *dev,
1286 const struct ethtool_tunable *tuna,
1289 const struct mlx5e_priv *priv = netdev_priv(dev);
1293 case ETHTOOL_TX_COPYBREAK:
1294 *(u32 *)data = priv->channels.params.tx_max_inline;
1304 static int mlx5e_set_tunable(struct net_device *dev,
1305 const struct ethtool_tunable *tuna,
1308 struct mlx5e_priv *priv = netdev_priv(dev);
1309 struct mlx5_core_dev *mdev = priv->mdev;
1310 struct mlx5e_channels new_channels = {};
1314 mutex_lock(&priv->state_lock);
1317 case ETHTOOL_TX_COPYBREAK:
1319 if (val > mlx5e_get_max_inline_cap(mdev)) {
1324 new_channels.params = priv->channels.params;
1325 new_channels.params.tx_max_inline = val;
1327 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1328 priv->channels.params = new_channels.params;
1332 err = mlx5e_open_channels(priv, &new_channels);
1335 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1343 mutex_unlock(&priv->state_lock);
1347 static void mlx5e_get_pauseparam(struct net_device *netdev,
1348 struct ethtool_pauseparam *pauseparam)
1350 struct mlx5e_priv *priv = netdev_priv(netdev);
1351 struct mlx5_core_dev *mdev = priv->mdev;
1354 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1355 &pauseparam->tx_pause);
1357 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1362 static int mlx5e_set_pauseparam(struct net_device *netdev,
1363 struct ethtool_pauseparam *pauseparam)
1365 struct mlx5e_priv *priv = netdev_priv(netdev);
1366 struct mlx5_core_dev *mdev = priv->mdev;
1369 if (pauseparam->autoneg)
1372 err = mlx5_set_port_pause(mdev,
1373 pauseparam->rx_pause ? 1 : 0,
1374 pauseparam->tx_pause ? 1 : 0);
1376 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1383 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1384 struct ethtool_ts_info *info)
1388 ret = ethtool_op_get_ts_info(priv->netdev, info);
1392 info->phc_index = priv->tstamp.ptp ?
1393 ptp_clock_index(priv->tstamp.ptp) : -1;
1395 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1398 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1399 SOF_TIMESTAMPING_RX_HARDWARE |
1400 SOF_TIMESTAMPING_RAW_HARDWARE;
1402 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1403 BIT(HWTSTAMP_TX_ON);
1405 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1406 BIT(HWTSTAMP_FILTER_ALL);
1411 static int mlx5e_get_ts_info(struct net_device *dev,
1412 struct ethtool_ts_info *info)
1414 struct mlx5e_priv *priv = netdev_priv(dev);
1416 return mlx5e_ethtool_get_ts_info(priv, info);
1419 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1423 if (MLX5_CAP_GEN(mdev, wol_g))
1426 if (MLX5_CAP_GEN(mdev, wol_s))
1427 ret |= WAKE_MAGICSECURE;
1429 if (MLX5_CAP_GEN(mdev, wol_a))
1432 if (MLX5_CAP_GEN(mdev, wol_b))
1435 if (MLX5_CAP_GEN(mdev, wol_m))
1438 if (MLX5_CAP_GEN(mdev, wol_u))
1441 if (MLX5_CAP_GEN(mdev, wol_p))
1447 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1451 if (mode & MLX5_WOL_MAGIC)
1454 if (mode & MLX5_WOL_SECURED_MAGIC)
1455 ret |= WAKE_MAGICSECURE;
1457 if (mode & MLX5_WOL_ARP)
1460 if (mode & MLX5_WOL_BROADCAST)
1463 if (mode & MLX5_WOL_MULTICAST)
1466 if (mode & MLX5_WOL_UNICAST)
1469 if (mode & MLX5_WOL_PHY_ACTIVITY)
1475 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1479 if (mode & WAKE_MAGIC)
1480 ret |= MLX5_WOL_MAGIC;
1482 if (mode & WAKE_MAGICSECURE)
1483 ret |= MLX5_WOL_SECURED_MAGIC;
1485 if (mode & WAKE_ARP)
1486 ret |= MLX5_WOL_ARP;
1488 if (mode & WAKE_BCAST)
1489 ret |= MLX5_WOL_BROADCAST;
1491 if (mode & WAKE_MCAST)
1492 ret |= MLX5_WOL_MULTICAST;
1494 if (mode & WAKE_UCAST)
1495 ret |= MLX5_WOL_UNICAST;
1497 if (mode & WAKE_PHY)
1498 ret |= MLX5_WOL_PHY_ACTIVITY;
1503 static void mlx5e_get_wol(struct net_device *netdev,
1504 struct ethtool_wolinfo *wol)
1506 struct mlx5e_priv *priv = netdev_priv(netdev);
1507 struct mlx5_core_dev *mdev = priv->mdev;
1511 memset(wol, 0, sizeof(*wol));
1513 wol->supported = mlx5e_get_wol_supported(mdev);
1514 if (!wol->supported)
1517 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1521 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1524 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1526 struct mlx5e_priv *priv = netdev_priv(netdev);
1527 struct mlx5_core_dev *mdev = priv->mdev;
1528 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1534 if (wol->wolopts & ~wol_supported)
1537 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1539 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1542 static int mlx5e_set_phys_id(struct net_device *dev,
1543 enum ethtool_phys_id_state state)
1545 struct mlx5e_priv *priv = netdev_priv(dev);
1546 struct mlx5_core_dev *mdev = priv->mdev;
1547 u16 beacon_duration;
1549 if (!MLX5_CAP_GEN(mdev, beacon_led))
1553 case ETHTOOL_ID_ACTIVE:
1554 beacon_duration = MLX5_BEACON_DURATION_INF;
1556 case ETHTOOL_ID_INACTIVE:
1557 beacon_duration = MLX5_BEACON_DURATION_OFF;
1563 return mlx5_set_port_beacon(mdev, beacon_duration);
1566 static int mlx5e_get_module_info(struct net_device *netdev,
1567 struct ethtool_modinfo *modinfo)
1569 struct mlx5e_priv *priv = netdev_priv(netdev);
1570 struct mlx5_core_dev *dev = priv->mdev;
1574 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1578 /* data[0] = identifier byte */
1580 case MLX5_MODULE_ID_QSFP:
1581 modinfo->type = ETH_MODULE_SFF_8436;
1582 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1584 case MLX5_MODULE_ID_QSFP_PLUS:
1585 case MLX5_MODULE_ID_QSFP28:
1586 /* data[1] = revision id */
1587 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1588 modinfo->type = ETH_MODULE_SFF_8636;
1589 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1591 modinfo->type = ETH_MODULE_SFF_8436;
1592 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1595 case MLX5_MODULE_ID_SFP:
1596 modinfo->type = ETH_MODULE_SFF_8472;
1597 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1600 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1608 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1609 struct ethtool_eeprom *ee,
1612 struct mlx5e_priv *priv = netdev_priv(netdev);
1613 struct mlx5_core_dev *mdev = priv->mdev;
1614 int offset = ee->offset;
1621 memset(data, 0, ee->len);
1623 while (i < ee->len) {
1624 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1631 if (size_read < 0) {
1632 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1633 __func__, size_read);
1638 offset += size_read;
1644 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1646 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1648 struct mlx5e_priv *priv = netdev_priv(netdev);
1649 struct mlx5_core_dev *mdev = priv->mdev;
1650 struct mlx5e_channels new_channels = {};
1651 bool rx_mode_changed;
1652 u8 rx_cq_period_mode;
1655 rx_cq_period_mode = enable ?
1656 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1657 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1658 rx_mode_changed = rx_cq_period_mode != priv->channels.params.rx_cq_period_mode;
1660 if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1661 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1664 if (!rx_mode_changed)
1667 new_channels.params = priv->channels.params;
1668 mlx5e_set_rx_cq_mode_params(&new_channels.params, rx_cq_period_mode);
1670 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1671 priv->channels.params = new_channels.params;
1675 err = mlx5e_open_channels(priv, &new_channels);
1679 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1683 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1685 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1686 struct mlx5e_channels new_channels = {};
1689 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1690 return new_val ? -EOPNOTSUPP : 0;
1692 if (curr_val == new_val)
1695 new_channels.params = priv->channels.params;
1696 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1698 mlx5e_set_rq_type_params(priv->mdev, &new_channels.params,
1699 new_channels.params.rq_wq_type);
1701 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1702 priv->channels.params = new_channels.params;
1706 err = mlx5e_open_channels(priv, &new_channels);
1710 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1714 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1717 struct mlx5e_priv *priv = netdev_priv(netdev);
1718 struct mlx5_core_dev *mdev = priv->mdev;
1720 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1723 if (enable && priv->tstamp.hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
1724 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1728 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1729 priv->channels.params.rx_cqe_compress_def = enable;
1734 static int mlx5e_handle_pflag(struct net_device *netdev,
1736 enum mlx5e_priv_flag flag,
1737 mlx5e_pflag_handler pflag_handler)
1739 struct mlx5e_priv *priv = netdev_priv(netdev);
1740 bool enable = !!(wanted_flags & flag);
1741 u32 changes = wanted_flags ^ priv->channels.params.pflags;
1744 if (!(changes & flag))
1747 err = pflag_handler(netdev, enable);
1749 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1750 enable ? "Enable" : "Disable", flag, err);
1754 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
1758 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1760 struct mlx5e_priv *priv = netdev_priv(netdev);
1763 mutex_lock(&priv->state_lock);
1764 err = mlx5e_handle_pflag(netdev, pflags,
1765 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1766 set_pflag_rx_cqe_based_moder);
1770 err = mlx5e_handle_pflag(netdev, pflags,
1771 MLX5E_PFLAG_RX_CQE_COMPRESS,
1772 set_pflag_rx_cqe_compress);
1775 mutex_unlock(&priv->state_lock);
1779 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1781 struct mlx5e_priv *priv = netdev_priv(netdev);
1783 return priv->channels.params.pflags;
1786 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1789 struct mlx5e_priv *priv = netdev_priv(dev);
1792 case ETHTOOL_SRXCLSRLINS:
1793 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1795 case ETHTOOL_SRXCLSRLDEL:
1796 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1806 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1807 struct ethtool_flash *flash)
1809 struct mlx5_core_dev *mdev = priv->mdev;
1810 struct net_device *dev = priv->netdev;
1811 const struct firmware *fw;
1814 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1817 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1824 err = mlx5_firmware_flash(mdev, fw);
1825 release_firmware(fw);
1832 static int mlx5e_flash_device(struct net_device *dev,
1833 struct ethtool_flash *flash)
1835 struct mlx5e_priv *priv = netdev_priv(dev);
1837 return mlx5e_ethtool_flash_device(priv, flash);
1840 const struct ethtool_ops mlx5e_ethtool_ops = {
1841 .get_drvinfo = mlx5e_get_drvinfo,
1842 .get_link = ethtool_op_get_link,
1843 .get_strings = mlx5e_get_strings,
1844 .get_sset_count = mlx5e_get_sset_count,
1845 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1846 .get_ringparam = mlx5e_get_ringparam,
1847 .set_ringparam = mlx5e_set_ringparam,
1848 .get_channels = mlx5e_get_channels,
1849 .set_channels = mlx5e_set_channels,
1850 .get_coalesce = mlx5e_get_coalesce,
1851 .set_coalesce = mlx5e_set_coalesce,
1852 .get_link_ksettings = mlx5e_get_link_ksettings,
1853 .set_link_ksettings = mlx5e_set_link_ksettings,
1854 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1855 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1856 .get_rxfh = mlx5e_get_rxfh,
1857 .set_rxfh = mlx5e_set_rxfh,
1858 .get_rxnfc = mlx5e_get_rxnfc,
1859 .set_rxnfc = mlx5e_set_rxnfc,
1860 .flash_device = mlx5e_flash_device,
1861 .get_tunable = mlx5e_get_tunable,
1862 .set_tunable = mlx5e_set_tunable,
1863 .get_pauseparam = mlx5e_get_pauseparam,
1864 .set_pauseparam = mlx5e_set_pauseparam,
1865 .get_ts_info = mlx5e_get_ts_info,
1866 .set_phys_id = mlx5e_set_phys_id,
1867 .get_wol = mlx5e_get_wol,
1868 .set_wol = mlx5e_set_wol,
1869 .get_module_info = mlx5e_get_module_info,
1870 .get_module_eeprom = mlx5e_get_module_eeprom,
1871 .get_priv_flags = mlx5e_get_priv_flags,
1872 .set_priv_flags = mlx5e_set_priv_flags,
1873 .self_test = mlx5e_self_test,